JP2022165666A - Inverter device, control method for inverter device, and control program for inverter device - Google Patents

Abstract

To provide an inverter device that can effectively prevent ringing caused by a common mode resonance current.SOLUTION: An inverter device 100 comprises: an inverter circuit 3 that is provided with a plurality of switching elements, converts a DC voltage input thereto into an AC voltage, and outputs the voltage to a load; a target waveform generator 4 that generates a target waveform of the voltage output from the inverter circuit; and a switching controller 5 that controls opening and closing of the plurality of switching elements so that an output waveform of the voltage output from the inverter circuit becomes the target waveform. When the target waveform includes a transition section in which a first target voltage is reduced to a second target voltage, the target waveform generator generates the target waveform so that it is maintained at a maintenance voltage smaller than the first target voltage and larger than the second target voltage by a predetermined value VC in a period from a predetermined time point until the completion of transition to the second target voltage.SELECTED DRAWING: Figure 3

Description

The present invention relates to an inverter device that converts a DC voltage into an AC voltage and outputs the AC voltage to a load.

2. Description of the Related Art An inverter device used for driving a compressor of an air conditioner, for example, includes a converter circuit that converts commercial alternating current into direct current and an inverter circuit that converts direct current into alternating current. In such an inverter circuit, oscillation (ringing) of the output voltage and current may occur when the switching element is turned on.

In the invention described in Patent Document 1, the peak value due to the reverse recovery current is suppressed by suppressing di/dt at turn-on. As a result, the increase in turn-on loss is suppressed while reducing ringing.

However, the ringing due to the common mode resonance current flowing to the ground through the load connected to the switching element cannot be sufficiently suppressed even if the above configuration is adopted.

Japanese Patent No. 5186095

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an inverter device capable of effectively suppressing ringing due to common mode resonance current.

That is, an inverter device according to the present invention includes an inverter circuit that includes a plurality of switching elements, converts an input DC voltage into an AC voltage and outputs the voltage to a load, and a target waveform of the voltage that is output from the inverter circuit. and a switching controller for controlling opening and closing of the plurality of switch elements so that the output waveform of the voltage output from the inverter circuit becomes the target waveform, wherein the target waveform generator However, when the target waveform includes a transition interval in which the first target voltage is lowered to the second target voltage, the period from the predetermined time to the transition completion time of the transition to the second target voltage is lower than the first target voltage. The target waveform is generated so as to be maintained at a sustain voltage which is smaller than the second target voltage and which is higher than the second target voltage by a predetermined value VC.

A control method according to the present invention is a control method for an inverter device including an inverter circuit that includes a plurality of switching elements and converts an input DC voltage into an AC voltage for output to a load. A target waveform generation step of generating a target waveform of the voltage output from the circuit; and a switching control step of controlling opening and closing of the plurality of switch elements so that the output waveform of the voltage output from the inverter circuit becomes the target waveform. and, in the target waveform generation step, when the target waveform includes a transition interval in which the first target voltage is decreased to the second target voltage, a transition completion time at which the transition is made from a predetermined time point to the second target voltage. The target waveform is generated so as to maintain a sustain voltage that is lower than the first target voltage and higher than the second target voltage by a predetermined value VC during the period until.

In the case of a conventional inverter device, the common-mode resonant current starts free oscillation as a resonant circuit at the end of the transition section. On the other hand, according to the present invention, the sustain voltage is maintained at a level higher than the second target voltage by the predetermined value VC before the end of the transition interval. can be terminated. Therefore, the resonance energy at the start of free resonance can be reduced to reduce the peak value of ringing due to the common mode current. Moreover, since it is not necessary to lower the switching speed in the inverter circuit, the loss due to switching can be suppressed.

As a specific aspect in which the ringing suppression effect of the present invention is preferably exhibited, the LC resonance parasitically inserted into the common mode of resonance is caused by the parasitic inductance of the wiring connecting between the inverter circuit and the load. and those caused by the parasitic capacitance of the load.

When the target waveform includes a transition section in which the target waveform transitions from a first target voltage to a second target voltage, the target waveform generator parasiticly performs a common mode at the completion of the transition to the second target voltage. If the phase of the resonance current is matched with the phase of the transition completion time so that the resonance current due to the LC resonance to be inserted becomes zero, the energy of the resonance current at the end of the transition section can be further reduced.

In order for the amplitude of the resonance current at the end of the transition interval to be substantially zero, the target waveform generator controls the time length of the transition interval to substantially match an integer multiple of the resonance period of the LC resonance. What is necessary is just to generate the said target waveform so that it may carry out.

In order to make it difficult for the LC resonant circuit composed of parasitic inductance and parasitic capacitance to generate a resonant current due to changes in the output voltage of the inverter circuit, the target waveform generator converts the target waveform or the output waveform into a Fourier waveform. What is necessary is just to generate the waveform in the transition section so that when transformed, the Fourier coefficients near the resonance frequency of the LC resonance are relatively zero with respect to other Fourier coefficients.

As a specific mode for preventing a resonance current from being generated in the LC resonance circuit, when the target waveform generator Fourier-transforms the target waveform or the output waveform, a Fourier transform of a higher order than a predetermined order is obtained. One example is to generate the waveform of the transition interval so that the coefficient has a value that can be regarded as zero relative to other Fourier coefficients.

In a configuration in which the plurality of switching elements includes a high-side switching element and a low-side switching element, the output of the inverter circuit becomes low impedance during a period when current flows through the high-side switching element, making it difficult to control with the low-side switching element. may become. In order to avoid such a problem, the target waveform generator is configured to generate separate target waveforms for the high-side switching element and the low-side switching element. The transition section of the target waveform may be set to start from the storage charge completion time of the high-side switching element.

A specific configuration example of the switching controller includes a voltage comparator that calculates a deviation between the voltage output from the inverter circuit and the voltage of the target waveform at a corresponding time, and and a gate drive pulse generator that controls each gate of the plurality of switching elements so that the deviation becomes small.

A common current detector for detecting the common current is provided in order to make it possible to align the time of occurrence of the resonance current with the start time of the transition section, and to easily set the time length of the transition section to an integral multiple of the resonance period. In addition, the target waveform generator may be configured to set the start point of the transition section based on the common current.

In order to achieve substantially the same effect as the inverter circuit according to the present invention by updating the program in the existing inverter device, a plurality of switching elements are provided and the input DC voltage is converted to AC voltage. A control program for an inverter device having an inverter circuit that outputs to a load, comprising a target waveform generator that generates a target waveform of a voltage that is output from the inverter circuit, and an output waveform of the voltage that is output from the inverter circuit. The computer functions as a switching controller that controls opening and closing of the plurality of switch elements so that the target waveform is obtained by the target waveform generator, wherein the target waveform is changed from the first target voltage to the first target voltage. When a transition section transitioning to two target voltages is included, the transition is completed so that the resonance current due to the LC resonance parasitically inserted in the common mode at the time of completion of the transition to the second target voltage becomes zero. A control program for an inverter device, which is characterized in that it is configured to match the time and the phase of the resonance current, may be used.

Note that the control program may be electronically distributed, or may be recorded on a program recording medium such as a CD, DVD, or flash memory.

As described above, the inverter circuit according to the present invention can sufficiently consume the energy of the resonance current of the LC resonance circuit due to the common mode current at the end of the transition section. Therefore, it is possible to suppress ringing due to common mode current, which could not be sufficiently suppressed in the past. Also, switching loss in the inverter circuit can be suppressed.

1 is a schematic diagram showing the configuration of an inverter device according to a first embodiment of the present invention; FIG. The graph which shows the output characteristic in the conventional inverter apparatus. FIG. 3 is a schematic diagram showing the details of the control mechanism of the inverter device in the first embodiment; 4 is a graph showing the relationship between the time length of the transition section and the resonance period of the LC resonance; Graphs and relationships showing V _out , VC, _VL and i _L when the time length of the transition section is N times the resonance period. The schematic diagram which shows the inverter apparatus in 2nd Embodiment of this invention. The schematic diagram which shows the inverter apparatus in 3rd Embodiment of this invention. The schematic diagram which shows the inverter apparatus in the modification of 3rd Embodiment of this invention. The schematic diagram which shows the inverter apparatus in 4th Embodiment of this invention. The schematic diagram which shows the inverter apparatus in 5th Embodiment of this invention. The graph which shows the effect of the inverter apparatus in 5th Embodiment.

An inverter device 100 according to a first embodiment of the present invention will be described with reference to each drawing. This inverter device 100 is used, for example, to operate a three-phase motor of a compressor of an air conditioner. That is, as shown in FIG. 1, the input end of the inverter device 100 is connected to the commercial three-phase AC power supply 1, and the output end of the inverter device 100 and the load compressor are connected by cables. After converting the commercial three-phase AC voltage into DC voltage, the inverter device 100 converts it again into a desired AC voltage and supplies it to the three-phase motor of the compressor. Further, when the output of the inverter device 100 transitions due to the parasitic inductance SI present in the cable connecting the inverter device 100 and the compressor and the parasitic capacitance SC present in the compressor, parasitic insertion into the common mode A resonance current is generated due to the LC resonance.

Next, details of the inverter device 100 will be described.

As shown in FIG. 1, the inverter device 100 includes a converter circuit 2 that converts a three-phase AC voltage into a DC voltage, an inverter circuit 3 that converts the DC voltage into an AC voltage, and a control mechanism that controls at least the inverter circuit 3. , is equipped with

The converter circuit 2 includes a three-phase full-bridge diode circuit that rectifies a three-phase AC voltage, and a smoothing capacitor connected between DC terminals on the output side of the three-phase full-bridge diode circuit.

The inverter circuit 3 has an upper arm with three switching elements and a lower arm with three switching elements. Each switching element is three-phase bridge-connected, converts the DC power input from the converter circuit 2 into three-phase AC power, and outputs the three-phase AC power to the compressor, which is the load. The switching elements are typically power switching elements IGBTs (Insulated Gate Bipolar Transistors), but are not limited to and can be any suitable semiconductor switching elements. A flywheel diode is connected in anti-parallel to each switching element.

Further, a common current detector 6 for detecting a common current is provided on a cable connecting the inverter circuit 3 and the compressor.

Such an inverter device 100 has characteristics as shown in FIG. That is, when the switching speed of the switching element is fast, the loss due to the switching element generated when the output voltage of the inverter circuit 3 transitions is small, whereas the LC resonance caused by the parasitic inductance SI and the parasitic capacitance SC is growing. On the other hand, when the switching speed is slow, the loss due to the switching element generated when the output voltage of the inverter circuit 3 transitions increases, but the LC resonance decreases. The inverter circuit 3 of this embodiment is configured to suppress ringing due to resonance while reducing losses in the switching elements by switching control in the transition of the output voltage.

Specifically, the control mechanism is, for example, a computer having a CPU, a memory, an A/D converter, a D/A converter, and various input/output means, and a control program for the inverter device 100 stored in the memory is executed. As a result, each device cooperates to exhibit the functions of at least the target waveform generator 4 and the switching controller 5 as shown in FIG.

The target waveform generator 4 generates a target waveform of the voltage output from the inverter circuit 3 and outputs it to the switching controller 5 . The switching controller 5 controls opening and closing of each switching element so that the output waveform of the voltage output from the inverter circuit 3 becomes a target waveform. Specifically, the switching controller 5 includes a voltage comparator 51 that calculates the deviation between the voltage indicated by the output waveform and the voltage indicated by the target waveform, and generates a gate drive pulse for each switching element so that the calculated deviation becomes small. and a gate drive pulse generator 52 for

Next, details of the target waveform generator 4 will be described. The target waveform generator 4 is parasitically inserted into the common mode at the completion of the transition to the second target voltage when the target waveform includes a transition section in which the first target voltage transitions to the second target voltage. The transition completion point and the phase of the resonance current are matched so that the resonance current due to the LC resonance is zero. In this embodiment, the second target voltage is a voltage lower than the first target voltage, and the second target voltage is zero. Also, in the transition section, the voltage drops in a ramp shape from the first target voltage toward the second target voltage, for example.

The transition time (length of time) of the transition interval is set to substantially match an integral multiple of the resonance period of the LC resonance, as shown in the graph of FIG. As shown in the graph of FIG. 4, when the time length of the transition interval is an integral multiple of the resonance cycle of the LC resonance, voltage oscillation due to resonance can be almost eliminated after the transition interval ends. Such an effect is obtained by setting the output voltage of the inverter circuit 3 to V _out , the common mode parasitic inductance SI to L, the common mode parasitic capacitance SC to C, and each frequency of LC resonance to ω _n =1/(LC)^( 1/2), the voltage applied to the parasitic capacitance SC is V _C (t), the voltage across the parasitic inductance SI is V _L (t), the current flowing through the parasitic inductance SI is i _L (t), and the transition of V _out When the time is _tf and an arbitrary integer is N, each voltage and current can be represented by the graph and formula shown in FIG. Substituting t _f =N·2π/ω _n into V _out , V _C (t), and i _L (t), it is found that each becomes zero. Therefore, after t= _tf , that is, after the transition interval ends, no resonance occurs.

In the inverter device 100 of the first embodiment configured as described above, in the transition section of the voltage output from the inverter circuit 3, the transition time is an integral multiple of the resonance period of the LC resonance caused by each parasitic element. , so that resonance can be prevented from occurring after the transition period ends. Therefore, it is not necessary to slow down the switching speed of the switching element to prevent resonance as in the conventional art, and the switching speed can be kept high. Therefore, it is possible to suppress the occurrence of ringing due to parasitic elements even when the output voltage transitions, while reducing loss due to switching. In addition, since it is possible to suppress the noise component of the low resonance frequency, which is difficult to deal with EMI, and directly suppress the resonance, it is possible to reduce the number of noise countermeasure parts such as ferrite cores. In addition, the peak due to the reverse recovery current can be suppressed as in the conventional case.

Next, the inverter device 100 of 2nd Embodiment is demonstrated, referring FIG. In addition, suppose that the same code|symbol is attached|subjected about the part corresponding to each part demonstrated in 1st Embodiment.

In the inverter device 100 of the second embodiment, a Rogowski coil 61 is provided as the common current detector 6 on the cable connecting between the output terminal of the inverter circuit 3 and the compressor. Specifically, a Rogowski coil 61 bundles three cables connected to the compressor. Since the differential waveform of the common current is obtained by the Rogowski coil 61, the differential waveform is passed through an integrator to be converted into a common current waveform. Based on the obtained common current waveform, one or more detectors extract common current amplitude and phase information. The detector can use, for example, an A/D converter to obtain amplitude and phase information. Further, the detector may be a comparator circuit for obtaining phase information and a peak hold circuit for obtaining amplitude information. Based on information on the phase and amplitude of the common current obtained by the Rogowski coil 61, the target waveform generator 4 determines the start timing and transition time of the transition interval. That is, the start timing of the transition period is set so as to substantially coincide with the generation timing of the LC resonance.

As described above, with the inverter device 100 of the second embodiment, the timing of occurrence of LC resonance and its resonance period can be obtained by the Rogowski coil 61, which is the common current detector 6. It is possible to accurately set the period to an integral multiple of the resonance period, and to align the start timing of the transition section and the generation timing of the LC resonance. For this reason, the resonance current can be made zero at the end of the transition section, so that the resonance can be prevented from occurring after that.

Next, the inverter device 100 of 3rd Embodiment is demonstrated, referring FIG.7 and FIG.8.

In the third embodiment, when the target waveform or the output waveform is Fourier-transformed as shown in FIG. 7, the target waveform generator 4 has a Fourier coefficient near the resonance frequency of the LC resonance relative to the other Fourier coefficients. It is configured to generate a waveform in the transition section so that it has a value that can be considered zero. Here, to be regarded as relatively zero means that the amplitude of the spectrum after Fourier transform is 30 to 40 dB or less with respect to the amplitude of the source signal component.

With the inverter device 100 of the third embodiment as described above, it is possible to prevent the LC resonance circuit from generating a resonance current, so that ringing after the end of the transition period can be further suppressed.

A modification of the third embodiment will be described. As shown in FIG. 8, when the target waveform generator 4 Fourier-transforms the target waveform or the output waveform, Fourier coefficients higher than a predetermined order become values that can be regarded as zero relative to other Fourier coefficients. A waveform in the transition section may be generated as follows.

Next, the inverter device 100 of 4th Embodiment is demonstrated, referring FIG.

The fourth embodiment is characterized by switching control of the high-side switching element and the low-side switching element in the inverter circuit 3 . That is, the target waveform generator 4 is configured to generate separate target waveforms for the high-side switching element and the low-side switching element, and as shown in the graph of FIG. , is set to start from the storage charge completion time of the high-side switching element.

In the inverter device 100 of the fourth embodiment, in a state where the current flows through the high-side switching element and the impedance of _Vout becomes low, the control of the low-side switching element becomes difficult. No control. That is, since the control of the low-side switching element is started at the timing when the current of the high-side switching element becomes zero, stable control can be realized.

A modification of the fourth embodiment will be described. In order to perform the control in the fourth embodiment more accurately, a current detector for detecting the high side current is provided, and the low side switching is performed at the timing when the current detected by this current detector becomes zero. The device target voltage waveform may be configured to fall into the transition interval. Moreover, the timing of starting control of the high-side switching element may be the time when the current flowing through the low-side switching element becomes zero. That is, it can be realized by a configuration in which the high side and the low side are read interchangeably in the above-described fourth embodiment.

Next, the inverter device 100 of 5th Embodiment is demonstrated, referring FIG.10 and FIG.11.

In the fifth embodiment, as shown in the graph of FIG. 10, when the target waveform includes a transition section in which the target voltage is lowered from the first target voltage to the second target voltage, the target waveform generator 4 generates the second target voltage from a predetermined time point. The target waveform is configured to be maintained at a sustain voltage that is lower than the first target voltage and higher than the second target voltage by a predetermined value VC in a period until the transition to the voltage is completed. .

Here, the Q value of the LC resonant series is set within the range of about 0.5 to 3 by voltage control with a predetermined value VC. Q=1/R*(L/C)^(1/2), R=VC/IP, where IP is the peak value of the resonant current, L is the value of the parasitic inductance SI, and C is the parasitic capacitance SC is the value of

In the inverter device 100 of the fifth embodiment, as shown in the graph of FIG. 11, before the voltage becomes zero in the transition section, the voltage is maintained at a sustain voltage greater than zero by a prescribed value VC for a prescribed period of time. The energy of the resonance current can be consumed. In the case where such a correction to provide a sustain voltage is not performed in the transition interval, a large amplitude of the resonance current remains even after the transition interval ends. can suppress the amplitude of In addition, it can be seen that the switching loss can be reduced as compared with the conventional case where the switching speed is lowered to suppress the resonance current. In other words, with the inverter device 100 of the fifth embodiment, the voltage gradient in the transition section is steep to reduce the switching loss, and ringing can be sufficiently suppressed after the transition section ends.

A modification of the fifth embodiment will be described.

Other embodiments will be described. By increasing the voltage of VC and setting the Q value to 1 or less, the attenuation of the resonance energy can be converged more quickly, but there is a trade-off that loss in the switching elements of the inverter circuit 3 increases. Therefore, the value of VC should be set within a range that allows both.

Other embodiments will be described.

The inverter device according to the present invention is not limited to being applied to compressors, and may be used by being connected to various loads. That is, the load may be an alternator.

Moreover, as long as it does not violate the gist of the present invention, it is possible to combine parts of each embodiment with each other, or to modify a part of each embodiment.

1: Three-phase AC power supply 2: Converter circuit 3: Inverter circuit 4: Target waveform generator 5: Switching controller 6: Common current detector 51: Voltage comparator 52: Gate drive pulse generator 61: Rogowski coil 100: Inverter device SC: parasitic capacitance SI: parasitic inductance

Claims (11)

an inverter circuit that includes a plurality of switching elements, converts an input DC voltage into an AC voltage, and outputs the AC voltage to a load;
a target waveform generator for generating a target waveform of the voltage output from the inverter circuit;
a switching controller that controls opening and closing of the plurality of switch elements so that the output waveform of the voltage output from the inverter circuit becomes the target waveform;
In the case where the target waveform generator includes a transition section in which the target waveform is lowered from the first target voltage to the second target voltage, the period from a predetermined point to the transition completion point of transition to the second target voltage is the An inverter device configured to generate a target waveform so as to maintain a sustain voltage that is lower than a first target voltage and higher than the second target voltage by a predetermined value VC. 2. The inverter device according to claim 1, wherein the LC resonance that is parasitically inserted into the common mode is caused by the parasitic inductance of the wiring connecting the inverter circuit and the load and the parasitic capacitance of the load. When the target waveform includes a transition section in which the target waveform transitions from a first target voltage to a second target voltage, the target waveform generator parasiticly performs a common mode at the completion of the transition to the second target voltage. 3. The inverter device according to claim 1 or 2, wherein said transition completion point and said resonance current are in phase so that a resonance current due to LC resonance to be inserted becomes zero. 4. The inverter device according to any one of claims 1 to 3, wherein said target waveform generator generates said target waveform such that the time length of said transition interval substantially matches an integral multiple of a resonance period of said LC resonance. . When the target waveform generator Fourier-transforms the target waveform or the output waveform, the Fourier coefficient near the resonance frequency of the LC resonance is a value that can be regarded as zero relative to other Fourier coefficients. 5. The inverter device according to any one of claims 1 to 4, wherein the waveform of the transition section is generated. When the target waveform generator Fourier-transforms the target waveform or the output waveform, the Fourier coefficients higher than a predetermined order are set to a value that can be regarded as zero relative to other Fourier coefficients. 6. The inverter device according to claim 5, wherein the waveform of the transition section is generated. the plurality of switching elements includes a high-side switching element and a low-side switching element;
wherein the target waveform generator is configured to generate separate target waveforms for the high side switching device and the low side switching device;
7. The inverter device according to claim 1, wherein said transition section of said target waveform for said low-side switching element is set to start from a storage charge completion time of said high-side switching element. The switching controller is
a voltage comparator that calculates the deviation between the voltage output from the inverter circuit and the voltage of the target waveform at the corresponding time;
8. The inverter device according to claim 1, further comprising a gate drive pulse generator that controls each gate of said plurality of switching elements so that the deviation calculated by said voltage comparator becomes small. further comprising a common current detector for detecting the common current,
9. The inverter device according to any one of claims 1 to 8, wherein said target waveform generator is configured to set the start time of said transition interval based on said common current. A control method for an inverter device including an inverter circuit that includes a plurality of switching elements and converts an input DC voltage into an AC voltage and outputs the AC voltage to a load,
a target waveform generating step of generating a target waveform of the voltage output from the inverter circuit;
a switching control step of controlling opening and closing of the plurality of switch elements so that the output waveform of the voltage output from the inverter circuit becomes the target waveform;
In the target waveform generating step, if the target waveform includes a transition section in which the first target voltage is decreased to the second target voltage, the period from a predetermined time point to the transition completion time point of transition to the second target voltage is the A control method for an inverter device, wherein a target waveform is generated so as to maintain a sustain voltage that is lower than a first target voltage and higher than the second target voltage by a predetermined value VC. A control program for an inverter device including an inverter circuit that includes a plurality of switching elements and converts an input DC voltage into an AC voltage and outputs the AC voltage to a load,
a target waveform generator for generating a target waveform of the voltage output from the inverter circuit;
causing a computer to exhibit a function as a switching controller that controls opening and closing of the plurality of switch elements so that the output waveform of the voltage output from the inverter circuit becomes the target waveform,
In the case where the target waveform generator includes a transition section in which the target waveform is lowered from the first target voltage to the second target voltage, the period from a predetermined point to the transition completion point of transition to the second target voltage is the A control program for an inverter device, characterized in that it is configured to generate a target waveform so as to maintain a sustain voltage that is lower than a first target voltage and higher than the second target voltage by a predetermined value VC.

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