JP2022158870A - Method of manufacturing light-emitting element, and light-emitting element - Google Patents

Abstract

To provide a method of manufacturing a light-emitting element in which a reflection layer is formed on a surface opposite to a light extraction surface of a semiconductor laminate whereas no reflection layer is formed on a lateral face of the semiconductor laminate, and to provide the light-emitting element.SOLUTION: A method of manufacturing a light-emitting element includes the steps of: preparing a wafer that has a semiconductor laminate having a first semiconductor layer, an active layer, and a second semiconductor layer and including a plurality of element regions which include a part of the first semiconductor layer, a part of the active layer, and a part of the second semiconductor layer, the respective element regions being separated from each other; forming a first reflection layer continuous to the second semiconductor layer in the plurality of element regions and to the second semiconductor layer located between adjacent element regions among the plurality of element regions; forming a plurality of first masks covering the first reflection layer located above the plurality of element regions; and removing part of the semiconductor laminate and the reflection layer in a region between adjacent first masks among the plurality of first masks so as to expose the first semiconductor layer to form a groove on the semiconductor laminate located between the adjacent element regions among the plurality of element regions.SELECTED DRAWING: Figure 9

Description

The present invention relates to a method for manufacturing a light-emitting device and a light-emitting device.

In a light-emitting element, a structure in which a reflective layer is formed on the surface opposite to the light extraction surface of the semiconductor laminate and no reflective layer is formed on the side surface of the semiconductor laminate to increase the light extraction efficiency. can be done.

JP 2013-21175 A

The present invention provides a method for manufacturing a light-emitting element and a light-emitting element in which a reflective layer is formed on the surface opposite to the light extraction surface of a semiconductor laminate and no reflective layer is formed on the side surface of the semiconductor laminate. aim.

According to one aspect of the present invention, a method for manufacturing a light emitting device includes: a first semiconductor layer; an active layer provided on the first semiconductor layer; a second semiconductor layer provided on the active layer; A wafer having a semiconductor stack including a portion of the first semiconductor layer, a portion of the active layer, and a portion of the second semiconductor layer, each including a plurality of isolated element regions a first reflective layer in succession to the preparing step, the second semiconductor layers of the plurality of device regions, and the second semiconductor layer positioned between the device regions adjacent to each other among the plurality of device regions; forming a plurality of first masks covering the first reflective layer positioned above the plurality of element regions; and between adjacent first masks among the plurality of first masks part of the first reflective layer and the semiconductor laminate in the region of (1) is removed so as to expose the first semiconductor layer, and the semiconductor laminate located between the adjacent element regions among the plurality of element regions; forming a groove in the body.

According to the method for manufacturing a light-emitting device and the light-emitting device of the present invention, a light-emitting device in which a reflective layer is formed on the surface opposite to the light extraction surface of the semiconductor laminate and no reflective layer is formed on the side surface of the semiconductor laminate. can be provided.

It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic plan view which shows the manufacturing method of the light emitting element of one Embodiment of this invention. FIG. 3 is a schematic cross-sectional view taken along line III-III of FIG. 2; It is a schematic plan view which shows the manufacturing method of the light emitting element of one Embodiment of this invention. FIG. 5 is a schematic cross-sectional view taken along line VV of FIG. 4; It is a schematic plan view which shows the manufacturing method of the light emitting element of one Embodiment of this invention. FIG. 7 is a schematic cross-sectional view taken along line VII-VII of FIG. 6; It is a schematic plan view which shows the manufacturing method of the light emitting element of one Embodiment of this invention. FIG. 9 is a schematic cross-sectional view taken along line IX-IX of FIG. 8; It is a schematic plan view which shows the manufacturing method of the light emitting element of one Embodiment of this invention. FIG. 11 is a schematic cross-sectional view taken along line XI-XI of FIG. 10; It is a schematic plan view which shows the manufacturing method of the light emitting element of one Embodiment of this invention. 13 is a schematic cross-sectional view taken along line XIII-XIII of FIG. 12; FIG. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic plan view which shows the manufacturing method of the light emitting element of one Embodiment of this invention. FIG. 17 is a schematic cross-sectional view taken along line XVII-XVII of FIG. 16; It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. 1 is a schematic bottom view of a light emitting device according to one embodiment of the present invention; FIG. It is a schematic bottom view of the modification of the light emitting element of one embodiment of the present invention. It is a schematic bottom view of the modification of the light emitting element of one embodiment of the present invention. 1 is a schematic perspective view of a light-emitting element according to an embodiment of the present invention, viewed from a conductive member side; FIG. FIG. 4 is a schematic perspective view of a modification of the light-emitting device according to one embodiment of the present invention, viewed from the conductive member side. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic plan view which shows the manufacturing method of the light emitting element of one Embodiment of this invention. FIG. 35 is a schematic cross-sectional view taken along line XXXV-XXXV of FIG. 34; It is a schematic plan view which shows the manufacturing method of the light emitting element of one Embodiment of this invention. FIG. 37 is a schematic cross-sectional view taken along line XXXVII-XXXVII of FIG. 36; It is a schematic plan view which shows the manufacturing method of the light emitting element of one Embodiment of this invention. FIG. 39 is a schematic cross-sectional view taken along line XXXIX-XXXIX of FIG. 38; It is a schematic plan view which shows the manufacturing method of the light emitting element of one Embodiment of this invention. 41 is a schematic cross-sectional view along line XLI-XLI in FIG. 40; FIG. It is a schematic plan view which shows the manufacturing method of the light emitting element of one Embodiment of this invention. FIG. 43 is a schematic cross-sectional view taken along line XLIII-XLIII of FIG. 42;

Hereinafter, embodiments will be described with reference to the drawings. In addition, the same code|symbol is attached|subjected to the same structure in each drawing. As a cross-sectional view, an end view showing only the cut surface may be used.

A method for manufacturing a light-emitting device according to one embodiment of the present invention has a step of preparing a wafer W shown in FIG. The step of preparing the wafer W includes the step of forming the semiconductor stack 10 on the first substrate 101, as shown in FIG.

The semiconductor laminate 10 includes, for example, a nitride semiconductor such as In _x Al _y Ga _1-xy N (0≦x, 0≦y, x+y≦1). For the first substrate 101, for example, an insulating substrate such as sapphire or spinel (MgAl ₂ O ₄ ) having any one of the C-plane, R-plane, and A-plane as the main surface can be used. Also, as the first substrate 101, a conductive substrate such as SiC (including 6H, 4H, and 3C), ZnS, ZnO, GaAs, and Si may be used.

The semiconductor laminate 10 has a first semiconductor layer 11 , an active layer 13 provided on the first semiconductor layer 11 , and a second semiconductor layer 12 provided on the active layer 13 . In FIG. 1, the lower surface of the first semiconductor layer 11 is the first surface 10a of the semiconductor laminate 10, and the upper surface of the second semiconductor layer 12 is the second surface 10b of the semiconductor laminate 10. As shown in FIG. In this embodiment, the first semiconductor layer 11 is an n-side semiconductor layer, and the second semiconductor layer 12 is a p-side semiconductor layer. The active layer 13 is a light-emitting layer that emits light. The active layer 13 includes a plurality of barrier layers and a plurality of well layers, and can have a multiple quantum well structure in which the barrier layers and the well layers are alternately laminated.

For example, the first semiconductor layer 11, the active layer 13, and the second semiconductor layer 12 are sequentially formed on the first substrate 101 by MOCVD (Metal Organic Chemical Vapor Deposition). The step of preparing the wafer W may include the step of purchasing the first substrate 101 on which the semiconductor stack 10 is formed.

Also, a conductive current diffusion layer 15 may be formed on the second surface (upper surface of the second semiconductor layer 12) 10b of the semiconductor stack 10. FIG. The current diffusion layer 15 is formed by, for example, sputtering or vapor deposition. As a material of the current diffusion layer 15, for example, oxide films such as ITO (Indium Tin Oxide), AZO (Aluminum Zinc Oxide), IZO (Indium Zinc Oxide), and Ga ₂ O ₃ can be used. The current diffusion layer 15 diffuses current supplied through a second electrode, which will be described later, in the planar direction of the second semiconductor layer 12 .

Next, the steps shown in FIGS. 2 and 3 are performed.
FIG. 2 is a schematic plan view of the semiconductor laminate 10 on the second surface 10b side. FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG.

A portion of the current diffusion layer 15, a portion of the second semiconductor layer 12, and a portion of the active layer 13 are removed by, for example, RIE (Reactive Ion Etching), and a portion of the first semiconductor layer 11 is formed as a current diffusion layer. 15, the second semiconductor layer 12 and the active layer 13 are exposed. Gases for removing part of the second semiconductor layer 12 and part of the active layer 13 by RIE include, for example, Cl ₂ and SiCl ₄ . The exposed part of the first semiconductor layer 11 is used as the third surface 10 c of the semiconductor stacked body 10 . At the same time when the third surface 10c is formed, the convex portion 20 of the semiconductor stacked body 10 is formed. The protrusion 20 includes a first semiconductor layer 11 , an active layer 13 and a second semiconductor layer 12 .

In addition, part of the current diffusion layer 15 provided on the upper surface of the second semiconductor layer 12 (the second surface 10b of the semiconductor laminate 10) of the convex portion 20 is removed, and the upper surface of the second semiconductor layer 12 (the semiconductor laminate 10 is partially exposed from the current spreading layer 15 . As shown in FIG. 2, the current spreading layer 15 is divided into a plurality of portions separated from each other in plan view.

The semiconductor stack 10 includes a plurality of device regions 100 that are separated from each other. In FIG. 2, lines defining each element region 100 are represented by two-dot chain lines. FIG. 2 represents a portion including, for example, two device regions 100 .

Each device region 100 includes a portion of the first semiconductor layer 11 , a portion of the active layer 13 and a portion of the second semiconductor layer 12 . The current diffusion layer 15 is separated for each device region 100 . A region between adjacent element regions 100 is a region in which a groove is formed in a step to be described later. As shown in FIG. 2, the third surface 10c may be partially continuous from the element region 100 to a region where grooves are formed in a process described below.

Next, the steps shown in FIGS. 4 and 5 are performed.
FIG. 4 is a schematic plan view of the same region as in FIG. FIG. 5 is a schematic cross-sectional view taken along line VV of FIG.

A first electrode 31 is formed on the third surface 10 c that is part of the first semiconductor layer 11 included in the element region 100 . Also, the second electrode 32 is formed on the current diffusion layer 15 on the second surface 10b, which is part of the second semiconductor layer 12 included in the element region 100. Next, as shown in FIG. The first electrode 31 and the second electrode 32 are formed by sputtering or vapor deposition, for example. Alternatively, only the current diffusion layer 15 may be used as the second electrode.

The first electrode 31 and the second electrode 32 are, for example, a single metal layer containing Ti, Rh, Au, Pt, Al, Ag, Rh or Ru, or a laminated structure containing at least two of these metal layers. is.

Through the steps up to this point, the wafer W having the first substrate 101, the semiconductor laminate 10, the current diffusion layer 15, the first electrode 31, and the second electrode 32 is prepared.

Next, the steps shown in FIGS. 6 and 7 are performed.
FIG. 6 is a schematic plan view of the same region as in FIG. 7 is a schematic cross-sectional view taken along line VII-VII of FIG. 6. FIG.

A first reflective layer 40 is formed on the upper surface of the wafer W shown in FIG. The first reflective layer 40 is formed continuously on the semiconductor laminate 10 of the plurality of element regions 100 and on the semiconductor laminate 10 located between the adjacent element regions 100 among the plurality of element regions 100 . be. The first reflective layer 40 covers the upper surface and side surfaces of the convex portion 20 . The first reflective layer 40 covers the third surface 10c. Also, the first reflective layer 40 covers the top surface and side surfaces of the current diffusion layer 15 . The first reflective layer 40 is continuously formed on the first electrode 31 and the second electrode 32 . The first reflective layer 40 covers the top surface of the first electrode 31 , the side surfaces of the first electrode 31 , the top surface of the second electrode 32 , and the side surfaces of the second electrode 32 .

The first reflective layer 40 has reflectivity for light from the active layer 13 . The first reflective layer 40 includes, for example, a dielectric multilayer film. The dielectric multilayer film includes, for example, alternately stacked SiO ₂ layers and Nb ₂ O ₅ layers. For the first reflective layer 40, for example, after forming a relatively thick SiO ₂ layer of 100 nm or more and 500 nm or less, a dielectric multilayer film is formed thereon by forming a Nb 2 O 5 layer of 10 nm or more and 100 nm or less and a Nb ₂ O ₅ layer of 10 nm or more and 100 nm or less. It is preferable to form pairs of SiO ₂ layers in the number of pairs of 2 or more and 6 or less. By setting the thickness of each layer of the first reflective layer 40 and the number of laminations of each layer in this way, it is possible to achieve good light reflectivity. For example, the first reflective layer 40 can be formed by forming a 300 nm SiO ₂ layer and then forming three pairs of 52 nm Nb ₂ O ₅ layers and 83 nm SiO ₂ layers thereon. Materials such as titanium oxide (TiO ₂ ), zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), and aluminum nitride (AlN) can also be used as the first reflective layer 40 . The first reflective layer 40 is formed by, for example, a CVD (Chemical Vapor Deposition) method or a sputtering method.

Next, the steps shown in FIGS. 8 and 9 are performed.
FIG. 8 is a schematic plan view of the same region as in FIG. 9 is a schematic cross-sectional view taken along line IX-IX of FIG. 8. FIG.

A plurality of first masks 91 are formed to cover the first reflective layer 40 located above the plurality of device regions 100 of the semiconductor stack 10 . As shown in FIG. 8, the plurality of first masks 91 are separated from each other in plan view. A region where the first mask 91 is formed substantially coincides with the device region 100 . The first reflective layer 40 positioned between adjacent element regions 100 (first mask 91 ) is exposed through the first mask 91 . The first mask 91 is, for example, a resist mask.

Next, the steps shown in FIGS. 10 and 11 are performed.
FIG. 10 is a schematic plan view of the same region as in FIG. 11 is a schematic cross-sectional view taken along line XI-XI of FIG. 10. FIG.

A part of the first reflective layer 40 and the semiconductor stacked body 10 in the region between the adjacent first masks 91 formed in the above-described process is removed so that the first semiconductor layer 11 is exposed. As a result, grooves 80 are formed in the semiconductor laminate 10 positioned between adjacent element regions 100 among the plurality of element regions 100 .

The trench 80 surrounds the device region 100 . As shown in FIG. 11 , the groove 80 may be formed so as not to penetrate the semiconductor stack 10 and reach the first substrate 101 .

In the step of forming the groove 80, the first reflective layer 40 and part of the semiconductor stack 10 are removed by, for example, RIE. The step of forming the grooves 80 by the RIE method includes a step of removing the first reflective layer 40 in the region between the first masks 91 by first etching using a fluorine-containing first gas; and removing part of the semiconductor stack 10 in the region between the first masks 91 by a second etching using two gases. The first gas includes CF ₄ and CHF ₃ , for example. The second gas contains, for example, Cl ₂ and SiCl ₄ .

As shown in FIG. 9, the semiconductor laminate 10 in the region between the adjacent first masks 91 includes a first portion 10-1 including the first semiconductor layer 11, the active layer 13, and the second semiconductor layer 12, and a first portion 10-1. and a second portion 10 - 2 of only one semiconductor layer 11 . There is a step between the first portion 10-1 and the second portion 10-2. Therefore, a step as shown in FIG. 11 is formed on the bottom surface defining the groove 80 formed by the RIE. In the groove 80, the depth of the second region 80b formed by etching the second portion 10-2 is deeper than the depth of the first region 80a formed by etching the first portion 10-1. The difference in depth between the first region 80a and the second region 80b is, for example, 0.5 μm or more and 5 μm or less.

In the semiconductor stacked body 10, the thickness of the portion between the bottom surface (the bottom surface of the first region 80a and the bottom surface of the second region 80b) defining the trench 80 and the first surface 10a is the same as the thickness of the third surface 10c and the thickness of the first surface 10c. It is thinner than the thickness of the portion between the surface 10a and the thickness of the portion between the second surface 10b and the first surface 10a.

Note that the groove 80 may be formed so as to penetrate the semiconductor laminate 10 and reach the first substrate 101 . Also in this case, the first semiconductor layer 11 is exposed on the side surfaces of the trench 80 .

Next, the steps shown in FIGS. 12 and 13 are performed.
FIG. 12 is a schematic plan view of one device region 100 out of the two device regions 100 shown in FIG. 2 and the like. One element region is also shown in subsequent steps. 13 is a schematic cross-sectional view taken along line XIII-XIII of FIG. 12. FIG.

A second reflective layer 50 is formed on the first reflective layer 40 . A detailed method of forming the second reflective layer 50 will be described later. The second reflective layer 50 is, for example, a metal layer. The second reflective layer 50 includes, for example, an Al layer, a Ti layer, or a laminated structure of these.

Next, the steps shown in FIG. 14 are performed.

A first opening 41 exposing a portion of the first electrode 31 and a second opening 42 exposing a portion of the second electrode 32 are formed in the first reflective layer 40 . The first opening 41 and the second opening 42 are formed simultaneously by, for example, the RIE method. The first opening 41 has, for example, a shape similar to that of the first electrode 31 in plan view. The second opening 42 has, for example, a shape similar to that of the second electrode 32 in plan view. The size of the first opening 41 is smaller than that of the first electrode 31 in plan view, and the size of the second opening 42 is smaller than that of the second electrode 32 in plan view. As will be described later, the first opening 41 and the second opening 42 may be formed in two stages.

Next, the steps shown in FIG. 15 are performed.

An insulating layer 61 is formed to cover the first reflective layer 40 and the second reflective layer 50 . The insulating layer 61 is formed on the side surface of the first reflective layer 40 that defines the first opening 41, the side surface of the first reflective layer 40 that defines the second opening 42, and the side surface of the semiconductor stack 10 that defines the groove 80. cover the The insulating layer 61 is, for example, an SiO2 layer. The exposed portion of the semiconductor laminate 10 is covered and protected by the insulating layer 61 . The insulating layer 61 is formed by, for example, a sputtering method, a CVD method, or the like.

Next, the steps shown in FIGS. 16 and 17 are performed.
16 is a schematic plan view of the same region as in FIG. 12. FIG. 17 is a schematic cross-sectional view taken along line XVII-XVII of FIG. 16. FIG.

A first conductive member 71 is formed in the first opening 41 and a second conductive member 72 is formed in the second opening 42 . The first conductive member 71 contacts the first electrode 31 . The second conductive member 72 contacts the second electrode 32 . The first conductive member 71 is also formed on the insulating layer 61 around the first opening 41 . The second conductive member 72 is also formed on the insulating layer 61 around the second opening 42 . The first conductive member 71 and the second conductive member 72 are separated from each other on the insulating layer 61 . The thickness of the first conductive member 71 and the second conductive member 72 is, for example, 0.1 μm or more and 5 μm or less. In plan view, the shape of the first conductive member 71 and the second conductive member 72 is, for example, substantially rectangular, and the length of the long side is 10 μm or more and 100 μm or less. For example, the first conductive member 71 is the cathode electrode and the second conductive member 72 is the anode electrode.

The first conductive member 71 and the second conductive member 72 are simultaneously formed by, for example, a sputtering method. The first conductive member 71 and the second conductive member 72 include, for example, a Ti layer, a Rh layer, an Au layer, or a laminated structure of any two of these.

Even if the first reflective layer 40 contains a conductive material (for example, Nb ₂ O ₅ ), the first reflective layer 40 and the first conductive member 71 and the first reflective layer 40 and the second Since the insulating layer 61 is provided between the conductive member 72 and the first conductive member 71 , a short circuit between the first conductive member 71 and the second conductive member 72 through the first reflective layer 40 can be prevented.

Moreover, even if the second reflective layer 50 is a metal layer, the insulating layer 61 is provided between the second reflective layer 50 and the first conductive member 71 and between the second reflective layer 50 and the second conductive member 72 . is provided, it is possible to prevent a short circuit between the first conductive member 71 and the second conductive member 72 through the second reflective layer 50 .

Thereafter, the steps shown in FIGS. 18-24A are continued. In FIGS. 18 to 24A, the top and bottom positions of the semiconductor stack 10 are reversed from the figures up to FIG.

In the process shown in FIG. 18 , the semiconductor laminate 10 and the second substrate 102 are joined with the resin member 70 interposed therebetween. The resin member 70 covers the first conductive member 71 , the second conductive member 72 and the insulating layer 61 and is also provided inside the groove 80 . The resin member 70 is mainly made of epoxy resin, acrylic resin, or polyimide resin, for example. For the second substrate 102, for example, a substrate such as sapphire, spinel, SiC, ZnS, ZnO, GaAs, and Si can be used like the first substrate 101.

After bonding the semiconductor laminate 10 and the second substrate 102, the first substrate 101 is removed, and as shown in FIG. expose. The first substrate 101 used for growing the semiconductor stack 10 is removed by LLO (Laser Lift Off), grinding, polishing, etching, or the like. In this embodiment, since the first substrate 101 is a sapphire substrate, it is preferably removed by the LLO method.

The first surface 10a contains, for example, GaN, and the laser light used for LLO is, for example, deep ultraviolet light. The first substrate 101 is separated from the first surface 10a by the sublimation of Ga in GaN due to the laser beam irradiation. At this time, by leaving a part of the semiconductor stacked body 10 between the bottom surface of the groove 80 and the first substrate 101 in the step of forming the groove 80 shown in FIG. There is a first surface 10a. This facilitates peeling of the first substrate 101 by the LLO method.

Next, the exposed first surface 10a is polished, for example, by CMP (Chemical Mechanical Polishing). In this polishing, for example, the first surface 10a has a maximum height difference of about 1 nm or more and 30 nm or less. As shown in FIG. 20, the first surface 10a is polished so that the semiconductor laminate 10 located in the groove 80 disappears. By removing the semiconductor laminate 10 located in the groove 80 , the semiconductor laminate 10 is singulated into a plurality of element portions 200 .

After separating the semiconductor laminate 10 into individual pieces, as shown in FIG. 21, a first protective film 62 is formed to cover the outer peripheral portion of the first surface 10a. The first protective film 62 also covers the end portion of the insulating layer 61 covering the side surface of the first semiconductor layer 11 on the side of the first surface 10a. The first protective film 62 has transparency to light from the active layer 13 . The first protective film 62 is, for example, a silicon oxide film. After the first protective film 62 is formed on the entire surface of the first surface 10a by, for example, sputtering, the first protective film 62 other than the outer peripheral portion of the first surface 10a is removed by RIE using a resist mask (not shown). be. Here, the "peripheral portion of the first surface 10a" means, for example, a region of the first surface 10a within 10 μm from the edge of the first surface 10a in plan view, and preferably 5 μm or less.

After forming the first protective film 62, as shown in FIG. 22, the first surface 10a exposed from the first protective film 62 is roughened to form a rough surface including irregularities on the first surface 10a. By forming a rough surface on the first surface 10a, which is the main light extraction surface of the light emitting element, the light extraction efficiency of the light emitting element can be improved. The light extraction efficiency of the light emitting element can be improved by setting the maximum height difference of the unevenness of the first surface 10a to, for example, about 1 μm or more and 3 μm or less. For example, the first surface 10a is roughened by RIE using a chlorine-containing gas or wet etching using an alkaline solution such as TMAH (Tetramethylammonium hydroxide).

When the entire surface of the first surface 10a is roughened, chipping of the first semiconductor layer 11 is likely to occur in the outer peripheral portion of the first surface 10a. In the present embodiment, since the end portion of the first surface 10a continuing to the side surface of the first semiconductor layer 11 is covered with the first protective film 62, the outer peripheral portion of the first semiconductor layer 11 on the first surface 10a, Non-roughened regions can be formed. As a result, chipping of the first semiconductor layer 11 can be suppressed in the outer peripheral portion of the first surface 10a. Note that the first surface 10a was left on the first protective film 62 in the outer peripheral portion of the first surface 10a with the resist mask used when removing the first protective film 62 other than the outer peripheral portion of the first surface 10a. Preferably, 10a is roughened. As a result, it is possible to reliably form a non-roughened region in the outer peripheral portion of the first semiconductor layer 11 on the first surface 10a.

As shown in FIG. 23, a second protective film 63 is formed on the roughened first surface 10a. The second protective film 63 may be formed on the first protective film 62 . The second protective film 63 has transparency to light from the active layer 13 . The second protective film 63 is, for example, an SiO2 layer. The second protective film 63 is formed by sputtering, for example. The thickness of the second protective film 63 is, for example, 0.1 μm or more and 3 μm or less. The insulating layer 61 covering the side surface of the first semiconductor layer 11 also has transparency to light from the active layer 13 .

After forming the second protective film 63, a part of the resin member 70 positioned between the individualized element portions 200 is removed by etching. Thereby, as shown in FIG. 24A, a plurality of light emitting elements 1 separated from each other with spaces on the second substrate 102 are obtained. 24B is a schematic bottom view of the light emitting element 1. FIG.

Each light emitting element 1 is supported on the second substrate 102 via the resin member 70 with the surface opposite to the first surface 10 a facing the second substrate 102 . For example, by irradiating laser light from the second substrate 102 side, the resin member 70 is partially removed, and the light emitting element 1 can be removed from the second substrate 102 . The light-emitting element 1 removed from the second substrate 102 is bonded to another support substrate with adhesive on the surface on the side of the second protective film 63 . The light emitting device 1 may be removed from the second substrate 102 after being bonded to another supporting substrate. After that, the resin member 70 remaining on the light emitting element 1 is removed to expose the first conductive member 71 and the second conductive member 72 . The resin member 70 remaining on the light emitting element 1 can be removed by, for example, the RIE method. The exposed first conductive member 71 and second conductive member 72 function as external connection terminals that are joined to the mounting board. The light emitting element 1 is a light emitting diode (Light Emitting Diode).

According to the light-emitting device 1 of this embodiment, light from the active layer 13 is mainly extracted to the outside from the first surface 10a. Furthermore, the light from the active layer 13 is extracted to the outside from the side surface 11a of the first semiconductor layer 11 as well. According to this embodiment, the first reflective layer 40 is provided on the surface opposite to the first surface 10a, and no reflective layer is provided on the side surface 11a. can be higher. It should be noted that as the size of the light emitting element 1 becomes smaller, the proportion of light extracted from the side surface 11a becomes larger. Therefore, the structure in which no reflective layer is provided on the side surface 11a is highly effective when the size of one side of the light emitting element 1 is 100 μm or less, and is even more effective when the size of one side of the light emitting element 1 is 60 μm or less.

By forming a dielectric multilayer film as the first reflective layer 40, it is possible to lower the light absorption rate and increase the reflectance compared to a metal layer. Further, by further providing the second reflective layer 50 on the side opposite to the first surface 10a, the reflectance can be further increased.

In forming the structure in which the reflective layer is provided on the surface opposite to the first surface 10a and the reflective layer is not provided on the side surface 11a, the following steps are considered as a first comparative example.

(First comparative example)
A plurality of element regions 100 of the semiconductor stack 10 are separated from each other by trenches 80 . The side surface of the semiconductor stack 10 (first semiconductor layer 11 ) is exposed in the groove 80 . After that, a resist mask is formed to cover the portion (including the side surface of the first semiconductor layer 11) other than the surface opposite to the first surface (light extraction surface) 10a of the element region 100, and the resist mask is formed by a CVD method, a sputtering method, or the like. forming a reflective layer; The surface of the element region 100 opposite to the first surface 10a is exposed through the opening of the resist mask. The reflective layer is formed on the surface opposite to the first surface 10a of the element region 100 through the openings of the resist mask. Furthermore, a reflective layer is also formed on the resist mask. Then, by lifting off the resist mask, a structure in which a reflective layer is formed on the surface opposite to the first surface 10a of the element region 100 and no reflective layer is formed on the side surface of the first semiconductor layer 11 is obtained.

When the reflective layer is formed by the method of the first comparative example, the stepped or tapered shape of the side surface of the opening of the resist mask makes it difficult for the material of the reflective layer to reach the portion near the side surface of the opening. There is a concern that the reflective layer may become thin in a portion near the side surface of the . If the thickness of the edge portion of the reflective layer becomes thin, the reflectance at the edge portion will decrease.

According to this embodiment, as shown in FIG. 7, the first reflective layer 40 is formed on the entire surface opposite to the first surface 10a without using a mask. Therefore, it is possible to prevent the thickness of the first reflective layer 40 from being thin at the portion near the side surface of the opening of the mask as in the first comparative example. That is, it is possible to prevent the edge of the first reflective layer 40 on each element region 100 shown in FIG. 11 from becoming thin and the reflectance of the edge from decreasing. In addition, since the first reflective layer 40 exposed from the first mask 91 is etched and removed by anisotropic RIE, side etching of the first reflective layer 40 covered with the first mask 91 can be suppressed. 1 It is possible to suppress thinning of the end portion of the reflective layer 40 .

(Second comparative example)
As a second comparative example of a method of forming a structure in which a reflective layer is provided on the surface opposite to the first surface 10a and no reflective layer is provided on the side surface of the first semiconductor layer 11, the semiconductor laminate 10 After the plurality of element regions 100 are separated from each other by grooves 80, a reflective layer is formed on the entire surface of the first semiconductor layer 11 including the side surfaces. Then, a method of forming a mask covering the surface opposite to the first surface 10a of the element region 100 and etching and removing the reflective layer formed on the side surface of the first semiconductor layer 11 can be considered. In the method of the second comparative example, it is difficult to remove the reflective layer on the side surface of the first semiconductor layer 11 . In other words, it is highly difficult to remove the reflective layer formed on a relatively large step like the groove 80 .

According to the present embodiment, the first reflective layer 40 is formed in a state before forming the grooves 80 separating the element regions 100, that is, in a state where the semiconductor stacked body 10 does not have a large step, and the etching for forming the grooves 80 is performed. , the first reflective layer 40 is removed. As shown in FIG. 9, the first reflective layer 40 is removed by anisotropic etching such as RIE on the exposed portion of the first reflective layer 40 from the first mask 91 in a state where there is no large step. Can be easily removed.

In the process of FIG. 2, it is preferable that the third surface 10c is formed outside the element region (the region inside the two-dot chain line) 100 . By doing so, after the groove 80 is formed outside the element region 100, the second semiconductor layer 12 having a small width (width in the horizontal direction in FIG. 2) and the active layer 12 are formed between the groove 80 and the third surface 10c. It is possible to prevent the laminated portion of the layer 13 from remaining. As a result, it is possible to suppress chipping of such a small-width stacked portion during the manufacturing process of the light-emitting element.

According to the present embodiment, as shown in FIG. 2, the third surface 10c is also formed outside the element region 100, thereby securing a sufficient area for arranging the first electrode 31 and allowing light emission. The device manufacturing process can be stabilized.

FIG. 26A is a schematic perspective view of the light-emitting element 1 viewed from the conductive members 71 and 72 side.

In the side surface 11a of the semiconductor laminate 10, the side surface continuous with the third surface 10c is a side surface 11b recessed inwardly from the side surface continuous with the second surface 10b. The recessed side surface 11b is a surface continuous with the second region 80b of the groove 80 shown in FIG. The recessed side surface 11b is continuous from the third surface 10c to the first surface 10a (the surface facing downward in FIG. 26A).

Further, as shown in FIG. 26B, the recessed side surface 11b does not have to be continuous to the first surface 10a. In other words, the recessed side surface 11b may be spaced apart from the first surface 10a. Since the recessed side surface 11b is separated from the first surface 10a, the area of the first surface 10a can be increased. For example, the length of the recessed side surface 11b in the direction from the third surface 10c to the first surface 10a is 50% or less of the length in the direction from the third surface 10c to the first surface 10a of the side surface 11a.

25A and 25B are schematic bottom views of modifications of the light-emitting element of the embodiment.

The light emitting element shown in FIG. 25A and the light emitting element shown in FIG. 24B described above have the same area of the lower surface (the surface on which the conductive members 71 and 72 are arranged). In the light emitting element shown in FIG. 25A, the length of extension of the third surface 10c toward the center of the light emitting element is shorter than in the light emitting element shown in FIG. 24B, and the area of the third surface 10c is smaller. Therefore, in the light-emitting element shown in FIG. 25A, the area of the active layer 13 emitting light is larger than that in the light-emitting element shown in FIG. 24B. In the light-emitting element shown in FIG. 25A, as the length of extension of the third surface 10c becomes shorter, the first electrode 31 arranged on the third surface 10c is arranged closer to the second electrode 32 than the light-emitting element shown in FIG. 24B. is located near the end (the right end in FIG. 25A) in the direction away from the . The second electrode 32 is arranged closer to the end (the left end in FIG. 25A) in the direction away from the first electrode 31 than the light emitting element shown in FIG. 24B. In the light emitting element shown in FIG. 25A, the distance between the first electrode 31 and the second electrode 32 is longer than that in the light emitting element shown in FIG. 24B within the same lower surface area. As a result, in the light-emitting element shown in FIG. 25A, concentration of current distribution density can be suppressed more than in the light-emitting element shown in FIG. 24B. Further, by bringing the first electrode 31 and the second electrode 32 closer to the edge, in the light emitting element shown in FIG. 25A, the area of the second reflective layer 50 can be made larger than in the light emitting element shown in FIG. 24B. can do better.

Further, as in the light emitting device shown in FIG. 25B, the planar shapes of the first electrode 31, the opening of the first reflective layer 40, the opening of the insulating layer 61, and the like may be substantially rectangular. 25B, the second electrode 32 is not provided, and only the current diffusion layer 15 is provided as an electrode connected to the second semiconductor layer 12. As shown in FIG. The current spreading layer 15 is in contact with the second semiconductor layer 12 and the second conductive member 72 .

Next, a detailed method for forming the second reflective layer 50 in the method for manufacturing the light emitting device of this embodiment will be described.

27 to 30 are schematic cross-sectional views showing a first example of the method of forming the second reflective layer 50. FIG.

The step of forming the second reflective layer 50 includes forming a second mask 92 covering the grooves 80 as shown in FIG. 27 after forming the grooves 80 by the steps up to FIG. The second mask 92 is also formed on the portions of the first reflective layer 40 where the openings above the electrodes 31 and 32 are to be formed. The second mask 92 is, for example, a resist mask.

Then, the second reflective layer 50 is formed on the first reflective layer 40 exposed from the second mask 92 . The second reflective layer 50 is also formed on the second mask 92 . The second reflective layer 50 is formed by, for example, sputtering.

After forming the second reflective layer 50, the second mask 92 is removed. As shown in FIG. 28, the second reflective layer 50 remains on the exposed portion (above the element region 100) from the second mask 92, and the second reflective layer 50 on the second mask 92 is removed. Here, when the unnecessary portion of the second reflective layer 50 is removed by the RIE method, there is a concern that the remaining end portion of the second reflective layer 50 may be corroded by being exposed to the RIE gas. According to the first example, it is possible to suppress the decrease in reflectance due to the RIE gas corroding the remaining end of the second reflective layer 50 .

After removing the second mask 92, the portion of the first reflective layer 40 that forms the first opening above the first electrode 31 is etched to form the first recess 41a. The bottom surface of the first recess 41 a does not reach the first electrode 31 . Also, a portion of the first reflective layer 40 on which the second electrode 32 is to be formed is etched to form a second concave portion 42a. The bottom surface of the second recess 42 a does not reach the second electrode 32 . The first concave portion 41a and the second concave portion 42a are formed at the same time, for example, by the RIE method.

Thereafter, as shown in FIG. 29, an insulating layer 61 covering the grooves 80, the first reflective layer 40, and the second reflective layer 50 is formed.

After forming the insulating layer 61, the insulating layer 61 on the first electrode 31 is removed, and further the first reflective layer 40 on the first electrode 31 is removed. Thereby, as shown in FIG. 30, a first opening 41 reaching the first electrode 31 is formed in the first reflective layer 40 . A portion of the first electrode 31 is exposed from the first reflective layer 40 and the insulating layer 61 . Also, the insulating layer 61 on the second electrode 32 is removed, and the first reflective layer 40 on the second electrode 32 is removed. Thereby, a second opening 42 reaching the second electrode 32 is formed in the first reflective layer 40 . A portion of the second electrode 32 is exposed from the first reflective layer 40 and the insulating layer 61 . The first opening 41 and the second opening 42 are formed simultaneously by, for example, the RIE method.

After forming the openings 41, 42, the above-described steps after FIG.

According to the method shown in FIGS. 27 to 30, the process of forming the openings 41 and 42 in the first reflective layer 40 is divided into two steps. That is, the process of forming the openings 42, 42 includes a first process of forming the recesses 41a, 42a of the first reflective layer 40 and a second process of removing the first reflective layer 40 remaining below the recesses 41a, 42a. and a step.

According to such a method, the electrodes 31 and 32 are exposed from the first reflective layer 40 after the insulating layer 61 is formed. Therefore, the conductive material of the electrodes 31 and 32 is etched and scattered during RIE, and the conductive member (for example, Nb ₂ O ₅ ) included in the first reflective layer 40 and the second reflective layer 50 which is a metal layer are damaged. can be suppressed from adhering to As a result, short circuits between the electrodes 31 and 32 through the first reflective layer 40 and the second reflective layer 50 can be suppressed.

Also, before forming the insulating layer 61, the first reflective layer 40 is etched to be thin in the first step. As a result, the thickness of the side surfaces adjacent to the openings 41 and 42 of the first reflective layer 40 which are not covered with the insulating layer 61 and which are formed in the second step can be reduced. That is, the amount of the electrode material adhering to the side surfaces adjacent to the openings 41 and 42 of the first reflective layer 40 can be reduced. At this time, it is preferable that the members of the first reflective layer 40 that are in contact with the electrodes 31 and 32 are made of members with relatively high insulating properties and have a relatively large thickness of 100 nm or more and 500 nm or less. As a result, the first reflective layer 40 exposed at the bottoms of the recesses 41a and 42a can be easily made of a member having relatively high insulation. As a result, the side surfaces of the dielectric multilayer film on the relatively thick and highly insulating member included in the first reflective layer 40 in the concave portions 41 a and 42 a can be easily covered with the insulating layer 61 . As a result, when the electrodes 31 and 32 are exposed from the first reflective layer 40, the conductive material of the electrodes 31 and 32 is etched and scattered during the RIE, and the conductive members included in the first reflective layer 40 ( For example, Nb ₂ O ₅ ) and the second reflective layer 50, which is a metal layer, can be suppressed from adhering to the metal layer, thereby further suppressing a short circuit between the electrodes 31 and 32 . Here, the member having relatively high insulating properties refers to, for example, SiO ₂ or SiON.

31 to 33 and 35 are schematic cross-sectional views showing a second example of the method of forming the second reflective layer 50. FIG.

After forming the first reflective layer 40 in the process shown in FIG. 7 described above, and before forming the grooves 80, the second reflective layer 50 is continuously formed on the first reflective layer 40 as shown in FIG. . The second reflective layer 50 is formed on the entire surface of the element region 100 and the first reflective layer 40 between the element regions 100 .

Then, a third mask 93 is formed to partially cover the second reflective layer 50 located on each element region 100 . The third mask 93 is not formed on the portions of the first reflective layer 40 where the openings above the electrodes 31 and 32 are to be formed. The third mask 93 is, for example, a resist mask.

Then, the second reflective layer 50 in the region between the third masks 93 (the region exposed from the third mask 93) is removed by RIE. As shown in FIG. 32, the second reflective layer 50 is left on part of the first reflective layer 40 in the device region 100 .

Also in this second example, the process of forming the openings 41 and 42 in the first reflective layer 40 is divided into two steps, as in the first example. Therefore, after removing the second reflective layer 50 on the electrodes 31 and 32 by RIE using the third mask 93, the first reflective layer 40 on the electrodes 31 and 32 is also thickened by RIE using the third mask 93. Etch halfway in the vertical direction. Thereby, the first recess 41 a and the second recess 42 a are formed in the first reflective layer 40 .

According to this second example, after the second reflective layer 50 is formed on the first reflective layer 40 , unnecessary portions of the second reflective layer 50 are removed by the RIE method using the third mask 93 . Therefore, the remaining second reflective layer 50 can be accurately formed up to the end portion.

Thereafter, as shown in FIG. 33, a first mask 91 is formed to cover the second reflective layer 50 and the first reflective layer 40 on each element region 100 . Then, the first reflective layer 40 and the semiconductor stacked body 10 exposed from the first mask 91 are removed by the RIE method. Thereby, as shown in FIGS. 34 and 35, grooves 80 are formed in the semiconductor laminate 10 . 34 is a schematic plan view of the same region as in FIG. 12, and FIG. 35 is a schematic cross-sectional view taken along line XXXV-XXXV of FIG.

Note that the third mask 93 used in the previous step may be left unremoved during the RIE for forming the grooves 80 . That is, the first mask 91 is formed to cover the third mask 93 . However, the surface of the third mask 93 is damaged during the etching for partially removing the second reflective layer 50, and there is a possibility that the formation of the first mask 91 on the third mask 93 will not be successful. Therefore, it is preferable to form the first mask 91 after removing the third mask 93 .

Thereafter, the step of forming the insulating layer 61 shown in FIG. 29 and the step of forming the first opening 41 and the second opening 42 shown in FIG. 30 are continued. Furthermore, the steps after FIG. 16 are continued.

In the steps shown in FIGS. 4, 6, 8 and 10 described above, two device regions 100 are shown. In contrast, FIGS. 36, 38, 40 and 42 show four device regions 100. FIG. FIG. 36 is a schematic plan view showing the same steps as in FIG. 37 is a schematic cross-sectional view taken along line XXXVII-XXXVII of FIG. 36. FIG. FIG. 38 is a schematic plan view showing the same steps as in FIG. 39 is a schematic cross-sectional view taken along line XXXIX-XXXIX of FIG. 38. FIG. FIG. 40 is a schematic plan view showing the same steps as in FIG. 41 is a schematic cross-sectional view along line XLI-XLI in FIG. 40. FIG. FIG. 42 is a schematic plan view showing the same steps as in FIG. 43 is a schematic cross-sectional view taken along line XLIII-XLIII of FIG. 42. FIG.

As shown in FIG. 5 described above, part of the second semiconductor layer 12 and part of the active layer 13 are removed from the second semiconductor layer 12 side, and the first semiconductor layer 11 is removed in each of the plurality of element regions 100 . A part of the third surface 10 c is exposed from the second semiconductor layer 12 and the active layer 13 .

In the wafer before forming the first reflective layer 40, as shown in FIGS. 4 and 36, the third surface 10c, which is part of the first semiconductor layer 11, is exposed because the first electrode 31 is arranged. area. In the wafer before forming the first reflective layer 40, the second surface 10b, which is the upper surface of the second semiconductor layer 12, is exposed on the upper surface of the semiconductor stack 10 other than the third surface 10c.

After the steps shown in FIGS. 4, 5, 36 and 37, the process proceeds to the step of forming the first reflective layer 40 as shown in FIGS. 6, 7, 38 and 39. FIG.

The first reflective layer 40 includes exposed portions (second surface 10b) of the second semiconductor layer 12 in the plurality of device regions 100 and exposed portions (third surface 10c) of the first semiconductor layer 11 in the plurality of device regions 100. , and the exposed portion (second surface 10 b ) of the second semiconductor layer 12 located between adjacent element regions 100 among the plurality of element regions 100 .

A side surface of the active layer 13 exposed when a part of the second semiconductor layer 12 and a part of the active layer 13 are removed from the second semiconductor layer 12 side to form the third surface 10c is as shown in FIG. It is covered with the first reflective layer 40 . As shown in FIG. 39, the side surfaces of the active layer 13 are not exposed and are not covered with the first reflective layer 40 in the regions where the third surface 10c is not formed.

After the steps shown in FIGS. 6, 7, 38 and 39, the step of forming the first mask 91 is performed as shown in FIGS. 8, 9, 40 and 41. FIG.

A first mask 91 covers the first reflective layer 40 located above the plurality of device regions 100 . A plurality of first masks 91 are arranged apart from each other in plan view. A region where the first mask 91 covers the first reflective layer 40 substantially coincides with the device region 100 . The first reflective layer 40 positioned between adjacent element regions 100 (first mask 91 ) is exposed through the first mask 91 .

After the steps shown in FIGS. 8, 9, 40 and 41, the process proceeds to form grooves 80 as shown in FIGS. 10, 11, 42 and 43. FIG.

The first reflective layer 40, the second semiconductor layer 12, and the active layer 13 in the region between the adjacent first masks 91 among the plurality of first masks 91 are removed so that the first semiconductor layer 11 is exposed. . As a result, grooves 80 are formed in the semiconductor laminate 10 positioned between adjacent element regions 100 among the plurality of element regions 100 .

As shown in FIGS. 11 and 43, the formation of the trench 80 exposes the side surface of the active layer 13 from the semiconductor stack 10. As shown in FIGS. Therefore, according to the embodiment, the first reflective layer 40 is arranged on the side of the second surface 10b and the side of the third surface 10c opposite to the first surface 10a, which is the main light extraction surface. Since a light-emitting element in which the first reflective layer 40 is not arranged on substantially the entire surface of the light-emitting element can be formed, the light extraction efficiency from the light-emitting element to the outside can be increased. As will be described later, a first reflective layer 40 is formed on part of the side surface of the active layer 13 .

As described above, according to the method for manufacturing the light emitting device 1 of the embodiment, the light emitting device 1 shown in FIG. 24A is obtained. A light emitting device 1 includes a semiconductor laminate 10 . As shown in FIG. 3, the semiconductor stack 10 has a first semiconductor layer 11, a second semiconductor layer 12, and an active layer 13 positioned between the first semiconductor layer 11 and the second semiconductor layer 12. . In addition, the semiconductor laminate 10 is located on the opposite side of the first surface 10a from the first surface 10a, and the second surface 10b where the second semiconductor layer 12 is exposed from the semiconductor laminate 10 is opposite to the first surface 10a. A third surface 10 c located on the side of the semiconductor layer 11 and a portion of the first semiconductor layer 11 exposed from the second semiconductor layer 12 and the active layer 13 . In addition, as shown in FIG. 24A, the semiconductor laminate 10 has a side surface 11a connecting the first surface 10a and the second surface and connecting the first surface 10a and the third surface.

The light emitting element 1 covers the first electrode 31 electrically connected to the third surface 10c, the second electrode 32 electrically connected to the second surface 10b, and the second surface 10b and the third surface 10c. and a first reflective layer 40 not disposed on 11a. That is, the side surface of the active layer 13 positioned on the side surface 11 a of the semiconductor stack 10 is exposed from the first reflective layer 40 . Further, as shown in FIGS. 11, 24A, etc., the side surface of the active layer 13 located on the surface connecting the second surface 10b and the third surface 10c is covered with the first reflective layer 40. FIG. The side surface of the active layer 13 located on the surface connecting the second surface 10b and the third surface 10c is covered with the first reflective layer 40, and the side surface 11a of the semiconductor stacked body 10, which is most of the side surface of the active layer 13, is covered with the first reflective layer 40. is exposed from the first reflective layer 40 .

The first reflective layer 40 has an edge including an edge connected to the side surface 11 a of the semiconductor stack 10 . The end portion of the first reflective layer 40 is within a range of, for example, 0.6 μm from the end surface connected to the side surface 11 a of the semiconductor stacked body 10 .

According to the embodiment, as described above, since the first reflective layer 40 is formed on the entire surface on the side opposite to the first surface 10a without using a mask, the first reflective layer 40 other than the end portion is formed. The film thicknesses of the portions can be made substantially the same. As a result, a decrease in reflectance due to thinning of the first reflective layer 40 can be suppressed. The film thickness of the first reflective layer 40 represents the thickness in the direction perpendicular to the surface of the member with which the first reflective layer 40 is in contact. In addition, the term "substantially the same film thickness" includes the case where the difference in film thickness is within a range of 10 nm.

The embodiments of the present invention have been described above with reference to specific examples. However, the invention is not limited to these specific examples. Based on the above-described embodiment of the present invention, all forms that can be implemented by those skilled in the art by appropriately designing and changing are also included in the scope of the present invention as long as they include the gist of the present invention. In addition, within the scope of the idea of the present invention, those skilled in the art can conceive of various modifications and modifications, and these modifications and modifications also belong to the scope of the present invention.

DESCRIPTION OF SYMBOLS 1... Light emitting element 10... Semiconductor laminated body 11... First semiconductor layer 12... Second semiconductor layer 13... Active layer 15... Current spreading layer 31... First electrode 32... Second electrode 40... First reflective layer 41 First opening 42 Second opening 50 Second reflective layer 61 Insulating layer 70 Resin member 71 First conductive member 72 Second conductive member 80... groove, 91... first mask, 92... second mask, 93... third mask, 100... element region, 101... first substrate, 102... second substrate, W... wafer

Claims (13)

a first semiconductor layer, an active layer provided on the first semiconductor layer, and a second semiconductor layer provided on the active layer, and a part of the first semiconductor layer, the active layer and a portion of the second semiconductor layer, each having a semiconductor stack including a plurality of spaced apart device regions;
forming a first reflective layer continuously to the second semiconductor layers of the plurality of element regions and the second semiconductor layer positioned between the adjacent element regions among the plurality of element regions; ,
forming a plurality of first masks covering the first reflective layer positioned above the plurality of device regions;
removing a portion of the first reflective layer and the semiconductor laminate in a region between the adjacent first masks among the plurality of first masks so as to expose the first semiconductor layer; a step of forming a groove in the semiconductor laminate positioned between the adjacent element regions among the regions;
A method for manufacturing a light-emitting device comprising: 2. The method of manufacturing a light-emitting device according to claim 1, wherein said part of said first reflective layer and said semiconductor laminate is removed by RIE in said step of forming said groove. The step of forming the groove includes:
removing the first reflective layer in a region between the first masks by etching using a fluorine-containing gas;
removing the portion of the semiconductor stack in the region between the first masks by etching using a chlorine-containing gas;
The method for manufacturing a light-emitting device according to claim 2, comprising: 4. The method of manufacturing a light emitting device according to claim 1, further comprising forming a second reflective layer on the first reflective layer after forming the first reflective layer. The step of forming the second reflective layer includes:
After forming the groove, forming a second mask covering the groove;
forming the second reflective layer on the second mask and the first reflective layer;
and removing the second mask and the second reflective layer on the second mask. The step of forming the second reflective layer includes:
forming the second reflective layer continuously on the first reflective layer before forming the groove;
forming a third mask covering the second reflective layer positioned above the plurality of device regions;
5. The method of manufacturing a light emitting device according to claim 4, further comprising removing the second reflective layer in a region between the third masks. The step of preparing the wafer includes forming a first electrode on the portion of the first semiconductor layer and forming a second electrode on the portion of the second semiconductor layer. death,
7. The light-emitting device according to claim 1, wherein in said step of forming said first reflective layer, said first reflective layer is formed continuously on said first electrode and said second electrode. manufacturing method. forming an opening in the first reflective layer to expose the first electrode and the second electrode;
forming a conductive member in the opening;
The method for manufacturing a light-emitting device according to claim 7, further comprising: An insulating layer is formed to cover the first reflective layer, the side surface of the first reflective layer defining the opening, and the side surface of the semiconductor stack defining the groove before the step of forming the conductive member. and
The method of manufacturing a light emitting device according to claim 8, further comprising: 10. The method of manufacturing a light emitting device according to claim 1, wherein the first reflective layer includes a dielectric multilayer film. preparing the wafer includes sequentially forming the first semiconductor layer, the active layer, and the second semiconductor layer on a first substrate;
a step of joining the semiconductor laminate and a second substrate via a resin member after forming the groove;
After bonding the semiconductor stack and the second substrate, removing the first substrate to expose the surface of the first semiconductor layer;
The method for manufacturing a light-emitting device according to any one of claims 1 to 10, further comprising: A semiconductor laminate having a first semiconductor layer, a second semiconductor layer, and an active layer positioned between the first semiconductor layer and the second semiconductor layer, wherein: a certain first surface, a second surface located on the opposite side of the first surface and being the surface of the second semiconductor layer, and a part of the first semiconductor layer located on the opposite side of the first surface, connects the first surface and the second surface to the third surface, which is the surface of the first semiconductor layer exposed from the second semiconductor layer and the active layer, and the first surface and the third surface. a semiconductor laminate having a side surface connecting the surface;
a first reflective layer that covers the second surface and the third surface and is not arranged on the side surface;
with
The first reflective layer has an end portion including an end surface connected to the side surface of the semiconductor laminate,
A light-emitting device, wherein film thicknesses of portions other than the end portion of the first reflective layer are substantially the same. The light emitting device of claim 12, wherein the first reflective layer comprises a dielectric multilayer film.

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