JP2022155444A - Source driver and display device - Google Patents

Abstract

To provide a source driver capable of detecting the generation of short circuit in a source line with a simple configuration.SOLUTION: The source driver comprises: a first gradation voltage generation part that sets a pixel on a first source line of a plurality of source lines as supply target and generates a first polarity gradation voltage; a first amplifier that receives input of the first polarity gradation voltage at an input end, and amplifies the first polarity gradation voltage to output it from an output end; a second gradation voltage generation part that sets a pixel on a second source line which is source line provided adjacent to the first source line as supply target and generates a second polarity gradation voltage opposite to the first polarity; a second amplifier that receives input of the second polarity gradation voltage at the input end, and amplifies the second polarity gradation voltage to output it from the output end; and a voltage comparison part that compares input end voltage of the second amplifier to output end voltage of the second amplifier and outputs the comparison result.SELECTED DRAWING: Figure 3

Description

The present invention relates to source drivers and display devices.

2. Description of the Related Art An active matrix driving system is employed as a driving system for display devices including display devices such as liquid crystal and organic EL (Electro Luminescence). In the active matrix driving type display device, the display panel is composed of a semiconductor substrate on which pixel portions and pixel switches are arranged in a matrix. By controlling the on/off of the pixel switch with the gate signal from the gate driver, and supplying the pixel unit with a driving signal corresponding to the video data signal when the pixel switch is turned on, the luminance of each pixel unit is controlled, display is performed. For example, a source driver applies an analog voltage to a horizontal row of pixels selected by a gate driver to display a horizontal row, and this is repeated in the vertical direction while changing the pixel row to be selected. Display the screen of the frame.

In recent years, as display devices used for TVs and monitors, high resolution and large screens such as 4K panels (pixel columns: 3840 × RGB, pixel rows: 2160) and 8K panels (pixel columns and pixel rows twice as large as 4K panels) Demand for a display device having a display panel of . Due to such high resolution, the number of data lines driven by the source driver is increasing.

As the number of data lines increases, short circuits tend to occur between adjacent channels when the display panel is mounted. If the reliability evaluation test of the display panel is performed in a state where the data line is short-circuited, there is a possibility that the display panel and the driver IC will be destroyed due to the overcurrent. Therefore, it is necessary to check whether adjacent channels are shorted before performing reliability evaluation.

As a device for inspecting whether or not there is a short circuit between adjacent channels of such a data line, the voltage level of the monitor output signal connected to the source line is determined, and the determination result is output to the expected value by a comparison circuit provided outside the driver. A display device and an inspection method for detecting the presence or absence of a short circuit by comparing with are proposed (for example, Patent Document 1).

International publication 2018/079636

In the inspection method such as the above-mentioned prior art, since it is necessary to provide a comparison circuit outside the driver, there is a problem that the cost of the inspection IC increases. Moreover, in the inspection method of the prior art, since the comparison circuit performs measurement and judgment while switching the voltages of all the source lines, there is a problem that the inspection takes time and effort.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a source driver capable of quickly detecting whether or not a data line is short-circuited with a simple configuration.

A source driver according to the present invention is connected to a display panel having a plurality of source lines and a plurality of pixel units connected to the plurality of source lines, and a video data signal including a series of a plurality of pixel data pieces. a source driver for receiving and outputting a gradation voltage to be applied to the plurality of pixel units based on the video data signal, the pixel on a first source line among the plurality of source lines being a supply target; a first gradation voltage generator for generating a gradation voltage of a first polarity, and an input terminal for receiving the gradation voltage of the first polarity, amplifying and outputting the gradation voltage of the first polarity. A first amplifier output from an end and a pixel on a second source line which is a source line provided adjacent to the first source line are to be supplied, and the polarity is opposite to the first polarity. a second grayscale voltage generator for generating a grayscale voltage of a second polarity; and an input terminal receiving the grayscale voltage of the second polarity, amplifying the grayscale voltage of the second polarity, and outputting the grayscale voltage. and a voltage comparison unit that compares the voltage at the input terminal of the second amplifier and the voltage at the output terminal of the second amplifier and outputs the comparison result. and

Further, the source driver according to the present invention is connected to a display panel having a plurality of source lines and a plurality of pixel units connected to the plurality of source lines, and is connected to a display panel including a series of a plurality of pixel data pieces. A source driver for receiving a data signal and outputting a gradation voltage to be applied to the plurality of pixel portions based on the video data signal, the source driver supplying a pixel on a first source line among the plurality of source lines. a first gradation voltage generation unit for generating a target gradation voltage of a first polarity; a first source output terminal for outputting the voltage output from the first amplifier to the first source line; the first amplifier and the first a first resistance element provided between a source output terminal and having one end connected to the output terminal of the first amplifier and the other end connected to the first source output terminal; and the first source. A second gradation for generating a gradation voltage of a second polarity opposite to the first polarity, which is supplied to pixels on a second source line which is a source line provided adjacent to the line. a voltage generator, a second amplifier that receives the grayscale voltage of the second polarity at an input terminal, amplifies the grayscale voltage of the second polarity, and outputs the grayscale voltage from the output terminal; A second source output terminal for outputting the output voltage to the second source line, and provided between the second amplifier and the second source output terminal, one end of the second amplifier a second resistance element connected to the output terminal and having the other end connected to the second source output terminal; a voltage at the output terminal of the second amplifier; the other end of the second resistance element; and a voltage comparison unit that compares the voltage of the connection node with the second source output terminal and outputs the comparison result.

Further, the display device according to the present invention includes a plurality of source lines, a plurality of gate lines, and a plurality of pixel portions provided in a matrix at each intersection of the plurality of source lines and the plurality of gate lines. and a source driver for receiving a video data signal including a series of a plurality of pixel data pieces and outputting a gradation voltage to be applied to the plurality of pixel units based on the video data signal. a first gradation voltage generator for generating a gradation voltage of a first polarity to be supplied to pixels on a first source line among the plurality of source lines; a first amplifier for receiving an input of the grayscale voltage of the first polarity, amplifying the grayscale voltage of the first polarity and outputting it from an output terminal; and applying the voltage output from the first amplifier to the first source line. A first source output terminal for output is provided between the first amplifier and the first source output terminal, one end is connected to the output end of the first amplifier, and the other end is the first source output terminal. and the first polarity and the pixel on the second source line which is the source line provided next to the first source line. a second grayscale voltage generation unit for generating a second polarity grayscale voltage opposite to the polarity of the second grayscale voltage generation unit; a second amplifier for amplifying and outputting from an output terminal; a second source output terminal for outputting the voltage output from the second amplifier to the second source line; a second resistance element provided between the source output terminal of the second amplifier and having one end connected to the output terminal of the second amplifier and the other end connected to the second source output terminal; a voltage comparison unit that compares the voltage at the output end of the amplifier with the voltage at the connection node between the other end of the second resistance element and the second source output terminal, and outputs a comparison result; characterized by having

Further, the display device according to the present invention includes a plurality of source lines, a plurality of gate lines, and a plurality of pixel portions provided in a matrix at each intersection of the plurality of source lines and the plurality of gate lines. and a source driver that receives a video data signal including a series of a plurality of pixel data pieces and outputs grayscale voltages to be applied to the plurality of pixel units based on the video data signal. and the source driver includes a first grayscale voltage generating section for generating a first polarity grayscale voltage to be supplied to pixels on a first source line among the plurality of source lines, and an input terminal. a first amplifier for receiving an input of the gradation voltage of the first polarity, amplifying the gradation voltage of the first polarity and outputting it from an output terminal; a first source output terminal for outputting to one source line, and provided between the first amplifier and the first source output terminal, one end of which is connected to the output end of the first amplifier; A pixel on a first resistor element having an end connected to the first source output terminal and a second source line, which is a source line provided adjacent to the first source line, is to be supplied. a second grayscale voltage generator for generating a grayscale voltage of a second polarity opposite to the first polarity; a second amplifier for amplifying the gradation voltage of and outputting it from an output terminal; a second source output terminal for outputting the voltage output from the second amplifier to the second source line; and the second source output terminal, one end of which is connected to the output terminal of the second amplifier and the other end of which is connected to the second source output terminal and the voltage at the output end of the second amplifier and the voltage at the connection node between the other end of the second resistance element and the second source output terminal, and output the comparison result. and a voltage comparator.

According to the source driver of the present invention, it is possible to quickly detect the presence or absence of short-circuiting of data lines with a simple configuration.

1 is a block diagram showing the configuration of a display device according to the present invention; FIG. 1 is a circuit diagram showing the configuration of a source driver according to the present invention; FIG. 3 is a circuit diagram showing a part of the internal configuration of the source driver of Example 1; FIG. 2 is a circuit diagram showing a simplified configuration of an amplifier within a source driver; FIG. FIG. 4 is a diagram schematically showing how current flows through a source line when a short circuit occurs; 3 is a diagram showing an image of the entire chip of the source driver of Example 1. FIG. FIG. 11 is a circuit diagram showing a part of the configuration inside the source driver of Example 2; FIG. 4 is a diagram schematically showing how current flows through a source line when a short circuit occurs; FIG. 10 is a diagram showing an image of the entire chip of the source driver of Example 2; FIG. 12 is a circuit diagram showing a part of the configuration inside the source driver of Example 3; FIG. 10 is a diagram showing an example of a short detection screen displayed on the display panel; 11 is a flow chart showing a processing routine of a defect detection operation of Example 3; FIG. 11 is a diagram showing an image of the entire chip of the source driver of Example 3;

Preferred embodiments of the present invention are described in detail below. In the following description of each embodiment and the attached drawings, substantially the same or equivalent parts are denoted by the same reference numerals.

FIG. 1 is a block diagram showing the configuration of a display device 100 according to the invention. The display device 100 is an active matrix driven liquid crystal display device. A display device 100 includes a display panel 11 , a timing controller 12 , a gate driver 13 and a source driver 14 .

The display panel 11 is composed of a semiconductor substrate on which a plurality of pixel portions P ₁₁ to P _nm and pixel switches M ₁₁ to M _nm (n and m are natural numbers equal to or greater than 2) are arranged in a matrix. The display panel 11 has n gate lines GL1 to GLn, each of which is a scanning line extending in the horizontal direction, and m source lines SL1 to SLm arranged to cross the gate lines GL1 to GLn. Pixel units P ₁₁ to P _nm and pixel switches M ₁₁ to M _nm are provided at intersections of gate lines GL1 to GLn and source lines SL1 to SLm.

The pixel switches M ₁₁ to M _nm are controlled to be on or off according to gate signals Vg 1 to Vgn supplied from the gate driver 13 .

The pixel portions P ₁₁ to P _nm are supplied with drive voltages (gradation voltages) corresponding to video data from the source driver 14 . Specifically, the drive voltage signals Dv1 to Dvm are output from the source driver 14 to the source lines SL1 to SLm, and when the pixel switches M ₁₁ to M _nm are turned on, the drive voltage signals Dv1 to Dvm are applied to the pixel portion P ₁₁ . ~P _nm . Thereby, the pixel electrodes of the pixel portions P ₁₁ to P _nm are charged and the brightness is controlled.

When the display device 100 is a liquid crystal display device, each of the pixel portions P ₁₁ to P _nm faces the semiconductor substrate with a transparent electrode connected to the source lines SL1 to SLm via the pixel switches M ₁₁ to M _nm . a liquid crystal enclosed between a counter substrate provided on the substrate and having a single transparent electrode formed over the entire surface thereof. Display is enhanced by changing the transmittance of the liquid crystal according to the potential difference between the drive voltage (gradation voltage) applied to the pixel portions P ₁₁ to P _nm and the counter substrate voltage for the backlight inside the display device. done.

The timing controller 12 generates a series (serial signal) of pixel data pieces PD representing the luminance level of each pixel, for example, in 8-bit 256-step luminance gradation based on the video data VS. Further, the timing controller 12 generates an embedded clock type clock signal CLK having a constant clock cycle based on the synchronization signal SS. The timing controller 12 generates a video data signal VDS, which is a serial signal integrating the series of pixel data pieces PD and the clock signal CLK, and supplies it to the source driver 14 to control the display of the video data. The video data signal VDS is configured as a video data signal serialized according to the number of transmission lines for every predetermined number of source lines.

In this embodiment, a video data signal VDS for one frame is formed by serially connecting n pixel data piece groups, each consisting of m pixel data pieces PD. Each of the n pixel data piece groups is a pixel data piece group made up of pixel data pieces corresponding to grayscale voltages to be supplied to pixels on one horizontal scanning line (that is, each of the gate lines GL1 to GLn). is. By the operation of the source driver 14, the driving voltage signals Dv1 to Dvm to be supplied to the n×m pixel units (that is, the pixel units P ₁₁ to P _nm ) are generated based on the m×n pixel data pieces PD. Applied through the source line.

The timing controller 12 also generates a frame synchronization signal FS indicating the timing of each frame of the video data signal VDS based on the synchronization signal SS, and supplies it to the source drivers 14-1 to 14-p.

The timing controller 12 also generates a gate timing signal GS for controlling the operation timing of the gate driver 13 based on the synchronization signal SS, and supplies the gate timing signal GS to the gate driver 13 .

The gate driver 13 receives the gate control signal GS from the timing controller 12, and sequentially supplies the gate signals Vg1 to Vgn to the gate lines GL1 to GLn based on the clock timing included in the gate control signal GS. By supplying the gate signals Vg1 to Vgn, the pixel portions P ₁₁ to P _nm are selected for each pixel row. Then, the driving voltage signals Dv1 to Dvm are applied from the source driver 14 to the selected pixel portion, thereby writing the gradation voltage to the pixel electrode.

In other words, by the operation of the gate driver 13, m pixel units arranged along the extending direction of the gate lines (that is, in a horizontal row) are selected as targets to be supplied with the drive voltage signals Gv1 to Gvm. The source driver 14 applies drive voltage signals Gv1 to Gvm to the selected horizontal row of pixel portions to display colors corresponding to the voltages. One frame of screen display is performed by repeating in the extension direction of the data line (that is, in the vertical direction) while selectively switching the pixel portions of one horizontal row selected to be supplied with the drive voltage signals Gv1 to Gvm. will be

The source drivers 14-1 to 14-p receive the video data signal VDS from the timing controller 12, and drive voltage signals corresponding to multilevel grayscale voltages corresponding to the number of grayscales indicated by the video data signal VDS. Dv1 to Dvm are generated and applied to the pixel portions P ₁₁ to P _nm through the source lines SL1 to SLm. In the following description, the drive voltage signals Dv1-Dvm are also referred to as gradation voltage signals Dv1-Dvm. Also, one of the gradation voltage signals Dv1 to Dvm is simply referred to as the gradation voltage signal Dv.

The source drivers 14-1 to 14-p are provided for each of a predetermined number of source lines obtained by dividing the source lines SL1 to SLm. The number of source lines driven by each source driver corresponds to the number of output channels of the source driver. For example, if one source driver has 960 ch outputs and the display panel has one source line per pixel column, the source lines are driven by 12 source drivers for 4K panels and 24 source drivers for 8K panels. be done. Each of the source drivers 14-1 to 14-p is formed on a different semiconductor IC (Integrated Circuit) chip.

Each of source drivers 14-1 to 14-p has a common configuration. In the following description, when describing such a common configuration, the source drivers 14-1 to 14-p are collectively referred to simply as "source driver 14".

FIG. 2 is a block diagram showing the internal configuration of the source driver 14. As shown in FIG. The source driver 14 has a data latch section 21 , a gradation voltage conversion section 22 and an output section 23 .

The data latch section 21 sequentially takes in the series of pixel data pieces PD included in the video data signal VDS supplied from the timing controller 12 . Then, the data latch section 21 outputs the fetched pixel data pieces PD to the gradation voltage conversion section 22 as the pixel data Q1 to Qj in response to fetching the pixel data pieces PD for jch.

The gradation voltage conversion unit 22 converts each of the pixel data Q1 to Qj supplied from the data latch unit 21 into a positive or negative gradation having a voltage value corresponding to the luminance gradation represented by the pixel data. It is converted into voltages A1 to Aj and supplied to the output section 23. FIG.

The output unit 23 generates signals obtained by amplifying the grayscale voltages A1 to Aj as grayscale voltage signals Dv1 to Dvj, and outputs them to the source lines SL1 to SLj.

Further, the output unit 23 has a circuit configuration for detecting whether or not adjacent channels of the source lines SL1 to SLj are short-circuited.

The source lines SL1 to SLj are divided into a source line to which the positive grayscale voltage signal Dv is applied (hereinafter referred to as a positive channel) and a source line to which the negative grayscale voltage signal Dv is applied (hereinafter referred to as a positive channel). (referred to as a negative channel) are alternately arranged. That is, the adjacent channels of the source lines SL1 to SLj are supplied with grayscale voltage signals Dv of different polarities.

The gradation voltage conversion unit 22 has a positive decoder that generates a positive gradation voltage and a positive amplifier that amplifies and outputs the gradation voltage. The grayscale voltage conversion unit 22 also has a negative decoder that generates a negative grayscale voltage and a negative amplifier that amplifies and outputs the grayscale voltage.

FIG. 3 is a circuit diagram showing a part of the configuration of the gradation voltage conversion section 22 and the output section 23. As shown in FIG. Here, a case where the source line SLA is a positive channel and the source line SLB is a negative channel is shown as an example.

The positive decoder 31p generates a positive gradation voltage (inp in FIG. 3) based on the pixel data Qp and outputs it. The output of the positive decoder 31p is connected to the non-inverting input terminal of the positive amplifier 32p.

The positive amplifier 32p receives the positive input voltage inp, which is the output voltage of the positive decoder 31p, at its non-inverting input terminal, amplifies it, and outputs it. The output terminal of the positive amplifier 32p is negative feedback connected to the inverting input terminal. In the following description, the connection node between the output terminal and the inverting input terminal of the positive amplifier 32p is referred to as node fbo.

Also, the output terminal of the positive amplifier 32p is connected to one end of the resistor R10 via the node fbo. A resistor R10 is provided at the output of the source driver 14 as a protection resistor from ESD (electro-static discharge). The resistor R10 is composed of a resistive element having a resistance value of 0.2 kΩ, for example. The other end of the resistor R10 is connected to the source output terminal OT1, which is the terminal from which the source driver 14 outputs the positive grayscale voltage signal Dv.

A source output terminal OT1 is connected to the source line SLA of the display panel 11 . The source line SLA has source line loads R11 to R1k and source line capacitances C11 to C1k.

The negative decoder 31n generates a negative gradation voltage (inn in FIG. 3) based on the pixel data Qn and outputs it. The output of the negative decoder 31n is connected to the non-inverting input terminal of the negative amplifier 32n.

The negative amplifier 32n receives the negative input voltage inn, which is the output voltage of the negative decoder 31n, at its non-inverting input terminal, amplifies it, and outputs it. The output terminal of the negative amplifier 32n is negatively fed back to the inverting input terminal. In the following description, the connection node between the output terminal and the inverting input terminal of the negative amplifier 32n will be referred to as node fbe.

Also, the output terminal of the negative amplifier 32n is connected to one end of the resistor R20 via the node fbe. Like the resistor R10, the resistor R20 is provided at the output of the source driver 14 as a protection resistor from ESD. The resistor R20 is composed of a resistive element having a resistance value of 0.2 kΩ, for example. The other end of the resistor R20 is connected to the source output terminal OT2 from which the source driver 14 outputs the negative gradation voltage signal Dv.

A source output terminal OT2 is connected to the source line SLB of the display panel 11 . The source line SLB has source line loads R21 to R2k and source line capacitances C21 to C2k.

Further, the output section 23 is provided with a power-down signal generation section 33 and a voltage comparison circuit 34 .

The power-down signal generator 33 generates power-down signals PDS and XPDS for reducing the drive capability of the negative amplifier 32n, and supplies them to the negative amplifier 32n. The power-down signals PDS and XPDS of this embodiment are signals for reducing the drive capability of the negative amplifier 32n to 1/10.

Specifically, the negative amplifier 32n of this embodiment is composed of a plurality of combs (multiple stages) of amplifiers in which a plurality of amplifiers are connected in parallel, and the output current is changed by switching the number of amplifier stages. It is configured to allow The power-down signals PDS and XPDS are signals for switching the number of amplifier stages.

FIG. 4 is a circuit diagram showing the configuration of the output stage 35 of the negative amplifier 32n.

The output stage 35 of the negative amplifier 32n is composed of 10 combs (10 stages) of amplifiers AP1 to AP10 connected in parallel. The first-stage amplifier AP1 has a configuration in which the drains of the P-channel MOS transistor PM1 and the N-channel MOS transistor NM1 are connected to each other.

The transistor PM1 has a source to which the power supply voltage VDD is applied, and a gate connected to the first drive line LH, which is the supply line of the positive drive voltage. The transistor NM1 has a source to which the ground potential VSS is applied, and a gate connected to the second drive line LL which is the supply line of the negative drive voltage.

The amplifiers AP2 to AP10 in the second and subsequent stages include a P-channel MOS transistor and an N-channel MOS transistor whose drains are connected to each other, and connection/disconnection of these to the first drive line LH and the second drive line LL, respectively. It consists of a changeover switch that switches connections. The changeover switch performs connection switching based on the power-down signals PDS and XPDS. The power-down signal PDS and the power-down signal XPDS are signals whose signal levels complementarily change to logic level 0 and logic level 1. FIG.

In this embodiment, the gate of the P-channel MOS transistor PM2 of the amplifier AP2 is connected to the first drive line LH via the switch S22. The gate of the P-channel MOS transistor PM2 is connected to the first drive line LH when the power-down signal PDS is at logic level 0, and is connected to the first drive line LH when the power-down signal PDS is at logic level 1. become connected. The gate of the P-channel MOS transistor PM2 is connected to the drain of the switch transistor S21, which is a P-channel MOS transistor. The switch transistor S21 has a source to which the power supply voltage VDD is applied and a gate to which the power-down signal XPDS is applied. When the power-down signal XPDS is at logic level 0, the switch transistor S21 is turned on, so that the power supply voltage VDD is applied to the gate of the P-channel MOS transistor PM2. Further, when the power-down signal XPDS is at logic level 1, the switch transistor S21 is turned off, so the power supply voltage VDD is not applied to the gate of the P-channel MOS transistor PM2, and is supplied to the first drive line LH. A positive drive voltage is applied.

Also, the gate of the N-channel MOS transistor NM2 of the amplifier AP2 is connected to the second drive line LL via the switch S23. The gate of the N-channel MOS transistor NM2 is connected to the second drive line LL when the power-down signal XPDS is at logic level 1, and is disconnected from the second drive line LL when the power-down signal XPDS is at logic level 0. become. Also, the gate of the N-channel MOS transistor NM2 is connected to the drain of the switch transistor S24, which is an N-channel MOS transistor. The switch transistor S24 has a source to which the ground voltage VSS is applied and a gate to which the power-down signal PDS is applied. When the power-down signal PDS is at logic level 1, the switch transistor S24 is turned on, so that the ground potential VSS is applied to the gate of the N-channel MOS transistor NM2. Further, when the power-down signal PDS is at logic level 0, the switch transistor S24 is turned off, so that the ground potential VSS is not applied to the gate of the N-channel MOS transistor NM2 and is supplied to the second drive line LL. A negative drive voltage is applied.

The amplifiers in the third and subsequent stages have the same configuration as the amplifier AP2 in the second stage. For example, when the power-down signal PDS is at logic level 0 and the power-down signal XPDS is at logic level 1, the amplifiers of each stage are connected to the first drive line LH and the second drive line LL, and the output stage 35 of the negative amplifier 32n is connected to the first drive line LH and the second drive line LL. has an amplifier configuration of 10 combs. On the other hand, when the power-down signal PDS is at logic level 1 and the power-down signal XPDS is at logic level 0, only the first-stage amplifier AP1 is connected to the first drive line LH and the second drive line LL, and the output stage of the negative amplifier 32n is connected to the first drive line LH and the second drive line LL. 35 has a one-comb amplifier configuration.

Referring to FIG. 3 again, the voltage comparison circuit 34 is composed of a comparator CMP. A first input terminal (shown as in in the figure) of the comparator CMP is connected to the node fbe. A second input terminal (indicated as Ref in the drawing) of the comparator CMP is connected to a node n0, which is a connection node between the output of the negative decoder 31n and the non-inverting input terminal of the negative amplifier 32n. Comparator CMP is at logic level 1 (i.e., H level) when the voltage at node fbe is greater than the voltage at node n0, and at logic level 0 (i.e., H level) when the voltage at node fbe is less than the voltage at node n0. output a comparison result signal CRS having a signal level of L level).

The voltage comparison circuit 34 is a circuit provided for determining whether or not the source line SLA and the source line SLB, which are adjacent channels, are short-circuited. A comparison result signal CRS output from the voltage comparison circuit 34 is output from the source driver 14 and supplied to a short-circuit determining section (not shown) provided in the timing controller 12 .

The operation of voltage comparison by the voltage comparison circuit 34 will be described with reference to FIG. Here, a case where the positive input voltage inp is 15V and the negative input voltage inn is 1V will be described as an example.

When the source line SLA and the source line SLB are short-circuited at the far end (that is, the end far from the source driver 14), the short-circuit current flows from the positive amplifier 32p toward the negative amplifier 32n in the direction of the dashed arrow in the drawing. flows. The current value of the short current is rate-determined by the drive capability of the negative amplifier 32n. As described above, since the driving capability of the negative amplifier 32n is reduced to 1/10, the current value of the short current Ishort is 1 mA. Assuming that the resistance values of the resistors R10 and R20 are 0.2 kΩ, respectively, and the source line loads of the source lines SLA and SLB are each 5 kΩ, 1 mA=(15 V−fbe)÷(0.4 kΩ+10 kΩ), and the voltage at the node fbe is becomes fbe≈5V.

Thus, when the source line SLA and the source line SLB are short-circuited, the voltage value of the node fbe becomes 5V, which is higher than the voltage value of 1V of the negative input voltage inn. Therefore, the comparison result signal CRS of logic level 1 is output from the comparator CMP.

On the other hand, if the source line SLA and the source line SLB are not short-circuited, the voltage of the node fbe becomes 1 V, which is the same as the negative input voltage inn, and the comparison result signal CRS of logic level 0 is output from the comparator CMP. output.

The comparison result signal CRS is supplied to a short-circuit determining section (not shown) provided in the timing controller 12 . The short-circuit determination unit determines that a short-circuit has occurred between the source lines when receiving the comparison result signal CRS of logic level 1, and determines that a short-circuit has occurred between the source lines when receiving the comparison result signal CRS of logic level 0. It is determined that a short circuit has not occurred between them.

In this embodiment, the power down signal PDS is supplied to the negative amplifier 32n so as to detect the short circuit even when the short circuit current generated between the source lines SLA and SLB is small. It reduces the driving ability. Since the negative amplifier 32n drives the panel load (source line load) of the display panel 11, it originally has a high driving capability. Therefore, if the driving capability of the negative amplifier 32n is not reduced, the current load can be driven even in the state of short circuit, and the voltage of the node fbe does not decrease, and the short circuit may not be detected. Therefore, in this embodiment, the output current of the negative amplifier 32 is reduced by reducing the number of amplifier stages (the number of combs) constituting the negative amplifier 32, thereby lowering the drive capability.

3 and 5 show a configuration in which the nodes positioned at the input and output of the negative amplifier 32n are connected to a pair of input terminals of the comparator CMP, respectively, and a negative voltage is compared. there is However, unlike this configuration, the nodes positioned at the input and output of the positive amplifier 32p are connected to a pair of input terminals of the comparator CMP, and the positive polarity voltage is compared to detect the occurrence of a short circuit. may be

Further, in the source driver 14 of this embodiment, the voltage comparison circuit 34 is not provided for each pair of source lines (hereinafter referred to as a source line pair) forming adjacent channels, but one voltage comparison circuit is provided. By switching the source lines for voltage comparison in a time-sharing manner, it is possible to detect the occurrence of short circuits for 24 channels.

FIG. 6 is a diagram showing an image of the entire chip of the source driver 14. As shown in FIG. The voltage comparison circuit 45 is configured to be able to perform voltage comparison while changing the target source line in units of 24 channels in a time division manner under the switching control of the switching control circuit 44 . Note that the power-down signal generator 33 is omitted here.

The L/S circuit 41p is a latch circuit that takes in pixel data pieces PD (shown as GSP in the figure) for 6 channels on the positive electrode side. The positive decoder 42p is a positive-side decoder that generates gradation voltages for 6 channels on the positive side based on the pieces of pixel data output from the L/S circuit 41p. The positive grayscale voltage output from the positive decoder 42p is input to the non-inverting input terminal of the positive amplifier 32p.

The L/S circuit 41n is a latch circuit that takes in pixel data pieces PD (shown as GSN in the figure) for 6 channels on the negative electrode side. The negative decoder 42n is a negative decoder that generates gradation voltages for 6 channels on the negative electrode side based on the pieces of pixel data output from the L/S circuit 41n. The negative grayscale voltage output from the negative decoder 42n is input to the non-inverting input terminal of the negative amplifier 32n.

The switching control circuit 44 receives an enable signal en indicating the start of execution of the voltage comparison process, and switches the switch SW2.

The switch SW2 is provided between the output terminal and the inverting input terminal of the negative amplifier 32n and the detection line JL. By turning on the switch SW2, the output terminal and the inverting input terminal of the negative amplifier 32n are connected to the input terminal of the comparator CM1.

Although FIG. 6 shows the positive amplifier 32p and the negative amplifier 32n corresponding to the source lines for 2ch and the switch SW2, in reality, the same configuration is provided for 6 pieces, that is, for 12ch. . The switching control circuit 44 switches the switch SW2 in a time division manner. As a result, the source lines to be subjected to voltage comparison are sequentially switched, and finally the voltage comparison is performed on the source lines for 12 channels, thereby detecting the presence or absence of short-circuiting between adjacent channels.

The L/S circuit 41p, the L/S circuit 41n, the positive decoder 42p, the negative decoder 42p, and the switching control circuit 44 are provided in the left side area of the chip constituting the source driver 14 (hereinafter referred to as chip left side area LA). A structure similar to these is provided in the right region (not shown) of the chip.

A voltage comparison circuit 45, a level-down circuit 46, and a signal output circuit 47 are provided in the chip center area CA located between the chip left side area LA and the chip right side area.

The voltage comparison circuit 45 includes a comparator CM1 that compares the voltages of source lines for 12 channels (6 channels on the positive electrode side and 6 channels on the negative electrode side) in the chip left side LA, and a comparator CM2 that performs voltage comparisons on the source lines for 12 channels in the right side area. , has

A first input terminal of the comparator CM1 is connected to the sensing line JL. A second input terminal of the comparator CM1 is connected to a connection node between the output section of the negative decoder 42n and the non-inverting input terminal of the negative amplifier 32 (that is, negative input voltage inn). The comparator CM1 is at logic level 1 (that is, H level) when the voltage of the detection line JL is higher than the voltage of the negative input voltage inn, and when the voltage of the detection line JL is equal to or lower than the negative input voltage inn. It outputs a comparison result signal having a signal level of logic level 0 (that is, L level). Note that the comparator CM2 also has the same configuration on the right side of the chip and performs the same operation, so the description is omitted here.

The level-down circuit 46 level-downs and outputs the comparison result signals output from the comparators CM1 and CM2. The output circuit 47 outputs the level-downped comparison result signal as the determination signal JS.

As described above, the source driver 14 of the present embodiment has the voltage of the node n0 connected to the input terminal of the negative amplifier 32n (that is, the negative input voltage inn) and the node fbe connected to the output terminal of the negative amplifier 32n. and compare the voltage of Thereby, it is determined whether or not the adjacent source line SLA and source line SLB are short-circuited. If a short circuit occurs between the source lines SLA and SLB, the voltage drop (because it is on the negative side, the voltage actually rises) caused by the short current flowing through the source lines SLA and SLB causes the voltage of the node fbe to becomes greater than the voltage at node n0. Therefore, as a result of the voltage comparison, if the voltage at the node fbe is higher than the voltage at the node n0, it is determined that a short circuit has occurred, and if not, it is determined that a short circuit has not occurred.

According to such a configuration, by providing the voltage comparison circuit in the IC chip constituting the source driver 14, it is possible to detect the occurrence of a short circuit between adjacent channels of the source line with a simple configuration.

In addition, by switching the source lines to be subjected to voltage comparison in a time-division manner, it is possible to detect the occurrence of short circuits in the entire chip. can be done.

Next, Example 2 of the present invention will be described. The display device of Example 2 differs from the display device of Example 1 in the configuration of the output section including the voltage comparison circuit in the source driver.

FIG. 7 is a circuit diagram showing a part of the configuration of the gradation voltage conversion section 22 and the output section 23 of the source driver 14 in this embodiment.

A first input terminal (shown as in in the drawing) of the comparator CMP that constitutes the voltage comparison circuit 34 is connected to a node out, which is a connection node between the other end of the resistor R20 and the source output terminal OT2. A second input terminal (indicated as Ref in the drawing) of the comparator CMP is connected to a node n0, which is a connection node between the output of the negative decoder 31n and the non-inverting input terminal of the negative amplifier 32n.

Comparator CMP is at logic level 1 (i.e., H level) when the voltage at node out is greater than the voltage at node n0, and at logic level 0 (i.e., H level) when the voltage at node out is less than the voltage at node n0. output a comparison result signal CRS having a signal level of L level).

The source driver 14 of this embodiment does not have the power-down signal generator PDS as in the first embodiment, and does not supply the power-down signal PDS to the negative amplifier 32n. Therefore, the driving capability of the negative amplifier 32n is the same as during normal operation.

FIG. 8 is a diagram schematically showing a short-circuit current that flows when a short-circuit occurs between the source lines SLA and SLB. When the source line SLA and the source line SLB are short-circuited at their far ends, a short-circuit current flows from the positive amplifier 32p toward the negative amplifier 32n in the direction of the dashed arrow in the figure. As described above, in this embodiment, the driving capability of the negative amplifier 32n is not lowered, so if the voltage of the node n0 is 1V, the voltage of the node fbe is also 1V. Since the voltage of the node out drops from the voltage of the node fbe by the voltage drop across the resistor R20, "out=1 V+(R20.times.Ishort)=1 V+Vdrop". Therefore, when a short circuit occurs, the voltage of node out will be greater than the voltage of node fbe.

Thus, when the source line SLA and the source line SLB are short-circuited, the voltage of the node out becomes higher than the voltage of the node fbe. Therefore, the comparison result signal CRS of logic level 1 is output from the comparator CMP.

On the other hand, when the source line SLA and the source line SLB are not short-circuited, the voltage of the node out has the same voltage value as the voltage of the node fbe, and the comparison result signal CRS of logic level 0 is output from the comparator CMP. be.

FIG. 9 is a diagram showing an image of the entire chip of the source driver 14 in this embodiment.

The switching control circuit 44 receives an enable signal en indicating the start of execution of the voltage comparison process, and switches the switch SW4.

The switch SW4 switches connection and disconnection between the output terminal and the inverting input terminal of the negative amplifier 32n and the first detection line JL1. Also, the switch SW4 switches between connection and non-connection between the second detection line JL2 and the node out, which is a connection node between the other end of the resistor R20 and the output terminal OT2. The switch SW4 is turned on to be in a "connected" state, whereby the output terminal and the inverting input terminal of the negative amplifier 32n are connected to one of the input terminals of the comparator CM1 via the first detection line JL1. At the same time, the node out is connected to the other input terminal of the comparator CM1 via the second detection line JL2.

The comparator CM1 outputs a comparison result signal of logic level 1 (that is, H level) when the voltage of the second detection line JL2 is higher than the voltage of the first detection line JL1. Further, the comparator CM1 outputs a comparison result signal of logic level 0 (ie, L level) when the voltage of the second detection line JL2 is equal to or lower than the voltage of the first detection line JL1.

As described above, the source driver 14 of this embodiment compares the voltage of the node fbe connected to the output terminal of the negative amplifier 32n with the voltage of the node out connected to the source output terminal OT2. Thereby, it is determined whether or not the adjacent source line SLA and source line SLB are short-circuited. If a short-circuit occurs between the source lines SLA and SLB, the short-circuit current flows through the source lines SLA and SLB, causing the voltage at the node out to drop by the voltage drop across the resistor R20 (because it is on the negative voltage rises). Therefore, if the voltage of the node out is higher than the voltage of the node fbe, it is determined that a short circuit has occurred, and if not, it is determined that a short circuit has not occurred.

According to this configuration, as in the first embodiment, it is possible to detect the occurrence of a short circuit between adjacent channels of the source line with a simple configuration in which a voltage comparison circuit is provided in the IC chip. Further, unlike the first embodiment, it is not necessary to provide the power-down signal generator 33, so that the occurrence of a short circuit can be detected with a simpler configuration than the first embodiment.

In the first embodiment, since the drive capability of the negative amplifier 32n is reduced, it is necessary to detect a short-circuit by performing a voltage comparison during a blank period during which pixel data is not supplied. In order not to degrade the performance, it is possible to detect a short circuit by performing voltage comparison while actually generating and supplying a gradation voltage signal based on pixel data.

Next, Example 3 of the present invention will be described. The display device of Example 3 differs from the display devices of Examples 1 and 2 in that it has a configuration for displaying the detection result of the occurrence of a short between adjacent channels of source lines on the display panel.

FIG. 10 is a circuit diagram showing a part of the configuration of the source driver in this embodiment. The source driver of this embodiment has an IF/data processing circuit 51 , latch circuits 52 A, 52 B and 52 C, decoders 53 A, 53 B and 53 C, a short detection determination circuit 54 , a data write circuit 55 and a counter 56 . The data write circuit 55 and the counter 56 are provided inside the IF/data processing circuit 51 . Although the source driver of this embodiment has a power-down signal generation circuit similar to that of the first embodiment, the illustration thereof is omitted in FIG.

The IF/data processing circuit 51 is an interface circuit that receives the video data signal VDS and frame synchronization signal FS transmitted from the timing controller 12 . Also, the IF/data processing circuit 51 performs various data processing based on the video data signal VDS and the frame synchronization signal FS. For example, the IF/data processing circuit 51 includes a serial/parallel conversion circuit (not shown), converts the series of pixel data pieces PD included in the video data signal VDS into parallel data, and supplies the parallel data to the latch circuits 52A, 52B, and 52C. .

Also, the IF/data processing circuit 51 receives a mode switching signal MS from the outside of the source driver, and switches the operation mode to either the normal operation mode or the short detection mode. In the normal operation mode, an operation for performing display based on the video data signal VDS from the timing controller 12, that is, an operation for supplying pixel data pieces PD obtained from the video data signal VDS to the latch circuits 52A, 52B and 52C is performed. .

On the other hand, in the short detection mode, the IF/data processing circuit 51 supplies pixel data pieces for displaying black on the entire screen of the display panel 11 to the latch circuits 52A, 52B and 52C.

The latch circuits 52A, 52B and 52C take in the pixel data pieces PD output from the IF/data processing circuit 51 and supply the taken in pixel data pieces PD as pixel data Q to the decoders 53A, 53B and 53C, respectively.

The decoders 53A, 53B and 53C generate grayscale voltages based on the pixel data Q and supply them to the positive amplifier 32p and the negative amplifier 32n. In FIG. 10, inp denotes the grayscale voltage supplied to the positive amplifier 32p, and inn denotes the grayscale voltage supplied to the negative amplifier 32n.

The short detection determination circuit 54 is a circuit provided for determining whether or not the source line SLA and the source line SLB, which are adjacent channels, are short-circuited. The short detection determination circuit 54 is composed of a comparator (not shown) that compares the voltage of the node n0 and the voltage of the node fbe, like the voltage comparison circuit 34 of the first embodiment.

The short detection determination circuit 54 sets the logic level 1 (H level) when the voltage of the node fbe is higher than the voltage of the node n0, and the logic level 0 (L level) when the voltage of the node fbe is lower than the voltage of the node n0. level).

As in the first embodiment, when the source line SLA and the source line SLB are short-circuited, a short-circuit current flows from the positive amplifier 32p to the negative amplifier 32n. Since the drive capability of the negative amplifier 32n is reduced to about 1/10 by a power-down signal (not shown), for example, the positive input voltage inp is 15 V, the negative input voltage inn is 1 V, and the resistance values of the resistors R10 and R20 are is 0.2 kΩ each, and the source line loads of the source lines SLA and SLB are each 5 kΩ, the voltage at the node fbEe is approximately 5V. Therefore, the comparison result signal CRS of logic level 1 is output from the short detection determination circuit 54 .

On the other hand, when the source line SLA and the source line SLB are not short-circuited, the voltage of the node fbe becomes 1 V, which is the same as the negative input voltage inn, and the comparison result signal CRS of logic level 0 is output from the comparator CMP. be.

Unlike the voltage comparison circuit of the first embodiment, the short detection determination circuit 54 of this embodiment supplies the comparison result signal CRS to the data write circuit 55 in the IF/data processing circuit 51 .

The data write circuit 55 receives the comparison result signal CRS, and is a pair of source lines adjacent to the outside of the source lines SLA and SLB, that is, adjacent source lines located on the opposite side of the source line SLB when viewed from the source line SLA. This circuit is provided for writing data to the source line SLX and the source line SLY, which is an adjacent source line located on the opposite side of the source line SLA from the source line SLB.

As described above, when the mode is switched to the short detection mode, the IF/data processing circuit 51 supplies the latch circuits 52A, 52B, and 52C with pixel data pieces for displaying black (pixel value 0). . In response to this, a gradation voltage for displaying black is output from the source driver, and a black screen is displayed on the display panel 11 .

In this state, when the comparison result signal CRS of logic level 1 is supplied from the short detection determination circuit 54 to the data write circuit 55, the data write circuit 55 responds to the latch circuit 52A corresponding to the source line SLX and the source line SLY. A piece of pixel data for displaying white (pixel value 255) is supplied to the latch circuit 52C. In response to this, a gradation voltage for displaying white is output from the source driver, and a white screen is displayed at positions corresponding to the source lines SLX and SLY of the display panel 11 .

On the other hand, when the comparison result signal CRS of logic level 0 is supplied from the short detection determination circuit 54 to the data write circuit 55, the data write circuit 55 does not supply pixel data pieces to the latch circuits 52A and 52C, and the display panel 11 continues to display a black screen.

The counter 56 is a circuit that generates a count value indicating which source line pair the short-circuit detection determination circuit 54 is to detect a short-circuit. FIG. 10 exemplifies a configuration in which only one pair of source lines SLA and SLB is detected for shorts. done. At this time, since the count value of the counter 56 indicates which source line pair is the target of short-circuit detection, the data write circuit 55 writes white to the source line adjacent to the source line pair to be detected. It becomes possible to perform the action to perform. The counter 56 generates a count value by counting based on the clock signal included in the video data signal VDS, for example, triggered by the supply of the mode switching signal MS to the IF/data processing circuit 51 .

FIG. 11 is a diagram showing an example of a short detection screen displayed on the display panel when a short circuit between the source line SLA and the source line SLB is detected.

Since it is in the short detection mode, the entire display panel 11 is displayed in black. In order to indicate that a short-circuit of the source lines SLA and SLB has been detected, the positions corresponding to the source lines SLX and SLY adjacent to the outside with the source lines SLA and SLB sandwiched therebetween are displayed in white.

Next, the processing operation of the short detection processing executed by the source driver of this embodiment will be described with reference to the flowchart of FIG.

The IF/data processing circuit 51 receives a mode switching signal MS requesting switching to the short detection mode, and switches the operation to the short detection mode (STEP 101).

The IF/data processing circuit 51 supplies the short detection mode pixel data pieces PD (pixel data pieces PD corresponding to black in this embodiment) to each latch circuit. A detection mode image (in this embodiment, a black screen) is displayed on the display panel 11 through the generation, amplification, and application of the gradation voltages to the source lines (STEP 102).

The short detection determination circuit 54 detects the presence or absence of the occurrence of a short in the source lines SLA and SLB, and supplies a comparison result signal CRS indicating the detection result to the data write circuit 55 of the IF/data processing circuit 51 . The data write circuit 55 determines whether or not a short circuit is detected based on the comparison result signal CRS (STEP 103).

If it is determined that a short circuit has been detected (STEP 103: YES), the data write circuit 55 writes to the latch circuits corresponding to the source lines SLX and SLY, which are the source lines adjacent to the source lines SLA and SLB in which the occurrence of the short circuit has been detected. , supplies a pixel data piece PD for displaying an image for detecting the occurrence of a short circuit (a white image in this embodiment) at a position on the display screen. After generating, amplifying, and applying the gradation voltage to the source line, a short-circuit detection image is displayed on the display panel 11 to indicate that the occurrence of the short-circuit has been detected (in this embodiment, the source line position adjacent to the short-circuited source line is displayed). white display) is performed (STEP 104).

On the other hand, if it is determined that the occurrence of a short circuit has not been detected (STEP 103: NO), the short circuit detection process ends.

In the source driver of this embodiment, as in the source driver of Embodiment 1, one short-circuit detection determination circuit is provided in the center of the chip, and the source line to be short-circuited can be switched in a time-sharing manner. Therefore, it is possible to detect the occurrence of a short circuit in the source lines for 24 channels.

FIG. 13 is a diagram showing an image of the entire source driver in this embodiment. The short-circuit detection determination circuit 61 performs short-circuit detection while changing the target source line in units of 24 channels in a time division manner under the switching control of the switching control circuit 44 .

The switching control circuit 44 receives an enable signal en indicating the start of execution of the short detection process, and sequentially switches the switch SW2 accordingly. The switch SW2 is provided between the output terminal and the inverting input terminal of the negative amplifier 32n and the detection line JL. By turning on the switch SW2, the output terminal and the inverting input terminal of the negative amplifier 32n are connected to the input terminal of the comparator CM1 in the short detection determination circuit 61. FIG.

The short-circuit occurrence detection circuit 61 is responsible for the other half of the chip and a comparator CM1 that performs voltage comparison on the source lines for 12 channels (6 channels on the positive electrode side and 6 channels on the negative electrode side) in the first region that is responsible for half of the chip constituting the source driver. and a comparator CM2 that performs voltage comparison on the source lines for 12ch in the second region.

A first input terminal of the comparator CM1 is connected to the sensing line JL. A second input terminal of the comparator CM1 is connected to a connection node between the output section of the negative decoder 42n and the non-inverting input terminal of the negative amplifier 32 (that is, negative input voltage inn). The comparator CM1 is at logic level 1 (that is, H level) when the voltage of the detection line JL is higher than the voltage of the negative input voltage inn, and when the voltage of the detection line JL is equal to or lower than the negative input voltage inn. It outputs a comparison result signal CRS having a signal level of logic level 0 (that is, L level). The comparator CM2 also has the same configuration in the second area of the chip and performs the same operation.

The comparators CM 1 and CM 2 supply the comparison result signal CRS to the data write circuit 55 . Based on the comparison result signal CRS, the data write circuit 55 writes to the latch circuit corresponding to the source line adjacent to the source line in which short-circuiting has been detected (that is, the comparison result signal CRS has become logic level 1). , supplies a pixel data piece PD (a pixel data piece corresponding to white in this embodiment) for displaying a short-circuit detection image.

As shown in FIG. 2, the IF/data processing circuit 51 is provided with a counter 56 which counts based on the clock signal and generates a count value. Since the switching of the target source line by the short detection determination circuit 61 is performed in synchronization with the clock signal, based on the count value generated by the counter 56, which source line is currently being detected by the short detection determination circuit 61. can be determined. Based on the count value generated by the counter 56, the data write circuit 55 supplies the pixel data piece PD for the short detection image to the latch circuit connected to the corresponding source line.

As described above, the source driver of this embodiment detects the occurrence of a short circuit between adjacent source line pairs and displays the result on the display panel. Specifically, in the short-circuit detection mode, the entire screen is displayed in black, and when the occurrence of a short-circuit is detected, the position adjacent to the location of occurrence is displayed in white. Such display enables the user to visually recognize that a short has occurred between any of the source lines.

Further, according to the source driver of the present embodiment, since the position of the source line adjacent to the location of the short-circuit is displayed in white, the user can recognize the fact that the short-circuit has occurred and can also identify the location of the short-circuit. Visual identification becomes possible.

Further, according to the source driver of the present embodiment, the above process can be performed without depending on the operation of the timing controller 12. Therefore, the short detection result can be obtained without mounting a special configuration on the timing controller 12. It can be displayed on the display panel 11 .

In addition, this invention is not limited to the said embodiment. For example, in the above embodiments, a plurality of source drivers 14-1 to 14-p are provided, each of which is provided with a voltage comparison circuit as in the above embodiment. However, unlike this, the configuration of the above embodiment can also be applied to a display device provided with only one source driver.

Further, in the above embodiment, the case where the timing controller 12 has a short-circuit judging section (not shown) and judges whether or not there is a short-circuit based on the comparison result signal from the voltage comparator circuit has been described as an example. However, the configuration is not limited to this, and the short circuit determination section may be provided in the source driver 14 or other portions of the display device 100 .

Further, in the above embodiment, the case of detecting the occurrence of a short circuit by comparing the input and output voltages of the negative amplifier 32n has been described as an example. However, unlike this, it is also possible to detect the occurrence of a short circuit by comparing the input and output voltages of the positive amplifier 32p.

Further, in the above embodiment, the case where the gradation voltages of different polarities are supplied to adjacent channels has been described as an example. However, it is possible to apply the configuration of the above embodiment even when grayscale voltages of the same polarity are supplied. For example, by setting the input data of adjacent channels to be different data, a potential difference is provided between the adjacent channels, and a current flows from one channel to the other when a short circuit occurs, thereby detecting a short circuit by voltage comparison. It is possible.

Further, in the third embodiment, an example has been described in which a black screen is displayed on the display panel 11 as the detection mode screen, and the source line position adjacent to the location where the occurrence of the short circuit is detected is displayed in white. However, color selection and display methods are not limited to this. For example, the display panel 11 may display a screen in a color other than black as the detection mode screen. Also, it may be configured to display a specific color other than white when the occurrence of a short circuit is detected. Further, it may be configured such that a specific color is displayed at a position corresponding to another source line instead of the source line adjacent to the source line pair in which the occurrence of the short circuit is detected.

Further, when the occurrence of a short circuit is detected, the entire screen (that is, all source lines other than the short circuit occurrence location) may be displayed in a specific color. According to this method, for example, when the user needs to be aware of the occurrence of the short circuit but does not need to specify the location of the occurrence, it is possible to display the occurrence of the short circuit in a more comprehensible manner. .

In the third embodiment, the short detection determination circuit 54 supplies the comparison result signal CRS to the data write circuit 55. In addition, the timing controller 12 may also be supplied with the comparison result signal CRS. good. According to such a configuration, in addition to displaying the short circuit detection result on the display panel 11, it is possible to perform the short circuit determination in the timing controller 12 in the same manner as in the first embodiment.

Moreover, in the third embodiment, the case of detecting the occurrence of a short circuit by the same method as in the first embodiment has been described as an example. However, unlike this, the method of the second embodiment may be used to detect the occurrence of a short circuit.

100 display device 11 display panel
12 Timing controller 13 Gate driver 14 Source driver 21 Data latch unit 22 Gradation voltage conversion unit 23 Output unit 31p Positive decoder 32p Positive amplifier 31n Negative decoder 32n Negative amplifier 33 Power down signal generator 34 Voltage comparison circuits 41p, 41n LS circuit 42p Positive decoder 42n Negative decoder 44 Switch control circuit 45 Voltage comparison circuit 46 Level down circuit 47 Output circuit

Claims (15)

connected to a display panel having a plurality of source lines and a plurality of pixel units connected to the plurality of source lines; receiving a video data signal including a series of a plurality of pixel data pieces; A source driver for outputting grayscale voltages to be applied to the plurality of pixel units based on
a first gradation voltage generating unit configured to generate a first polarity gradation voltage to be supplied to pixels on a first source line among the plurality of source lines;
a first amplifier that receives the grayscale voltage of the first polarity at an input terminal, amplifies the grayscale voltage of the first polarity, and outputs the amplified grayscale voltage from an output terminal;
generating a gradation voltage of a second polarity opposite to the first polarity to be supplied to pixels on a second source line which is a source line provided adjacent to the first source line; a second gradation voltage generator;
a second amplifier that receives the grayscale voltage of the second polarity at an input terminal, amplifies the grayscale voltage of the second polarity, and outputs the amplified grayscale voltage from an output terminal;
a voltage comparison unit that compares the voltage at the input end of the second amplifier and the voltage at the output end of the second amplifier and outputs a comparison result;
A source driver characterized by having: 2. The source driver according to claim 1, wherein said second amplifier is configured such that its output current is variable. The second amplifier includes a plurality of stages of amplifiers provided in parallel so as to be switchable between connection and non-connection,
3. The source driver according to claim 2, wherein the output current can be changed by switching the number of connected amplifiers among the plurality of stages of amplifiers. the second amplifier has a non-inverting input terminal for receiving the grayscale voltage of the second polarity and an inverting input terminal feedback-connected to the output terminal;
The voltage comparison section includes a first input terminal connected between the output terminal of the second gradation voltage generation section and the non-inverting input terminal of the second amplifier, and the input terminal of the second amplifier. a second input connected between the output and the second source output; and an output for outputting a comparison result between the voltage at the first input and the voltage at the second input. 4. The source driver according to any one of claims 1 to 3, comprising a comparator having and. connected to a display panel having a plurality of source lines and a plurality of pixel units connected to the plurality of source lines; receiving a video data signal including a series of a plurality of pixel data pieces; A source driver for outputting grayscale voltages to be applied to the plurality of pixel units based on
a first gradation voltage generating unit configured to generate a first polarity gradation voltage to be supplied to pixels on a first source line among the plurality of source lines;
a first amplifier that receives the grayscale voltage of the first polarity at an input terminal, amplifies the grayscale voltage of the first polarity, and outputs the amplified grayscale voltage from an output terminal;
a first source output terminal for outputting the voltage output from the first amplifier to the first source line;
A first amplifier provided between the first amplifier and the first source output terminal, one end of which is connected to the output terminal of the first amplifier, and the other end of which is connected to the first source output terminal. a resistive element of
generating a gradation voltage of a second polarity opposite to the first polarity to be supplied to pixels on a second source line which is a source line provided adjacent to the first source line; a second gradation voltage generator;
a second amplifier that receives the grayscale voltage of the second polarity at an input terminal, amplifies the grayscale voltage of the second polarity, and outputs the amplified grayscale voltage from an output terminal;
a second source output terminal for outputting the voltage output from the second amplifier to the second source line;
A second amplifier provided between the second amplifier and the second source output terminal, one end of which is connected to the output terminal of the second amplifier, and the other end of which is connected to the second source output terminal. a resistive element of
Voltage comparison for comparing the voltage at the output end of the second amplifier and the voltage at the connection node between the other end of the second resistor element and the second source output terminal, and outputting the comparison result. Department and
A source driver characterized by having: the second amplifier has a non-inverting input terminal for receiving the grayscale voltage of the second polarity and an inverting input terminal feedback-connected to the output terminal;
The voltage comparison unit includes a first input terminal connected to the inverting input terminal and the output terminal of the second amplifier, the other terminal of the second resistance element, and the second source output terminal. a comparator having a second input terminal connected between and an output terminal for outputting a comparison result between the voltage of the first input terminal and the voltage of the second input terminal; The source driver according to claim 5. When the comparison result of the voltage comparator indicates a predetermined result, a specific voltage is applied to a third source line and a fourth source line that are different from the first source line and the second source line. 7. The source driver according to any one of claims 1 to 6, further comprising a data writing section for writing data corresponding to color display. an interface unit that receives the video data signal and acquires the plurality of pixel data pieces from the received video data signal;
a plurality of latch units provided corresponding to the plurality of source lines for latching and outputting pieces of pixel data from the interface unit;
provided corresponding to the plurality of source lines and including the first grayscale voltage generation section and the second grayscale voltage generation section, each based on the pixel data pieces output from the plurality of latch sections; a plurality of grayscale voltage generators for generating grayscale voltages;
has
The interface section operates in one of a first operation mode and a second operation mode, and in the first operation mode, supplies pixel data pieces according to the video signal to the plurality of latch sections, in the second operation mode, supplying pixel data pieces corresponding to a first color display to the plurality of latch units regardless of the video signal;
The data writing section displays a second color different from the first color display when the interface section operates in the second operation mode and the comparison result of the voltage comparing section indicates a predetermined result. 8. The source driver according to claim 7, wherein a piece of pixel data corresponding to display is supplied to latch sections corresponding to said third source line and said fourth source line. the third source line is provided at a position adjacent to the first source line and facing the second source line across the first source line;
8. The fourth source line is provided at a position adjacent to the second source line and opposed to the first source line with the second source line interposed therebetween. Or the source driver according to 8. a display panel having a plurality of source lines, a plurality of gate lines, and a plurality of pixel portions provided in a matrix at each intersection of the plurality of source lines and the plurality of gate lines;
a source driver that receives a video data signal including a series of a plurality of pixel data pieces and outputs grayscale voltages to be applied to the plurality of pixel units based on the video data signal;
has
The source driver is
a first gradation voltage generating unit configured to generate a first polarity gradation voltage to be supplied to pixels on a first source line among the plurality of source lines;
a first amplifier that receives the grayscale voltage of the first polarity at an input terminal, amplifies the grayscale voltage of the first polarity, and outputs the amplified grayscale voltage from an output terminal;
generating a gradation voltage of a second polarity opposite to the first polarity to be supplied to pixels on a second source line which is a source line provided adjacent to the first source line; a second gradation voltage generator;
a second amplifier that receives the grayscale voltage of the second polarity at an input terminal, amplifies the grayscale voltage of the second polarity, and outputs the amplified grayscale voltage from an output terminal;
a voltage comparison unit that compares the voltage at the input end of the second amplifier and the voltage at the output end of the second amplifier and outputs a comparison result;
A display device comprising: a display panel having a plurality of source lines, a plurality of gate lines, and a plurality of pixel portions provided in a matrix at each intersection of the plurality of source lines and the plurality of gate lines;
a source driver that receives a video data signal including a series of a plurality of pixel data pieces and outputs grayscale voltages to be applied to the plurality of pixel units based on the video data signal;
has
The source driver is
a first gradation voltage generating unit configured to generate a first polarity gradation voltage to be supplied to pixels on a first source line among the plurality of source lines;
a first amplifier that receives the grayscale voltage of the first polarity at an input terminal, amplifies the grayscale voltage of the first polarity, and outputs the amplified grayscale voltage from an output terminal;
a first source output terminal for outputting the voltage output from the first amplifier to the first source line;
A first amplifier provided between the first amplifier and the first source output terminal, one end of which is connected to the output terminal of the first amplifier, and the other end of which is connected to the first source output terminal. a resistive element of
generating a gradation voltage of a second polarity opposite to the first polarity to be supplied to pixels on a second source line which is a source line provided adjacent to the first source line; a second gradation voltage generator;
a second amplifier that receives the grayscale voltage of the second polarity at an input terminal, amplifies the grayscale voltage of the second polarity, and outputs the amplified grayscale voltage from an output terminal;
a second source output terminal for outputting the voltage output from the second amplifier to the second source line;
A second amplifier provided between the second amplifier and the second source output terminal, one end of which is connected to the output terminal of the second amplifier, and the other end of which is connected to the second source output terminal. a resistive element of
Voltage comparison for comparing the voltage at the output end of the second amplifier and the voltage at the connection node between the other end of the second resistor element and the second source output terminal, and outputting the comparison result. Department and
A display device comprising: A short-circuit determination unit that determines whether or not a short-circuit has occurred between the first source line and the second source line based on the comparison result of the voltage comparison unit. 12. The display device according to Item 10 or 11. The source driver, when the comparison result of the voltage comparison unit indicates a predetermined result, causes a third source line and a fourth source line, which are source lines different from the first source line and the second source line. 13. The display device according to any one of claims 10 to 12, further comprising a data writing section for writing data corresponding to a specific color display to the source line. The source driver is
an interface unit that receives the video data signal and acquires the plurality of pixel data pieces from the received video data signal;
a plurality of latch units provided corresponding to the plurality of source lines for latching and outputting pieces of pixel data from the interface unit;
provided corresponding to the plurality of source lines and including the first grayscale voltage generation section and the second grayscale voltage generation section, each based on the pixel data pieces output from the plurality of latch sections; a plurality of grayscale voltage generators for generating grayscale voltages;
has
The interface section operates in one of a first operation mode and a second operation mode, and in the first operation mode, supplies pixel data pieces according to the video signal to the plurality of latch sections, in the second operation mode, supplying pixel data pieces corresponding to a first color display to the plurality of latch units regardless of the video signal;
The data writing section displays a second color different from the first color display when the interface section operates in the second operation mode and the comparison result of the voltage comparing section indicates a predetermined result. 14. The display device according to claim 13, wherein pixel data pieces corresponding to display are supplied to latch sections corresponding to said third source line and said fourth source line. the third source line is provided at a position adjacent to the first source line and facing the second source line across the first source line;
13. The fourth source line is provided at a position adjacent to the second source line and opposed to the first source line with the second source line interposed therebetween. Or the display device according to 14.

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