JP2022151587A - キャップが低減された自己整合ゲートエンドキャップ（ｓａｇｅ）アーキテクチャ - Google Patents

キャップが低減された自己整合ゲートエンドキャップ（ｓａｇｅ）アーキテクチャ Download PDF

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JP2022151587A
JP2022151587A JP2022004048A JP2022004048A JP2022151587A JP 2022151587 A JP2022151587 A JP 2022151587A JP 2022004048 A JP2022004048 A JP 2022004048A JP 2022004048 A JP2022004048 A JP 2022004048A JP 2022151587 A JP2022151587 A JP 2022151587A
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gate
dielectric
gate electrode
integrated circuit
trench contact
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JP2022151587A5 (https=
Inventor
フーン スン セウン
Seung Hoon Sung
トロニック トリスタン
Tronic Tristan
エス． リアオ スズヤ
S Liao Szuya
ティー． カバリエロス ジャック
T Kavalieros Jack
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Intel Corp
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Intel Corp
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Priority to JP2024228683A priority Critical patent/JP2025069125A/ja
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    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
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    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
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    • H10D84/0135—Manufacturing their gate conductors

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2022004048A 2021-03-24 2022-01-14 キャップが低減された自己整合ゲートエンドキャップ（ｓａｇｅ）アーキテクチャ Pending JP2022151587A (ja)

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JP2024228683A JP2025069125A (ja) 2021-03-24 2024-12-25 キャップが低減された自己整合ゲートエンドキャップ（ｓａｇｅ）アーキテクチャ

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US17/211,751 US20220310818A1 (en) 2021-03-24 2021-03-24 Self-aligned gate endcap (sage) architectures with reduced cap
US17/211,751 2021-03-24

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JP2022151587A true JP2022151587A (ja) 2022-10-07
JP2022151587A5 JP2022151587A5 (https=) 2024-10-30

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JP2024228683A Pending JP2025069125A (ja) 2021-03-24 2024-12-25 キャップが低減された自己整合ゲートエンドキャップ（ｓａｇｅ）アーキテクチャ

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12170203B2 (en) * 2021-07-23 2024-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit with conductive via formation on self-aligned gate metal cut
US20230180451A1 (en) * 2021-12-03 2023-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Structure With Source/Drain Contact Plugs And Method For Forming The Same
US20230197826A1 (en) * 2021-12-21 2023-06-22 Christine RADLINGER Self-aligned gate endcap (sage) architectures with improved cap

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180138092A1 (en) * 2016-11-14 2018-05-17 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US20190363085A1 (en) * 2018-05-25 2019-11-28 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US20200286890A1 (en) * 2019-03-06 2020-09-10 Intel Corporation Self-aligned gate endcap (sage) architecture having gate contacts
US20200303373A1 (en) * 2017-12-28 2020-09-24 Intel Corporation Pmos and nmos contacts in common trench

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11217582B2 (en) * 2018-03-30 2022-01-04 Intel Corporation Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls
US11329138B2 (en) * 2018-04-02 2022-05-10 Intel Corporation Self-aligned gate endcap (SAGE) architecture having endcap plugs
US12057491B2 (en) * 2019-01-03 2024-08-06 Intel Corporation Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180138092A1 (en) * 2016-11-14 2018-05-17 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US20200303373A1 (en) * 2017-12-28 2020-09-24 Intel Corporation Pmos and nmos contacts in common trench
US20190363085A1 (en) * 2018-05-25 2019-11-28 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US20200286890A1 (en) * 2019-03-06 2020-09-10 Intel Corporation Self-aligned gate endcap (sage) architecture having gate contacts

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JP2025069125A (ja) 2025-04-30
US20250022936A1 (en) 2025-01-16
US20250142935A1 (en) 2025-05-01
US20220310818A1 (en) 2022-09-29

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