JP2022146993A - Filter operation circuit, data transmission circuit, and protective relay device - Google Patents

Abstract

To provide a filter operation circuit, a data transmission circuit, and a protective relay device that can combine multiple stages of digital filters according to the number of analog inputs, and improves the efficiency of a multiplier of the filter operation circuit by freely designing the filter operation circuit according to a desired system.SOLUTION: In a data transmission circuit, a filter operation block 201 of a filter operation unit includes a MUX 2411 that can receive two pieces of data, an IIR filter 2511 connected to the output side of the MUX 2411, a delay unit 2611 that adjusts the delay caused by the calculation of the IIR filter 2511 with respect to the input of one data, a MUX 2421 connected to the output side of IIR filter 2511 and the delay unit 2611, an IIR filter 2521 connected to the output side of the MUX 2421, and a delay unit 2621 that adjusts the delay caused by the calculation of the IIR filter 2521 with respect to the output data of the IIR filter 2511.SELECTED DRAWING: Figure 2

Description

The present invention relates to a technology of a protection relay device for analog-to-digital conversion of analog amounts of voltage and current of a power system, and more particularly to a technique of performing digital filter processing on converted digital amounts.

When the analog amounts of the voltage and current of the electric power system are supplied to a protection relay device (Patent Document 1) that performs A/D (analog-to-digital) conversion, they are first filtered by a digital filter connected to the A/D conversion means. be done. Then, it is subjected to computation by a CPU (Central Processing Unit) via a buffer memory and a system bus.

JP 2011-135709 A

The analog-to-digital converted digital quantity is filtered by a digital signal processing unit in an SoC (System-on-a-chip), and then supplied to the CPU for necessary processing.

Processing by the digital signal processing unit uses a dedicated block such as a multiplier built into the SoC, but the number of dedicated blocks is limited. Also, the upper limit of the number of analog inputs is determined by the physical structure of the system. When the same filter processing is implemented for each analog input in accordance with the upper limit of the number of analog inputs, if the number of analog inputs is less than the upper limit, some filters will not be used, and the usage rate of multipliers will decrease.

In view of the above circumstances, the present invention makes it possible to combine multiple stages of digital filters according to the number of analog inputs, and by freely designing the filter operation circuit according to the desired system, the efficiency of the multiplier of the filter operation circuit is improved. The challenge is to make it more flexible.

Accordingly, one aspect of the present invention provides a first multiplexer capable of inputting two data, a first digital filter connected to the output side of the first multiplexer, and the first A first delay unit for adjusting delay caused by the operation of the digital filter, a second multiplexer connected to the output side of the first digital filter and the first delay unit, and connected to the output side of the second multiplexer A filter operation circuit comprising: a second digital filter; and a second delay section for adjusting a delay caused by operation of the second digital filter with respect to output data of the first digital filter.

In one aspect of the present invention, the filter arithmetic circuit includes a filter coefficient register that stores filter coefficients of the first digital filter and the second digital filter.

One aspect of the present invention is a data transmission circuit comprising a plurality of the filter operation circuits, wherein the output data of the second digital filter of one of the filter operation circuits is input to the first multiplexer of the other filter operation circuits. is.

One aspect of the present invention is a protection relay device including the data transmission circuit.

According to the present invention described above, it is possible to combine a plurality of stages of digital filters according to the number of analog input points. is planned.

1 is a block configuration diagram of a data transmission circuit that is one embodiment of the present invention; FIG. 4 is a block configuration diagram of a filter operation circuit in the data transmission circuit; FIG.

Embodiments of the present invention will be described below with reference to the drawings.

A data transmission circuit 1 according to one aspect of the present invention shown in FIG. 1 aims to increase the number of analog input points by connecting analog conversion boards with a sampling data bus. In particular, in a digital filter operation circuit that filters digital data obtained by sampling a plurality of analog quantities using hardware having a fixed number of multipliers, the number of stages of filtering performed on one analog input is set to the number of analog input points. can be changed accordingly. As a result, it is possible to combine a plurality of stages of digital filters according to the number of analog inputs, and it is possible to freely design a filter operation circuit according to a desired system, so that the efficiency of the multiplier is increased.

Further, in this aspect, by securing a sampling data bus for transmitting digital data obtained by simultaneously sampling a plurality of analog amounts and a general-purpose bus for control, the number of analog inputs can be easily expanded with a simple configuration. It is also possible to increase the number of input points by other peripheral transmission means instead of the sampling data bus. It becomes available.

[Example of Mode of Data Transmission Circuit 1]
The data transmission circuit 1 has an SoC 101 and an A/D converter 102 connected to this SoC 101 .

The A/D converter 102 is provided with analog input signals 111, 112, . . . , 11m.

The SoC 101 implements an internal bus 100 , a CPU 103 , a timing controller 104 , a RAM 105 , an A/D converter controller 106 , a filter calculator 107 , and DMACs (Direct Memory Access Controllers) 108 and 109 . A CPU 103 , a timing control unit 104 , a RAM 105 , a filter calculation unit 107 and DMACs 108 and 109 are connected to the internal bus 100 . Timing control section 104 is further connected to A/D converter control section 106 . This A/D converter control section 106 is further connected to the A/D converter 102 , filter calculation section 107 and DMAC 109 .

As shown in FIG. 2, the filter operation unit 107 implements filter operation blocks 201, 202, . . . , 20m as a plurality of digital filter operation circuits.

, 20m receives input data 2111, 2112, 2121, 2122, . , 221m, 2221, 2222, . . . , 222m and filter coefficients 2311, 2312, . , 281m, 282m are output.

The filter operation blocks 201, 202, . . . , 20m have the same structure.

The filter operation block 201 comprises an MUX 2411, an IIR filter 2511, a delay section 2611, a MUX 2421, an IIR filter 2521 and a delay section 2621, as shown in FIG.

The MUX 2411 is a first multiplexer capable of inputting two data, and supplies either one of the two data to the IIR filter 2511 based on the input switching signal 2211 from the CPU 103 . For example, input data 2111 and a zero value (000h) are input as the two data.

IIR Filter 2511 is a first infinite impulse response filter as a first digital filter connected to the output side of MUX 2411 .

The delay unit 2611 is a first delay unit that adjusts the delay caused by the calculation of the IIR filter 2511 with respect to the input of one point of data (input data 2121).

The MUX 2421 is a second multiplexer connected to the IIR filter 2511 and the output side of the delay unit 2611 , and provides the IIR filter 2511 or the output signal of the delay unit 2611 to the IIR filter 2521 based on the input switching signal 2221 from the CPU 103 .

IIR Filter 2521 is a second infinite impulse response filter as a second digital filter connected to the output side of MUX 2421 .

The delay unit 2621 is a second delay unit that adjusts the delay caused by the calculation of the IIR filter 2521 with respect to the input data from the IIR filter 2511 .

The filter operation blocks 202, .

In particular, the MUX 2412 of the filter operation block 202 is provided with, as two input data, the input data 2112 and the output data 2821 from the IIR Filer 2521 of the filter operation block 201, which is one block before the filter operation block 202. .

Similarly, the MUX 241m of the filter operation block 20m receives, as two input data, the input data 211m and the output data from the second infinite impulse response filter of the filter operation block one block before the filter operation block 20m. provided.

[Example of operation of data transmission circuit 1]
An operation example of the data transmission circuit 1 of the present embodiment will be described with reference to FIGS.

CPU 103 generates a predetermined sampling timing from timing control section 104 via internal bus 100 . , 11m are converted into digital data by the A/D converter 102 according to this sampling timing, and then input to the A/D converter control section 106 of the SoC 101 .

Data stored in the A/D converter control section 106 is transmitted to the filter calculation section 107 and the DMAC 109 . , 221m, 2221, 2222, . . . , 222m and filter coefficients 2311, 2312, . 107.

The filter calculation unit 107 performs filtering according to the contents of the setting, and transmits the filtered data to the DMAC 108 . The DMAC 108 and DMAC 109 store data in the RAM 105 according to the settings made by the CPU 103 .

As shown in FIG. 2, in filter operation section 107 , filter operation block 201 stores input data 2111 and 2121 from A/D converter control section 106 .

Either input data 2111 or zero value (000h) is selected by MUX 2411 based on input switching signal 2211 and input to IIR filter 2511 as the output signal of MUX 2411 .

The IIR Filter 2511 uses the filter coefficient 2311 set in the filter coefficient register 2711 by the CPU 103 to perform filter arithmetic processing.

The output result of IIR Filter 2511 is input to MUX 2421 . Input data 2121 is input to MUX 2421 via delay section 2611 in order to balance the delay due to the computation in IIR Filter 2511 . The MUX 2421 outputs either the output signal of the IIR filter 2511 or the output signal of the delay unit 2611 based on the input switching signal 2221 .

The output signal of the MUX 2421 is input to the IIR Filter 2521 , and the IIR Filter 2521 performs a predetermined filtering operation according to the filter coefficient register 2711 and outputs output data 2821 .

The output signal of the IIR Filter 2511 is output as the output data 2811 via the delay section 2621 in order to balance the delay due to the calculation in the IIR Filter 2521 .

The filter operation block 202 operates in the same manner as the filter operation block 201 except that the output data 2821 of the filter operation block 201 is input instead of the zero value input to the MUX 2412 .

Since a plurality of filter operation blocks can be connected in the filter operation unit 107, a filter with an arbitrary number of stages can be configured. Since filter coefficients can be set for each IIR filter using a filter coefficient register, various filtering processes such as low-pass filtering and high-pass filtering can be implemented.

A configuration method of a filter when there are filter operation blocks 201, 202, 203, and 204 with the number of filter operation blocks m=4 is shown.

(1st stage filter)
By using the output of the MUX 2411 of the filter operation block 201 as the input data 2111 and the output of the MUX 2421 as the output of the delay unit 2611, the input data 2111 is filtered by the IIR filter 2511, and the filter processing result is passed through the delay unit 2621. output as output data 2811 via the On the other hand, the input data 2121 is filtered by the IIR filter 2521 through the delay unit 2621 and the MUX 2421, and the result of this processing is output as the output data 2821. FIG. One stage of IIR filtering can be performed on two pieces of input data per block.

(2-stage filter)
By using the output of the MUX 2411 of the filter operation block 201 as the input data 2111 and the output of the MUX 2421 as the output of the IIR filter 2511, the input data 2111 is filtered by the IIR filter 2511 and the IIR filter 2521, and the processing result is It is output as output data 2821 . Two-stage IIR filter processing can be performed on one point of input data per block.

(three-stage filter)
By using the output of the MUX 2411 of the filter operation block 201 as the input data 2111 and the output of the MUX 2421 as the output of the IIR Filter 2511, the input data 2111 is filtered by the IIR Filter 2511 and the IIR Filter 2521, and the processing result is output. Output as data 2821 . By using the output of the MUX 2412 of the filter operation block 202 as the output data 2821 and the output of the MUX 2422 as the input data 2122, the output of the IIR filter 2512 is output as the output data 2812 via the delay unit 2622, and the data of the input data 2122 is output as output data 2822 via the delay section 2612, MUX 2422, and IIR Filter 2522. That is, the input data 2111 passes through the IIR filter three times to become the output data 2812, and the input data 2122 passes through the IIR filter once to become the output data 2822. With two blocks, three-stage IIR filter processing and one-stage IIR filter processing can be performed on one point of input data.

(4-stage filter)
By setting the output of the MUX 2411 of the filter operation block 201 as the input data 2111 and the output of the MUX 2421 as the output of the IIR filter 2511, the input data 2111 is filtered by the IIR filter 2511 and the IIR filter 2521, and the processing result is the output data. 2821 is output. The output of the MUX 2412 of the filter operation block 202 is used as the output data 2821 and filtered by the IIR 2512 . The output of the MUX 2422 is used as the output of the IIR Filter 2512 , filtering is performed by the IIR Filter 2522 , and the result of this processing is output as output data 2822 . That is, the input data 2111 passes through the IIR Filter four times. With two blocks, four-stage IIR filter processing can be performed on one point of input data.

Similarly, 5-stage, 6-stage, 7-stage, and 8-stage filters can be constructed. The number of filter stages can be combined arbitrarily according to the number of input data points.
For example, if the number of input data points is 2,
・1-stage filter x 1 input + 7-stage filter x 1 input ・2-stage filter x 1 input + 6-stage filter x 1 input ・3-stage filter x 1 input + 5-stage filter x 1 input ・4-stage filter x 1 input + 4-stage filter x 1 input can be constructed,
When the number of input data points is 5,
・1-stage filter x 4 inputs + 4-stage filter x 1 input ・1-stage filter x 3 inputs + 2-stage filter x 1 input + 3-stage filter x 1 input ・1-stage filter x 2 inputs + 2-stage filter x 3 inputs .

Table 1 shows combinations of the number of input data points and the number of filter stages when m=4. The table shows the number of input data points in the row direction and the number of filter steps in the column direction. When the number of filter operation blocks m=4, 19 combinations of filters are possible.

The configuration of the IIR filter of this embodiment is configured by applying a dedicated block such as a multiplier built into the SoC 101 . The number of filter operation blocks m and the number of filter stages per block in the IIR Filter block can be designed according to the number of dedicated blocks such as multipliers built into SoC 101 and the minimum number of filter stages required by the system. It is possible.

According to the data transmission circuit 1 described above, since the input signal of the IIR filter can be switched using the MUX, it is possible to pass through one or two stages of IIR filters in one filter operation block, and furthermore, different blocks IIR filter processing can also be performed on the output data of . Also, since a plurality of different blocks can be combined, the number of filter stages can be freely set within the range of the number of filter operation blocks. Furthermore, since the number of filter stages can be freely set according to the number of input data points and the number of filter operation blocks, filter operations can be performed flexibly from systems with a small number of input data points but many filter stages to systems with a large number of input data points but few filter stages. It can be carried out.

A specific application example of the data transmission circuit 1 is a protection relay device. Examples of protective relay devices include devices for preventing equipment damage and power outages caused by accidents such as lightning strikes, birds and animals, and short circuits caused by wind and snow, and for quick recovery. The protection relay device samples the voltage and current of the electric power system at regular intervals, performs fault determination by the CPU, and outputs a trip instruction to the circuit breaker.

More specific examples of the protective relay device include a busbar protection relay for protecting a busbar in a substation and a generator protection relay in a power station. Since the busbar protection relay protects the busbar in the premises of the substation, the number of input data points is as large as about 150 points, but the IIR filter may be a two-stage low-pass filter. On the other hand, since the generator protection relay targets the generator, the number of input data points is about 25, which is less than the bus protection relay. The IIR filter requires a 4-stage bandpass filter to cope with driving. By using the present invention, it can be flexibly applied to systems with different numbers of input data points and IIR filter stages, such as bus protection relays and generator protection relays.

An IIR filter is applied to the data transmission circuit 1 of the above embodiment, but even if an FIR filter (finite impulse response filter), which is a digital filter other than the IIR filter, is applied, the same effect as that of the embodiment can be obtained. be done.

Reference Signs List 1 Data transmission circuit 101 SoC 102 A/D converter 100 Internal bus 103 CPU 104 Timing controller 105 RAM 106 A/D converter control section 107 Filter operation part, 108, 109...DMAC
201, 202, 20m... filter calculation blocks 2411, 2412... MUX, 2511, 2512... IIR Filter, 2611, 2612... delay section, 2421, 2422... MUX, 2521, 2522... IIR Filter, 2621, 2622... delay section

Claims (4)

a first multiplexer capable of inputting two data;
a first digital filter connected to the output side of the first multiplexer;
a first delay unit that adjusts the delay caused by the operation of the first digital filter with respect to the input of one data;
a second multiplexer connected to the output side of the first digital filter and the first delay unit;
a second digital filter connected to the output side of the second multiplexer;
a second delay unit that adjusts the delay caused by the calculation of the second digital filter with respect to the output data of the first digital filter;
A filter operation circuit, comprising: 2. The filter operation circuit according to claim 1, further comprising a filter coefficient register for storing filter coefficients of said first digital filter and said second digital filter. A plurality of filter operation circuits according to claim 1 or 2,
A data transmission circuit, wherein the output data of said second digital filter of one said filter operation circuit is input to said first multiplexer of another said filter operation circuit. A protection relay device comprising the data transmission circuit according to claim 3 .

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