JP2022144775A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device with a built-in snubber circuit, which is flexibly applicable to various electrical equipment.SOLUTION: A semiconductor device 100, in which a cell region A1 and a peripheral region A2 are defined, comprises: a semiconductor substrate 110 having a drift layer 112, a base region 113, and a source region 114; a source electrode 120; a gate wiring 140 having a first gate wiring part 141 and a second gate wiring part 142 arranged at positions at which the first gate wiring part 141 and the second gate wiring part 142 face each other with the source electrode 120 therebetween; a shield wiring 140 having a first shield wiring part 141 and a second shield wiring part 142 arranged at positions at which the first shield wiring part 141 and the second shield wiring part 142 face each other; a plurality of trenches 151; a gate electrode 153; a shield electrode 154; and an insulation region 155. The shield wiring 140 is electrically connected with the source electrode 120 through a snubber resistance adjustment part 160 having a resistance component.SELECTED DRAWING: Figure 1

Description

The present invention relates to semiconductor devices.

2. Description of the Related Art Conventionally, there is known a semiconductor device having a shield gate structure in which a gate electrode and a shield electrode for a source potential are formed in a trench (see, for example, Japanese Unexamined Patent Application Publication No. 2002-100000). As a semiconductor device having such a shield gate structure, the following semiconductor device can be considered (semiconductor device 900 according to background art).

As shown in FIG. 11A, a semiconductor device 900 according to the background art includes a cell area A1 and a peripheral area A2 in plan view. A semiconductor device 900 according to the background art includes a semiconductor substrate 910 , a source electrode 920 , a gate wiring 930 , a shield wiring 940 and a plurality of trenches 951 .

A semiconductor device 900 according to the background art includes a gate insulating film 952, a gate electrode 953, a shield electrode 954, an insulating region 955, an interlayer insulating film 980, and a drain electrode 990, as shown in FIG. Prepare. The semiconductor substrate 910 includes an n-type (n ⁺ -type) low-resistance semiconductor layer 911, an n-type (n ⁻ -type) drift layer 912 formed in the cell region A1 and the peripheral region A2, and the drift layer 912 in the cell region A1. It has a p-type base region 913 formed on the surface and an n-type (n ⁺ -type) source region 914 formed on part of the surface of the base region 913 .

Source electrode 920 is arranged on the surface of semiconductor substrate 910 in cell region A1 with interlayer insulating film 980 interposed therebetween, and is connected to semiconductor substrate 910 through metal plug Pg3.
The gate wiring 930 is arranged on the surface of the semiconductor substrate 910 in the peripheral region A2 with an interlayer insulating film 980 interposed therebetween. It has a wiring portion 932 and a gate pad 933 .
The shield wiring 940 is arranged on the surface of the semiconductor substrate 910 in the peripheral region A2 with an interlayer insulating film 980 interposed therebetween, and is positioned to face each other with the first gate wiring portion 931, the source electrode 920 and the second gate wiring portion 932 interposed therebetween. It has a first shield wiring portion 941 and a second shield wiring portion 942 which are arranged in the same direction.

In the semiconductor device 900 according to the background art, the end portion of the first shield wiring portion 941 and the end portion of the second shield wiring portion 942 are electrically connected to the source electrode 920 via relatively wide connection wiring ( See the area surrounded by the dashed line A in FIG. 11(a)). Therefore, the potential of the shield wiring 940 is the same as the potential of the source electrode 920 .

In the semiconductor device 900 according to the background art, the shield electrode 954 is made of polysilicon and has internal resistance. In addition, since the insulating region 955 that separates the drift layer 912 and the shield electrode 954 is provided, there is a parasitic capacitance between the shield electrode 954 and the drain electrode 990 that are at the source potential. Therefore, the internal resistance of the shield electrode 954 and the parasitic capacitance between the shield electrode 954 and the drift layer 912 are connected in series between the source electrode 920 and the drain electrode 990 in the semiconductor device. , and a snubber circuit is formed secondarily. Therefore, the semiconductor device 900 according to the background art is a semiconductor device with a built-in snubber circuit.

Japanese Patent No. 4790908

However, in the semiconductor device 900 according to the background art, the parasitic capacitance between the shield electrode 954 and the drain electrode 990 and the internal resistance of the shield electrode 954 are determined by designing the semiconductor device based on the characteristics of the MOSFET. Therefore, it is difficult to change the snubber circuit characteristics (for example, snubber resistance) according to the electrical equipment to be used. , there is a problem.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device with a built-in snubber circuit that can be flexibly applied to various electric devices.

A semiconductor device according to the present invention is a semiconductor device in which a cell region and a peripheral region formed in a region surrounding the cell region are defined in plan view, wherein the cell region and the peripheral region are formed A drift layer of a first conductivity type, a base region of a second conductivity type formed on the surface of the drift layer at least in the cell region, and a source of the first conductivity type formed on a part of the surface of the base region. a source electrode arranged on the surface of the semiconductor substrate in at least the cell region with an interlayer insulating film interposed therebetween; and arranged on the surface of the semiconductor substrate in the peripheral region with an interlayer insulating film interposed therebetween. a gate wiring having a first gate wiring portion and a second gate wiring portion arranged at positions facing each other with the source electrode interposed therebetween when viewed in plan; and an interlayer on the surface of the semiconductor substrate in the peripheral region. A first shield wiring portion and a second shield which are arranged with an insulating film interposed therebetween and which are arranged at positions facing each other with the first gate wiring portion, the source electrode and the second gate wiring portion interposed in a plan view. a shield wiring having a wiring portion; and a region formed in parallel on the surface of the semiconductor substrate and overlapping with the second shield wiring portion across the cell region from a region overlapping with the first shield wiring portion in plan view. in the cell region, a plurality of trenches formed with a depth reaching the drift layer, and a gate insulating film formed on the inner surface of the trench inside each of the plurality of trenches. a gate electrode connected to the gate wiring portion in the peripheral region; In a peripheral region, a shield electrode connected to the first shield wiring portion and the second shield wiring portion; an insulating region separating the shield electrode from the electrode and extending between the inner surface of the trench and the shield electrode to separate the shield electrode from the inner surface of the trench; It is electrically connected to the source electrode via a snubber resistance adjusting section.

According to the semiconductor device of the present invention, since the shield wiring is electrically connected to the source electrode via the snubber resistance adjustment section having a resistance component, a MOSFET is included in the current path between the drain electrode and the source electrode. A resistance component other than the resistance component determined by the design of the semiconductor device based on the characteristics of can be added. Therefore, by adjusting the resistance component of the snubber resistance adjusting section, it is possible to change the characteristics of the snubber resistance and thus the characteristics of the snubber circuit according to the electrical equipment using the semiconductor device without changing the characteristics of the MOSFET. As a result, a semiconductor device with a built-in snubber circuit can be flexibly applied to various electric devices.

1 is a diagram for explaining the semiconductor device 100 according to Embodiment 1; FIG. 1(a) is a plan view of the semiconductor device 100, FIG. 1(b) is a cross-sectional view taken along line AA of FIG. 1(a), and FIG. 1(c) is a line BB of FIG. 1(a). It is a sectional view. It is a CC cross-sectional view of FIG. 1(a). 4 is an enlarged plan view of a main part shown for explaining the snubber resistance adjusting section 160 according to the first embodiment; FIG. The illustration of the peripheral trench structure 170 is omitted except for the outermost peripheral trench structure 170b. 4 is a diagram for explaining the snubber circuit of the semiconductor device 100 according to the first embodiment; FIG. 4(a) is an equivalent circuit of the semiconductor device 100, FIG. 4(b) is a diagram for explaining the capacitance of the snubber circuit, and FIG. 4(c) is for explaining the resistance of the snubber circuit. is a diagram for FIG. 11 is an enlarged plan view of a main part shown for explaining a snubber resistance adjusting section 160a in Embodiment 2; FIG. 11 is an enlarged plan view of a main part shown for explaining a snubber resistance adjusting section 160b in Embodiment 3; FIG. 14 is an enlarged plan view of a main part shown for explaining a snubber resistance adjusting section 160c in Embodiment 4; FIG. 16 is an enlarged plan view of a main part shown for explaining a snubber resistance adjusting section 160d in Embodiment 5; It is a figure shown in order to demonstrate the semiconductor device 105 which concerns on Embodiment 6. FIG. 9A is a plan view of the semiconductor device 105, and FIG. 9B is an enlarged plan view of the semiconductor device 105. FIG. FIG. 21 is a diagram for explaining a snubber resistance adjusting section 160e according to a sixth embodiment; FIG. FIG. 10(a) is an enlarged plan view of a main part for explaining a snubber resistance adjusting portion 160e in the semiconductor device 105, and FIG. 10(b) is a cross-sectional view taken along line DD of FIG. 10(a). FIG. 10(a) shows the state of the semiconductor substrate 110 in the same region as the region shown in FIG. 9(b). It is a figure shown in order to demonstrate the semiconductor device 900 based on background art. 11(a) is a plan view of the semiconductor device 900, and FIG. 11(b) is a cross-sectional view taken along line EE of FIG. 11(a).

A semiconductor device of the present invention will be described below based on embodiments shown in the drawings. Each drawing is a schematic diagram and does not necessarily strictly reflect actual dimensions. Each embodiment described below does not limit the invention according to the scope of claims. Also, not all of the elements and their combinations described in each embodiment are essential to the solution of the present invention. In each embodiment, the same basic configuration, features, functions, etc. are the same configuration, elements (including components whose shape etc. are not completely the same.) may be omitted.

[Embodiment 1]
1. Configuration of the semiconductor device 100 according to the first embodiment
As shown in FIG. 1A, the semiconductor device 100 according to the first embodiment is a trench gate type semiconductor device (MOSFET) including a cell region A1 and a peripheral region A2 defined in a region surrounding the cell region A1. is. The cell region A1 is a region in which a source electrode 120 is arranged on one surface of the semiconductor substrate 110 (hereinafter simply referred to as the surface) and a vertical MOSFET is formed.

As shown in FIG. 1A, the semiconductor device 100 according to the first embodiment includes a semiconductor substrate 110, a source electrode 120, a gate wiring 130, a shield wiring 140, a plurality of trenches 151, connection trenches 157, 158, a snubber resistance adjustment portion 160, and a peripheral trench structure 170 (170b). The semiconductor substrate 110 has a rectangular shape with long sides X1, X2 and short sides X3, X4 when viewed two-dimensionally. The multiple trenches 151 extend from the long side X1 toward the long side X2.
Further, the semiconductor device 100 according to the first embodiment includes an interlayer insulating film 180 and a drain electrode 190, as shown in FIGS. 1(b) and 1(c).

As shown in FIGS. 1A to 1C, the semiconductor substrate 110 is formed on the n ⁺ -type low-resistance semiconductor layer 111 and the low-resistance semiconductor layer 111, and the impurity concentration is lower than that of the low-resistance semiconductor layer 111. n ⁻ -type drift layer 112 with a low concentration, p-type base region 113 formed on the surface of the drift layer 112 at least in the cell region A1, and formed on the surface of the base region 113 with an impurity concentration higher than that of the drift layer 112. n ⁺ -type source region 114 with a high . and a p-type peripheral diffusion region 115 formed on the surface.

The thickness of the low-resistance semiconductor layer 111 is 50 μm to 500 μm (eg, 350 μm), and the impurity concentration of the low-resistance semiconductor layer 111 is 1×10 ¹⁸ cm ⁻³ to 1×10 ²¹ cm ⁻³ (eg, 1×10 ¹⁹ cm ^-3 ). The thickness of the drift layer 112 in the region where the trench 151 is not formed is 3 μm to 50 μm (eg, 15 μm), and the impurity concentration of the drift layer 112 is 1×10 ¹⁴ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ (eg, 1×10 ¹⁵ cm ⁻³ ). The depth of the base region 113 and the peripheral diffusion region 115 is 0.5 μm to 10 μm (eg, 5 μm), and the impurity concentration of the base region 113 and the peripheral diffusion region 115 is 1×10 ¹⁶ cm ⁻³ to 1×10 ¹⁹ cm. ⁻³ (for example, 1×10 ¹⁷ cm ⁻³ ).

As shown in FIG. 1A, the source electrode 120 covers the entire cell region A1 and extends along the axis from the short side X3 to the short side X4 to the region overlapping the peripheral region A2 on the short side X4 side. It has a substantially rectangular shape. In other words, when viewed from the source electrode 120, the source electrode 120 extends in the direction (long side X1 side) in which the first shield wiring portion 141 and the first gate wiring portion 131, which will be described later, are arranged, and in the second shield wiring portion. 142 and the second gate wiring portion 132 along the direction (the direction from the short side X3 side to the short side X4) different from the direction (long side X2 side) in which the second gate wiring portion 132 is arranged, extending to the region overlapping the peripheral region A2. is doing.
The source electrode 120 has five source electrode side connection portions 121 protruding toward the long side X1 side (first shield wiring portion 141 side) in the peripheral region A2 extending on the short side X4 side, and five source electrode side connection portions 122 projecting toward the X2 side (the second shield wiring portion 142 side).

As shown in FIGS. 1B and 1C, the source electrode 120 is arranged on the surface of the semiconductor substrate 110 with an interlayer insulating film 180 interposed therebetween. ), contact is made with the source region 114 and the base region 113 through the metal plug Pg3 in the contact hole formed in the interlayer insulating film 180, and in the peripheral region A2, as shown in FIG. The peripheral trench 171 in the peripheral trench structure 170b on the outermost side (short side X4 side) of the peripheral trench structure 170 through the metal plug Pg4 in the contact hole formed in the interlayer insulating film 180 at the end on the X3 side. It is in contact with the polysilicon layer 173 inside.

As shown in FIG. 1A, the gate wiring 130 is arranged on the long side X1 side of the source electrode 120 on the surface of the semiconductor substrate 110 in the peripheral region A2, and extends from the short side X3 side to the short side X4 side. and the first gate wiring portion 131 (first gate finger) extending along the length of the source electrode 120 on the long side X2 side of the source electrode 120 at a position facing the first gate wiring portion 131 with the source electrode 120 interposed therebetween. The second gate wiring portion 132 (second gate finger) extending from the X3 side toward the short side X4 side, and the ends of the first gate wiring portion 131 and the second gate wiring portion 132 on the short side X3 side and a gate pad 133 arranged in a substantially central region on the short side X3 side of the source electrode 120 .

The gate wiring 130 is arranged on the surface of the semiconductor substrate 110 with an interlayer insulating film 180 interposed therebetween, as shown in FIG. 1(b). In the peripheral region A2, the first gate wiring portion 131 is in contact with one end (the end on the long side X1 side) of the gate electrode 153 through the metal plug Pg1 in the contact hole formed in the interlayer insulating film 180. The second gate wiring portion 132 is in contact with the other end (the end on the long side X2 side) of the gate electrode 153 via a metal plug Pg1 in a contact hole formed in the interlayer insulating film 180. .

As shown in FIG. 1A, the shield wiring 140 is arranged on the long side X1 side of the first gate wiring portion 131 on the surface of the semiconductor substrate 110 in the peripheral region A2, and extends along the long side X1 along the short side. The first shield wiring portion 141 extending from the X4 side toward the short side X3 side and the second gate wiring portion 132 are arranged on the long side X2 side, and extend along the long side X2 from the short side X4 side to the short side X3 side. and a second shield wiring portion 142 extending toward the side. The second shield wiring portion 142 is arranged at a position facing the first shield wiring portion 141 with the first gate wiring portion 131, the source electrode 120 and the second gate wiring portion 132 interposed therebetween.

In the portion on the short side X4 side of the first shield wiring portion 141 , they are provided at positions facing each of the five source electrode side connection portions 121 of the source electrode 120 and protrude toward each of the source electrode side connection portions 121 . It has five shield-side connection portions 143 that are connected to each other. In the portion on the short side X4 side of the second shield wiring portion 142 , they are provided at positions facing each of the five source electrode side connection portions 122 of the source electrode 120 , and protrude toward each of the source electrode side connection portions 122 . It has five shield-side connection portions 144 that are connected to each other. The total width of the five shield-side connection portions 143 or the total width of the five shield-side connection portions 144 is narrower than the width of the first shield wiring portion 141 or the second shield wiring portion 142 .

As shown in FIG. 1B, the shield wiring 140 is arranged on the surface of the semiconductor substrate 110 with an interlayer insulating film 180 interposed therebetween. As shown in FIGS. 1B and 3, the first shield wiring portion 141 is a metal plug Pg2 in a rectangular contact hole formed in the interlayer insulating film 180 and extending from the short side X3 to the short side X4. The second shield wiring portion 142 is formed in the interlayer insulating film 180 from the short side X3 toward the short side X4. The shield electrode 154 is in contact with the other end (the end on the long side X2 side) through a metal plug Pg2 in a rectangular contact hole extending through. 3, shield wiring 140 is connected to semiconductor substrate 110 through metal plug Pg5 in a contact hole formed in interlayer insulating film 180 in a region between adjacent trenches 151. As shown in FIG.

The source electrode 120, the gate wiring 130, and the shield wiring 140 can be collectively formed by depositing a metal film while masking predetermined portions. The source electrode 120, the gate wiring 130, and the shield wiring 140 are made of, for example, an Al film or an Al alloy film (eg, AlSi film) and have a thickness of 1 μm to 10 μm (eg, 3 μm).

The drain electrode 190 is formed on the other surface side of the semiconductor substrate 110 (on the surface of the low resistance semiconductor layer 111), as shown in FIGS. 1(b) and 1(c). The drain electrode 190 is made of a laminated film in which Ti, Ni, and Au (or Ag) are laminated in this order, and the thickness of the drain electrode 190 is 0.2 μm to 1.5 μm (eg, 1 μm).

Each of the plurality of trenches 151 is formed on the surface of the semiconductor substrate 110, and as shown in FIG. It crosses and extends in a stripe shape to a region overlapping with the second shield wiring portion 142 on the long side X2 side. The ends on the long side X1 side of the plurality of trenches 151 are connected to a connection trench 157 extending from the short side X3 toward the short side X4 along the long side X1, and the ends on the long side X2 side are connected to the long side X2. are connected to a connection trench 158 extending from the short side X3 toward the short side X4. Therefore, in Embodiment 1, the plurality of trenches 151 and the connection trenches 157 and 158 are formed in a grid pattern.

The plurality of trenches 151 are formed with a depth reaching the drift layer 112 in the cell region A1, as shown in FIG. 1(c).
As shown in FIGS. 1B and 1C, the semiconductor device 100 according to the first embodiment includes a gate insulating film 152, a gate electrode 153, a shield electrode 154, an insulating region 155.

The gate electrode 153 is arranged inside and above each of the plurality of trenches 151 and extends in a stripe shape along the trenches 151 in plan view. Gate electrode 153 is arranged via gate insulating film 152 formed on the inner surface of the upper side wall of trench 151 , and gate electrode 153 faces base region 113 via gate insulating film 152 . there is Gate electrode 153 is formed of polysilicon. The bottom of gate electrode 153 is deeper than the position of the pn junction between drift layer 112 and base region 113 .

The shield electrode 154 is arranged below each of the plurality of trenches 151 and extends in a stripe shape along the trenches 151 when viewed in plan. The shield electrode 154 is spaced apart from the inner surfaces (bottom and sidewalls) of the trench 151 and the gate electrode 153 . The shield electrode 154 is connected to the first shield wiring portion 141 via the metal plug Pg2 at the end on the long side X1 side, and is connected to the second shield wiring portion 141 via the metal plug Pg2 at the end on the long side X2 side. 142. Shield electrode 154 is formed of polysilicon.

The insulating region 155 extends between the gate electrode 153 and the shield electrode 154 inside each of the plurality of trenches 151 , separates the shield electrode 154 from the gate electrode 153 , and extends between the inner surface of the trench 151 and the shield electrode 154 . to separate the shield electrode 154 from the inner surface of the trench 151 . The insulating region 155 is a CVD oxide film formed by a CVD method, but may be a thermal oxide film, an oxide film in which both are laminated, or an insulating film other than an oxide film.

As shown in FIG. 1A, the snubber resistance adjusting section 160 is located between the short side X4 side end of the first shield wiring section 141 and the source electrode 120, and between the short side of the second shield wiring section 142. It is formed between the end on the X4 side and the source electrode 120 . As shown in FIG. 3, in the snubber resistance adjusting portion 160, shield side connection portions 143 and 144 and source electrode side connection portions 121 and 122 are formed. A strip-shaped peripheral diffusion region 115 is formed on the surface of the drift layer between the shield-side connection portions 143 and 144 of . The peripheral diffusion region 115 is a p-type semiconductor region formed on the surface of the drift layer 112 . The plurality of source electrode side connection portions 121 and 122 are connected to the peripheral diffusion region 115 via metal plugs Pg6 in contact holes formed in the interlayer insulating film 180, and the plurality of shield side connection portions 143 and 144 are connected to the interlayer insulating film 180. It is connected to peripheral diffusion region 115 through metal plug Pg7 in a contact hole formed in insulating film 180. As shown in FIG. In Embodiment 1, all the five shield side connection portions 143 and 144 are connected to the corresponding five source electrode side connection portions 121 and 122 via the peripheral diffusion region 115 .

Shield side connection portions 143 and 144 and source electrode side connection portions 121 and 122 are formed in the snubber resistance adjustment portion 160, and the current conduction path between the source electrode 120 and the shield wiring 140 is narrow, and the current It is difficult to flow. In addition, the p-type peripheral diffusion region 115 has lower electrical conductivity than the metal forming the source electrode 120 and the shield wiring 140, making it difficult for current to flow. For these reasons, the snubber resistance adjustment section 160 becomes a resistance component.

In Embodiment 1, in one snubber resistance adjustment section, all five shield side connection sections 143 and 144 are connected to the corresponding source electrode side connection sections 121 and 122 via the peripheral diffusion region 115. , there may be shield-side connection portions 143 and 144 that are not connected to the peripheral diffusion region 115 . The snubber resistance can be adjusted by determining or changing the number of connections through the peripheral diffusion region 115 and the number of non-connections according to the electrical equipment used.

The plurality of peripheral trench structures 170 are, as shown in FIG. and a polysilicon layer 173 . A plurality of peripheral trench structures 170 are formed at least in regions where the source electrodes 120 and the peripheral region A2 overlap. In Embodiment 1, it is formed with the same depth as the trench 151 . The peripheral insulating region 172 is made of, for example, an oxide film.

Among the plurality of peripheral trench structures 170, in the peripheral trench structure 170a closest to the cell region A1, the polysilicon layer 173 is shielded through a metal plug (not shown) in a contact hole formed in the interlayer insulating film 180. In the peripheral trench structure 170b connected to the wiring 140 and farthest from the cell region A1 among the plurality of peripheral trench structures 170, the polysilicon layer 173 is formed in the interlayer insulating film 180 and the metal plug Pg4 in the contact hole is formed. is connected to the source electrode 120 via the . Peripheral trench structure 170b is arranged around the circumference of semiconductor substrate 110 .

2. Snubber Circuit in Semiconductor Device 100 According to Embodiment 1 In the semiconductor device 100 according to Embodiment 1, as shown in FIGS. , are connected to the shield electrode 154 via a metal plug Pg2. Therefore, the shield electrode 154 has a potential close to the source electrode 120 (strictly, from the potential of the source electrode 120, the resistance divided by the combined resistance R1 of the internal resistance of each shield electrode 154 and the resistance R2 of the snubber resistance adjustment section 160). potential).
Further, as shown in FIGS. 1B and 1C, the shield electrode 154 faces the drift layer 112 via the insulating region 155, and the drift layer 112 is positioned via the low-resistance semiconductor layer 111. It is connected to the drain electrode 190 .
Therefore, as shown in FIG. 4(b), a capacitance _CDS1 exists between each shield electrode 154 and the drift layer 112. As shown in FIG.

On the other hand, in the semiconductor device 100 according to the first embodiment, there is a capacitance _CDS2 due to the depletion layer of the pn junction between the base region 113 and the drift layer 112 .

That is, in the semiconductor device 100 according to the first embodiment, between the source electrode 120 and the drain electrode 190, the capacitance C _DS1 (combined capacitance C _DS1 between each shield electrode 154 and the source region 114 capacitance) and capacitance _CDS2 are arranged, and these capacitances (parasitic capacitances) form a capacitor C between the source electrode 120 and the drain electrode 190 (see FIG. 4A). ).

The shield electrode 154 is made of polysilicon containing impurities at a predetermined concentration and has an internal resistance. In addition, since the shield electrode 154 is arranged in the trench 151 formed in a stripe shape when viewed in plan (see FIG. 1(a)), the cross-sectional area of the current conduction path is relatively small and The length of the current conducting path becomes relatively long. Therefore, the internal resistance of the shield electrode 154 becomes a resistance value that cannot be ignored. Therefore, each shield electrode 154 has a resistance component, and the combined resistance of the internal resistance of each shield electrode 154 constitutes the resistance R1 between the shield wiring 140 and the drain electrode 190 (FIGS. 4A and 4B). c) see). The cross-sectional area means the area of the cross section perpendicular to the current path.

Also, the snubber resistance adjusting section 160 is a resistance component and constitutes a resistance R2 between the drain electrode 190 and the source electrode 120 (see FIGS. 4A and 4C).

Therefore, the semiconductor device 100 becomes a semiconductor device (MOSFET) incorporating an RC snubber circuit in which the capacitor C and the resistor R (combined resistance of the resistor R1 and the resistor R2) are connected in series (Fig. 4(a) reference).

Here, since the resistance R2 of the snubber resistance adjustment unit 160 can be changed regardless of the characteristics of the MOSFET, the semiconductor device 100 according to the first embodiment can easily adjust the resistance value of the snubber circuit. It becomes a semiconductor device with high performance.

3. Effects of the semiconductor device 100 according to the first embodiment According to the semiconductor device 100 according to the first embodiment, the shield wiring 140 is electrically connected to the source electrode 120 via the snubber resistance adjusting section 160 having a resistance component. Therefore, the current path between the drain electrode 190 and the source electrode 120 can have a resistance component other than the resistance component determined by the design of the semiconductor device based on the characteristics of the MOSFET. Therefore, by adjusting the resistance component of the snubber resistance adjusting section 160, it is possible to change the characteristics of the snubber resistance and, in turn, the characteristics of the snubber circuit according to the electrical equipment using the semiconductor device without changing the characteristics of the MOSFET. . As a result, a semiconductor device with a built-in snubber circuit can be flexibly applied to various electric devices.

Further, according to the semiconductor device 100 according to the first embodiment, in the snubber resistance adjustment section 160 , the first shield wiring section 141 and the second shield wiring section 142 are p-type peripheral diffusions formed on the surface of the drift layer 112 . Since the source electrode 120 is connected to the source electrode 120 through the region 115, the source electrode 120 and the shield wiring 140 can be electrically connected, and the width, depth, and length of the peripheral diffusion region 115 can be adjusted to the impurity concentration. By adjusting, the resistance value between the shield wiring 140 and the source electrode 120 can be easily adjusted. Therefore, the semiconductor device can easily adjust the snubber resistance.

Further, according to the semiconductor device 100 according to the first embodiment, the first shield wiring portion 141 and the second shield wiring portion 142 each have a plurality of shield side connection portions 143 and 144, and the source electrode 120 has a plurality of shield side connection portions 143 and 144. Since the plurality of source electrode side connection portions 121 and 122 are provided at positions facing the side connection portions 143 and 144, the cross-sectional area for connection can be made smaller than when the shield wiring 140 and the source electrode 120 are directly connected. can contribute to the resistive component of the snubber resistor. Moreover, since the plurality of shield-side connection portions 143 and 144 are connected to the corresponding source electrode-side connection portions 121 and 122 via the peripheral diffusion region 115, the plurality of shield-side connection portions 143 and 144 are connected to the peripheral diffusion region. By adjusting the number of contacts with 115, the snubber resistance can be adjusted. Therefore, the semiconductor device can more easily adjust the snubber resistance.

Further, according to the semiconductor device 100 according to the first embodiment, since it has a plurality of peripheral trench structures 170, when a reverse bias is applied, the depletion layer can be extended to the peripheral region A2, and the oxide film (peripheral The dielectric constant of the insulating region) is higher than that of silicon, and even if a large voltage is applied to the oxide film, it is difficult to break down.

Further, according to the semiconductor device 100 according to the first embodiment, in the peripheral trench structure 170 a closest to the cell region A 1 among the plurality of peripheral trench structures 170 , the polysilicon layer 173 is formed in the interlayer insulating film 180 . Since it is connected to the shield wiring 140 via a metal plug (not shown) in the hole, p-type is formed between the trench 151 closest to the peripheral region A2 and the peripheral trench structure 170a closest to the cell region A1. The depletion layer extends from each of the base region 113, the trench 151 closest to the peripheral region A2, and the peripheral trench structure 170 closest to the cell region A1, and the pinch-off effect facilitates extension of the depletion layer. Therefore, the breakdown voltage in this region is increased.

By the way, in general, the polysilicon layer 173 in the peripheral trench 171 is connected to the shield wiring 140, and the shield wiring 140 is directly electrically connected to the source electrode 120, so the polysilicon layer 173 is at the source potential. Therefore, when the source electrode 120 becomes 0V, the shield wiring 140 also becomes 0V.
However, in the semiconductor device 100 according to the first embodiment, the shield wiring 140 is electrically connected to the source electrode 120 via the snubber resistance adjustment section 160 having a resistance component. will have a different potential than Therefore, even if the source electrode 120 becomes 0V, the shield wiring 140 does not become 0V and the polysilicon layer 173 has a potential. Since such a potential is slight, it is unlikely that the potential distribution in the semiconductor substrate 110 will be affected and a problem will occur. In the peripheral trench structure 170b farthest from the cell region A1, the polysilicon layer 173 is connected to the source electrode 120 through the metal plug Pg4 in the contact hole formed in the interlayer insulating film 180. Since the polysilicon layer 173 in 171 is at the source potential, it is possible to more reliably prevent problems caused by affecting the potential distribution in the semiconductor substrate.

[Embodiment 2]
The semiconductor device 101 according to the second embodiment basically has the same configuration as the semiconductor device 100 according to the first embodiment, but the configuration of the snubber resistance adjustment section is different from that of the semiconductor device 100 according to the first embodiment. . That is, in the semiconductor device 101 according to the second embodiment, in the snubber resistance adjustment portion 160a, the plurality of shield-side connection portions 143 and 144 are connected to the corresponding source electrodes via the metal connection wiring 162 instead of the peripheral diffusion region 115. It is connected to the side connection portions 121 and 122 (see FIG. 5).

The connection wiring 162 may be formed by thinning the metal film formed together with the source electrode 120 and the shield wiring 140 by etching or the like. In this case, the snubber resistance can also be adjusted by cutting the connection wiring 162 by locally irradiating a laser or the like. The connection wiring 162 may be a wire or connector made of a conductive material (for example, made of metal). Since the total width (cross-sectional area) of the connection wiring 162 is narrower (smaller) than the width (cross-sectional area) of the first shield wiring portion 141 or the second shield wiring portion 142, it is difficult for current to flow, resulting in a resistance component.

As described above, the semiconductor device 101 according to the second embodiment differs from the semiconductor device 100 according to the first embodiment in the configuration of the snubber resistance adjustment unit, but the semiconductor device 101 according to the first embodiment has the following characteristics. Since the shield wiring 140 is electrically connected to the source electrode 120 via the snubber resistance adjustment portion 160a having a resistance component, the current path between the drain electrode 190 and the source electrode 120 is affected by the characteristics of the MOSFET. A resistance component other than the resistance component determined by the design of the semiconductor device can be added. Therefore, by adjusting the resistance component of the snubber resistance adjusting section 160a, it is possible to change the characteristics of the snubber resistance and, in turn, the characteristics of the snubber circuit according to the electrical equipment using the semiconductor device without changing the characteristics of the MOSFET. . As a result, a semiconductor device with a built-in snubber circuit can be flexibly applied to various electric devices.

Further, according to the semiconductor device 101 according to the second embodiment, the plurality of shield side connection portions 143 and 144 are connected to the corresponding source electrode side connection portions via the connection wiring 162 made of a conductive material (for example, made of metal). 121 and 122, the source electrode 120 and the shield wiring 140 can be electrically connected, and by adjusting the cross-sectional area, length, material, etc. of the connection wiring 162, the shield wiring 140 can be connected. The resistance value between the source electrode 120 can be easily adjusted. Therefore, the semiconductor device can easily adjust the snubber resistance.

Further, according to the semiconductor device 101 according to the second embodiment, since the plurality of shield side connection portions 143 and 144 are connected to the corresponding source electrode side connection portions 121 and 122 via the connection wiring 162, the source electrode side connection portions 121 and 122 are connected. 120, the gate wiring 130 and the shield wiring 140 can be collectively formed. In this case, the snubber resistance is adjusted by interrupting the connection of some connection wirings 162 with a laser or the like even at the final stage of manufacturing the semiconductor device, for example, after the formation of the source electrode 120, the gate wiring 130, and the shield wiring 140. can do.

Since the semiconductor device 101 according to the second embodiment has the same configuration as the semiconductor device 100 according to the first embodiment except for the configuration of the snubber resistance adjustment section, the semiconductor device 100 according to the first embodiment has the same effect. have the corresponding effect.

[Embodiment 3]
The semiconductor device 102 according to the third embodiment basically has the same configuration as the semiconductor device 101 according to the second embodiment, but the configuration of the snubber resistance adjustment section is different from that of the semiconductor device 101 according to the second embodiment. . That is, in the snubber resistance adjusting portion 160b of the semiconductor device 102 according to the third embodiment, a predetermined number of the plurality of shield-side connecting portions 143 and 144 (the first shield wiring portion 141 and the source electrode 120 in the third embodiment) are connected to the source electrode side connection portions 121 and 122 via metal connection wirings 162, and the rest are not connected (see FIG. 6).

As described above, the semiconductor device 102 according to the third embodiment differs from the semiconductor device 100 according to the first embodiment in the configuration of the snubber resistance adjustment section, but the semiconductor device 102 according to the second embodiment has the following characteristics. Since the shield wiring 140 is electrically connected to the source electrode 120 via the snubber resistance adjusting portion 160b having a resistance component, the current path between the drain electrode 190 and the source electrode 120 is affected by the characteristics of the MOSFET. A resistance component other than the resistance component determined by the design of the semiconductor device can be added. Therefore, by adjusting the resistance component of the snubber resistance adjusting section 160b, it is possible to change the characteristics of the snubber resistance and, in turn, the characteristics of the snubber circuit according to the electrical equipment using the semiconductor device without changing the characteristics of the MOSFET. . As a result, a semiconductor device with a built-in snubber circuit can be flexibly applied to various electric devices.

Further, according to the semiconductor device 102 according to the third embodiment, since some of the plurality of shield side connection portions 143 and 144 are not connected to the source electrode side connection portions 121 and 122 in the snubber resistance adjustment portion 160b, The resistance value between the source electrode 120 and the shield wiring 140 becomes larger. Therefore, the snubber resistor can be selected from a wider range of resistance values, and the semiconductor device with a built-in snubber circuit can be flexibly applied to a wider range of electrical equipment.

Note that the semiconductor device 102 according to the third embodiment has the same configuration as the semiconductor device 101 according to the second embodiment except for the configuration of the snubber resistance adjustment section, so the effects of the semiconductor device 101 according to the second embodiment have the corresponding effect.

[Embodiment 4]
The semiconductor device 103 according to the fourth embodiment basically has the same configuration as the semiconductor device 100 according to the first embodiment, but the configuration of the snubber resistance adjustment unit is different from that of the semiconductor device 100 according to the first embodiment. . That is, in the snubber resistance adjusting portion 160c of the semiconductor device 103 according to the fourth embodiment, among the plurality of shield-side connecting portions 143 and 144, a predetermined number (between the first shield wiring portion 141 and the source electrode 120 in the fourth embodiment). are connected to the corresponding source electrode side connection portions 121 and 122 via metal connection wiring 162, and the remaining (the first shield wiring portion 141 in the fourth embodiment and the source electrode 120) are connected to the corresponding source electrode side connection portions 121 and 122 via the peripheral diffusion region 115 (see FIG. 7).

As described above, the semiconductor device 103 according to the fourth embodiment differs from the semiconductor device 100 according to the first embodiment in the configuration of the snubber resistance adjustment section, but, like the semiconductor device 100 according to the first embodiment, Since the shield wiring 140 is electrically connected to the source electrode 120 via the snubber resistance adjustment portion 160c having a resistance component, the current path between the drain electrode 190 and the source electrode 120 is affected by the characteristics of the MOSFET. A resistance component other than the resistance component determined by the design of the semiconductor device can be added. Therefore, by adjusting the resistance component of the snubber resistance adjusting section 160c, it is possible to change the characteristics of the snubber resistance and, in turn, the characteristics of the snubber circuit according to the electrical equipment using the semiconductor device without changing the characteristics of the MOSFET. . As a result, a semiconductor device with a built-in snubber circuit can be flexibly applied to various electric devices.

Further, according to the semiconductor device 103 according to the fourth embodiment, a predetermined number of the plurality of shield side connection portions 143 and 144 are connected to the corresponding source electrode side connection portions 121 and 122 via the metal connection wiring 162 . , and the rest are connected to the corresponding source electrode side connection portions 121 and 122 via the peripheral diffusion region 115 . By adjusting the number, the resistance value between the source electrode 120 and the shield electrode 30 can be adjusted widely and in detail, resulting in a semiconductor device with a built-in snubber circuit that can be flexibly applied to a wider range of electrical equipment.

Note that the semiconductor device 103 according to the fourth embodiment has the same configuration as the semiconductor device 100 according to the first embodiment except for the configuration of the snubber resistance adjustment section, so the effects of the semiconductor device 100 according to the first embodiment have the corresponding effect.

[Embodiment 5]
The semiconductor device 104 according to the fifth embodiment basically has the same configuration as the semiconductor device 103 according to the fourth embodiment, but the configuration of the snubber resistance adjustment section is different from that of the semiconductor device 103 according to the fourth embodiment. . That is, in the snubber resistance adjusting portion 160d of the semiconductor device 104 according to the fifth embodiment, among the plurality of shield-side connecting portions 143 and 144, a predetermined number (between the first shield wiring portion 141 and the source electrode 120 in the fifth embodiment). are connected to the corresponding source electrode side connection portions 121 and 122 via metal connection wiring 162, and a predetermined number (the first shield wiring in the fifth embodiment) are connected to the corresponding source electrode side connection portions 121 and 122 141 and the source electrode 120) are connected to the corresponding source electrode side connection portions 121 and 122 via the peripheral diffusion region 115, and the rest are connected to the source electrode side connection portions 121 and 122. 121 and 122 are not connected (see FIG. 8).

The peripheral diffusion region 115 is formed between the multiple (five in Embodiment 5) shield-side connecting portions 143 and 144 and the multiple (five in Embodiment 5) source electrode-side connecting portions 121 and 122. formed. With this configuration, the shield-side connection portions 143 and 144 and the source electrode-side connection portions 121 and 122 are connected by the connection wiring 162, connected by the peripheral diffusion region 115, or not connected. You can choose either

As described above, the semiconductor device 104 according to the fifth embodiment differs from the semiconductor device 103 according to the fourth embodiment in the configuration of the snubber resistance adjustment unit, but the semiconductor device 104 according to the fourth embodiment has the following characteristics. Since the shield wiring 140 is electrically connected to the source electrode 120 via the snubber resistance adjusting portion 160d having a resistance component, the current path between the drain electrode 190 and the source electrode 120 is affected by the characteristics of the MOSFET. A resistance component other than the resistance component determined by the design of the semiconductor device can be added. Therefore, by adjusting the resistance component of the snubber resistance adjusting section 160d, it is possible to change the characteristics of the snubber resistance and, in turn, the characteristics of the snubber circuit according to the electrical equipment using the semiconductor device without changing the characteristics of the MOSFET. . As a result, a semiconductor device with a built-in snubber circuit can be flexibly applied to various electric devices.

Since the semiconductor device 104 according to the fifth embodiment has the same configuration as the semiconductor device 103 according to the fourth embodiment except for the configuration of the snubber resistance adjustment section, the semiconductor device 103 according to the fourth embodiment has the same effect. have the corresponding effect.

[Embodiment 6]
The semiconductor device 105 according to the sixth embodiment basically has the same configuration as the semiconductor device 104 according to the fifth embodiment, but the configuration of the snubber resistance adjustment section is different from that of the semiconductor device 104 according to the fifth embodiment. . That is, the snubber resistance adjusting portion 160e of the semiconductor device 105 according to the sixth embodiment is formed not outside the grid-like trenches 151, 157, 158 but between adjacent trenches 151. FIG. In Embodiment 6, the first shield wiring portion 141 and the second shield wiring portion 142 are separated from the source electrode 120 (see FIGS. 9 and 10).

The snubber resistance adjusting portion 160e is a region where the first shield wiring portion 141 and the second shield wiring portion 142 are electrically connected to the source electrode 120 via the diffusion region 116, which will be described later.

The semiconductor substrate 110a extends from the region where the first shield wiring portion 141 or the second shield wiring portion 142 is connected to the semiconductor substrate 110a between the trenches 151 adjacent to each other in the peripheral region A2 (sandwiched regions). Between regions where the source electrode 120 is connected to the semiconductor substrate 110a, there is a p-type diffusion region 116 formed on the surface of the drift layer 112 (see FIG. 10). Diffusion region 116 is connected to source electrode 120 via metal plug Pg3 in a contact hole formed in interlayer insulating film 180 . It is also connected to the shield wiring 140 through a metal plug Pg5 in a contact hole formed in the interlayer insulating film 180. FIG.

The diffusion region 116 extends from the region where the first shield wiring portion 141 or the second shield wiring portion 142 is connected to the semiconductor substrate 110a to the region where the source electrode 120 is connected to the semiconductor substrate 110a when viewed in plan. has a region narrower than the length between the trenches 151 adjacent to each other. That is, the diffusion region 116 is partially formed only in the vicinity of the center separated from the trench 151 in plan view, and the drift layer 112 is exposed to the surface between the diffusion region 116 and each trench 151 . ing. Since the diffusion region 116 is formed together with the base region 113 , the diffusion region 116 has the same depth as the base region 113 .

Since the diffusion region 116 is a region doped with p-type impurities, it has an internal resistance. Since the snubber resistance can be changed by adjusting the width and depth of the diffusion region 116 and the impurity concentration of the p-type impurity, the semiconductor device has high flexibility.

As described above, the semiconductor device 105 according to the sixth embodiment differs from the semiconductor device 100 according to the first embodiment in the configuration of the snubber resistance adjustment section, but the semiconductor device 105 according to the first embodiment has the following characteristics. Since the shield wiring 140 is electrically connected to the source electrode 120 via the snubber resistance adjustment portion 160e having a resistance component, the current path between the drain electrode 190 and the source electrode 120 is affected by the characteristics of the MOSFET. A resistance component other than the resistance component determined by the design of the semiconductor device can be added. Therefore, by adjusting the resistance component of the snubber resistance adjusting section 160e, it is possible to change the characteristics of the snubber resistance and, in turn, the characteristics of the snubber circuit according to the electrical equipment using the semiconductor device without changing the characteristics of the MOSFET. . As a result, a semiconductor device with a built-in snubber circuit can be flexibly applied to various electric devices.

Further, according to the semiconductor device 105 according to the sixth embodiment, the semiconductor substrate 110a has the first shield wiring portion 141 or the second shield wiring portion 142 between the trenches 151 adjacent to each other in the peripheral region A2. has a p-type diffusion region 116 formed from the region where the source electrode 120 is connected to the region where the semiconductor substrate 110a is connected, and the snubber resistance adjusting portion 160e includes the first shield wiring portion 141 and the second 2. Since the shield wiring portion 142 is a region electrically connected to the source electrode 120 through the diffusion region 116, it is compared with the case where the snubber resistance adjustment portion is formed outside the region where the trench 151 is formed. As a result, the area occupied by the semiconductor device can be reduced, and a miniaturized semiconductor device can be obtained.

Further, according to the semiconductor device 105 according to the sixth embodiment, the diffusion region 116 extends from the region overlapping the first shield wiring portion 141 or the second shield wiring portion 142 to the region overlapping the source electrode 120 . Since the width of the trench is narrower than the length between adjacent trenches, the resistance value of the snubber resistor can be increased, and the semiconductor device can be easily applied to electrical equipment.

Since the semiconductor device 105 according to the sixth embodiment has the same configuration as the semiconductor device 100 according to the first embodiment except for the configuration of the snubber resistance adjustment section, the semiconductor device 100 according to the first embodiment has the same effect. have the corresponding effect.

Although the present invention has been described based on the above embodiments, the present invention is not limited to the above embodiments. It can be implemented in various aspects without departing from the spirit thereof, and for example, the following modifications are also possible.

(1) The shapes, positions, sizes, and the like described in each of the above-described embodiments (including modifications; the same shall apply hereinafter) are examples, and can be changed within a range that does not impair the effects of the present invention. Further, each embodiment and modifications may be combined.

(2) In Embodiments 1 to 5, the shield-side connecting portion protruding toward the source electrode 120 is provided, but the present invention is not limited to this. It may have a shield-side connection portion that does not protrude toward the source electrode 120 . In addition, although a plurality of source electrode side connection portions projecting toward the first shield wiring portion 141 or the second shield wiring portion 142 are provided, the present invention is not limited to this. A source electrode side connection portion that does not protrude toward the first shield wiring portion 141 or the second shield wiring portion 142 may be provided.

(3) In each of the above embodiments, the number of source electrode side connection portions and shield side connection portions is arbitrary. Also, the number of source electrode side connection portions connected to the shield side connection portions via the connection wiring and the number of connection via the peripheral diffusion region can be set to an appropriate number.

(4) In Embodiment 6, the diffusion region 116 has a narrowed region, but the present invention is not limited to this. Diffusion region 116 need not be narrow. Even in this case, the electrical conductivity of the diffusion region 116 is lower than that of metal, and it is a resistance component.

(5) In Embodiment 6, the diffusion region 116 has the same depth as the base region, but the present invention is not limited to this. The diffusion region may have a region shallower than the base region or a region deeper than the base region.

(6) In the sixth embodiment, the diffusion region 116 has the same impurity concentration as the base region, but the present invention is not limited to this. The diffusion region may have an impurity concentration different from that of the base region. Also, the impurity in the diffusion region 116 may be of a different type from the impurity in the base region.

(7) In each of the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this. The first conductivity type may be p-type, and the second conductivity type may be n-type.

DESCRIPTION OF SYMBOLS 100, 101, 102, 103, 104, 105... Semiconductor device, 110, 110a... Semiconductor substrate, 111... Low resistance semiconductor layer, 112... Drift layer, 113... Base region, 114... Source region, 115... Peripheral diffusion region, 116... Diffusion region 120... Source electrode 121, 122... Source electrode side connection part 130... Gate wiring 131... First gate wiring part 132... Second gate wiring part 140... Shield wiring 141... First Shield wiring portion 142 Second shield wiring portion 143, 144 Shield side connection portion 151 Trench 152 Gate insulating film 153 Gate electrode 154 Shield electrode 155 Insulating region 157, 158 Connection trenches 160, 160a, 160b, 160c, 160d, 160e... Snubber resistance adjustment part 162... Connection wiring 170, 170a, 170b... Peripheral trench structure 171... Peripheral trench 172... Peripheral insulating region 173... Polysilicon Layer 180 Interlayer insulating film 190 Drain electrode A1 Cell area A2 Peripheral area Pg1 to Pg7 Metal plug

Claims (10)

A semiconductor device in which a cell region and a peripheral region formed in a region surrounding the cell region are defined in plan view,
a drift layer of a first conductivity type formed in the cell region and the peripheral region; a base region of a second conductivity type formed on the surface of the drift layer in at least the cell region; a semiconductor body having a source region of a first conductivity type formed in a portion thereof;
a source electrode disposed on the surface of the semiconductor substrate at least in the cell region with an interlayer insulating film interposed therebetween;
A first gate wiring portion and a second gate wiring portion which are arranged on the surface of the semiconductor substrate in the peripheral region with an interlayer insulating film interposed therebetween and which are arranged at positions opposed to each other with the source electrode interposed therebetween when viewed in a plan view. a gate wiring having
arranged on the surface of the semiconductor substrate in the peripheral region with an interlayer insulating film interposed therebetween, and facing each other across the first gate wiring portion, the source electrode and the second gate wiring portion in plan view; a shield wiring having a first shield wiring portion and a second shield wiring portion arranged;
are formed in parallel on the surface of the semiconductor substrate and extend from a region overlapping with the first shield wiring portion in plan view to a region overlapping with the second shield wiring portion across the cell region; In, a plurality of trenches formed with a depth reaching the drift layer;
a gate electrode disposed inside each of the plurality of trenches via a gate insulating film formed on the inner surface of the trench and connected to the gate wiring in the peripheral region;
a shield disposed inside each of the plurality of trenches, separated from the inner surface of the trench and the gate electrode, and connected to the first shield wiring portion and the second shield wiring portion in the peripheral region; an electrode;
Inside each of the plurality of trenches, extending between the gate electrode and the shield electrode, separating the shield electrode from the gate electrode, extending between an inner surface of the trench and the shield electrode, an insulating region separating the shield electrode from the inner surface of the trench;
The semiconductor device according to claim 1, wherein the shield wiring is electrically connected to the source electrode via a snubber resistance adjusting section having a resistance component. In the snubber resistance adjusting section, the first shield wiring section and the second shield wiring section have a cross-sectional area smaller than that of either the first shield wiring section or the second shield wiring section; 2. The semiconductor device according to claim 1, wherein said drift layer is connected to said source electrode through at least one of a second conductivity type peripheral diffusion region formed on the surface of said drift layer. in the peripheral region,
The first shield wiring portion and the second shield wiring portion each have a plurality of shield side connection portions,
the source electrode has a plurality of source electrode side connection portions provided at positions facing the plurality of shield side connection portions, respectively;
a plurality of peripheral diffusion regions each formed in a strip shape are formed on the surface of the drift layer between the plurality of shield-side connection portions and the plurality of source electrode-side connection portions in plan view,
3. The snubber resistance adjusting portion, wherein at least one of the plurality of shield side connection portions is connected to the corresponding plurality of source electrode side connection portions via the peripheral diffusion region. 3. The semiconductor device according to 2. in the peripheral region,
The first shield wiring portion and the second shield wiring portion each have a plurality of shield side connection portions,
the source electrode has a plurality of source electrode side connection portions provided at positions facing the plurality of shield side connection portions;
2. In said snubber resistance adjusting section, at least one of said plurality of shield side connection sections is connected to said plurality of corresponding source electrode side connection sections through said connection wiring. The semiconductor device according to . in the peripheral region,
The first shield wiring portion and the second shield wiring portion each have a plurality of shield side connection portions,
the source electrode has a plurality of source electrode side connection portions provided at positions facing the plurality of shield side connection portions;
In the snubber resistance adjustment unit, at least one of the plurality of shield side connection portions is connected to the corresponding source electrode side connection portion via the connection wiring or the peripheral diffusion region, and the plurality of shield side connection portions 3. The semiconductor device according to claim 2, wherein at least one of the side connection portions is not connected to the source electrode side connection portion. the first shield wiring portion and the second shield wiring portion are separated from the source electrode;
Between the trenches adjacent to each other in the peripheral region, the semiconductor substrate extends from a region where the first shield wiring portion or the second shield wiring portion and the semiconductor substrate are connected to the source electrode and the semiconductor substrate. further having a diffusion region of the second conductivity type formed on the surface of the drift layer between the region connected to the
2. The method according to claim 1, wherein in said snubber resistance adjusting portion, said first shield wiring portion and said second shield wiring portion are electrically connected to said source electrode through said diffusion region. semiconductor device. The diffusion region has a width from a region where the first shield wiring portion or the second shield wiring portion and the semiconductor substrate are connected to a region where the source electrode and the semiconductor substrate are connected. 7. The semiconductor device according to claim 6, having a region narrower than a length between said trenches adjacent to each other. a depth of the diffusion region between a region where the first shield wiring portion or the second shield wiring portion and the semiconductor substrate are connected to a region where the source electrode and the semiconductor substrate are connected; 7. The semiconductor device according to claim 6, wherein has a region shallower than said base region. an impurity concentration of the diffusion region between a region where the first shield wiring portion or the second shield wiring portion and the semiconductor substrate are connected to a region where the source electrode and the semiconductor substrate are connected; 7. The semiconductor device according to claim 6, wherein has a region lower than said base region. The direction in which the first shield wiring portion and the first gate wiring portion are arranged and the direction in which the second shield wiring portion and the second gate wiring portion are arranged when viewed from the source electrode extends to a region overlapping the peripheral region along a direction different from the direction in which the
In a region where the source electrode and the peripheral region overlap,
a plurality of peripheral trench structures having a plurality of peripheral trenches on one surface of the semiconductor substrate and a polysilicon layer embedded via a peripheral insulating region formed inside each of the plurality of peripheral trenches;
the polysilicon layer is connected to the shield wiring in a peripheral trench structure closest to the cell region among the plurality of peripheral trench structures,
10. The polysilicon layer is connected to the source electrode in a peripheral trench structure farthest from the cell region among the plurality of peripheral trench structures. semiconductor device.

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