JP2022132051A - power converter - Google Patents

Abstract

To provide a power converter that maintains the effect of reducing output current ripple by driving converters connected in parallel, and can output pulses normally to a drive terminal of the converter even when a current command value is small, thereby suppressing current waveform distortion.SOLUTION: Two or more n converters 5 connected in parallel generate pulses and output them to a motor 4 to drive the motor 4. On the basis of control information output from a control unit 11, a pulse generation unit 12 generates a multiplex pulse for multiplexing the n converters 5 of a three-phase converter 3. A multiplexing number switching unit 25 changes a multiplexing operation number na in which the converters 5 are simultaneously multiplexed.SELECTED DRAWING: Figure 1

Description

The present invention relates to power converters.

A power generator for a hybrid vehicle has been proposed as this type of power converter (see, for example, Patent Document 1). The power generator disclosed in Patent Document 1 connects a multiphase converter to each phase of a permanent magnet synchronous motor, and connects the multiphase converters connected to each phase in parallel. Each multiphase converter outputs a sinusoidal voltage by driving while changing the phase, thereby reducing the output current ripple.

In general, the output current ripple can be reduced by increasing the number of converters connected in parallel.

If the pulse width driven by the converter is short, the converter may not be able to output pulses normally. In this case, current waveform distortion occurs, which causes an increase in noise.

JP 2009-219299 A

An object of the present invention is to drive the converters in parallel so that the output current ripple reduction effect can be maintained, and even when the current command value is small, the converters can normally output pulses to suppress current waveform distortion. To provide a power converter with

The invention according to claim 1 is intended for a power converter provided with two or more n converters connected in parallel. When the control unit outputs control information according to the input current command value, the pulse generation unit causes the n converters of the power converter to perform multiple operations based on the control information output by the control unit. Generate multiple pulses to output to At this time, the multiple operation number changing unit changes the number of multiple operations to be performed.

By switching the multiplexing number of converters that operate according to the current command value, the multiple operation number switching unit can suppress shortening of the pulse width even when the current command value is small. Distortion can be suppressed.

Overall electrical configuration diagram in the first embodiment Electrical configuration diagram for one phase in the first embodiment Control configuration diagram of the converter in the first embodiment Drive voltage and drive current waveforms of converter in the case of quadruple multiplexing in the first embodiment Part 1 of a flowchart for schematically explaining multiple pulse generation processing in the first embodiment Explanatory diagram of a method for generating multiple pulses in the first embodiment Flowchart 2 for schematically explaining the multiple pulse generation process in the first embodiment Part 1 of the explanatory diagram showing the relationship between the inductor current and the output current in the first embodiment Part 2 of the explanatory diagram showing the relationship between the inductor current and the output current in the first embodiment Part 1 of an explanatory diagram showing an example of setting the number of multiple operations with respect to the current command value in the first embodiment Part 2 of the explanatory diagram showing a setting example of the number of multiple operations with respect to the current command value in the first embodiment Explanatory diagram showing the relationship between the rotation speed command value, the output current, and the number of multiple operations in the first embodiment. Flowchart for schematically explaining pulse generation processing in the second embodiment A diagram for explaining a problem that occurs when switching the number of multiple operations in the third embodiment. Explanatory drawing schematically showing a method of generating interpolation pulses in the third embodiment. Overall electrical configuration diagram in a modification related to the first to third embodiments FIG. 11 is a diagram schematically explaining the switching logic of the operation multiplex number with respect to the current command value in the modification related to the first to third embodiments; A diagram showing comparison results before and after application in modifications related to the first to third embodiments. Explanatory diagram of defects of comparative example technology with respect to modifications related to the first to third embodiments Diagrams for explaining effects in modifications related to the first to third embodiments Overall electrical configuration diagram in the fourth embodiment Example of interpolated multiple pulse generation in the fourth embodiment FIG. 11 is a diagram for explaining a method of generating interpolated multiple pulses in the fourth embodiment; Flowchart for schematically explaining a method for generating interpolated multiple pulses in the fourth embodiment Timing chart for schematically explaining a method of generating multiple pulses in the fifth embodiment Generation Example of Interpolated Multiple Pulses in Fifth Embodiment Overall electrical configuration diagram in a modification related to the fourth to fifth embodiments A diagram showing a comparison result between the fourth and fifth embodiments and related modifications A diagram showing comparison results before and after application in modifications related to the fourth to fifth embodiments. Explanatory diagram of defects of comparative example technology with respect to modifications related to the fourth to fifth embodiments A diagram for explaining effects in modifications related to the fourth and fifth embodiments. Examples of current waveforms affected by harmonic current distortion in conventional technology Overall electrical configuration diagram in the sixth embodiment Part 1 of the diagram for schematically explaining the electrical configuration of the pulse generator in the sixth embodiment 2 of the diagram schematically explaining the electrical configuration of the pulse generator in the sixth embodiment; Current waveform example when the pulse width command value is corrected according to the back electromotive force in the sixth embodiment Overall electrical configuration diagram in a modification related to the sixth and seventh embodiments FIG. 11 is a processing explanatory diagram of a back electromotive force correction unit in a modified example related to the sixth and seventh embodiments; A diagram showing comparison results before and after application in modifications related to the sixth and seventh embodiments. Example of change in current waveform before and after application in modifications related to the sixth and seventh embodiments Explanatory diagram of a voltage utilization factor improvement control unit in a modified example related to the sixth and seventh embodiments Explanatory diagram of comparative example technology and upper/lower limit clamping action in modifications related to the sixth and seventh embodiments Overall electrical configuration diagram in the eighth embodiment Overall electrical configuration diagram in the ninth embodiment

Several embodiments will be described below with reference to the drawings. In some embodiments, the same or similar components may be denoted by the same or similar reference numerals, and descriptions thereof may be omitted.

(First embodiment)
A first embodiment will be described with reference to FIGS. 1 to 12. FIG. As illustrated in FIG. 1, the battery 2 is connected with a three-phase inverter 3 as a power converter. The battery 2 is a storage battery such as a nickel-metal hydride storage battery or a lithium storage battery. A motor 4 is connected to the three-phase inverter 3 . The motor 4 is, for example, a power generator that drives the wheels of a hybrid vehicle, and exemplifies a permanent magnet synchronous motor (PMSM).

The three-phase inverter 3 is provided with multi-phase converters 6u, 6v, and 6w for a plurality of phases of U-phase, V-phase, and W-phase. The three-phase inverter 3 is composed of multi-phase converters 6u, 6v and 6w, each of which is formed by connecting two or more n converters 5u, 5v and 5w as basic units in parallel.

In FIG. 1, converters 5u, 5v, and 5w, which are basic units, are shown with suffixes "1 to n" added to their reference numerals. 5un, 5v1, 5v2, 5v3 . . . 5vn, 5w1, 5w2, 5w3 . Further, the converters 5u1, 5v1, and 5w1 that are targets for detection of the current flowing through the inductor (hereinafter, inductor current I _L ) may also be referred to as "master-phase converters 5". A configuration example of the converter 5 is shown in FIG.

For example, the U-phase multiphase converter 6u divides the total current flowing through the n converters 5 by 1/n, and is driven with a phase difference of T/n. Level the drive current. Since the output currents of the respective converters 5u1 . . . 5un are synthesized, current ripples can be canceled, thereby outputting a desired current waveform, here a sinusoidal current. The same applies to the V-phase and W-phase multiphase converters 6v and 6w.

As shown in FIG. 3, each of the converters 5 described above is provided with an upper arm switch SW1, a lower arm switch SW2, an inductor L, and a capacitor C in the illustrated form, and is a step-down non-converter for converting the voltage of the battery 2 as desired. It consists of an inverting buck converter.

The upper arm switch SW1 and the lower arm switch SW2 are configured as power switches such as N-channel power MOSFETs, and freewheeling diodes D1 and D2 are connected between the drain and source, respectively, to commutate the load current. In the following description, both or one of the upper arm switch SW1 and the lower arm switch SW2 may be referred to as "power switch".

In the control system 1 according to the present embodiment, a control device 10 is connected to the three-phase inverter 3, and control is performed mainly by the control device 10 shown in FIG. The control device 10 is configured by a computer including a plurality of cores, volatile and non-volatile memories 37, etc., and functionally includes a control section 11 and a pulse generation section 12. FIG. The memory 37 is used as a holding unit that holds various data as a non-transitional substantive storage medium. A voltage sensor 13 is installed in the battery 2 , and the detected voltage of the voltage sensor 13 is input to the controller 11 .

Further, a current sensor 14 is provided in the conducting path of the inductors L forming the converters 5u1, 5v1, and 5w1 serving as master phases of the UVW phases. The controller 11 receives the _inductor current IL detected by the current sensor 14 . A voltage sensor 15 is provided to detect the output voltage Vout of the capacitor C, and the voltage detected by the voltage sensor 15 is input to the control section 11 .

The control unit 11 inputs a current command value Io calculated according to the required torque as a command value, and outputs control information according to the current command value Io to the pulse generation unit 12 . The update cycle of the current command value Io is set to a sufficiently short time compared to the cycle of the AC frequency, so that the current command value Io that changes with the AC frequency can be finely set.

A current sensor 16 is provided to detect the phase currents Iu, Iv, and Iw to be input to the motor 4 , and the current detected by the current sensor 16 is input to the controller 11 . The control unit 11 inputs the rotor angle θ from a rotational position sensor 4a such as a resolver installed in the motor 4, and calculates information on the angular velocity ω. The control unit 11 outputs these pieces of information to the pulse generation unit 12 as feedback control information.

Based on the control information input from the control unit 11, the pulse generation unit 12 generates multiple pulses (multiphase pulses) so that the 3×n converters 5 of the three-phase inverter 3 are operated in a multiple manner.

As functionally illustrated in FIG. 2 , the pulse generator 12 has functional configurations as a gate driver 21 , a zero current detector 22 , and a pulse calculator 23 . As shown in FIG. 3, the pulse calculator 23 includes counters 24 including a pulse width counter 24a, a start phase counter 24b, and an end phase counter 24c.

The pulse calculator 23 calculates the on-time Ton and off-time Toff of the upper arm switch SW1 and the lower arm switch SW2 when each converter 5 of the multiphase converters 6u, 6v, and 6w of each phase operates in the current boundary mode, the period Each parameter of T and a phase difference Td between multiple pulses to be input to a plurality of converters 5 in phase (for example, U phase) is calculated.

The current boundary mode indicates a mode in which the upper arm switch SW1 and the lower arm switch SW2 are switched on/off on condition that the inductor current IL is detected to be zero. Each parameter of on-time Ton, off-time Toff, period T, and phase difference Td is set to be the same among the multiplex pulses input to each converter 5 of the in-phase multiphase converters (eg, 6u).

The gate drive section 21 drives the three-phase inverter 3 based on the calculation result of the pulse calculation section 23 . The gate driving section 21 turns on/off the upper arm switch SW1 or the lower arm switch SW2 based on the ON time Ton, period T, and phase difference Td calculated by the pulse calculating section 23 .

In this embodiment, for example, when the current command value Io of a certain phase, for example, the U-phase exceeds 0, the gate driving section 21 keeps the lower arm switch SW2 of each converter 5 constituting the multiphase converter 6u off. In this state, the upper arm switch SW1 is turned on/off. When the upper arm switch SW1 is turned on, the capacitor _C is charged while the inductor current IL is gradually increased from the battery 2 through the upper arm switch SW1.

After that, when the ON time Ton elapses, the gate driving section 21 turns off the upper arm switch SW1. Even if the upper arm switch SW1 is turned off, the inductor current _IL continues to flow through the free wheel diode D2 attached to the lower arm switch SW2.

The inductor current _IL gradually decreases, but the zero current detector 22 detects the timing when the inductor current _IL becomes zero. When the inductor current _IL becomes zero, the gate driving section 21 turns on the upper arm switch SW1 again. This operation is repeated as long as the current command value Io exceeds zero. Each converter 5 operates in the current boundary mode in which the upper arm switch SW1 is turned on on condition that the zero current detector 22 detects zero _inductor current IL.

Conversely, when the current command value Io is less than 0, the gate driving section 21 turns on/off the lower arm switch SW2 while keeping the upper arm switch SW1 off. When the lower arm switch SW2 is turned on, the capacitor _C is discharged while the inductor current IL is gradually decreased. After that, when the ON time Ton elapses, the gate driving section 21 turns off the lower arm switch SW2. Even if the lower arm switch SW2 is turned off, the inductor current _IL continues to flow through the free wheel diode D1 connected to the upper arm switch SW1.

The inductor current _IL gradually increases, and the zero current detector 22 detects the timing when the inductor current _IL becomes zero. The gate driver 21 turns on the lower arm switch SW2 again when the inductor current _IL becomes zero. This operation is repeated as long as the current command value Io is less than zero. Each converter 5 operates in the current boundary mode in which the lower arm switch SW2 is turned on on condition that the zero current detector 22 detects zero _inductor current IL.

FIG. 4 shows an example of waveforms when the number of multiple operations is n=4, the period is T, and the phase difference Td is T/n. When the inductor current IL gradually increases and then gradually decreases, the inductor current _IL flows through the inductor _L in a triangular waveform.

The control device 10 outputs control information to the pulse generator 12 while gradually changing the current command value Io of each UVW phase in a sinusoidal shape based on the aforementioned feedback information. The pulse generator 12 changes each parameter (on-time Ton, off-time Toff, period T, phase difference Td) of the multiplex pulse as illustrated in FIG.

Each converter 5 supplies phase currents Iu, Iv, and Iw with the same phase difference Td=T/n to the motor 4, thereby superimposing the output current of each converter 5 by the multiple number n. , UVW phases of the motor 4 can be energized. As a result, the phase currents Iu, Iv, and Iw can be controlled to the desired current command value Io, here, the current command value Io that varies sinusoidally.

The maximum output of each phase current Iu, Iv, and Iw is determined so as to be smaller than the inductor saturation current and satisfy the heat generation requirements of the three-phase inverter 3, and the number of multiple operations n should be determined based on the upper limit that satisfies the maximum output. Also, the frequency corresponding to the period T of the multiplex pulse should be set higher than the audible frequency.

It is desirable to increase the number n of multiplexed operation as much as possible because the larger the number n, the higher the current ripple canceling effect. Note that if the multiple operation number n is too large, the control by the control device 10 becomes a factor of complication.

The processing operations of the multiphase converters 6u, 6v, and 6w for each phase will be described in detail below with reference to flowcharts. Since the operations of the UVW phases are generally the same, the processing operation of the U-phase multiphase converter 6u will be described, and the processing operation of the V-phase and W-phase multiphase converters 6v and 6w will be omitted.

As shown in FIG. 5 for the processing steps of the converter _5u1 of the first multiplex, the zero current detection unit 22 detects the timing at which the inductor current IL becomes zero in S1 and S2. Alternatively, in S4, the upper arm switch SW1 or the lower arm switch SW2 is turned on. At this time, the pulse calculator 23 determines in S2 whether to turn on the upper arm switch SW1 or the lower arm switch SW2 based on the value of the current command value Io.

If the current command value _Io exceeds zero, the gate driver 21 turns on the upper arm switch SW1 in S3, and if the current command value _Io is less than zero, the gate driver 21 turns on the lower arm switch in S4. Turn on switch SW2.

When driving the converter 5u1, the pulse calculator 23 calculates the on-time Ton for keeping the power switch SW1 or SW2 of each converter 5 on, and the phase difference Td between the multiple pulses applied to each converter 5. FIG.

Assuming that the current command value of the phase current Iu is Io and the multiplexing number of the converter 5 is n, the average current I of the converter 5 is Io/n. In this control system 1, the inductor current IL repeats a gradual increase or a gradual decrease with zero as the boundary, so the peak current _ILp of the inductor current _IL is twice the average current I ₌ 2I.

ここで、Ｖinは入力電圧、Ｖoutは相電圧、Ｌはインダクタのインダクタンス、ｎはコンバータ５の多重動作数を示す。 When the current command value Io>0, the pulse calculator 23 calculates the ON time Ton and OFF time Toff of the upper arm switch SW1, the period T and the phase difference Td according to the following equations (1-1) to (1 -4) Calculate based on the formula.

Here, Vin is the input voltage, Vout is the phase voltage, L is the inductance of the inductor, and n is the number of multiple operations of the converter 5.

When the current command value Io<0, the pulse calculation unit 23 calculates the on-time Ton and off-time Toff of the lower arm switch SW2, the period T and the phase difference Td using the following equations (2-1) to (2 -4) Calculate based on the formula.

The pulse generator 12 generates pulses for driving the upper arm switch SW1 and the lower arm switch SW2, and the gate driver 21 turns on the upper arm switch SW1 or the lower arm switch SW2 in S3 and S4.

FIG. 6 shows an example of pulse generation for activating the 1st to n-th multiplexed converters 5 . The pulse width counter 24a measures the on-time Ton by setting the counter value to a predetermined value and counting down on the condition that the zero current detector 22 detects zero _inductor current IL.

If the on-time Ton has passed, the pulse calculator 23 determines YES in S5 of FIG. 5, and turns off the power switch SW1 or SW2 that is on in S6. As a result, the power switch SW1 or SW2 can be kept ON for the ON time Ton.

Further, the pulse calculation section 23 of the pulse generation section 12 operates the start phase counter 24b at the same time as the pulse width counter 24a. The start phase counter 24b indicates a counter for measuring the start timing of the pulse input to the second to n-th multiplexed converters 5u2 . . . 5un. The start phase counter 24b measures the time corresponding to the phase difference Td calculated by the pulse calculator 23 by setting the counter value to a predetermined value and counting down. The end phase counter 24c is a counter for measuring the end timing of the pulses input to the 1st to n-th converters 5u1 . . . 5un. The end phase counter 24c measures the time corresponding to the phase difference Td calculated by the pulse calculator 23 by setting the counter value to a predetermined value and counting down.

FIG. 7 shows the processing steps of the m-th multiple converter 5 (where m≧2). The pulse generating section 12 performs the processing from S12 onward on the condition that the power switch SWm-1 of the m-1th multiple converter 5 is turned on in S11. The power switch _SWm -1 shown here indicates either the upper arm switch SW1 or the lower arm switch SW2 of the m-1th multiple converter 5, and changes based on the current command value Io.

After the power switch SWm-1 of the m-1th multiple converter 5 is turned on, the start phase counter 24b measures whether or not the phase difference Td=Ton/n, which is the start timing of the m-th multiplex, has passed in S12. , S12, the power switch SWm of the m-th multiple converter 5 is turned on in S13. The power switch _SWm indicates either the upper arm switch SW1 or the lower arm switch SW2 of the m-th converter 5 and changes based on the current command value Io.

Thereafter, the pulse generator 12 generates a pulse for sequentially turning on the power switch SWm of the m-th multiple converter 5 each time the count of the start phase counter 24b ends. As a result, it is possible to start outputting driving pulses with a phase difference Td.

On the other hand, as shown in FIG. 6, when the count by the pulse width counter 24a of the converter 5u1 of the first multiplex ends, it is determined that the ON time Ton has passed, and the pulse generator 12 switches the power switch of the converter 5u1 of the first multiplex. Stop pulse output to SW1 or SW2. The pulse generator 12 starts counting by the end phase counter 24c at the timing when the pulse width counter 24a finishes counting. After that, the pulse generator 12 terminates counting by the end phase counter 24c, and sequentially stops the pulses being output to the power switch SWm of the m-th multiple converter 5 each time the ON time Ton elapses in S14. As a result, the m-th power switch SWm is sequentially turned off.

Hard switching occurs when the power switch SW1 or SW2 is turned off. However, if the charging time of the capacitor C provided at the output of the power switches SW1 and SW2 is made sufficiently longer than the switching time, the period for limiting the voltage rise can be lengthened, and ZVS (Zero Voltage Switching) can be achieved. This makes it possible to reduce the switching loss to approximately zero. If the capacity of the output capacitor is insufficient, a capacitor C should be added in parallel.

As a result, the pulse operation unit 23 sequentially outputs pulses after the phase difference Td calculated as described above from the timing of outputting the pulse to the 1st multiplexed converter 5u1, so that the 1 . . . . can generate multiple pulses to be input to 5un.

The resonance time of each converter 5 is determined by the output capacitance of power switches SW1 and SW2, the junction capacitance of freewheeling diodes D1 and D2, and the inductance of inductor L. FIG. It is preferable to set the ON timing of the power switches SW1 and SW2 to the voltage lowest point after the resonance half cycle due to these capacitances and inductances. The voltage lowest point after the resonance half cycle is the timing when the inductor current IL _overshoots zero and approaches zero again by turning off the power switch SW1 or SW2. As a result, ZCS (Zero-Current-Switching) and pseudo ZVS (Zero-Voltage-Switching) can be realized, and the switching loss at turn-on can be substantially reduced to zero.

<Description of Multiplex Number Switching Unit 25>
The configuration and technical significance of the multiplex number switching unit 25, which characterizes this embodiment, will be described below. As shown in FIG. 1, the pulse generation unit 12 includes a block that functions as a multiplexing number switching unit 25 that changes the multiplexing operation number n _a (operational multiplexing number) in which the converters 5 are simultaneously operated in multiplexing. The multiplexing number switching unit 25 corresponds to a multiplexing operation number changing unit.

The multiplexing number switching unit 25 is _a block that changes the multiplexing number na of the converter 5 according to the current command value Io or the maximum value of the current command value Io that changes depending on the input command rotation speed. be. In the following, the method of switching the multiplexing operation number _na by the multiplexing number switching unit 25 according to the present application will be explained, and the significance thereof will be explained.

The multiplex number switching unit 25 calculates the multiple operation number _na according to the current command value Io or the rotation speed command value, and outputs it to the pulse calculation unit 23 . Alternatively, the control device 10 calculates the multiple operation number _na from the current command value Io or the rotation speed command value, outputs the multiple operation number _na to the multiplex number switching section 25, and the multiplex number switching section 25 operates based on this data. It is also possible to switch the multiple operation number _na by

When the current command value _Io > 0, the multiplexing number switching unit 25 uses the multiplexing operation number na to determine the ON time Ton1, the OFF time _Toff1 , the period T, and the phase difference between the converters of the upper arm switch SW1. Td is calculated based on each of formulas (3-1) to (3-4).

Further, the multiplexing number switching unit 25 disables the operation of the gate driving unit 21 that outputs pulses to the slave phase converters 5 exceeding the number _na of multiplexing operations. That is, the power switches SW1 and SW2 are kept off. As shown in FIGS. 8 and 9, when the current command value Io is the same, the smaller the multiple operation number _na , the longer the period and the wider the pulse width.

Further, the multiplexing number switching unit 25 may switch the multiplexing operation number _na according to the current command value Io. As shown in FIG. 10, the larger the current command value Io, the larger the multiple operation number _na , and the smaller the current command value Io, the smaller the multiple operation number _na . FIG. 10 shows _a form in which the switching timing of the current command value Io coincides with the switching timing of the multiple operation number na, but it is not limited to this.

As shown in FIG. 11, the timing at which the multiplexing number switching unit 25 switches the multiplexing operation number _na does not have to be the same timing as the switching timing of the current command value Io. The multiple operation number na may be switched at _a timing delayed from the current switching timing. By reducing the number _na of multiple operations, shortening of the pulse width can be suppressed, and even when the current command value Io is relatively small, the converter 5 can output pulses normally.

As shown in FIG. 12, when the command rotation speed is used as the command value, the multiple operation number _na may be switched according to the command rotation speed. When the command rotation speed is input, the control device 10 changes the output current sinusoidally based on the current command value Io.

In this case, the multiplex number switching unit 25 preferably switches the multiple operation number na to _a larger value as the commanded rotation speed increases, and to _a smaller number as the command rotation speed decreases. Further, the multiplex number switching unit 25 may switch the multiple operation number _na according to the maximum value of the current command value Io that changes depending on the input command rotation speed. The number _na of operations may be switched.

According to this embodiment, the number of multiplexing operations _na can be changed and switched by the multiplexing number switching unit 25 . Reduction of the pulse width can be suppressed by reducing the number _na of multiple operations. Therefore, the converter 5 can be normally driven even when the commanded rotation speed is relatively small.

(Second embodiment)
A second embodiment will be described with reference to FIG. Regarding the second embodiment, only the parts different from the first embodiment will be explained, and the explanation of the same parts will be omitted.

FIG. 13 shows a flowchart that replaces FIG. As shown in FIG. 13, from the timing when the power switch SW1 or SW2 of the converter 5 of the first multiplex is turned on in S11a, the phase difference T _dm =Ton× After (m−1)/n has elapsed, the power switch SWm of the m-th multiple converter 5 may be turned on in S13.

It should be noted that the phase difference Tdm of the m-th multiplexing start phase with respect to the first multiplexing start phase can be calculated based on the relationship of the following equation (4).

For example, in the case of the U-phase, the first multiple converter 5u1 is used as the master phase, and after turning on the power switch SW1 or SW2 of the master-phase converter 5u1, 2 or more m-th multiple converters 5u2 . . . 5un are used as slave phases. The power switches SW1 or SW2 may be turned on in order. Also in this embodiment, the same effects as in the first embodiment are obtained.

(Third embodiment)
A third embodiment will be described with reference to FIGS. 14 and 15. FIG. A portion different from the first and second embodiments will be described. When the multiplexing number switching unit 25 switches the multiplexing operation number _na of the converter 5, there are cases where the rule in the current boundary mode cannot be continued.

As exemplified in FIG. 14, consider switching the multiple operation number na from 2 to 4 at _a certain switching timing ta, and switching the cycle T of the multiplexed pulse to cycle T2=T/2.

As shown in FIG. 14, before the switching timing ta, the phase current Iu is controlled to the desired current command value Io while the current boundary mode is continued by operating the first and third multiplex converters 5u1 and 5u3. ing.

However, if the operations of the converters _5u1 , . The inductor current IL of the third multiplex converter _5u3 of the slave phase cannot be made zero, and the current boundary mode operation cannot be continued.

In this way, when switching the current multiple operation number n to the next multiple operation number _na , the pulse generation unit 12 receives the switching output from the multiplex number switching unit 25 and generates the interpolated multiple pulse Pu to generate the current boundary. I would like to continue the mode.

An example in which the pulse generator 12 generates the interpolated multiple pulse Pu to continue the operation in the current boundary mode when switching the multiple operation number _na will be described with reference to FIG.

Pre-switching cycle T, post-switching cycle T _a , pre-switching multiple operation number n, post-switching multiple operation number n _a , where n<n _a . At this time, the phase difference before switching T _d =T/ _na and the phase difference after switching T _da =T _a / _na .

Here, the pre-switching phase difference _Td is expressed as _a phase difference in the case of the multiple operation number na. As shown in FIG. 15, since the number of multiple operations before switching is n, there is no change in the phase current Iu before and after the switching timing tb.

At this time, assuming that the m-th multiple cycle in the interpolated multiple pulse Pu is Tm, the cycles T1 to Tm can be calculated based on FIG. 15 and the following equation (5).

By generating the interpolated multiple pulse Pu with the m-th multiple cycle Tm from the switching timing tb shown in FIG. 15, the multiple operation number n can be switched while continuing the current boundary mode.

The method described above is merely an example, and the method for generating the interpolated multiple pulse Pu is not limited to the method described above. For example, the phase difference T _o between the interpolated multiple pulses Pu may be set to any value between the pre-switching phase difference T/ _na and the post-switching phase difference T _a / _na .

As described above, according to the third embodiment, the interpolated multiplexed pulse Pu is generated in the middle of switching the number n of multiplexed operations. As a result, the current boundary mode can be stably continued even when the number n of converters 5 in multiple operation is switched.

(Modified Example of Feedback Control Configuration Related to First to Third Embodiments)
Modifications of the feedback control configuration related to the first to third embodiments will be described with reference to FIGS. 16 to 20. FIG. The control device 10A may be configured as shown in FIG. The control device 10A incorporates a control section 11A, a pulse generation section 12A, and a memory 37. FIG. The control unit 11A is configured by connecting a subtractor 30, a current controller 31, a two-to-three-phase converter 32 as a phase converter, and a three-to-two-phase converter 34 in the illustrated form.

The controller 11A inputs a d-axis current command value Id* and a q-axis current command value Iq*. The three-phase to two-phase converter 34 of the control unit 11A inputs the phase currents Iu, Iv, and Iw, and also inputs the rotor angle θ from the rotational position sensor 4a such as a resolver installed in the motor 4 to obtain the angular velocity ω. Compute information. A three-phase to two-phase converter 34 converts the three-phase currents Iu, Iv, and Iw of the motor 4 into a d-axis current Id and a q-axis current Iq, and outputs the currents to the subtractor 30 .

The subtractor 30 subtracts the d-axis current Id and the q-axis current Iq from the d-axis current command value Id* and the q-axis current command value Iq*, respectively, and outputs the result to the current controller 31 . The current controller 31 outputs dq-axis current command values Id_cmd and Iq_cmd to the two-to-three-phase converter 32 by, for example, proportional integral control. The two-to-three-phase converter 32 converts the dq-axis current command values input from the current controller 31 into current command values Iu_cmd, Iv_cmd, and Iw_cmd for each of the three phases of the motor 4, and outputs them to the pulse generator 12A. do.

The pulse generation section 12A includes pulse generation blocks 12u, 12v, and 12w for each of three phases, and one multiplex number switching section 25 for changing the operating multiplex number. Each of the pulse generation blocks 12u, 12v, and 12w has functional configurations as a zero current detector 22, a pulse calculator 23, and a gate driver 21, respectively. The pulse calculation units 23 of the phases of the pulse generation blocks 12u, 12v, and 12w respectively receive current command values Iu_cmd, Iv_cmd, and Iw_cmd for the three phases of the motor 4 . The zero current detector 22 detects zero current for each phase and outputs it to the pulse calculator 23 .

The pulse calculator 23 calculates the on-time Ton and off-time Toff of the upper arm switch SW1 and the lower arm switch SW2 when each converter 5 of the multiphase converters 6u, 6v, and 6w of each phase operates in the current boundary mode, the period Each parameter of T and a phase difference Td between multiple pulses to be input to a plurality of converters 5 in phase (for example, U phase) is calculated.

The gate drive section 21 drives the three-phase inverter 3 based on the calculation result of the pulse calculation section 23 . The gate driving section 21 turns on/off the upper arm switch SW1 or the lower arm switch SW2 based on the ON time Ton, period T, and phase difference Td calculated by the pulse calculating section 23 .

The multiplexing number switching unit 25A is a block that receives the current command value _{Iq_cmd} of the q-axis current from the current controller 31 and changes the multiplexing operation number na of the converter 5 . The multiplexing number switching unit 25A switches and changes the multiplexing operation number na based on the value of the current command value _{Iq_cmd} as shown in FIG. For example, if the current command value _{Iq_cmd} exceeds 10, the multiple operation number na is set to 8; if the current command value _{Iq_cmd} exceeds 4 and is 10 or less, the multiple operation number na is set to 4; If the value _{Iq_cmd} exceeds 1 and is 4 or less, the multiple operation number na may be set to 2, and if the current command value _{Iq_cmd} is 1 or less, the multiple operation number na may be set to 1.

In this way, when the multiple operation number n is changed every 2̂n in accordance with the current command value Iq_cmd, the phase difference calculation in the pulse calculator 23 can be omitted. An example of the operation when changing the number _na of multiplex operations is the same as the flow shown in FIGS. As shown in FIG. 18, waveform examples of the three-phase currents Iu, Iv, and Iw before and after application, the influence of harmonic current distortion can be improved.

For example, as exemplified in FIG. 19, when the converter 5 is operating in 4-multiplex mode and the multiplex number switching unit 25 switches to 3-multiplex mode, the signal associated with the phase difference T/3 with respect to the period T is reproduced. need to calculate. As described above, the converter 5 to be operated can be changed by switching the operation/stop of the corresponding converter 5 based on a predetermined condition. As shown in FIG. 20, an example of switching to 2-multiplex operation is required only by stopping the signals of the 2nd and 4th multiplexes. can be reduced.

(Fourth embodiment)
A fourth embodiment will be described with reference to FIGS. 21 to 24. FIG. In the present embodiment, an embodiment will be described in which phase currents Iu, Iv, and Iw based on multiple pulses are smoothly changed in accordance with changes in current command value Io while keeping the number n of converters 5 in multiple operation the same. That is, in this embodiment, the configuration of the multiplex number switching section 25 described in the first to third embodiments may be omitted.

The pulse generation unit 112 generates a plurality of multiplex pulses that are sequentially output to each converter 5 so that the current boundary mode operation can be continued even in a transient state where the pulse width is changed according to changes in the current command value Io. It is preferable that the interpolating multiple pulse Pu for interpolating between is generated by the function of the interpolating section 12b. As shown in FIG. 21, the pulse generator 112 functions as an interpolator 12b.

For example, the interpolator 12b calculates the value of the phase difference between the turn-off timings between the current first multiplexed pulses and the phase difference between the turn-off timings between the next second multiplexed pulses to be input to each converter 5 in each UVW phase. It is preferable to set the value of the phase difference between the turn-off timings between the interpolated multiple pulses Pu between the value and .

Specifically, it is desirable to generate the interpolated multiple pulse Pu as follows by the function of the interpolator 12b. As shown in FIG. 22, if the phase difference between the turn-off timings of the current first multiplexed pulse is Pk, and the phase difference between the turn-off timings of the next multiplexed pulse is Pk _{+ 1} , then between the interpolated multiplexed pulses Pu A phase difference _Pka between turn-off timings is calculated based on the following equation (6).

Although the linear interpolation method exemplifying the equation (6) is described here, the method is not limited to this. The phase difference between the turn-off timings or the turn-on timings between the interpolated multiple pulses Pu may be set to a value between the phase differences between the current and next multiple pulses. Then, the output current between the current and next multiple pulses can be smoothly interpolated, and the driving current output of the converter 5 can be leveled.

FIG. 23 shows changes in each counter value of the pulse width counter 24a, the start phase counter 24b, and the end phase counter 24c, and the pulse calculation when the interpolated multiple pulse Pu is generated using the counter 24 described in the above embodiment. An example of an output result of the interpolated multiple pulse Pu by the unit 23 is shown.

A method for generating the interpolated multiple pulse Pu will be described below with reference to the flow chart of FIG. As shown in FIG. 24, the pulse generator 12 determines in S11 whether the inductor current IL of the master-phase converter _5u1 has been detected as zero. do.

The pulse calculation unit 23 sets the counter values of the pulse width counter 24a, the start phase counter 24b, and the end phase counter 24c using the same method as the method shown in the first embodiment, thereby setting the power switch SW1 or SW2. on-time Ton, off-time Toff, period T, and on/off timing phase difference Td between the master-phase and slave-phase converters 5u1 . . . 5un.

When the current command value Io does not change and the next pulse width is not changed from the current pulse width of the multiple pulse, the pulse generator 12 determines NO in S13, and determines the next pulse width in S18 based on the set counter value. Output multiple pulses.

However, when the current command value Io changes and the pulse width of the multiple pulse is changed from the current pulse width to the next pulse width, YES is determined in S13, and the condition for the phase difference between the interpolated multiple pulses Pu is adjusted in S14. A counter value is calculated so as to satisfy the condition, and an interpolated multiple pulse Pu is output in S15.

On the other hand, when the pulse generator 12 detects the zero current of the master phase of the interpolated multiple pulse Pu in S16, it again sets the counter value based on the pulse width and phase difference of the next multiple pulse in S17. Output multiple pulses.

In the above description, the flow is illustrated as a flow chart for easy understanding, but each processing step may be processed in parallel as needed.

When the conventional technique is applied, it is necessary to calculate the widths of the pulses to be input to the converter 5 of the master phase and each slave phase as interpolated values between multiple pulses. It has been confirmed that the output current increases temporarily.

According to the present embodiment, attention is paid to the phase difference between the current first multiplexed pulse and the next second multiplexed pulse, and the interpolated multiplexed pulse Pu is generated so as to linearly interpolate the phase difference by the function of the interpolator 12b. is doing. In the above-described method, when the phase difference between the first multiple pulses before interpolation is Pk and the phase between the second multiple pulses after interpolation is Pk _{+ 1} , the phase difference between the interpolated multiple pulses Pu is the phase difference P It is set to a value between _k and the phase difference _Pk+1 . As a result, the current multiple pulse and the next multiple pulse can be smoothly interpolated, and the drive current output of each converter 5 can be leveled.

Further, according to this embodiment, the phase differences between the interpolated multiple pulses Pu can all be set to the same phase difference, so that the calculation process can be completed only once. When the phase difference between interpolated multiple pulses Pu is linearly interpolated, for example, it can be obtained from the average value of the phase difference Pk between the current multiple pulses and the phase difference Pk _{+ 1} between the next multiple pulses. It is possible to reduce the calculation load with respect to the interpolation calculation amount of . The width of the interpolated multiple pulse Pu corresponding to the multiplexing number of the converter 5 and the phase difference between the interpolated multiple pulses Pu are mapped and stored in the memory 37, and the map stored in the memory 37 is used for calculation. You can do it.

(Fifth embodiment)
The fifth embodiment will be described with reference to FIGS. 25 and 26. FIG. Since this embodiment is a modified example of the fourth embodiment, only parts different from the fourth embodiment will be described.

As shown in FIG. 25, the pulse calculator 23 includes a start phase counter 24b for measuring the start phase of each pulse of the multiplexed pulse, and a multiplexed pulse width counter 24d for controlling the pulse width of each pulse of the multiplexed pulse. Prepare. The pulse generator 112 inputs a pulse to the next multiple converter 5 each time the start phase counter 24b expires.

The start phase counter 24b measures the start phase at which output of each pulse of the multiplex pulse is started. Further, the multiple pulse width counter 24d is a counter for measuring the time of each pulse width input to the first to fourth multiplex converters 5u1 to 5u4, and measures the start phase measured by the start phase counter 24b as a reference. At the same time, the pulse width of each multiple pulse is measured.

Let Tk be the pulse width of a group of multiplexed pulses to be input to the master-slave-phase converter 5 this time, and let _{Pk be} the phase difference between these multiplexed pulses. If the pulse width of a group of multiplexed pulses to be input to the next master-phase to slave-phase converter 5 is T _k+1 and the phase difference between these multiplexed pulses is _Pk+1 , the interpolated multiplexed pulse Pu shown in FIG. The width _Tka can be calculated based on the following equation (7).

The pulse calculation unit 23 sequentially measures the phase differences P _k and P _k+1 with the start phase counter 24b, and measures the pulse widths T _k , T _ka , and T _k+1 with the multiple pulse width counter 24d, thereby determining the current multiple pulse, interpolation The multiple pulse Pu and the next multiple pulse can be calculated sequentially. Since multiple pulses can be generated also by the method of this embodiment, the same effects as those of the fourth embodiment can be obtained.

(Modification of Feedback Control Configuration Related to Third to Fifth Embodiments)
Modifications of the feedback control configuration related to the third to fifth embodiments will be described with reference to FIGS. 27 to 31. FIG. The control device 10B may be configured as shown in FIG. The control device 10B incorporates a control section 11B, a pulse generation section 12B, and a memory 37. FIG. The control unit 11B is configured by connecting a subtractor 30, a current controller 31, a two-to-three-phase converter 32 as a phase converter, and a three-to-two-phase converter 34 in the illustrated form.

The controller 11B inputs the d-axis current command value Id* and the q-axis current command value Iq*. The three-phase to two-phase converter 34 of the control unit 11 inputs the phase currents Iu, Iv, and Iw, and also inputs the angle θ of the rotor from the rotational position sensor 4a such as a resolver installed in the motor 4 to obtain the angular velocity ω. Compute information. A three-phase to two-phase converter 34 converts the three-phase currents Iu, Iv, and Iw of the motor 4 into a d-axis current Id and a q-axis current Iq, and outputs the currents to the subtractor 30 .

The subtractor 30 subtracts the d-axis current Id and the q-axis current Iq from the d-axis current command value Id* and the q-axis current command value Iq*, respectively, and outputs the result to the current controller 31 . The current controller 31 outputs dq-axis current command values Id_cmd and Iq_cmd to the two-to-three-phase converter 32 by, for example, proportional integral control. The two-to-three-phase converter 32 converts the operation amount of the dq axis input from the current controller 31 into the current command values Iu_cmd, Iv_cmd, and Iw_cmd for each of the three phases of the motor 4, and outputs them to the pulse generator 12B. .

The pulse generator 12B includes pulse generation blocks 12u, 12v, and 12w for each of the three phases. Each of the pulse generation blocks 12u, 12v, and 12w has functional configurations as a zero current detector 22, a pulse calculator 23Z, and a gate driver 21, respectively. The pulse calculation units 23Z of the phases of the pulse generation blocks 12u, 12v, and 12w respectively receive the current command values Iu_cmd, Iv_cmd, and Iw_cmd for each of the three phases of the motor 4. FIG. The zero current detector 22 detects zero current for each phase and outputs it to the pulse calculator 23Z.

The pulse calculator 23Z calculates the on-time Ton and off-time Toff of the upper arm switch SW1 and the lower arm switch SW2 when each converter 5 of the multiphase converters 6u, 6v, and 6w of each phase operates in the current boundary mode, the period Each parameter of T and the phase difference Td between multiplexed pulses to be input to a plurality of in-phase converters 5 is calculated.

The gate drive section 21 drives the three-phase inverter 3 based on the calculation result of the pulse calculation section 23 . The gate driving section 21 turns on/off the upper arm switch SW1 or the lower arm switch SW2 based on the ON time Ton, period T, and phase difference Td calculated by the pulse calculating section 23 .

The pulse calculator 23Z for each phase calculates the on-time Ton and off-time Toff, the period T and the phase difference Td of the upper arm switch SW1 based on the current command values Iu_cmd, Iv_cmd and Iw_cmd. For example, in the U-phase pulse generation block 12u, when the current command value Iu_cmd>0, the pulse calculation unit 23Z calculates the ON time Ton and OFF time Toff of the upper arm switch SW1, the period T and the phase difference Td as follows: Each is calculated based on the formulas (1-1) to (1-4).

In the V-phase pulse generation block 12v, when the current command value Iv_cmd>0, the pulse calculation unit 23Z calculates the on-time Ton and off-time Toff of the upper arm switch SW1, the period T, and the phase difference Td, respectively ( It is calculated based on the formulas 1-1) to (1-4). In the W-phase pulse generation block 12w, when the current command value Iw_cmd>0, the pulse calculation unit 23Z calculates the on-time Ton and off-time Toff of the upper arm switch SW1, the period T, and the phase difference Td, respectively ( It is calculated based on the formulas 1-1) to (1-4).

The pulse calculator 23Z calculates the on-time Ton and off-time Toff, the period T and the phase difference Td of the upper arm switch SW1 based on the current command values Iu_cmd, Iv_cmd and Iw_cmd. For example, in the U-phase pulse generation block 12u, when the current command value Iu_cmd<0, the pulse calculation unit 23Z calculates the ON time Ton and OFF time Toff of the lower arm switch SW2, the period T and the phase difference Td as follows: Each is calculated based on formulas (2-1) to (2-4).

In the V-phase pulse generation block 12v, when the current command value Iv_cmd<0, the pulse calculation unit 23Z calculates the on-time Ton and off-time Toff of the lower arm switch SW2, the period T, and the phase difference Td, respectively ( It is calculated based on the formulas 2-1) to (2-4). In the W-phase pulse generation block 12w, when the current command value Iw_cmd<0, the pulse calculation unit 23Z calculates the on-time Ton and off-time Toff of the lower arm switch SW2, the period T, and the phase difference Td, respectively ( It is calculated based on the formulas 2-1) to (2-4).

FIG. 23 shows changes in the counter values of the pulse width counter 24a, the start phase counter 24b, and the end phase counter 24c when the counter 24 is used to generate the interpolated multiple pulse Pu. The pulse calculation unit 23 can realize the generation of the interpolated multiple pulse Pu even with the hardware configuration shown in the upper part of FIG.

The pulse calculation unit 23Z executes the processing of the formulas (1-1) to (2-4) to convert the on-time Ton and period T of the upper arm switch SW1 and the lower arm switch SW2 into parameters of the counter 24. is input to the pulse width counter 24a. Then, the pulse calculator 23 inputs the phase difference _Pk+1 between the next multiple pulses to the start phase counter 24b and the end phase counter 24c.

When the phase difference between interpolated multiple pulses Pu is linearly interpolated, for example, the pulse calculator 23Z calculates the average value P _k of the phase difference P _k between the previous multiple pulses and the phase difference P _k+1 between the current multiple pulses. +P _k+1 /2 is obtained, the average value is output to the end phase counter 24c, and the end phase is corrected by the end phase counter 24c. As a result, the counter 24 can be used to generate the 1st to n-th interpolated multiple pulses Pu as shown in FIG. By generating the interpolated multiple pulse Pu using this method, it is possible to maintain the current boundary mode when the pulse width is changed. be.

If the phase voltages Vu, Vv, and Vw are in the region of the maximum value and the minimum value in which they are substantially constant, the interpolated pulse output of the pulse calculator 23 does not cause any problem. See the central view of FIG. However, in the time domain where the phase voltages Vu, Vv, and Vw change sharply, there is a difference between the output of the first multiplexed pulse serving as the master and the output of the second to fourth multiplexed pulses serving as the slave. Voltage is changing. As a result, the current for the ON time Ton of the pulse calculator 23 decreases or increases, and the cycle of the pulse of the slave changes, resulting in an unintended output. See the right diagram of FIG. In the embodiments described later, correction based on the back electromotive voltage is shown, but there are cases where the current boundary mode cannot be maintained even with correction based on the back electromotive force. Experimental examples of the first and second multiplexed pulses at this time are shown in the upper diagram of FIG.

In order to solve this problem, the pulse calculation section 23Z should have the hardware configuration shown in the lower part of FIG. In this hardware configuration, the pulse calculator 23Z corrects the end phase each time the start phase counter 24b and the end phase counter 24c complete the measurement.

At this time, the pulse calculation unit 23Z executes the arithmetic processing of the formulas (1-1) to (2-4) to calculate the on-time Ton and the period T of the upper arm switch SW1 and the lower arm switch SW2 by using a counter. 24 is input to the pulse width counter 24a. Further, the pulse calculator 23Z inputs the phase difference _Pk+1 between the next multiple pulses to the start phase counter 24b and the end phase counter 24c. In the same manner as described above, when the phase difference between interpolated multiple pulses Pu is linearly interpolated, for example, the pulse calculator 23Z calculates the difference between the previous phase difference _Pk between multiple pulses and the current phase difference _Pk+1 between multiple pulses. An average value P _k +P _k+1 /2 is obtained, this average value is output to the end phase counter 24c, and the end phase is corrected by the end phase counter 24c. Further, the pulse calculator 23Z updates the counter values by outputting the correction value A to the end phase counter 24c based on the counter correction instruction every time the start phase counter 24b and the end phase counter 24c complete the measurement.

As shown in the timing chart on the right side of FIG. 30, the value of the end phase counter 24c is gradually changed based on the value of the correction value A. Then, the phase currents Iu, Iv, and Iw can be maintained at intended amplitudes. By doing so, the pulse current boundary mode can be maintained as shown in the lower diagram of FIG.

(Sixth embodiment)
A sixth embodiment will be described with reference to FIGS. 32 to 35. FIG.

The motor 4 generates counter electromotive force due to changes in magnetic flux according to the rotation speed, and the output voltage fluctuates. If the responsiveness of control is insufficient, the counter electromotive force will affect the phase currents Iu, Iv, and Iw, causing harmonic current distortion as shown in FIG. This high-frequency current component causes the motor 4 to generate noise. In this case, unless the responsiveness of the control is increased, the influence of the harmonic current distortion cannot be improved, and there is a possibility that the control device 10 with limited physical resources cannot improve it. In particular, when the motor 4 is rotated at a speed equal to or higher than a predetermined number of revolutions, the output voltage Vout is significantly affected by the back electromotive force, and the current distortion may further increase.

Therefore, in this embodiment, a method for correcting the pulse width of multiple pulses based on the back electromotive force generated in the motor 4 will be described. As shown in FIG. 33 , the control device 10 has a pulse generation section 212 . The control device 10 has a function as a back electromotive voltage corrector 12c.

At this time, let Vm be the amplitude at which the back electromotive force is maximum, and let (ω _e t + φ)=(2πf _e t + φ) be the phase information of the back electromotive force. Here, t is time, ω _e is electrical angular velocity, φ is phase difference with respect to current, and f _e is electrical frequency. It is preferable that the output voltage Vout is operated around half the input voltage Vin, that is, Vin/2. good.

Further, when the pulse generator 212 calculates the amplitude Vm of the back electromotive force, it is preferable to calculate based on the rotation speed of the motor 4 . Then, the pulse generator 212 can calculate the output voltage Vout based on the rotational position of the motor 4, the amplitude Vm of the back electromotive force, and the phase information, and correct the pulse width of the multiplexed pulse based on the output voltage Vout. desirable. Specifically, for example, Vout can be calculated as the formula (8).

The back electromotive force is a peculiar value based on the individual motor 4, so it can be predicted. For example, it is preferable to calculate and predict the counter electromotive force by multiplying the number of rotations of the motor 4 by the counter electromotive voltage constant unique to the motor 4 . Further, in order to correct the pulse width with high accuracy, the voltage generated in the winding resistance and inductance of the motor 4 should be considered in addition to the back electromotive force of the output voltage Vout.

The control device 10 obtains the rotation speed of the motor 4 using the sensing result of the rotation position sensor 4a of the motor 4, and based on the three phase currents Iu, Iv, and Iw and the position of the rotor of the motor 4, the phase currents Iu, Vector control is performed by converting Iv and Iw into currents in the direction of magnetic force related to torque.

An example of the feedback control configuration at this time will be described with reference to FIG. The control unit 11 is configured by connecting a subtractor 30, a current controller 31, a two-to-three-phase converter 32 as a phase converter, and a three-to-two-phase converter 34 in the illustrated form.

The control unit 11 inputs the current command value Io and performs current feedback control based on the current difference between the phase currents Iu, Iv, and Iw of the motor 4 . The three-phase to two-phase converter 34 converts the three-phase currents into dq-axis currents, and the current controller 31 outputs dq-axis manipulated variables by, for example, proportional integral control. The two-to-three-phase converter 32 converts the operation amount of the dq axes input from the current controller 31 into an operation amount for each of the three phases of the motor 4 .

In this embodiment, the pulse generator 212 has the functions of the back electromotive voltage corrector 12 c and the pulse calculator 33 . The pulse calculator 33 calculates parameters including the on-time Ton1, the off-time Toff1, the period T, and the phase difference Td of the multiple pulses to be input to the converter 5 for each phase of the motor 4. FIG. These on-time Ton1, off-time Toff1, period T, and the on-time Ton1, off-time Toff1, period T, and the above-described formulas (1-1) to (1-4) when the current command value Io is positive. It can be calculated using the phase difference Td. Also, when the current command value Io is negative, it can be calculated using the on-time Ton2, off-time Toff2, period T, and phase difference Td of the above-described equations (2-1) to (2-4).

The function of the back electromotive voltage correction unit 12c here is, for example, a process of calculating the amplitude Vm of the back electromotive force from the rotation speed of the motor 4, and calculating the output voltage Vout based on the amplitude Vm of the back electromotive voltage and phase information. including processing. When the parameters are calculated for each phase of the motor 4, the pulse calculator 33 corrects the width of the pulse based on the output voltage in consideration of the counter electromotive force by the function of the counter electromotive voltage corrector 12c. Since the amplitude Vm of the back electromotive force is proportional to the number of revolutions of the motor 4, it is desirable to calculate the amplitude Vm of the back electromotive force so as to be proportional to the number of revolutions of the motor 4. FIG.

As a control method, the current control method is exemplified above, but a control unit 211 may be configured instead of the control unit 11 as shown in FIG. The control unit 211 includes a speed controller 35 and a subtractor 36 in addition to the subtractor 30 , current controller 31 , two-to-three-phase converter 32 and three-to-two-phase converter 34 . As shown in the controller 211, the rotational position sensor 4a may be used to determine the angular velocity .omega. . At this time, a non-interference control method that eliminates mutual interference between the d-axis current and the q-axis current may be used. As a result, destabilizing factors that occur when the motor 4 is driven can be eliminated. If the counter-electromotive voltage becomes large with respect to the input voltage Vin, it is desirable to perform field-weakening control.

Each converter 5 is configured by connecting step-down converters in parallel as shown in FIG.

In the above example, the back electromotive force is calculated from the number of revolutions of the motor 4, but a map linking the number of revolutions of the motor 4, the amplitude Vm of the back electromotive force, and the phase information is prepared in advance in the memory 37. You can leave it. The pulse generator 212 may refer to the amplitude Vm and phase information of the back electromotive force stored in the memory 37 corresponding to the number of revolutions of the motor 4 to correct the width of the multiplex pulse. Further, while the output voltage Vout is being detected by the voltage sensor 15, the delay time based on the detection by the voltage sensor 15 may be considered and used for the calculation.

The pulse generation unit 212 preferably causes the memory 37 to store the result of periodically correcting the width of the multiple pulse according to the counter electromotive force by the back electromotive voltage correcting unit 12c in correspondence with the current command value Io or the command rotation speed. . Further, while the pulse calculation unit 33 is periodically calculating the correction contents based on the next current command value Io, the present or past calculation results regarding the multiple pulses held in the memory 37 are used. , the width of the multiple pulse may be corrected by the function of the back electromotive voltage corrector 12c.

As shown in the present embodiment, by correcting the pulse width based on the back electromotive force by the back electromotive force correction unit 12c, the back electromotive force of the motor 4 can be incorporated into the calculation of the pulse width in a feedforward manner. . As a result, as shown in FIG. 36, the current waveform can be more closely approximated to the desired ideal sine wave, and high efficiency, low noise, and low EMC can be achieved. Moreover, it can be realized by a simple and simple control system with only current feedback control.

(Seventh embodiment)
A seventh embodiment will be described. For example, in the converter 5 shown in FIGS. 3 and 33, when the upper arm switch SW1 as the first arm switch is turned on/off while the lower arm switch SW2 is kept off, the current is commutated through the inductor L and the free wheel diode D2.

At this time, instead of the freewheeling action of the freewheeling diode D2, synchronous rectification may be performed by turning on the lower arm switch SW2 facing the upper arm switch SW1 as a second arm switch.

Loss can be further reduced by synchronous rectification. In addition, the external freewheeling diode D2 becomes unnecessary, and the size can be reduced. For synchronous rectification, the above-described off-time Toff of the pulse is calculated using the formula (for example, the off-time Toff1 in formula (1-2), the off-time Toff2 in formula (2-2), or the off-time Toff2 in formula (3-2). It is preferable to turn on the opposite upper arm switch SW1 only for the time set based on the off time Toff1). However, in order to prevent a short circuit between the power switches SW1 and SW2, it is desirable to provide a dead time between the on-time Ton of the upper arm switch SW1 and the lower arm switch SW2.

According to the synchronous rectification method described above, the synchronous rectification time can be estimated and obtained by calculation. In this case, there is no need to provide a separate sensor outside to detect the timing of synchronous rectification, so the system can be made smaller and less expensive.

As described above, when the current command value Io>0, the on-time Ton1 of the upper arm switch SW1, the period T, and the phase difference Td are expressed by the equations (1-1), (1-3), and (1-1), respectively. 4) The synchronous rectification time is set in the same manner as the formula (1-2), but it is preferable to set the time equal to the OFF time Toff1 shown in the formula (1-2) corresponding to the ON time Ton2 of the lower arm switch SW2 during synchronous rectification. .

When the current command value Io<0, the on-time Ton2, period T, and phase difference Td of the lower arm switch SW2 are given by equations (2-1), (2-3), and (2-4) respectively. A time equal to the off-time Toff2 shown in equation (2-2) may be set corresponding to the on-time Ton1 of the upper arm switch SW1 during synchronous rectification.

(Modification of Feedback Control Configuration Related to Sixth and Seventh Embodiments)
Modifications of the feedback control configuration related to the sixth and seventh embodiments will be described with reference to FIGS. 37 to 42. FIG. The control device 10C may be configured as shown in FIG. The controller 10C incorporates a controller 11C, a pulse generator 12C, and a memory 37. FIG. The control unit 11C is configured by connecting a subtractor 30, a current controller 31, a two-to-three-phase converter 32 as a phase converter, and a three-to-two-phase converter 34 in the illustrated form.

The controller 11C inputs a d-axis current command value Id* and a q-axis current command value Iq*. A three-phase to two-phase converter 34 of the control unit 11C receives the phase currents Iu, Iv, and Iw, and also inputs the rotor angle θ from the rotational position sensor 4a to calculate information on the angular velocity ω. A three-phase to two-phase converter 34 converts the three-phase currents Iu, Iv, and Iw of the motor 4 into a d-axis current Id and a q-axis current Iq, and outputs the currents to the subtractor 30 .

The subtractor 30 subtracts the d-axis current Id and the q-axis current Iq from the d-axis current command value Id* and the q-axis current command value Iq*, respectively, and outputs the result to the current controller 31 . The current controller 31 outputs dq-axis current command values Id_cmd and Iq_cmd to the two-to-three-phase converter 32 by, for example, proportional integral control. The two-to-three-phase converter 32 converts the operation amount of the dq axis input from the current controller 31 into current command values Iu_cmd, Iv_cmd, and Iw_cmd for each of the three phases of the motor 4, and outputs them to the pulse generator 12A. .

The pulse generation unit 12C includes pulse generation blocks 12u, 12v, and 12w for each of three phases. Each of the pulse generation blocks 12u, 12v, and 12w includes a zero current detection unit 22, a pulse calculation unit 23, a gate drive unit 21, and a back electromotive force correction unit 12c for correcting the pulse based on the back electromotive force. It has a functional configuration. The pulse calculation units 23 of the phases of the pulse generation blocks 12u, 12v, and 12w respectively receive current command values Iu_cmd, Iv_cmd, and Iw_cmd for the three phases of the motor 4 . The zero current detector 22 detects zero current for each phase and outputs it to the pulse calculator 23 .

The pulse calculator 23 calculates the on-time Ton and off-time Toff of the upper arm switch SW1 and the lower arm switch SW2 when each converter 5 of the multiphase converters 6u, 6v, and 6w of each phase operates in the current boundary mode, the period Each parameter of T and a phase difference Td between multiple pulses to be input to a plurality of converters 5 in phase (for example, U phase) is calculated.

The gate drive section 21 drives the three-phase inverter 3 based on the calculation result of the pulse calculation section 23 . The gate driving section 21 turns on/off the upper arm switch SW1 or the lower arm switch SW2 based on the ON time Ton, period T, and phase difference Td calculated by the pulse calculating section 23 .

The memory 37 stores in advance a map that associates the rotation speed of the motor 4 with the amplitude Vm of the back electromotive voltage and the phase difference φ. The back electromotive force correction unit 12c for each phase refers to the motor rotation speed dependent on the angle θ of the motor 4 by comparing it with the stored contents of the memory 37, and calculates the amplitudes Vm_u, Vm_v, Vm_w, and the amplitudes of the back electromotive force for each phase. Input the phase differences φ_u, φ_v and φ_w.

The back electromotive force correction unit 12c of each phase calculates the output voltages Vout_u, Vout_v, and Vout_w based on the power supply voltage Vin as well as the amplitudes Vm_u, Vm_v, and Vm_w of the back electromotive force and the phase differences φ_u, φ_v, and φ_w. At this time, the back electromotive force correcting unit 12c calculates the output voltage Vout as shown in the above equation (8) as shown in FIG. As a result, the influence of the back electromotive force can be corrected in the same manner as in the above-described embodiment. As illustrated in FIG. 39, the output voltage Vout can be corrected based on the back electromotive force, and as illustrated in FIG. 40, the influence of harmonic current distortion can be eliminated as much as possible for improvement.

Further, when the number of revolutions of the motor 4 becomes high, the amplitude Vm of the back electromotive force becomes large. As the amplitude Vm of the output voltage Vout approaches the power supply voltage Vin, the voltage generated in the inductor L becomes smaller and current cannot flow through the inductor L. In this case, there is a possibility that control becomes impossible and operation becomes impossible. Therefore, as shown in FIG. 41, it is desirable to provide a power supply voltage utilization factor improvement control unit 21d for improving the utilization factor of the power supply voltage Vin. When the amplitude Vm of the back electromotive force exceeds a predetermined threshold value, the voltage utilization rate improvement control unit 12d sets upper and lower limits to the output voltage Vout after correcting the back electromotive voltage and outputs the corrected output voltage Vout.

For example, the upper limit is set to a value slightly lower than the power supply voltage Vin, and the lower limit is set to a value slightly higher than the reference value 0 of the power supply voltage Vin. If the output voltage Vout after correction of the back electromotive force exceeds the upper limit, the voltage utilization factor improvement control unit 12d clamps it to stay at the upper limit, and if it falls below the lower limit, clamps it to stay at the lower limit.

As a result, the pulse calculation unit 23 can perform pulse calculation in a state in which the sine wave peak of the output voltage Vout for pulse width correction calculation is limited by the upper limit and the lower limit. Since upper and lower limits are set for the output voltage Vout, even if a relatively large back electromotive force is generated, the device can be operated without problems, and the operable range can be widened. Also, the voltage utilization rate can be increased.

(Eighth embodiment)
An eighth embodiment will be described with reference to FIG. In the sixth and seventh embodiments described above, the number n of multiple operations is not limited to 2 or more, and can be applied to the case of n=1.

That is, as shown in FIG. 43, in each phase of the UVW phase, converters 5u1, 5v1, and 5w1 corresponding to the master phase and having n=1 in multiple operation are used to generate a single pulse for each phase to drive the motor 4. You may make it drive.

(Ninth embodiment)
The ninth embodiment will be described with reference to FIG. The control device 10D may be configured as shown in FIG. The control device 10D includes all of the multiplex number switching section 25A in the control device 10A, the pulse calculation section 23Z in the control device 10B, and the back electromotive voltage correction section 12c in the control device 10C described in the above embodiment. That is, it can be applied to a configuration having all the features of the above-described embodiments. Here, the multiplex number switching section may be configured by 25, the pulse calculation section by 23, and the back electromotive voltage correction section by "12" or "12d".

(Other embodiments)
The present invention is not limited to the above-described embodiments, but can be implemented in various modifications, and can be applied to various embodiments without departing from the scope of the invention. For example, the following modifications or extensions are possible.

Although the power converter using the step-down converter 5 is described in the above-described embodiment, the present invention is not limited to this, and for example, a step-up or step-up/step-down converter 5 can be used. Also, the converter 5 may be of a non-insulated type or an insulated type. The voltage sensor 15 may be provided as required.

In the above embodiment, the number n of multiple operations is set to 4 or 2, but the number n of multiple operations may be 3 or 5 or more. In the above-described embodiment, the power switches SW1 and SW2 are N-channel power MOSFETs, but they may be composed of other types of power switching elements.

In the above embodiment, the freewheeling diodes D1 and D2 are provided in parallel to commutate the load current to the power MOSFETs forming the power switches SW1 and SW2, but the present invention is not limited to this. A body diode added to the power MOSFET may be used instead of the freewheeling diodes D1 and D2. Alternatively, a power switch having reverse conductivity (for example, a reverse-conducting IGBT (RC-IGBT)) may be used.

5un, 5v2 . . . _5vn , 5w2 . After detection, the corresponding power switch SW1 or SW2 may be turned on. As the on-time Ton of the power switches SW1 and SW2, it is desirable to use the on-time Ton calculated by the above-described formula (1-1), formula (2-1), or formula (3-1).

The "control unit 11" and "pulse generation units 12, 112, 212", which are the components of the control device 10, may be realized using hardware that combines logic circuits, or hardware such as a microcomputer may be used. It may be realized by executing a program.

The approach according to the controllers 10, 10A, 10B, 10C, 10D described in this disclosure is by configuring a processor and memory programmed to perform one or more functions embodied by a computer program. It may be realized by a provided dedicated computer. Alternatively, the controllers 10, 10A, 10B, 10C, 10D and techniques described in this disclosure may be implemented by a dedicated computer provided by configuring a processor with one or more dedicated hardware logic circuits. . Alternatively, the controllers 10, 10A, 10B, 10C, 10D and techniques described in this disclosure can be implemented using a processor and memory and one or more hardware logic circuits programmed to perform one or more functions. It may be implemented by one or more dedicated computers configured in combination with a processor configured by . The computer program may also be stored as computer-executable instructions on a computer-readable non-transitional tangible storage medium.

Although the present invention has been described with reference to the embodiments described above, it is understood that the invention is not limited to such embodiments or constructions. The present invention includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations including one, more, or less elements thereof, are within the scope and spirit of the invention.

In the drawing, 3 is a three-phase converter (power converter), 5, 5u1, 5v1, 5w1, 5u2, 5v2, 5w2, 5u3, 5v3, 5w3, 5un, 5vn, and 5wn are converters, and 6u, 6v, and 6w are multiphase 10 and 10A are controllers; 11 and 11A are control units; 12 is a pulse generator; 22 is a zero current detector; , SW2 denotes a lower arm switch.

Claims (8)

A power converter (3) comprising two or more n converters (5u1...5un, 5v1...5vn, 5w1...5wn) connected in parallel,
a control unit (11; 11A) that outputs control information according to an input command value;
a pulse generation section (12; 12A), comprising a pulse calculation section, for generating a multiple pulse so as to cause the n converters to perform multiple operations based on the control information output from the control section;
a multiple operation number changing unit (25, 25A) for changing the multiple operation number of the converter;
a power converter. The pulse generator is
a gate driver (21) for driving the converter;
a zero current detector (22) for detecting when the current of the converter driven by the gate driver reaches zero;
the pulse calculation unit (23) for obtaining the on-time and period of the multiple pulses when operating the converter, and the phase difference between the multiple pulses and outputting them to the gate driving unit;
The power converter according to claim 1, wherein the gate drive section drives the converter based on the output of the pulse calculation section. The converter includes an upper arm switch (SW1) and a lower arm switch (SW2) to which a power supply voltage is input, and a step-down converter using an inductor (L) and a capacitor (C),
The gate driving section drives the upper arm switch of the converter when the current command value as the command value is positive. , and the period T and the phase difference Td between the multiple pulses are set based on formulas (1-1) to (1-4), respectively,
The gate drive section drives the lower arm switch of the converter when the current command value as the command value is negative. 3. The power converter according to claim 2, wherein the period T and the phase difference Td between the multiple pulses are set based on the formulas (2-1) to (2-4).
Here, Vin is the input voltage, Vout is the output voltage, IL is the inductor current, _L is the inductance of the inductor, and n is the number of multiple operation converters.

The multiple operation number changing unit
4. The power converter according to any one of claims 1 to 3, wherein the number of multiple operations of the converter is changed according to a current command value as the command value. The multiple operation number changing unit
5. The power converter according to claim 4, wherein the phase difference calculation in the pulse calculation unit is omitted by changing the number of multiple operations in units of 2̂n according to the current command value. The pulse generator is
6. The power converter according to any one of claims 1 to 5, wherein an output of said multiplexing operation number changing unit is received to generate an interpolated multiplexed pulse for interpolating between said current multiplexed pulse and said next multiplexed pulse. vessel. 7. The power converter according to any one of claims 1, 2, 4 to 6, wherein the converter is configured by a step-down type, step-up type, or buck-boost type converter. 8. The power converter according to any one of claims 1, 2, 4 to 7, wherein said converter is configured by a non-isolated or isolated converter.

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