JP2022124715A - Dcdc converter - Google Patents

Abstract

To provide a DCDC converter in which power consumption is small and switching operation can be performed at a high frequency.SOLUTION: A DCDC converter includes a comparator 10 that compares a reference voltage and a feedback voltage, an on-time control circuit 11 that controls an on time of a power FET 2, and a R-S flip-flop circuit 13 that outputs a signal for controlling the power FET 2. The on-time control circuit 11 includes a switch 23 that is controlled by a signal based on the on of the power FET 2, a capacitor 22 that is discharged when the switch 23 is turned on and is charged by a first current source 21, and a detection circuit that is formed of a MOS transistor 25 the gate voltage of which is controlled by voltages of a second current source 24 and the capacitor 22, and that outputs a signal for turning off the power FET 2 on the basis of the voltage of the capacitor 22.SELECTED DRAWING: Figure 2

Description

The present invention relates to DCDC converters.

2. Description of the Related Art Constant on-time control with excellent load responsiveness is often used in power supply devices such as DCDC converters. Constant on-time control is a control method in which a switching transistor is controlled by an output signal based on a signal from an on-time control circuit (see Patent Document 1, for example).

FIG. 4 is a circuit diagram showing a conventional on-time control circuit. A conventional on-time control circuit includes a capacitor 42 and a comparator 45 that measures the time until the capacitor 42 is charged to a desired voltage by the current supplied by the current source 41 .

U.S. Pat. No. 8,476,887

However, in the conventional on-time control circuit, it was difficult to switch the switching transistor at a high frequency due to the effect of the delay time from when the comparator 45 detects the voltage of the capacitor 42 to when it outputs the signal. In particular, a DCDC converter with low current consumption is required to set the operating current of the comparator 45 (the current of the current source 44) to be small, so it has been difficult to increase the frequency.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a DCDC converter that consumes less current and is capable of high-frequency switching operation.

The DCDC converter of the present invention includes a comparator that compares a reference voltage and a feedback voltage, an on-time control circuit that controls the on-time of the power FET, and controls the power FET according to the signal of the comparator and the signal of the on-time control circuit. an RS flip-flop circuit for outputting a signal, the on-time control circuit comprising: a switch controlled by a signal based on turning on of the power FET; and a first current source discharged by turning on the switch. and a detection circuit configured by a second current source and a MOS transistor whose gate voltage is controlled by the voltage of the capacitor and outputting a signal to turn off the power FET based on the voltage of the capacitor. characterized by

According to the DCDC converter of the present invention, the switching operation can be performed at a high frequency with low current consumption.

1 is a block diagram showing a DCDC converter of this embodiment; FIG. It is a circuit diagram showing an on-time control circuit of an embodiment of the present invention. It is a circuit diagram showing another example of the on-time control circuit of the present embodiment. 1 is a circuit diagram showing a conventional on-time control circuit; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a DCDC converter 100 of this embodiment.
The DCDC converter 100 of this embodiment includes a power FET 2, an inductor 3, a Schottky diode 4, a capacitor 5, a comparator 10, an on-time control circuit 11, a reference voltage circuit 12, and an RS flip-flop circuit. 13 , an output control circuit 14 , a driver circuit 15 , and feedback resistors 17 and 18 .

Feedback resistors 17 and 18 are connected between the output terminal OUT and the GND terminal. The comparator 10 has an inverting input terminal − connected to the output terminals of the feedback resistors 17 and 18 and a non-inverting input terminal + connected to the reference voltage circuit 12 . The RS flip-flop circuit 13 has a set terminal S connected to the output terminal of the comparator 10, a reset terminal R connected to the output terminal of the on-time control circuit 11, and an output terminal Q connected to the input terminal of the output control circuit 14. , and the output terminal QB is connected to the input terminal of the on-time control circuit 11 . The driver circuit 15 has an input terminal connected to the output terminal of the output control circuit 14 and an output terminal connected to the gate of the power FET 2 . The power FET 2 has a source connected to the power supply terminal and a drain connected to one terminal of the inductor 3 and the cathode of the Schottky diode 4 . The other terminal of inductor 3 is connected to output terminal OUT and one terminal of capacitor 5 . The other terminal of Schottky diode 4 is connected to the GND terminal. The other terminal of capacitor 5 is connected to the GND terminal.

FIG. 2 is a circuit diagram showing the on-time control circuit 11 of this embodiment.
The on-time control circuit 11 of this embodiment includes current sources 21 and 24 , a capacitor 22 , NMOS transistors 23 and 25 and an inverter circuit 26 .

The current source 21 has one end connected to the power supply terminal and the other end connected to one end of the capacitor 22 . The NMOS transistor 23 has a drain connected to one end of the capacitor 22 , a source connected to the GND terminal, and a gate connected to the output terminal QB of the RS flip-flop circuit 13 . The other end of the capacitor 22 is connected to the GND terminal. The current source 24 has one end connected to the power supply terminal and the other end connected to the input terminal of the inverter circuit 26 . The NMOS transistor 25 has a drain connected to the other end of the current source 24 , a source connected to the GND terminal, and a gate connected to one end of the capacitor 22 . The output terminal of the inverter circuit 26 is connected to the reset terminal R of the RS flip-flop circuit 13 . In the on-time control circuit 11, the gate of the NMOS transistor 23 is the input terminal, and the output terminal of the inverter circuit 26 is the output terminal. Current source 24 and NMOS transistor 25 constitute a detection circuit that detects the voltage of capacitor 22 .

The operations of the on-time control circuit 11 and the DCDC converter 100 of this embodiment will be described below with reference to FIGS.

The DCDC converter 100 outputs an output voltage Vout from an output terminal when a voltage Vin is input to a power supply terminal. Feedback resistors 17 and 18 output a feedback voltage based on the output voltage Vout. The comparator 10 outputs an H level signal when the feedback voltage is lower than the reference voltage output from the reference voltage circuit 12 . Since the set terminal S of the RS flip-flop circuit 13 receives an H level signal, the output terminal Q outputs an H level signal, and the output terminal QB outputs an L level signal. When the output control circuit 14 receives an H level signal, it outputs an L level signal from the output terminal to turn on the power FET 2 via the driver circuit 15 .

When the ON-time control circuit 11 receives an L-level signal, the ON-time control circuit 11 outputs an H-level signal after a predetermined time has elapsed. Since an H level signal is input to the reset terminal R of the RS flip-flop circuit 13, the output terminal Q outputs an L level signal and the output terminal QB outputs an H level signal. The output control circuit 14 outputs an H level signal from the output terminal when the L level signal is input, and turns off the power FET 2 via the driver circuit 15 .

In the on-time control circuit 11 of FIG. 2, when an H level signal is input from the output terminal QB of the RS flip-flop circuit 13 to the input terminal, the NMOS transistor 23 is turned on and the NMOS transistor 25 is turned off. Therefore, an L level signal is output from the output terminal.

When the input terminal of the on-time control circuit 11 receives an L level signal from the output terminal QB of the RS flip-flop circuit 13, the NMOS transistor 23 is turned off, and the current from the current source 21 charges the capacitor 22. is started. When the voltage of the capacitor 22 rises due to charging and the gate voltage of the NMOS transistor 25 reaches a predetermined voltage, the voltage of the input terminal of the inverting circuit 26 becomes L level. Output a signal.

Here, the gate voltage of the NMOS transistor 25 for changing the voltage of the input terminal of the inverting circuit 26 from the H level to the L level is constant with respect to the voltage characteristics and the temperature characteristics. It is possible to That is, the on-time control circuit 11 can guarantee a constant on-time with respect to power supply voltage and temperature.

As described above, the DCDC converter 100 of the present embodiment does not use a comparator in the on-time control circuit 11, so current consumption is small and switching operation can be performed at a high frequency. In addition, it is possible to guarantee a constant ON time with respect to power supply voltage and temperature. Furthermore, since the on-time control circuit 11 does not use a comparator, it is effective in reducing the circuit area.

FIG. 3 is a circuit diagram showing another example of the on-time control circuit 11 of this embodiment.
The on-time control circuit 11 of FIG. 3 includes current sources 31 and 34, a capacitor 32, and PMOS transistors 33 and 35.

The current source 31 has one end connected to the GND terminal and the other end connected to one end of the capacitor 32 . The PMOS transistor 33 has a drain connected to one end of the capacitor 32 , a source connected to the power supply terminal, and a gate connected to the output terminal Q of the RS flip-flop circuit 13 . The other end of the capacitor 32 is connected to the power supply terminal. The current source 34 has one end connected to the GND terminal and the other end connected to the reset terminal R of the RS flip-flop circuit 13 . The PMOS transistor 35 has a drain connected to the other end of the current source 34 , a source connected to the power supply terminal, and a gate connected to one end of the capacitor 32 . The on-time control circuit 11 has the gate of the PMOS transistor 33 as an input terminal and the other end of the current source 34 as an output terminal. Current source 34 and PMOS transistor 35 constitute a detection circuit that detects the voltage of capacitor 32 .

Since the operation of the on-time control circuit 11 in FIG. 3 is the same as that of the on-time control circuit 11 in FIG. 2 except that the level of the signal is inverted, detailed description thereof will be omitted. Therefore, even if the on-time control circuit 11 is configured as shown in FIG. 3, the same effects as those of the on-time control circuit 11 of FIG. 2 can be obtained.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the present invention. For example, the NMOS transistor 23 and the PMOS transistor 33 are not limited to MOS transistors as long as they have a switch function. Also, for example, the on-time control circuit 11 is configured to start operation by the output signal of the RS flip-flop circuit 13, but it is not limited to this signal as long as it indicates that the power FET 2 is turned on.

2 power FETs
3 inductor 4 Schottky diode 5 capacitor 10 comparator 11 ON time control circuit 12 reference voltage circuit 13 RS flip-flop circuit 14 output control circuit 15 driver circuit 17, 18 feedback resistor 21, 24, 31, 34 current source 22, 32 Capacitor 23, 25 NMOS transistor 26 Inversion circuit 33, 35 PMOS transistor 100 DCDC converter

Claims (3)

a comparator that compares the reference voltage and the feedback voltage;
an on-time control circuit for controlling the on-time of the power FET;
an RS flip-flop circuit that outputs a signal for controlling the power FET according to the signal of the comparator and the signal of the on-time control circuit;
The on-time control circuit includes a switch controlled by a signal based on the turn-on of the power FET, a capacitor discharged by the turn-on of the switch and charged by a first current source, and a second current source. and a detection circuit configured by a MOS transistor whose gate voltage is controlled by the voltage of the capacitor and outputting a signal for turning off the power FET based on the voltage of the capacitor. 2. The DCDC converter according to claim 1, wherein said second current source is composed of a depression type MOS transistor. 3. The DCDC converter according to claim 1, wherein said switch is composed of a MOS transistor of the same conductivity type as said MOS transistor.

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