JP2022122356A - game machine - Google Patents

Abstract

To secure the capacity of the control area for performing a game control process.SOLUTION: A game machine of the present invention comprises: winning type lottery means for determining by lottery one of winning areas corresponding to each of multiple winning types; a group identification unit for identifying which of a first group information piece or a second group information piece, that includes the determined winning area out of multiple first group information pieces (performance determination groups) grouping a part of the multiple winning areas and multiple second group information pieces (specific identifiers) grouping a part of the multiple winning areas; a first processing execution unit for executing a first process on the basis of the first group information piece; and a second processing execution unit for executing a second process on the basis of a combination (winning combination group) of the first group information piece and the second group information piece.SELECTED DRAWING: Figure 48

Description

TECHNICAL FIELD The present invention relates to a gaming machine that determines by lottery whether or not to give a game profit to a player.

2. Description of the Related Art In a slot machine as a gaming machine, a lottery for a winning combination is performed in accordance with a player's betting of medals (game media) and operation of a start switch, and rotation of a plurality of reels on which various symbols are marked is controlled. . Then, the reels are sequentially stopped according to the result of the lottery and the operation of the stop switch by the player, and when the symbol combination corresponding to the winning combination is displayed on the effective line, which is the line to be paid out, a predetermined number of symbols are displayed. medals are paid out (hereinafter simply referred to as "game profit") is given to the player.

Further, in the slot machine, a plurality of game states are provided in which the player's degree of advantage (game profit) differs during the progress of the game. For example, when a winning combination with a large gaming profit (hereinafter referred to as a correct combination) and another winning combination are won in a winning type (hereinafter referred to as a selected winning combination), a stop switch is used as a winning condition for the correct combination. (hereinafter referred to as the correct operation mode) (hereinafter referred to as the operation mode of the winning condition for such a predetermined winning combination (assisting the winning of the correct combination)) simply assists the effect. There are also slot machines provided with an AT effect state in which a so-called AT (assist time) is executed, in which the player can easily display the symbol combination corresponding to the correct combination on the activated line. be. In addition, an RT (replay time) game state in which the probability of winning a replay combination is set to be high may be used, or a so-called ART game state in which the above AT effect state and RT game state progress at the same time may be used (for example, patent Reference 1).

JP 2011-010751 A

In a game machine, a program related to game control processing for controlling the progress of a game must be placed in a use area (control area 4.5 kbytes+data area 3.0 kbytes) in the ROM of the main control board.

However, when the main control board manages the AT effect state in which the above-described auxiliary effect is executed, or when the main control board manages the so-called reel effect that rotates the reel unit in various modes, the use area especially the control area of the

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gaming machine capable of securing the capacity of a control area for performing game control processing.

In order to solve the above-mentioned problems, the gaming machine of the present invention includes winning type lottery means for determining by lottery one of the winning areas corresponding to each of a plurality of winning types, and grouping a part of the plurality of winning areas. First group information and second group information including the determined winning area among the plurality of first group information and the plurality of second group information obtained by grouping a part of the plurality of winning areas a group identifying unit that identifies a group, a first processing executing unit that executes a first process based on the first group information, and a second process that executes a combination of the first group information and the second group information and a second process execution unit.

According to the present invention, it is possible to ensure the capacity of the control area for performing the game control process.

1 is an external view for explaining a schematic mechanical configuration of a slot machine; FIG. FIG. 2 is an external view of the slot machine with the front door opened, for explaining the schematic mechanical configuration of the slot machine; FIG. 10 is a diagram for explaining symbol arrays on reels and activated lines; 1 is a block diagram showing a schematic electrical configuration of a slot machine; FIG. It is an explanatory diagram for explaining a winning combination. It is a figure which shows a prize type lottery table. It is an explanatory diagram for explaining the transition of the game state. It is an explanatory view for explaining the transition of the production state. It is a flow chart explaining CPU initialization processing in a main control board. 4 is a flowchart for explaining cold start processing in the main control board; It is a flow chart explaining error stop processing in a main control board. 4 is a flowchart for explaining set value switching processing in a main control board; It is a flow chart explaining initialization start processing in a main control board. It is a flowchart explaining the state return processing in a main control board. It is a flow chart explaining the game start processing in the main control board. It is a flow chart explaining game medal insertion processing in the main control board. It is a flow chart explaining internal lottery processing in a main control board. It is a flow chart explaining the design code setting processing in the main control board. 4 is a flowchart for explaining execution flag setting processing in a main control board 200; FIG. 11 is a flowchart for explaining non-advantageous section processing executed in state-specific module execution processing; FIG. It is a flowchart explaining the normal production|presentation state processing performed by module execution processing classified by state. FIG. 11 is a flowchart for explaining CZ effect state processing executed in state-specific module execution processing; FIG. FIG. 10 is a flowchart for explaining reel effect state processing executed in state-specific module execution processing; FIG. It is a flow chart explaining the withdrawal effect state processing that is executed in the module execution processing by state. FIG. 10 is a flowchart for explaining processing during rotation of the drum in the main control board; FIG. FIG. 11 is a flow chart for explaining a spinning drum stopping process in a main control board; FIG. It is a flow chart explaining display judging processing in a main control board. It is a flow chart explaining the payout process in the main control board. It is a flow chart explaining the game transition processing in the main control board. FIG. 10 is a flow chart for explaining save processing at power-off in the main control board; FIG. It is a flow chart explaining timer interruption processing in a main control board. FIG. 2 is a diagram for explaining electrical connections around a main CPU; 2 is a block diagram showing the internal configuration of a CPU core; FIG. FIG. 4 is a diagram explaining the configuration of a register; FIG. 4 is an explanatory diagram showing a memory map; It is a program code showing specific processing of the winning combination group setting processing. It is the program code which showed the specific process of the lottery data acquisition process. It is a program code which shows an internal lottery offset table. It is a program code which shows another example of an internal lottery offset table. It is the program code which showed the specific process of a subtraction number acquisition process. FIG. 11 is a program code showing another example of winning combination group setting processing; FIG. 7 is program code showing another example of subtraction number acquisition processing. It is the program code which showed the concrete processing of the design code initialization processing. It is a program code showing a symbol bit offset table. FIG. 11 is a program code showing another example of winning combination group setting processing; FIG. It is the program code which showed the other example of the design code initialization process. It is a program code showing another example of the symbol bit offset table. It is an explanatory view for explaining a winning type lottery table. FIG. 11 is a program code showing another example of winning combination group setting processing; FIG.

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The dimensions, materials, and other specific numerical values shown in these embodiments are merely examples for facilitating understanding of the invention, and do not limit the invention unless otherwise specified. In the present specification and drawings, elements having substantially the same function and configuration are given the same reference numerals to omit redundant description, and elements that are not directly related to the present invention are omitted from the drawings. do.

(Mechanical Configuration of Slot Machine 100)
As shown in the external views of FIGS. 1 and 2, a slot machine 100 as a game machine includes a housing 102 with an open front surface and a front surface arranged vertically and rotatably at one end of the front surface of the housing 102. An upper door 104 and a lower front door 106 are provided. A colorless and transparent pattern display window 108 made of a glass plate, a transparent resin plate, or the like is provided at approximately the center of the lower portion of the upper front door 104. At a position corresponding to the pattern display window 108 in the housing 102 , three reels 110 (a left reel 110a, a middle reel 110b, and a right reel 110c) are independently rotatable. As shown in the pattern arrangement of FIG. 3(a), a plurality of types of symbols are arranged in each area divided into 20 on the outer peripheral surfaces of the left reel 110a, the middle reel 110b, and the right reel 110c. Through the symbol display window 108, the player can visually recognize a total of nine symbols, which are three continuous symbols of the left reel 110a, the middle reel 110b, and the right reel 110c located in the upper, middle, and lower stages.

An operation unit installation table 112 is formed on the upper part of the front lower door 106, and the operation unit installation table 112 is provided with a medal insertion unit 114, a bet switch 116, a start switch 118, a stop switch 120, a production switch 122, and the like. there is The medal insertion unit 114 receives insertion of medals as game value through a medal insertion slot 114a. The bet switch 116 inserts (bets) a prescribed number of medals required for one game among the medals electrically stored (hereinafter simply referred to as credits) inside the slot machine 100 .

The start switch 118 is composed of, for example, a lever capable of detecting a tilting operation, and detects a game start operation by the player. The stop switches 120 (stop switch 120a, stop switch 120b, stop switch 120c) are provided corresponding to the left reel 110a, middle reel 110b, and right reel 110c, respectively, and detect a player's stop operation. In addition, when the stop switch 120 can be stopped, the player first stops any one of the stop switch 120a, the stop switch 120b, and the stop switch 120c, which is called a first stop. After that, stopping one of the two stop switches 120 that have not been stopped is called a second stop, and stopping the last remaining stop switch 120 after the second stop is called a third stop. . The effect switch 122 is composed of, for example, a press switch and a jog dial switch rotatably arranged around it, and detects a player's press operation or rotation operation.

A liquid crystal display section 124 for displaying various images associated with the performance is provided at approximately the center of the upper portion of the front upper door 104 . In addition, on the upper part and on the left and right of the front upper door 104, there are provided lamps 126 for effect, which are composed of, for example, high-intensity light-emitting diodes (LEDs). Speakers 128 are provided at the left and right positions of the liquid crystal display section 124 on the rear surface of the front upper door 104 and at the left and right positions on the rear surface of the front lower door 106 to produce auditory effects such as sound effects and musical tones.

A main credit display section 130 and a main payout display section 132 are provided on the operating section installation table 112 . A sub-credit display section 134 and a sub-payout display section 136 are provided between the symbol display window 108 and the operation section installation table 112 . The main credit display portion 130 and the sub-credit display portion 134 display the number of credited medals (the number of credits), and the main payout display portion 132 and the sub-payout display portion 136 display the number of payout medals. .

Below the reel 110 in the housing 102, a medal payout device (medal hopper) 142 for paying out medals from the medal outlet 140a is provided. In addition, a receiving tray portion 140 for storing medals dispensed from the medal discharge port 140a is provided at the lower front portion of the lower front door 106. As shown in FIG. A power switch 144 is also provided in the housing 102 . The power switch 144 is operated by an administrator who manages the slot machine 100, and is used to switch between two states, a power-off state and a power-on state.

In the housing 102, a main control board 200, which will be described later, is provided with setting keys and setting change switches (not shown) (collectively referred to as setting value setting means). In the slot machine 100, when a predetermined key (operation key) is inserted into the setting key and rotated from the OFF position to the ON position, the power is turned on through the power switch 144, and the setting change mode is entered. , the setting value can be changed (simply referred to as setting change). The set value indicates the degree of advantage of the player (machine ratio) in stages, and is represented, for example, in six stages from 1 to 6. In general, the higher the value of the set value, the more advantageous the game as a whole. It is set to be high (expected acquisition number is high). The set value is incremented by 1 each time the setting change switch is pressed in a state in which the setting can be changed. Then, the setting value is determined, and the setting change mode is terminated by returning the setting key to the original position (OFF position), and the game becomes possible. Note that setting changes are possible only for a certain period of time after the power switch 144 is operated and the power is turned on.

In the slot machine 100, when a game can be started and a specified number of medals are betted, the activated line is activated and the operation of the start switch 118 is activated. Here, bets are made by inserting credited medals through operation of the bet switch 116, inserting medals through the medal inserting unit 114, and displaying a replay combination, which will be described later in detail, on the activated line. Including any cases where medals are automatically inserted based on Also, the effective lines are lines for judging the winning of the winning combination, and there are two in this embodiment. As shown in FIG. 3(b), among nine symbols (three reels x three stages of upper, middle and lower) facing the symbol display window 108, the effective line A is the upper stage of the left reel 110a, the middle stage of the middle reel 110b, and the middle stage of the middle reel 110b. The line is set to connect the positions corresponding to the symbols stopped on the lower stage of the right reel 110c. The invalid line is used to determine the winning combination by displaying other symbol combinations that make it easier to grasp the winning combination when it is difficult to grasp the winning combination only from the combination of symbols displayed on the valid line A. In this embodiment, four invalid lines B1, B2, B3, C, D1 and D2 shown in FIG. 3B are assumed.

When the player operates the start switch 118, the game is started, the rotation of the left reel 110a, the middle reel 110b and the right reel 110c is controlled, and the winning type lottery and the like are executed. After that, according to the operation of the stop switches 120a, 120b and 120c, the corresponding left reel 110a, middle reel 110b and right reel 110c are stopped respectively. Then, when a winning combination that can receive medals wins according to the combination of the lottery results of the winning type lottery and the symbols displayed on the activated line A, the medals are paid out, and the winning type that can receive the medals is paid out. , or if the player wins but does not win, the left reel 110a, the middle reel 110b, and the right reel 110c are all stopped, and the game ends.

In the present embodiment, in the above-mentioned one game, a medal is inserted through the medal insertion section 114, a credited medal is inserted through operation of the bet switch 116, or a replay combination is displayed on the activated line A. After one of the medals is automatically inserted based on the above, the rotation of the left reel 110a, the middle reel 110b, and the right reel 110c is controlled according to the player's operation of the start switch 118, and the winning type lottery is executed. The left reel 110a, the middle reel 110b, and the right reel corresponding to the operated stop switches 120a, 120b, and 120c according to the lottery result of the lottery type lottery and the operation of the plurality of stop switches 120a, 120b, and 120c by the player. 110c are respectively controlled to be stopped, and when a winning combination capable of receiving medals is won, the game is played until the medals are paid out. In addition, when the winning type for which medals can be paid out is not won, or when the player wins but does not win, the left reel 110a, the middle reel 110b, and the right reel 110c all stop, and one game ends. However, the start of one game may be read as the operation of the start switch 118 by the player instead of the insertion of medals or the winning of a replay combination. Also, the number of times such one game is repeated is the number of games. In addition, in order to distinguish such a single game in which a winning type lottery is executed and one payout can be received from a pseudo-game (pseudo-game) to be described later, it may be referred to as a basic game. Here, even when the basic game is played alone or when the basic game is played in combination with a pseudo-game, completion of the basic game is regarded as completion of one game. Therefore, the completion of the pseudo-game does not affect the counting of the number of games in the slot machine 100. - 特許庁However, with respect to the number of games managed by a hall computer (not shown), the pseudo-game may be counted as the number of games, or may not be counted, depending on the specifications.

FIG. 4 is a block diagram showing a schematic electrical configuration of the slot machine 100. As shown in FIG. As shown in FIG. 4, the slot machine 100 includes a main control board 200 (main control section) that controls the progress of the game, and a sub-control board 202 (sub-control section) that controls the effects according to the progress of the game. A control board is provided that includes. In addition, electrical signal transmission between the main control board 200 and the sub control board 202 is limited to one direction only from the main control board 200 to the sub control board 202 from the viewpoint of fraud prevention.

(Main control board 200)
The main control board 200 has a semiconductor integrated circuit including a main CPU 200a that is a central processing unit, a main ROM 200b that stores programs and the like, a main RAM 200c that functions as a work area, and the like, and controls the entire slot machine 100. . The data in the main RAM 200c is retained without being erased, even when the power is turned off, unless the setting is changed and the RAM is cleared.

In addition, the main control board 200 functions by the main CPU 200a cooperating with the main RAM 200c based on the program stored in the main ROM 200b. 306, determination means 308, payout control means 310, game state control means 312, effect state control means 314, command transmission means 316 and other functional units.

The main control board 200 receives various detection signals from an inserted medal detector 414b that detects insertion of medals into the medal slot 114a, a bet switch 116, a start switch 118, and stop switches 120a, 120b, and 120c. Based on the received detection signal, the main CPU 200a executes various processes.

The initialization means 300 executes initialization processing in the main control board 200 . The betting means 302 bets medals to be used for games. Based on the operation of the start switch 118, the winning type lottery means 304 performs a winning type lottery for determining whether a winning combination is appropriate, more specifically, whether a winning combination includes a winning combination.

The reel control means 306 controls the rotation of the left reel 110a, the middle reel 110b and the right reel 110c according to the operation of the start switch 118, and corresponds to the rotating left reel 110a, the middle reel 110b and the right reel 110c. Depending on the operation of the stop switches 120a, 120b, 120c, the corresponding left reel 110a, middle reel 110b, and right reel 110c are controlled to stop. In addition, the reel control means 306 activates the operation of the stop switches 120a, 120b, and 120c in the previous game in response to the operation of the start switch 118, and then displays the lottery result of the winning type lottery. The time until the operation of the stop switches 120a, 120b, and 120c is validated (invalidated by the completion of the operation of the stop switches 120a, 120b, and 120c in the previous game) is extended beyond the specified time, and during that time, the reel 110a. , 110b, and 110c in a variety of manners to control the rotation of the reels (freeze effect). In the reel performance, an arbitrary switch that should be enabled is not enabled for a predetermined time, processing that should be executed is suspended for a predetermined time, or a signal of an arbitrary switch that should be transmitted and received is transmitted or received for a predetermined time. It can be realized by doing or not. Further, in this embodiment, as a reel performance, the basic game is interrupted in response to the operation of the start switch 118 in the basic game, the rotation of the reels 110a, 110b and 110c is controlled, and the stop switches 120a, 120b and 120c are operated. In some cases, a pseudo game similar to the basic game is performed by controlling the reels 110a, 110b, and 110c to stop (temporary stop control) according to the conditions. In addition, the pseudo game ends on condition that the start switch 118 is operated again or a predetermined time has passed since the temporary stop control, and the rotation control of the reels 110a, 110b, 110c in the basic game is resumed. In addition, as an example of a pseudo-game, in response to the operation of the stop switches 120a, 120b, 120c, predetermined symbols in each reel 110a, 110b, 110c (e.g., symbols constituting a bonus combination), automatic temporary stop control You can also In such a pseudo-game, the performance can be executed in a rotation control and stop mode similar to that of the basic game or in a different rotation control and stop mode, so that the interest in the game can be enhanced. Temporary stop means that the reels 110a, 110b, and 110c seem to be stopped at first glance, but by continuing to change the phase signals of the stepping motors 152 of the reels 110a, 110b, and 110c within 500 msec, a state in which they are not completely stopped is indicated. Control indicates control for temporarily stopping the reels 110a, 110b, and 110c. However, unless otherwise specified, both stop and temporary stop are simply treated as stop in the sense that the position is maintained without rotating in one direction. 110a, middle reel 110b, and right reel 110c are controlled to rotate, and according to the operation of stop switches 120a, 120b, and 120c corresponding to the rotating left reel 110a, middle reel 110b, and right reel 110c, the corresponding left reel is operated. Stop control and temporary stop control are simply treated as stop control in the sense of stopping 110a, middle reel 110b, and right reel 110c.

A reel drive control section 150 is also connected to the main control board 200 . The reel drive control unit 150 drives a stepping motor 152 based on a rotation start signal for the left reel 110a, the middle reel 110b, and the right reel 110c, which is transmitted from the reel control means 306 in response to the operation signal of the start switch 118. do. In addition, the reel drive control unit 150 detects the respective stop signals of the left reel 110a, the middle reel 110b, and the right reel 110c, which are transmitted from the reel control means 306, and the rotation position detection circuit 154 in response to the operation signal of the stop switch 120. Drive of the stepping motor 152 is stopped based on the signal.

The determining means 308 determines whether or not the symbol combination corresponding to the winning combination is displayed on the activated line A. Here, the fact that the symbol combination corresponding to the winning combination is displayed on the activated line A may simply be called winning. A payout control means 310 pays out medals in the number (amount of value) corresponding to the winning combination based on the symbol combination corresponding to the winning combination being displayed on the activated line A (winning). A medal payout device 142 is connected to the main control board 200, and the payout control means 310 discharges medals while counting the number of payout medals.

The game state control means 312 refers to the result of the winning type lottery and the determination result of the determination means 308, and shifts the game state to one of a plurality of types of game states. In addition, the effect state control means 314 refers to the result of the winning type lottery, the determination result of the determination means 308, and the transition information of the game state, and shifts the effect state to one of a plurality of types of effect states.

The command transmission means 316 is a game-related command associated with the operation of the betting means 302, the winning type lottery means 304, the reel control means 306, the determination means 308, the payout control means 310, the game state control means 312, the effect state control means 314, and the like. are sequentially determined, and the determined commands are sequentially transmitted to the sub control board 202 .

The main control board 200 is also provided with a random number generator (random number generating means) 200d. The random number generator 200d sequentially increments the count value, and resets the count value (determines the initial value by changing the numerical sequence) after a predetermined number of counts, thereby looping the count value within a predetermined numerical range. The main control board 200 obtains a random number by extracting a count value from the random number generator 200d at a predetermined time. The random number generated by the random number generator 200d of the main control board 200 (hereinafter referred to as the winning type lottery random number) is used to determine the game profit to be given to the player, for example, the winning type lottery means 304 to determine the winning type. be done.

(Sub control board 202)
The sub-control board 202, like the main control board 200, has various semiconductor integrated circuits including a sub-CPU 202a as a central processing unit, a sub-ROM 202b storing programs and the like, and a sub-RAM 202c functioning as a work area. , based on the command from the main control board 200, especially controls the performance. A backup power supply (not shown) is connected to the sub-RAM 202c as well as the main RAM 200c, so that data is retained without being erased even when the power is turned off. The sub control board 202 is also provided with a random number generator (random number generating means) 202d, similar to the main control board 200. Mainly used to determine the mode of production.

Also, in the sub-control board 202, the sub-CPU 202a functions by cooperating with the sub-RAM 202c based on the program stored in the sub-ROM 202b. It has a functional part.

The initialization determination means 330 executes initialization processing in the sub control board 202 . The command receiving means 332 receives commands from other control boards such as the main control board 200 and processes the commands. The effect control means 334 receives the detection signal from the effect switch 122, and determines the effect of the game performed by each device of the liquid crystal display unit 124, the speaker 128, and the effect lamp 126 based on the received command. Specifically, the effect control means 334 controls the image data displayed on the liquid crystal display unit 124, the effect lamp 126, the sub-credit display unit 134, the sub-payout display unit 136, and other illumination equipment for effects. Along with determining the decoration data, the audio data constituting the audio to be output from the speaker 128 is also determined. And the production|presentation control means 334 performs the production|presentation of the determined game. Note that the production includes an auxiliary production. In the winning type lottery, when a selected winning type in which a correct combination and an incorrect combination are duplicated is won, the auxiliary performance notifies the correct operation mode of the stop switches 120a, 120b, 120c which is a winning condition for the correct combination. It is a performance. With such an auxiliary effect, the player can easily display the symbol combination corresponding to the correct combination on the activated line A. The correct combination means a winning combination that is more advantageous than the incorrect combination, including not only the payout of medals due to the winning of the winning combination, but also all the game profits obtained by winning the winning combination. An effect state in which such an assist effect is executed is called an AT (assist time) effect state. Also, a so-called ART game state may be used in which an AT effect state and an RT (replay time) game state with a high probability of winning a replay combination progress in parallel.

In the following, information managed by a board other than the main control board 200, including the sub control board 202, such as the liquid crystal display section 124, the effect lamp 126, the speaker 128, the sub credit display section 134, and the sub payout display section 136 The means may be called other notification means. On the other hand, the notification means managed by the main control board 200, such as the main credit display section 130 and the main payout display section 132, may be called main notification means (instruction monitor). Also, the main notification means and other notification means capable of executing the auxiliary effect may be collectively referred to as the auxiliary effect execution means. The effect state control means 314 causes the auxiliary effect executing means to execute the auxiliary effect in the AT effect state. In particular, in this embodiment, as the main notification means (instruction monitor), the main payout display section 132 displays a numerical value (instruction number) that can specify the operation mode (hitting order), and as other notification means, the liquid crystal display section. 124, an effect lamp 126, and a speaker 128 notify the operation order.

(Table used in main control board 200)
FIG. 5 is an explanatory diagram for explaining winning combinations, and FIG. 6 is an explanatory diagram for explaining a winning type lottery table.

As will be described later in detail, the slot machine 100 is provided with a plurality of types of game states and effect states, and the game states and effect states are changed in accordance with the progress of the game. In the main control board 200, the main ROM 200b stores a plurality of winning type lottery tables corresponding to the game states managed and controlled by the game state control means 312. FIG. The winning type lottery means 304 stores the corresponding winning type lottery table in the main ROM 200b according to the current set value (indicating the easiness of obtaining a game profit in stages) stored in the main RAM 200c and the current gaming state. Based on the extracted winning type lottery table, it is determined which winning type in the winning type lottery table the winning type lottery random number acquired in response to the operation signal of the start switch 118 corresponds to.

Here, the winning combination constituting the winning type extracted from the winning type lottery table includes a replay combination, a minor combination, and a bonus combination. The replay combination is a combination in which, when the symbol combination corresponding to the replay combination is displayed on the activated line A, the game can be played again without the player betting new medals. A small combination is a combination in which a predetermined number of medals can be paid out according to the symbol combination by displaying a symbol combination corresponding to the minor combination on the activated line A. In addition, the bonus combination is changed to a bonus game state (a game state during RBB operation to be described later), which is managed by the game state control means 312, by displaying a symbol combination corresponding to the bonus combination on the activated line A. It is a role that can be transferred to

As for the winning combination in this embodiment, as shown in FIG. 5, a winning combination "RBB1" is provided as a bonus combination. Also, as the replay combination, winning combinations "Replay 1" to "Replay 14" are provided. In addition, as the small winning combination, winning combinations "small winning combination 1" to "small winning combination 37" are provided. In FIG. 5, the left reel 110a, the middle reel 110b, and the right reel 110c are associated with one or a plurality of symbols forming each winning combination. In the following, the winning role of "small role 1" to "small role 6" is the winning role of "7 cards", the winning role of "small role 7" is the winning role of "15 cards", and the winning role of "small role 8". is sometimes abbreviated as a winning combination "three-piece combination", and a winning combination "small combination 9" to "small combination 37" is sometimes abbreviated as a winning combination "one-piece combination".

Here, in the present embodiment, when the stop switch 120 is operated by the player, if the symbols forming the symbol combination corresponding to the possible winning combination are on the effective line A, the reel control means By 306, stop control is performed so that the symbol is stopped on the activated line A. Further, when the stop switch 120 is operated, there are 4 symbols in the direction opposite to the rotation direction of the reel 110, although the symbols constituting the symbol combination corresponding to the winning combination that can be won are not on the activated line A. If it exists within the range corresponding to the minute (pull-in range), the reel control means 306 controls the number of symbols away from each other to be the number of sliding symbols, and the symbols constituting the symbol combination corresponding to the winning combination are valid. Stop control is performed so as to stop after maintaining the rotation for the number of sliding frames so as to draw onto the line A. In addition, when there are a plurality of symbols corresponding to winning combinations that can be won on the reel 110, and all of them exist within the pull-in range of the reel 110, which symbol is placed on the effective line A according to a predetermined priority. It is determined whether to pull it upward, and stop control is performed so as to stop after maintaining the rotation for the number of sliding frames so as to pull the prioritized symbol onto the effective line A. - 特許庁Incidentally, when the stop switch 120 is pressed, if a symbol constituting a symbol combination corresponding to a winning combination other than a winable winning combination is on the effective line A, the reel control means 306 controls the symbol is not stopped on the effective line A, so-called kicking processing is also executed in parallel. In addition, as will be described later, when an operation mode (operation order or operation timing) is set as a winning condition for a winning combination included in the winning type, the reel control means 306 controls the winning combination according to the player's operation mode. The symbol combination corresponding to is controlled to be displayed on the activated line A.

And, for example, the winning roles "replay 1", "replay 2", "replay 7" to "replay 10", "replay 12" to "replay 14", winning roles "small role 1" to "small role 7", The symbols forming the symbol combinations corresponding to the "small winning combination 33" and "small winning combination 34" are arranged on each reel 110 so that they can always be displayed on the activated line A by the stop control described above. Such a winning combination may be expressed as PB=1. On the other hand, for example, the winning hand "RBB1", the winning hands "Replay 3" to "Replay 6", "Replay 11", the winning hands "Small hand 8" to "Small hand 32", "Small hand 35" to "Small hand The symbols forming the symbol combination corresponding to "37" are not necessarily arranged so as to be displayable on the effective line A due to the above-described stop control on each reel 110, so that a so-called omission may occur. Such a winning combination may be expressed as PB≠1.

As shown in FIG. 6, a plurality of winning areas are defined in the winning type lottery table, and the winning type to be the lottery target differs depending on each game state, and the presence or absence of non-winning (losing) differs depending on the game state. In FIG. 6, a winning area (winning type) allocated for each game state (non-internal game state (non-internal), RBB internal game state (RBB internal), RBB active game state (RBB active)) is indicated by "⊚" or "○", but in reality, the main ROM 200b stores a winning type lottery table corresponding to each of a plurality of game states. In addition, "◎" indicates that it is possible to draw a lottery to move to an advantageous section, and "○" indicates that it is impossible to draw a lottery to move to an advantageous section. It shows that it is a winning type.

In the winning type lottery table, each partitioned winning area is associated with a predetermined number (winning range value), which is a numerical value indicating a winning range, and a winning type. The total number of winning type lottery random numbers (65536) is obtained by summing up the numbers set in the winning areas. Therefore, the probability that each winning type is determined is a value obtained by dividing the number associated with the winning area by the total number of winning type lottery random numbers. A winning-type lottery means 304 sequentially obtains set numbers from a plurality of winning areas in the winning-type lottery table in descending order of numbers based on the game state at that time, and converts the set numbers to winning-type lottery random numbers. When the value after subtraction becomes less than 0, the winning type associated with the winning area at that time is taken as the lottery result of the winning type lottery. Also, the set numbers of all the winning areas of 1 or more winning areas are subtracted from the winning type lottery random number, and if the value after subtraction is 0 or more, the winning type "losing" of the winning area 0 is the winning type lottery. lottery result.

Here, the winning combination “RBB1” will be supplemented. Predetermined Type 1 Special Accessory (RB) is an accessory that increases the number of combinations of symbols related to winning for each prescribed number, or increases the probability of operating the conditional device related to winning for each prescribed number, It is activated at a predetermined time and can be continued until the result of the number of games not exceeding 12 is obtained. Here, the conditional device is a device whose operation is a necessary condition for displaying a combination of symbols related to winning, replay, the operation of the accessory or the operation of the accessory continuous operation device, and the winning type lottery ( It means a winning flag that operates when winning a lottery by an electronic computer performed in a game machine.

According to the winning type lottery table of FIG. 6, for example, the winning area 0 is associated with the winning type "lost". No combination is displayed on the activated line A, and medals are not paid out.

The winning area 1 is associated with the winning type "small winning combination ALL" in which the winning combinations "small winning combination 1" to "small winning combination 37" are overlapped. 1” to “small win 6” and “small win 37” are duplicated and included in the winning type “Bell ALL”. A win type "one card ALL" in which "small winning combination 35" to "small winning combination 37" are duplicated is associated.

In addition, in the winning areas 4 to 15, there are either a correct combination (winning combination "small combination 1" to "small combination 6") in which the number of payouts is 7, and an incorrect combination (winning combination) in which the number of payouts is 1. Selected winning types (winning types "Bell A1" to "Bell A6", winning types "Bell B1" to "Bell B6") that overlap with any of "Small win 9" to "Small win 32") are associated with each other. In the following description, the 12 winning types in the winning areas 4 to 15 may be abbreviated simply as the winning type "batting order bell".

In addition, in the winning areas 16 to 18, there are either a correct combination (winning combination "small combination 33" to "small combination 36") in which the number of payouts is 1, and an incorrect combination (winning combination) in which the number of payouts is 15. "Minor win 7") and any of the selected winning types (winning types "batting order chance 1" to "batting order chance 3" are associated with each other. In the following, the winning areas 16 to 18 The three winning types are sometimes abbreviated as winning types "batting order chance".

The winning area 19 is associated with the winning type "common bell" in which the winning combinations "small combination 1" to "small combination 6" are overlapped, and the winning area 20 is associated with the winning combination "small combination 4". is associated with the winning type "strong bell 1" including The winning type "chance eye" including the winning combination "small winning combination 8" is associated.

In addition, the winning area 23 is associated with the winning type "weak champ" in which the winning hands "replay 1" and "replay 13" are overlapped. The winning type "upper stage watermelon" in which "replay 7" is duplicated is associated, and the winning area 25 is associated with the winning type "middle stage watermelon" in which the winning combination "replay 1" and "replay 8" are duplicated. The winning area 26 is associated with the winning type "upper row watermelon champ" in which the winning combination "replay 1" and "replay 9" are duplicated, and the winning area 27 is associated with the winning combination "replay 1". ", and "Replay 10" are associated with the winning type "Middle Watermelon Chan Lip", and the winning area 28 is associated with the winning combination "Replay 1", "Replay 10" to "Replay 12", and "Replay 14". , and the winning area 29 includes the winning types ``Replay 1'', ``Replay 10'' to ``Replay 14''. "Heart fanning Chanlip 2" is associated. Incidentally, hereinafter, the ten winning types in the winning areas 20 to 29 may be simply referred to as the winning type "rare combination".

In addition, the winning area 30 is associated with the winning type ``heart fanning lip 1'' including the winning combinations ``replay 1'' to ``replay 12'' and ``replay 14''. The winning type ``Heart fanning Rip 2'' in which the roles ``Replay 1'' to ``Replay 14'' are overlapped is associated, and the winning role ``Replay 1'' and ``Replay 14'' overlap in the winning area 32. The winning type "Replay 1" is associated with the winning type "Replay 1", and the winning combination "Replay 1", "Replay 7", "Replay 13", and "Replay 14" are redundantly included in the winning area 33. 2”, and the winning area 34 is associated with the winning type “replay 3”, which includes overlapping winning combinations “replay 1”, “replay 8”, “replay 13”, and “replay 14”. ing. Incidentally, hereinafter, the five winning types of the winning areas 30 to 34 may be simply abbreviated as the winning type "replay".

In addition, in the winning area 35, a winning combination "RBB1" and winning combinations with a payout number of 1 (winning combinations "small combination 9" to "small combination 12", "small combination 17" to "small combination 24", "Small win 37") is associated with the winning type "RBB single win", and the winning area 36 is associated with the winning type "RBB" including the winning combination "RBB1". .

Then, when a winning type in which a plurality of winning hands are overlapped is won, a winning condition, such as stop The order in which the switches 120a, 120b and 120c are operated, and the operation timings of the stop switches 120a, 120b and 120c (operating positions of the reel 110) are set.

In the following description, the operations of the stop switches 120a, 120b, and 120c that stop the reels in the order of the left reel 110a, the middle reel 110b, and the right reel 110c are referred to as "batting order 1," and the left reel 110a, the right reel 110c, and the middle reel 110b are operated. The operations of the stop switches 120a, 120b, and 120c that sequentially stop the reels are referred to as "batting order 2", and the operations of the stop switches 120a, 120b, and 120c that stop the reels in the order of the middle reel 110b, the left reel 110a, and the right reel 110c are referred to as the "batting order." 3", and the operation of the stop switches 120a, 120b, 120c for stopping the reels in the order of the middle reel 110b, the right reel 110c, and the left reel 110a is set to "hitting order 4", and the right reel 110c, the left reel 110a, and the middle reel 110b are operated in this order. The operation of the stop switches 120a, 120b, and 120c for stopping the reels is defined as "hitting order 5", and the operation of the stop switches 120a, 120b, and 120c for stopping the reels in the order of the right reel 110c, middle reel 110b, and left reel 110a is defined as "hitting order 6". ”.

For example, if the winning type "batting order bell A1" in the winning area 4 is won and an operation is performed in the correct operation mode (batting order 1), the winning combination "small win 1", which is the correct combination with the number of payouts of 7, is performed. Stop control is performed so that the symbol combination corresponding to is preferentially displayed on the activated line A. Further, when the operation is performed in the batting order 2 to 6, the symbol combination corresponding to the winning combination "1-card combination", which is an incorrect combination of paying out 1 card, is 1/2 or 1/4 on the activated line A. Stop control is performed so that it is displayed with a probability of

It should be noted that the winning probability (set number) of each winning type in the winning areas 4 to 15 is set to be equal. Since the player usually cannot know which type of winning has been won, by providing the above-described winning areas 4 to 15, it is made difficult for the correct combination to win. Further, as described above, even if the stop switches 120a, 120b, and 120c are operated in an operation mode in which the incorrect combination is preferentially displayed, the symbol combination corresponding to the incorrect combination is necessarily displayed on the activated line A. Therefore, depending on the operation mode, there is a possibility that a missing item may occur (PB≠1).

In addition, if the winning type "batting order chance 1" in the winning area 16 is won and the operation is performed in the correct operation mode (batting order 1, 2), it corresponds to the winning combination "small winning combination 33" in which the number of payouts is 1. The stop control is performed so that the symbol combination corresponding to the winning combination "small combination 34" and the symbol combination corresponding to the winning combination "small combination 34" are simultaneously displayed on the active line A preferentially. Further, when the operation is performed in the batting order 3 to 6, stop control is performed so that the symbol combination corresponding to the winning combination "small combination 7" with the number of payouts of 15 is preferentially displayed on the activated line A. done.

It should be noted that the winning probability (set number) of each winning type of the winning areas 16 to 18 is set to be equal. Since the player usually cannot know which type of winning has been won, by providing the above-described winning areas 16 to 18, although no loss occurs (PB=1), the player can , it is not possible to know in advance whether the two winning combinations "1-card combination" will be won at the same time or the winning combination "15-card combination" will be won.

When one of the winning types described above is won, an internal winning flag corresponding to each winning type is established (ON), and each reel 110 is controlled to stop according to the state of establishment of this internal winning flag. The Rukoto. At this time, if a winning type including a small winning combination is won, but the combination of symbols corresponding to these winning combinations cannot be displayed on the activated line A in the game, after the end of the game. The internal winning flag is turned off. In other words, the right to win a minor winning combination is limited only within the game in which the winning type including the minor winning combination has been won, and the right cannot be carried over to the next game. On the other hand, if the winning type including the winning combination "RBB1" is won, the RBB internal winning flag is established (ON) and the symbol combination corresponding to the winning combination "RBB1" is displayed on the activated line A. The RBB internal winning flag is carried over across games until it is displayed. In addition, when the internal winning flag corresponding to the winning type including the replay combination is established, the symbol combination corresponding to any of the replay combinations included in the winning type is always on the activated line A. The internal win flag is turned off after the display is performed and the processing required to play the next game without medals is performed.

(Transition of game state)
Here, the game state transition will be described with reference to FIG. Here, a plurality of game states such as a non-internal game state, an RBB internal game state, and an RBB active game state are prepared. Each game state is changed according to winning of a bonus combination, winning (activation), and termination, as described later. Winning types that can be won in each game state are represented by "⊚" and "◯" in FIG.

The non-internal game state is a game state corresponding to an initial state in a plurality of game states. In such a non-internal game state, the winning probability of the replay combination is set to approximately 1/7.3. In addition, in the non-internal game state, the winning combination "RBB1" is determined with a predetermined probability (for example, approximately 1/30). The game state control means 312 changes the game state according to winning of the winning combination “RBB1”. For example, in a game in which the winning combination "RBB1" is won, when the symbol combination corresponding to the winning combination "RBB1" is displayed on the activated line A, the game state control means 312 changes the game state to the RBB active game state. Migrate (1).

In the RBB active gaming state, the probability of winning the replay combination is set to zero. In this RBB active gaming state, the winning types that can be won are the winning type "small win ALL" in the winning area 1, the winning type "Bell ALL" in the winning area 2, and the winning type "Bell ALL" in the winning area 3. ” is set. When the winning type "small hand ALL" is won, the symbol combination corresponding to any one of the winning hand "small hand 1" to "small hand 37" is displayed on the activated line A, and when the winning type "Bell ALL" is won. , a symbol combination corresponding to one of the winning hands ``small hand 1'' to ``small hand 6'' and ``small hand 37'' is displayed on the active line A, and when the winning type ``1 card ALL'' is won, the winning hand Stop control is performed so that symbol combinations corresponding to any one of “small win 9” to “small win 32” and “small win 35” to “small win 37” are displayed on the activated line A. Here, the expected winning number per unit game in the RBB-activated game state is lowered by such a configuration of the small combination.

When the conditions for ending the RBB-activated game state are established, that is, when the number of winning coins exceeds a predetermined number (for example, 22), the game state control means 312 shifts the game state to the non-internal game state (2).

On the other hand, in the game in which the winning combination "RBB1" is won, if the symbol combination corresponding to the winning combination "RBB1" cannot be displayed on the activated line A, the game state control means 312 changes the game state to the inside of the RBB. Transition to the middle game state (3).

In the RBB internal gaming state, the winning probability of the replay combination is set to approximately 1/7.3. In addition, in the RBB internal gaming state, the winning type "loss" is not won. In other words, when the symbol combination corresponding to the winning combination 'RBB1' cannot be displayed on the activated line A in the winning game of the winning combination 'RBB1', after that, a smaller combination or a smaller combination than the winning combination 'RBB1' can be displayed. Since the replay combination is preferentially stopped on the activated line A, the symbol combination corresponding to the winning combination "RBB1" cannot be displayed on the activated line A. - 特許庁Therefore, once the gaming state shifts to the RBB inside gaming state, the RBB inside gaming state is maintained without transition of the gaming state thereafter. Here, while maintaining the RBB inside game state, the AT effect state is realized in the RBB inside game state.

Here, in the RBB internal middle game state, since a plurality of types of correct hands are won without overlapping each other, the chances of winning the correct hands can be increased. By performing the auxiliary performance in the AT performance state in the state, it is possible to easily obtain medals. On the other hand, in the game state during RBB operation, since a plurality of types of correct hands are won in duplicate, there are few opportunities for winning the correct hands, so the correct hands are awarded more than in the AT presentation state in other game states. This reduces the number of chances that a player can play, which makes it difficult for a player to increase the number of medals he or she owns. Therefore, while providing the function of the RBB operating game state that the probability of winning a winning combination is higher than that of the RBB inside game state, the RBB operating game state is equivalent to the RBB inside game state in terms of medal acquisition performance. A specification (acceleration RBB) of being inferior can be realized.

(Transition of production state)
FIG. 8 is an explanatory diagram for explaining the transition of the effect state. Below, the effect states transitioned by the effect state control means 314 in the main control board 200 will be described in detail.

Here, in order to comprehensively and uniformly determine whether or not the game state with high medal acquisition performance is biased, the game section having the performance related to the instruction function, that is, the auxiliary performance (instruction function) is executed. A game section that is advantageous to a player, including a game section, is defined as an advantageous section. In the advantageous section, as a result of performing a lottery related to the operation of the auxiliary effect on the main control board 200, when the auxiliary effect is activated, the main control board 200 can identify the content of the instruction, for example, the main notification This is a game section in which information indicating the contents of instructions may be transmitted to peripheral boards such as the sub-control board 202 only when it is displayed on the means. Also, unlike the advantageous section, the game section in which the auxiliary effect (instruction function) cannot be executed is defined as the non-advantageous section. Therefore, the plurality of effect states belong to either the advantageous section or the non-advantageous section, which are game sections. In this embodiment, almost all the production states belong to the advantageous section, and some production states (here, several games from the start of the normal production state shifted from the pullback production state) realize the non-advantageous section.

In the advantageous section, among the winning modes in which the correct role is lost if there is no assistance effect, in the selection winning type in which the correct answer role has the maximum payout (here, 7), an assistance that assists the correct answer role to win a prize When an effect (auxiliary effect for obtaining the maximum number of coins to be paid out) is performed, for example, the effect must be notified by lighting the section indicator 160 .

In addition, in the non-advantageous section, it is possible to change the winning probability of the winning type for each set value, but the probability of determining the transition to the effect state (AT effect state) accompanied by the auxiliary effect in the same winning type must not be different for each set value. On the other hand, in the advantageous section, the winning probability of the winning type and the probability of determining the transition (or addition) to the production state (AT production state) with the auxiliary production in the same winning type are different for each set value. It is possible to

Therefore, the production state control means 314 manages the transition between the non-advantageous section and the advantageous section in addition to managing the transition of the production state. Also, regardless of such management, the advantageous section is forcibly terminated when the following termination conditions are satisfied. For example, when the value counted in the advantageous section reaches a predetermined value (for example, the number of staying games reaches 1500 games, or the net increase number exceeds 2400), the game is forcibly terminated. In either case, the effect state control means 314 resets all the information updated in the advantageous section (all variables affecting the performance related to the instruction function) by shifting from the advantageous section to the non-advantageous section. .

(Non-AT production state, AT production state)
In the non-AT production state, the execution frequency of the auxiliary production is much lower than in the AT production state, and the auxiliary production is almost not performed, so the number of medals that can be obtained is limited. Here, as the non-AT effect state, four effect states such as a normal effect state, a CZ effect state (chance zone effect state), a reel effect state, and a pullback effect state are provided.

In the AT performance state, it is possible to obtain a large number of medals while suppressing the consumption of medals by causing the assistance performance executing means to execute the assistance performance when the selected winning type is won. Therefore, by shifting to the AT effect state, the player can progress the game more advantageously than in the non-AT effect state. Here, as the AT effect state, four effect states such as a specialized AT effect state, a normal AT effect state, a chance AT effect state, and a battle AT effect state are provided. Each effect state will be individually described below.

(Each production state)
The normal rendering state is a rendering state corresponding to the initial state among a plurality of rendering states. A performance state control means 314 performs a CZ lottery at the start of the normal performance state. The CZ lottery is a lottery for determining transition to the CZ effect state. In this embodiment, the effect state control means 314 determines the number of transition games (for example, 600) to shift to the CZ effect state by lottery as a CZ lottery, and the number of games staying in the normal effect state is the number of transition games. , the presentation state is shifted to the CZ presentation state (1).

In the CZ production state, the production state control means 314 performs AT lottery. The AT lottery is a lottery for determining transition to an AT performance state (normal AT performance state), and a performance state control means 314 performs the AT lottery with different probabilities for each winning type determined by the winning type lottery. Then, when the AT lottery is won in the CZ effect state, the effect state control means 314 shifts the effect state to the specialized AT effect state which is the AT effect state (2). It should be noted that the CZ effect state can be said to be a more advantageous effect state than the normal effect state, since it may be decided to shift to the AT effect state in which the auxiliary effect is executed.

On the other hand, the effect state control means 314 shifts the effect state to the normal effect state when a predetermined end condition (for example, passing a predetermined number of games without winning the AT lottery) is established in the CZ effect state ( 3).

Further, when a predetermined condition is satisfied in the normal effect state (when the number of lighting of the rare combination counter, which will be described later, becomes 4), the effect state control means 314 shifts the effect state to the reel effect state (4). In the reel performance state, the performance state control means 314 performs AT lottery while at least deciding to shift to the CZ performance state, and notifies the result of the lottery through reel performance in which rotation and stop are repeated one or more times. For example, the effect state control means 314, transition to the CZ effect state, transition winning to the specialized AT effect state, winning transition to the specialized AT effect state + predetermined game profit, etc., depending on the result of the AT lottery, game The higher the profit is, the more the number of repetitions of rotation and stop is executed.

Then, when the AT lottery is won in the reel effect state, the effect state control means 314 shifts the effect state to the special AT effect state which is the AT effect state (5). Further, when the shift to the AT effect state is not determined in the reel effect state, the effect state control means 314 shifts the effect state to the CZ effect state (6). In this way, once the game is shifted to the reel effect state, the effect state control means 314 shifts the effect state to either the specialized AT effect state or the CZ effect state. It should be noted that the reel effect state can be said to be an effect state that is more advantageous than the normal effect state because the shift to either the AT effect state or the CZ effect state is determined.

Also, if a predetermined ceiling condition is met without transitioning to the specialized AT effect state (AT effect state), for example, any effect of the normal effect state, the CZ effect state, the reel effect state, and the pullback effect state. When the state (non-AT production state) is continuously stayed and the ceiling game number (for example, 1500) is consumed (so-called ceiling reaching), the production state control means 314 shifts the production state to the specialized AT production state. (7).

In the specialized AT effect state, until a predetermined end condition (for example, 4 games are completed) is satisfied, a predetermined difference number that can be acquired in the normal AT effect state to be shifted later is determined by lottery. When a predetermined end condition is satisfied in the specialized AT effect state, the effect state control means 314 shifts the effect state to the normal AT effect state (8).

In the normal AT effect state, the auxiliary effect is executed until a predetermined termination condition (for example, the difference number reaches a predetermined difference number determined in the specialized AT effect state) is satisfied. Then, in the normal AT effect state, if a predetermined transition condition to the chance AT effect state is met (for example, if a lottery is won according to the winning type), the effect state control means 314 changes the effect state to the chance AT effect state. (9).

In the chance AT effect state, the effect state control means 314 determines by lottery whether or not to stepwise increase the continuation rate of continuing the normal AT effect state (resulting in an increase in the expected number of winning coins). When it is determined to increase the continuation rate in the chance AT effect state, the effect state control means 314 shifts the effect state to the specialized AT effect state (10). Further, when it is not decided to increase the continuation rate in the chance AT effect state, the effect state control means 314 returns the effect state to the normal AT effect state (11).

Further, in the normal AT effect state, if a predetermined transition condition to the battle AT effect state is met (for example, if a lottery is won according to the winning type), the effect state control means 314 changes the effect state to the battle AT effect state. (12).

In the battle AT effect state, the effect state control means 314 executes the effect simulating the battle, and determines the outcome by lottery. When the battle is won in the battle AT effect state (if the shift to the chance AT effect state is determined), the effect state control means 314 shifts the effect state to the chance AT effect state (13). Further, when the battle is defeated in the battle AT effect state, the effect state control means 314 returns the effect state to the normal AT effect state (14).

When a predetermined end condition is satisfied in the normal AT effect state, the effect state control means 314 shifts the effect state to the pullback effect state (15).

In the pull-back effect state, the effect state control means 314 determines whether or not to shift again to the AT effect state (specialized AT effect state) based on the continuation rate determined in the chance AT effect state or the like (whether to continue). We perform continuation lottery of this. Then, when the continuation lottery is won, the effect state control means 314 continues the advantageous section and returns the effect state to the specialized AT effect state (16). On the other hand, when the continuation lottery is not won, the effect state control means 314 shifts the effect state to the normal effect state (17). In this case, the effect state control means 314 temporarily shifts the advantageous section to the non-advantageous section, and performs the advantageous section transition lottery with a high probability until the transition to the advantageous section. Therefore, the advantageous section transition lottery of the present embodiment is designed to always transition to the advantageous section.

Specific processing in the main control board 200 and the sub-control board 202 will be described below with reference to flowcharts.

(CPU initialization processing of main control board 200)
FIG. 9 is a flowchart for explaining CPU initialization processing in the main control board 200. FIG. When power is supplied from the power board, a system reset occurs in the main CPU 200a, and the main CPU 200a performs the following CPU initialization processing (S100).

(Step S100-1)
When the power is turned on, the main CPU 200a reads a startup program from the main ROM 200b as an initial setting process, and performs setting processes necessary for executing various processes.

(Step S100-3)
The main CPU 200a sets the wait processing time in the timer counter.

(Step S100-5)
The main CPU 200a determines whether a power-off warning signal is detected. A power interruption detection circuit is provided in the main control board 200, and a power interruption warning signal is output from the power interruption detection circuit when the power supply voltage drops below a predetermined value. If the power-off notice signal is detected, the process proceeds to step S100-3, and if the power-off notice signal is not detected, the process proceeds to step S100-7.

(Step S100-7)
The main CPU 200a determines whether or not the wait processing time set in step S100-3 has elapsed. As a result, when it is determined that the wait processing time has elapsed, the process proceeds to step S100-9, and when it is determined that the wait time has not elapsed, the process proceeds to step S100-5.

(Step S100-9)
The main CPU 200a executes necessary processing to permit access to the main RAM 200c.

(Step S100-11)
The main CPU 200a executes checksum confirmation processing. Here, the main CPU 200a calculates the checksum and determines whether the calculated checksum does not match the checksum saved at the time of power failure (abnormality) and whether the backup is abnormal. The main CPU 200a turns on the backup abnormality flag when determining that one or both of the backup and the checksum are abnormal, and turns on the backup abnormality flag when determining that both the backup and the checksum are not abnormal. Turn off.

(Step S100-13)
The main CPU 200a determines whether the backup abnormality flag is on. As a result, when it is determined that the backup abnormality flag is on, the process proceeds to step S110, and when it is determined that the backup abnormality flag is not on, the process proceeds to step S120.

(Step S110)
The main CPU 200a executes cold start processing. This cold start processing will be described later.

(Step S120)
The main CPU 200a executes setting value switching processing for switching setting values. This set value switching process will be described later.

(Step S130)
The main CPU 200a executes a state recovery process for returning to the state immediately before the power was turned off. This state return processing will be described later.

FIG. 10 is a flow chart explaining the cold start process (S110) in the main control board 200. As shown in FIG.

(Step S110-1)
The main CPU 200a clears the used area in the main RAM 200c and executes a used area RAM check process for detecting an abnormality in the used area.

(Step S110-3)
The main CPU 200a clears another area (unused area) in the main RAM 200c, and executes another area RAM check process for detecting an abnormality in the other area. If an abnormality is detected in another area in the separate area RAM check process, the main CPU 200a turns on the RAM read/write error flag.

(Step S110-5)
The main CPU 200a sets an error code "EA" indicating an abnormality in the main RAM 200c.

(Step S110-7)
The main CPU 200a determines whether an abnormality is detected in step S110-1. As a result, if it is determined that an abnormality has been detected in step S110-1, the process proceeds to step S112, and if it is determined that an abnormality has not been detected in step S110-1, the process proceeds to step S110-9. transfer processing.

(Step S110-9)
The main CPU 200a acquires a RAM read/write error flag that is turned on when an abnormality is detected in step S110-3.

(Step S110-11)
The main CPU 200a determines whether the RAM read/write error flag is on. As a result, when it is determined that the RAM read/write error flag is on, the process proceeds to step S112, and when it is determined that the RAM read/write error flag is not on, the process proceeds to step S120.

(Step S120)
The main CPU 200a executes setting value switching processing for switching setting values. This set value switching process will be described later.

(Step S110-13)
The main CPU 200a sets an error code "E7" indicating a backup error.

(Step S112)
The main CPU 200a executes error stop processing for stopping the progress of the game due to an error. This error stop processing will be described later.

FIG. 11 is a flowchart for explaining the error stop processing (S112) in the main control board 200. FIG.

(Step S112-1)
The main CPU 200a sets the initial stack pointer value as the address of the stack pointer.

(Step S112-3)
The main CPU 200a executes error setting processing for setting error display and warning sound.

(Step S112-5)
The main CPU 200a sets the external signal 1-3 output bit off to turn off the output image of the bit corresponding to the external signal 1-3.

(Step S112-7)
The main CPU 200a executes output port image setting processing for updating the output image for the bit set in step S112-5.

(Step S112-9)
The main CPU 200a shifts to an endless loop. As a result, the progress of the game is stopped.

FIG. 12 is a flow chart for explaining the setting value switching process (S120) in the main control board 200. As shown in FIG.

(Step S120-1)
The main CPU 200a acquires the signal of the input port 1, and determines whether or not the set value switching condition is satisfied based on the acquired signal of the input port 1. FIG. As a result, if it is determined that the set value switching condition is not satisfied, the set value switching process is terminated, and if it is determined that the set value switching condition is satisfied, the process proceeds to step S120-3. . Here, the signal of the input port 1 includes a signal indicating whether or not the front upper door 104 and the front lower door 106 are open, and a signal indicating whether or not the setting key is turned on. Here, when a signal indicating that the front upper door 104 and the front lower door 106 are open and a signal indicating that the setting key is turned on are obtained, the setting value switching condition is satisfied. It is determined that

(Step S120-3)
The main CPU 200a executes a RAM clearing process for clearing a used area to be cleared when changing settings in the main RAM 200c.

(Step S120-5)
The main CPU 200a executes a table content setting process for transferring the table data of the setting value switching time data table to the main RAM 200c.

(Step S120-7)
The main CPU 200a sets, in the transmission buffer, a setting change start command indicating to start changing setting values.

(Step S120-9)
The main CPU 200a executes edge check processing to detect the falling edge (on-edge) of the signal of the input port.

(Step S120-11)
The main CPU 200a acquires setting value data indicating the current setting value.

(Step S120-13)
The main CPU 200a determines whether or not the ON edge of the setting change switch is detected in step S120-9. As a result, if it is determined that the ON edge of the setting change switch has not been detected, the process proceeds to step S120-17, and if it is determined that the ON edge of the setting change switch has been detected, the process proceeds to step S120-15. .

(Step S120-15)
The main CPU 200a increments the set value data by one.

(Step S120-17)
The main CPU 200a determines whether the set value data is within the range (1 to 6) that can be set as the set value. As a result, if it is determined that the set value data is within the range, the process moves to step S120-21, and if it is determined that the set value data is not within the range, the process moves to step S120-19.

(Step S120-19)
The main CPU 200a sets the set value data to zero.

(Step S120-21)
The main CPU 200a updates the set value data to the value incremented or set in step S120-15 or step S120-19.

(Step S120-23)
The main CPU 200 a executes a display data conversion process for displaying the set value on the main credit display section 130 .

(Step S120-25)
The main CPU 200a determines whether or not the ON edge of the setting change switch is detected. As a result, if it is determined that the ON edge of the setting change switch has not been detected, the process proceeds to step S120-31, and if it is determined that the ON edge of the setting change switch has been detected, the process proceeds to step S120-27. to move.

(Step S120-27)
The main CPU 200a determines whether the setting change switch is on. As a result, when it is determined that the setting change switch is on, the process proceeds to step S120-27, and when it is determined that the setting change switch is not on, the process proceeds to step S120-29.

(Step S120-29)
The main CPU 200a sets a setting change switch interval timer.

(Step S120-31)
The main CPU 200a executes timer wait processing to wait until the setting change switch interval timer reaches zero.

(Step S120-33)
The main CPU 200a determines whether the ON edge of the start switch 118 is detected. As a result, if it is determined that the ON edge of the start switch 118 has not been detected, the process proceeds to step S120-9, and if it is determined that the ON edge of the start switch 118 has been detected, the process proceeds to step S120-35. to move.

(Step S120-35)
The main CPU 200a determines whether the setting key is off. As a result, when it is determined that the setting key is off, the process proceeds to step S120-35, and when it is determined that the setting key is not off, the process proceeds to step S120-37.

(Step S120-37)
The main CPU 200a determines whether the setting key is on. As a result, when it is determined that the setting key is on, the process proceeds to step S120-37, and when it is determined that the setting key is not on, the process proceeds to step S122.

(Step S122)
The main CPU 200a executes initialization start processing for starting initialization. This initialization start process will be described later.

FIG. 13 is a flow chart for explaining the initialization start process (S122) in the main control board 200. FIG.

(Step S122-1)
The main CPU 200a sets, in the transmission buffer, a setting change end command indicating that the change of the setting value has ended.

(Step S122-3)
The main CPU 200a sets, in the transmission buffer, a setting change state command indicating the state when the change of the setting value is completed.

(Step S122-5)
The main CPU 200a sets a wait timer at the start of initialization.

(Step S122-7)
The main CPU 200a executes a timer wait process of waiting until the wait timer reaches 0 at the start of initialization.

(Step S122-9)
The main CPU 200a executes RAM clear processing at the time of setting change to clear another area of the main RAM 200c.

(Step S122-11)
The main CPU 200a executes a RAM clearing process for clearing a used area to be cleared when changing settings in the main RAM 200c.

(Step S122-13)
The main CPU 200a sets a game state command indicating the current game state in the transmission buffer.

(Step S200)
The main CPU 200a executes a game start process for starting a game. Note that this game start processing will be described later.

FIG. 14 is a flow chart for explaining the state return processing (S130) in the main control board 200. As shown in FIG.

(Step S130-1)
The main CPU 200a restores the stack pointer.

(Step S130-3)
The main CPU 200a executes unused area clearing processing for clearing unused areas in the main RAM 200c.

(Step S130-5)
The main CPU 200a clears the stack pointer save buffer.

(Step S130-7)
The main CPU 200a sets (turns on) a flag after recovery from power failure.

(Step S130-9)
The main CPU 200a executes port input processing for updating the image of the input port.

(Step S130-11)
The main CPU 200a executes operation target bit extraction processing for extracting information on the operation target bit based on the image of the input port updated in step S130-9.

(Step S130-13)
The main CPU 200a sets the operation target bit extracted in step S130-11 as the operation target bit of the previous state.

(Step S130-15)
The main CPU 200a acquires the motor phases of the reels 110a, 110b, and 110c. Here, motor phases are set as the states of the reels 110a, 110b, and 110c. The motor phase indicates the operating state of the reels 110a, 110b, 110c, that is, during acceleration, during steady rotation, during stop, and during standby. Specifically, the 1-byte (storage unit) variable assigned to the motor phase is accelerated = 3, steady rotation = 2, stopped = 1, and waiting = It changes to a value such as 0.

(Step S130-17)
The main CPU 200a determines whether or not any of the reels 110a, 110b, and 110c is rotating steadily and accelerating based on the motor phase acquired in step S130-15. As a result, if it is determined that none of the reels 110a, 110b, and 110c are in steady rotation or acceleration, the process proceeds to step S130-21, and any one of the reels 110a, 110b, and 110c is in steady rotation or acceleration. If it is determined to be in the middle, the process moves to step S130-19.

(Step S130-19)
The main CPU 200a executes rotation error processing for setting when an error is detected for the reels 110a, 110b, and 110c.

(Step S130-21)
The main CPU 200a restores the saved register group.

(Step S130-23)
The main CPU 200a permits the interrupt and terminates the state return processing. As a result, the main CPU 200a returns to the state immediately before the power was turned off.

FIG. 15 is a flow chart for explaining the game start process (S200) in the main control board 200. As shown in FIG.

(Step S200-1)
The main CPU 200a executes a replay state identification signal output setting process for outputting a replay state identification signal indicating whether or not it is a replay.

(Step S200-3)
The main CPU 200a sets an input number display output bit OFF for turning off (turning off) the bit corresponding to the input number display indicating the number of inserted medals (number of bets).

(Step S200-5)
The main CPU 200a executes output port image setting processing for updating the output image for the bit set in step S200-3.

(Step S200-7)
The main CPU 200a sets a game start wait timer.

(Step S200-9)
The main CPU 200a executes timer wait processing for waiting until the game start wait timer reaches zero.

(Step S200-11)
The main CPU 200a executes a 1-game RAM clearing process for clearing an area to be cleared for each game out of the used area in the main RAM 200c.

(Step S200-13)
The main CPU 200a executes bonus signal setting processing for setting a bonus signal.

(Step S200-15)
The main CPU 200a executes edge clear processing for clearing the edge information of the input port image.

(Step S210)
The main CPU 200a executes game medal insertion processing for receiving insertion of medals. This game medal insertion process will be described later.

FIG. 16 is a flow chart for explaining the game medal insertion process (S210) in the main control board 200. As shown in FIG.

(Step S210-1)
The main CPU 200a executes error confirmation processing for confirming detection results of various errors.

(Step S210-3)
The main CPU 200a executes edge check processing to detect the falling edge (on-edge) of the signal of the input port.

(Step S210-5)
The main CPU 200a acquires a door open error detection flag that is set to 1 when the front upper door 104 or the front lower door 106 is open.

(Step S210-7)
The main CPU 200a determines whether the front upper door 104 and the front lower door 106 are closed based on the door open error detection flag acquired in step S210-5. As a result, when it is determined that the front upper door 104 and the front lower door 106 are closed, the process is shifted to step S210-17, and at least one of the front upper door 104 or the front lower door 106 is not closed. If so, the process moves to step S210-9.

(Step S210-9)
The main CPU 200a sets an error code "E8" indicating that at least one of the front upper door 104 and the front lower door 106 is open.

(Step S210-11)
The main CPU 200a performs error display, request for warning sound, and error wait processing for waiting for error recovery.

(Step S210-13)
The main CPU 200a executes setting value confirmation processing for confirming the setting values.

(Step S210-15)
The main CPU 200a executes edge clear processing for clearing the edge information of the input port image.

(Step S210-17)
The main CPU 200a executes credit button check processing for withdrawing accumulated medals when a credit switch (not shown) for withdrawing accumulated (credited) medals is pressed.

(Step S210-19)
The main CPU 200a executes game medal insertion button related processing for betting medals. Here, when the bet switch 116 is pressed, a prescribed number of accumulated (credited) medals is betted, and the number of accumulated medals is subtracted by the number of bets. Also, when medals are inserted through the medal slot 114a, medals are bet up to a specified number, and if more medals than the specified number are inserted, that amount is added to the number of stored medals.

(Step S210-21)
The main CPU 200a executes game medal acquisition processing for confirming whether the number of inserted coins is a specified number.

(Step S210-23)
The main CPU 200a determines whether or not the number of inserted coins is the specified number based on the confirmation result of step S210-21. As a result, if it is determined that the number of inserted coins is not the specified number, the process proceeds to step S210-1, and if it is determined that the number of inserted coins is the specified number, the process proceeds to step S210-25.

(Step S210-25)
The main CPU 200a sets a start indicator output bit for turning on (illuminates) a start indicator (not shown) that indicates whether the operation of the start switch 118 is effective.

(Step S210-27)
The main CPU 200a determines whether the falling edge (depression) of the start switch 118 has been detected. As a result, when it is determined that the falling edge of the start switch 118 has not been detected, the process proceeds to step S210-1, and when it is determined that the falling edge of the start switch 118 has been detected, step S210. -29 is processed.

(Step S210-29)
The main CPU 200a clears the main payout display portion buffer in order to clear the display of the main payout display portion 132. FIG.

(Step S210-31)
The main CPU 200a executes re-gaming state identification signal clear processing for clearing the re-gaming state identification signal.

(Step S210-33)
The main CPU 200a executes blocker blocking preprocessing for turning off (extinguishing) the start indicator.

(Step S210-35)
The main CPU 200a sets a lever depression command indicating that the start switch 118 has been depressed in the transmission buffer.

(Step S220)
The main CPU 200a executes an internal lottery process for performing a winning type lottery. This internal lottery process will be described later.

FIG. 17 is a flowchart for explaining the internal lottery process (S220) in the main control board 200. FIG.

(Step S220-1)
The main CPU 200a acquires set value data.

(Step S220-3)
The main CPU 200a sets an error code "EC" indicating a setting value abnormality error.

(Step S220-5)
The main CPU 200a determines whether the set value data obtained in step S220-1 is abnormal. As a result, when it is determined that the set value data is abnormal, the process proceeds to step S112, and when it is determined that the set value data is not abnormal, the process proceeds to step S220-7.

(Step S220-7)
The main CPU 200a acquires the winning type lottery random number updated by the random number generator 200d.

(Step S220-9)
The main CPU 200a executes a state offset acquisition process for acquiring an offset value related to the game state.

(Step S220-11)
The main CPU 200a sets the address of the internal lottery area definition table (winning type lottery table).

(Step S220-13)
The main CPU 200a sets, as the initial value of the winning area, the value indicated by the address obtained by adding the offset value obtained in step S220-9 to the address set in step S220-11. Here, the first winning area in the winning type lottery table in the current gaming state is set as the initial value.

(Step S220-15)
The main CPU 200a acquires lottery data, which is a numerical value indicating the winning range of the winning area, and executes a lottery data acquisition process for shifting the winning area by one.

(Step S220-17)
The main CPU 200a determines whether or not the winning type lottery is performed. As a result, when it is determined that the winning type lottery will not be performed, the process moves to step S220-21, and when it is determined to perform the winning type lottery, the process moves to step S220-19.

(Step S220-19)
The main CPU 200a subtracts the lottery data from the random number value.

(Step S220-21)
The main CPU 200a determines whether the result of the subtraction in step S220-19 is negative, that is, whether the winning region has been won by the winning type lottery. As a result, when it is determined that the winning type lottery has been won, the process moves to step S230, and when it is determined that the winning type lottery has not been won, the process moves to step S220-23.

(Step S220-23)
The main CPU 200a determines whether or not the winning type lottery has ended. As a result, when it is determined that the winning type lottery has not ended, the process moves to step S220-15, and when it is determined that the winning type lottery has ended, the process moves to step S220-25.

(Step S220-25)
The main CPU 200a clears the trigger role type.

(Step S230)
The main CPU 200a executes a symbol code setting process for setting a symbol code based on the winning area and the game state. This symbol code setting process will be described later.

FIG. 18 is a flow chart for explaining the symbol code setting process (S230) in the main control board 200. FIG.

(Step S230-1)
The main CPU 200a acquires the winning area that was won in step S220, and executes a game state setting process of setting the game state to the internal middle game state when the acquired winning area includes a bonus combination.

(Step S230-3)
The main CPU 200a sets the winning area obtained in step S230-1 as a stop control number.

(Step S230-5)
The main CPU 200a determines (sets) a winning combination group based on the winning area acquired in step S230-1. The main CPU 200a may turn on the pseudo-game execution flag depending on the determined winning combination group. In addition, the pseudo-game execution flag indicates that the pseudo-game is executed when it is on, and indicates that the pseudo-game is not executed when it is off.

(Step S230-7)
The main CPU 200a executes a symbol code initial setting process for setting a symbol code indicating a symbol that can be displayed and a symbol to be drawn based on the stop control number set in step S230-3.

(Step S230-9)
The main CPU 200a executes display symbol bit initial value setting processing for setting display symbol bits.

(Step S231)
The main CPU 200a executes an execution flag setting process for setting an execution flag, various processes related to the effect state, processing related to the auxiliary effect, and the like. This execution flag setting process will be described later.

(Step S230-13)
The main CPU 200a sets an effect command, which is a command relating to the advantageous section, in the transmission buffer.

(Step S230-15)
The main CPU 200a sets a winning information command indicating the winning type in the transmission buffer.

(Step S230-17)
The main CPU 200a checks the one-game timer.

(Step S230-19)
The main CPU 200a sets a reel before rotation command indicating that the reels 110a, 110b and 110c are before rotation in the transmission buffer.

(Step S230-21)
The main CPU 200a executes an excitation release waiting process for waiting for the excitation release of the stepping motor 152. FIG.

(Step S236)
The main CPU 200a executes a reel effect process for executing a pseudo game. Specifically, according to the operation of the stop switches 120a, 120b, 120c, predetermined symbols (for example, symbols constituting a bonus combination) on the respective reels 110a, 110b, 110c are automatically controlled to temporarily stop, and all When the reels 110a, 110b, 110c temporarily stop, or when they start rotating through random delay processing after the temporary stop, the pseudo-game execution flag is turned off.

(Step S230-23)
The main CPU 200a determines whether the one-game timer is not zero. As a result, when it is determined that the one-game timer is not 0, the process moves to step S230-23, and when it is determined that the one-game timer is 0, the process moves to step S230-25.

(Step S230-25)
The main CPU 200a executes reel start processing for starting rotation of the reels 110a, 110b, and 110c. Here, the motor phases of the reels 110a, 110b, and 110c are set during acceleration to start the rotation of each reel, and the one-game timer is set to a value corresponding to 4.1 seconds.

(Step S230-27)
The main CPU 200a sets a reel start command indicating that the reels 110a, 110b, and 110c have started rotating in the transmission buffer.

(Step S240)
The main CPU 200a executes processing during reel rotation, which is processing during rotation of the reels 110a, 110b, and 110c. Note that this process during rotation of the drum will be described later.

FIG. 19 is a flowchart for explaining the execution flag setting process (S231) in the main control board 200. FIG.

(Step S231-1)
The main CPU 200a executes AT state update processing for updating (transitioning) the effect state based on the next AT flag. It should be noted that the next AT flag indicates the effect state to be set in the next game, and is set by the following processing.

(Steps S232 to S236)
The main CPU 200a executes state-specific module execution processing for executing a module for each effect state and game section, and ends the execution flag setting processing. In addition, in the state-specific module execution process, a module (process) corresponding to the transferred effect state and game section is read from the main ROM 200b and executed. In the following, modules related to features of this embodiment will be described in detail, and descriptions of modules unrelated to features of this embodiment will be omitted.

FIG. 20 is a flowchart for explaining the non-advantageous section process (S232) executed in the state-specific module execution process. The non-advantageous section process is executed when the game section is a non-advantageous section.

(Step S232-1)
The main CPU 200a conducts an advantageous section lottery.

(Step S232-3)
The main CPU 200a determines whether or not the advantageous section lottery is won in step S232-1. As a result, when it is determined that the advantageous section lottery has been won, the process proceeds to step S232-5, and when it is determined that the advantageous section lottery has not been won, the non-advantageous section process is terminated.

(Step S232-5)
The main CPU 200a turns on an advantageous section flag indicating an advantageous section, and ends the non-advantageous section processing. As a result, in the advantageous interval update process of step S280-7, which will be described later, the transition to the advantageous interval is made.

FIG. 21 is a flowchart for explaining the normal effect state processing (S233) executed in the state-specific module execution processing. The normal effect state processing is executed when the effect state is the normal effect state.

(Step S233-1)
The main CPU 200a increments a continuous game number counter for counting the number of continuous games by one. Incidentally, the continuous game number counter is incremented by 1 for each game even in the following CZ effect state processing and the pull-back effect state processing (not shown) executed in the pull-back effect state. Further, the continuous game number counter is reset when shifting to the specialized AT effect state.

(Step S233-3)
The main CPU 200a determines whether the value of the continuous game number counter is equal to or greater than the ceiling game number. As a result, when it is determined that the value of the continuous game number counter is equal to or higher than the ceiling game number, the process is shifted to step S233-5, and when it is determined that the value of the continuous game number counter is not equal to or higher than the ceiling game number, step The process moves to S233-7.

(Step S233-5)
The main CPU 200a sets the next AT flag to a value corresponding to the specialized AT effect state, and terminates the normal effect state processing.

(Step S233-7)
The main CPU 200a determines whether or not the current game is the start timing of the normal effect state. As a result, when it is determined that it is time to start the normal effect state, the process moves to step S233-9, and when it is determined that it is not time to start the normal effect state, the process moves to step S233-11.

(Step S233-9)
The main CPU 200a performs a CZ lottery for determining the number of games to be shifted to the CZ effect state by lottery.

(Step S233-11)
The main CPU 200a determines whether or not the number of games staying in the normal effect state has reached the number of transition games. As a result, when it is determined that the transition game number has been reached, the process is shifted to step S233-13, and when it is determined that the transition game number has not been reached, the process is shifted to step S233-15.

(Step S233-13)
The main CPU 200a sets the next AT flag to a value corresponding to the CZ effect state.

(Step S233-15)
The main CPU 200a determines whether or not conditions for shifting to the reel effect state are satisfied. As a result, when it is determined that the transition condition is satisfied, the process proceeds to step S233-17, and when it is determined that the transition condition is not satisfied, the normal effect state processing is terminated.

(Step S233-17)
The main CPU 200a sets the next AT flag to a value corresponding to the reel effect state, and terminates the normal effect state processing.

FIG. 22 is a flowchart for explaining the CZ effect state processing (S234) executed in the state-specific module execution processing. The CZ effect state processing is executed when the effect state is the CZ effect state. Among the processes in the CZ effect state process, the same processes as in the normal effect state process are given the same reference numerals, and the description thereof is omitted.

(Step S234-1)
The main CPU 200a conducts an AT lottery based on the winning type determined by the winning type lottery.

(Step S234-3)
The main CPU 200a determines whether or not the AT lottery is won in step S234-1. As a result, when it is determined that the AT lottery has been won, the process moves to step S234-5, and when it is determined that the AT lottery has not been won, the process moves to step S234-7.

(Step S234-5)
The main CPU 200a sets the next AT flag to a value corresponding to the specialized AT effect state, and terminates the CZ effect state processing.

(Step S234-7)
The main CPU 200a determines whether it is the final game in the CZ effect state. As a result, when it is determined that it is the final game in the CZ effect state, the processing is shifted to step S234-9, and when it is determined that it is not the final game in the CZ effect state, the CZ effect state processing is terminated.

(Step S234-9)
The main CPU 200a sets the next AT flag to a value corresponding to the normal effect state.

FIG. 23 is a flowchart for explaining the reel effect state processing (S235) executed in the state-specific module execution processing. The reel effect state processing is executed when the effect state is the reel effect state. Among the processes in the reel effect state process, the same processes as in the normal effect state process are given the same reference numerals, and the description thereof will be omitted.

(Step S235-1)
The main CPU 200a conducts an AT lottery based on the winning type determined by the winning type lottery.

(Step S235-3)
The main CPU 200a determines whether or not the AT lottery is won in step S235-1. As a result, when it is determined that the AT lottery has been won, the process moves to step S235-5, and when it is determined that the AT lottery has not been won, the process moves to step S235-7.

(Step S235-5)
The main CPU 200a sets the next AT flag to a value corresponding to the specialized AT effect state, and terminates the reel effect state processing.

(Step S235-7)
The main CPU 200a determines whether it is the final game in the reel effect state. As a result, when it is determined that it is the final game in the reel effect state, the processing is shifted to step S235-9, and when it is determined that it is not the final game in the reel effect state, the reel effect state processing is terminated.

(Step S235-9)
The main CPU 200a sets the next AT flag to a value corresponding to the CZ effect state.

FIG. 24 is a flowchart for explaining the withdrawal effect state process (S236) executed in the state-specific module execution process. The pullback effect state processing is executed when the effect state is the pullback effect state.

(Step S236-1)
The main CPU 200a performs a continuation lottery as to whether or not to re-shift to the AT effect state (continue) based on the winning type determined by the winning type lottery.

(Step S236-3)
The main CPU 200a determines whether or not the continuation lottery is won in step S236-1. As a result, when it is determined that the continuation lottery has been won, the process proceeds to step S236-5, and when it is determined that the continuation lottery has not been won, the process proceeds to step S236-7.

(Step S236-5)
The main CPU 200a sets the next AT flag to a value corresponding to the specialized AT effect state, and ends the pullback effect state process.

(Step S236-7)
The main CPU 200a determines whether it is the final game in the pullback effect state. As a result, when it is determined that it is the final game in the pullback performance state, the processing is shifted to step S236-9, and when it is determined that it is not the final game in the pullback performance state, the pullback performance state processing is terminated. .

(Step S236-9)
The main CPU 200a sets the next AT flag to a value corresponding to the normal effect state, and turns off the advantageous section flag.

FIG. 25 is a flowchart for explaining the process during drum rotation (S240) in the main control board 200. As shown in FIG.

(Step S240-1)
The main CPU 200a sets the stop indicator output bit off (output image) to turn off (light off) the bit corresponding to the indicator (not shown) of the stop switches 120a, 120b, 120c. Here, the stop indicator output bit is composed of a 3-bit bit string, and each bit is associated with the emission color of the three stop switches 120a, 120b, and 120c, and is represented by blue=1 and red=0. be done.

(Step S240-3)
The main CPU 200a executes output port image setting processing for updating the output image for the bit set in step S240-1.

(Step S240-5)
The main CPU 200a executes error confirmation processing for confirming detection results of various errors.

(Step S240-7)
The main CPU 200a refers to the index flags and obtains the indices of the spinning reels 110a, 110b, and 110c. Note that the index flag is set only after the reels 110a, 110b, and 110c have reached the steady rotation speed. It will also show that it has been reached.

(Step S240-9)
The main CPU 200a determines whether the index flags of all the reels 110a, 110b, and 110c have been detected. As a result, if it is determined that all index flags have not been detected, the process proceeds to step S240-1, and if it is determined that all index flags have been detected, the process proceeds to step S240-11.

(Step S240-11)
The main CPU 200a acquires a stop spinning reel bit indicating the reels 110a, 110b, and 110c that are stopping or starting to stop. Here, the stop spinning reel bit is composed of a 3-bit bit string, and each bit is associated with one of the three reels 110a, 110b, and 110c. Stopped state=0.

(Step S240-13)
The main CPU 200a saves the stop reel bit obtained in step S240-11 as a reel rotating flag.

(Step S240-15)
The main CPU 200a sets the stop indicator output bit ON (output image) to turn on (light off) the bit corresponding to the indicator (not shown) of the stop switches 120a, 120b, 120c.

(Step S240-17)
The main CPU 200a acquires an image of the input port 0 and executes an operation target bit extraction process for extracting an operation target bit from the acquired image. Here, the operation target bit is composed of a 3-bit bit string, and each bit is associated with one of the three stop switches 120a, 120b, and 120c. =0.

(Step S240-19)
The main CPU 200a performs a logical product operation between the spinning drum flag acquired in step S240-13 and the operation target bit extracted in step S240-17. Here, if the reel 110 is rotating and the stop switch 120 corresponding to the reel is operated, that is, if the operated stop switch 120 corresponds to the effectively rotating reel 110 , the logical AND is 1.

(Step S240-21)
The main CPU 200a determines whether the logical product calculated in step S240-19 is 0, that is, whether the stop switch 120 corresponding to the spinning reel 110 has been operated. As a result, when it is determined that the stop switch 120 corresponding to the rotating reel 110 has not been operated, the process is shifted to step S240-3, and the stop switch 120 corresponding to the rotating reel 110 is operated. If it is determined that there is, the process moves to step S240-23.

(Step S240-23)
The main CPU 200a acquires the output image including the stop indicator output bit, and computes the logical product of the acquired output image and the logical product computed in step S240-19. Here, the logical product bit is 0 when the operated stop switch 120 is lit in red, and the logical product bit is 1 when it is lit in blue.

(Step S240-25)
The main CPU 200a determines whether the logical product calculated in step S240-23 is 0, that is, whether the operated stop switch 120 is lit in red. As a result, if it is determined that the operated stop switch 120 is lit in red, the process proceeds to step S240-1, and if it is determined that the operated stop switch 120 is not lit in red, step S240- 27 is processed.

(Step S240-27)
The main CPU 200a determines whether the operated stop switch 120 is valid. As a result, if it is determined that the operated stop switch 120 is not valid, the process proceeds to step S240-1, and if it is determined that the operated stop switch 120 is valid, the process proceeds to step S240-29. Transfer. Here, it is determined whether or not the number of stop switches 120 that have been operated is one. If it is determined that one stop switch 120 has been operated, the process proceeds to step S240-29, and if it is determined that there are two or more stop switches 120 operated to step S240-1.

(Step S240-29)
The main CPU 200a executes stop control reel setting processing for acquiring various parameters for stopping the reel 110 corresponding to the operated stop switch 120. FIG.

(Step S240-31)
The main CPU 200a prohibits interrupts.

(Step S240-33)
The main CPU 200a executes a depression reference position acquisition process for deriving the symbol number of the symbol positioned on the activated line A as the depression reference position.

(Step S240-35)
The main CPU 200 a executes a sliding frame number acquisition process for determining the number of sliding frames of the reel 110 .

(Step S250)
The main CPU 200a executes reel stop processing for stopping the reel 110 corresponding to the stop switch 120 that has been operated. Note that this spinning drum stop processing will be described later.

FIG. 26 is a flow chart for explaining the spinning drum stopping process (S250) in the main control board 200. As shown in FIG.

(Step S250-1)
The main CPU 200a acquires the depression reference position derived in step S240-35.

(Step S250-3)
The main CPU 200a calculates the stop request number by correcting the number of sliding frames determined in step S240-37 with respect to the depression reference position obtained in step S250-1.

(Step S250-5)
The main CPU 200a sets (sets to 1) a stop request flag. The stop request flag is a flag for requesting the stop processing of the target reel 110 to the programs that operate in parallel. By setting the stop request flag to 1, the symbol corresponding to the stop request number is enabled. It becomes possible to stop on line A. The stop request flag and the stop request number are read out by a program running in parallel, and the reel 110 is stopped. When the stop processing is completed, the program resets the stop request flag to 0 (OFF).

(Step S250-7)
The main CPU 200a permits interrupts.

(Step S250-9)
The main CPU 200a sets a stop information command indicating the stop order of the reels 110 in the transmission buffer.

(Step S250-11)
The main CPU 200a sets the stop indicator output bit off (output image) to turn off (light off) the bit corresponding to the indicator (not shown) of the stop switch 120. FIG.

(Step S250-13)
The main CPU 200a executes output port image setting processing for updating the output image for the bit set in step S250-11.

(Step S250-15)
The main CPU 200a executes display symbol bit setting processing for setting display symbol bits.

(Step S250-17)
The main CPU 200a executes the next cylinder setting preprocessing for stopping the next reel 110. FIG.

(Step S250-19)
The main CPU 200a determines whether the stop processing of all the reels 110 has been completed. As a result, if it is determined that the stop processing for all the reels 110 has not been completed, the process proceeds to step S240, and if it is determined that the stop processing for all the reels 110 has been completed, the process proceeds to step S250-21. transfer processing.

(Step S250-21)
The main CPU 200a determines whether the stop request flag is ON for any reel 110, that is, whether all the reels 110 have stopped. As a result, if it is determined that all the reels 110 have not stopped, the process moves to step S250-21, and if it is determined that all the reels 110 have stopped, the process moves to step S250-23.

(Step S250-23)
The main CPU 200a executes error confirmation processing for confirming detection results of various errors.

(Step S250-25)
The main CPU 200a executes an operation target bit extraction process for extracting information on the operation target bit.

(Step S250-27)
The main CPU 200a determines whether the stop switch 120 is pressed based on the operation target bit obtained in step S250-25. As a result, when it is determined that the stop switch 120 has been pressed, the process proceeds to step S250-23, and when it is determined that the stop switch 120 has not been pressed, the process proceeds to step S260.

(Step S260)
The main CPU 200a executes a display determination process for determining a winning winning combination. Note that this display determination processing will be described later.

FIG. 27 is a flow chart for explaining the display determination process (S260) in the main control board 200. FIG.

(Step S260-1)
The main CPU 200 a clears the buffer of the main payout display section 132 .

(Step S260-3)
The main CPU 200a determines whether or not a display determination abnormality has occurred, depending on whether or not the symbol combination displayed on the activated line A matches the symbol combination permitted to be displayed on the activated line A. Execute the detection process.

(Step S260-5)
The main CPU 200a sets an error code "EE" indicating display determination abnormality (error).

(Step S260-7)
The main CPU 200a determines whether display determination is abnormal based on the determination result of step S260-3. As a result, when it is determined that the display determination is abnormal, the process proceeds to step S112, and when it is determined that the display determination is not abnormal, the process proceeds to step S260-9.

(Step S260-9)
The main CPU 200a executes display symbol identification and generation processing for determining a winning combination based on the symbol combination stopped (displayed) on the activated line A. FIG.

(Step S260-11)
The main CPU 200a sets 0 as the initial value of the payout number.

(Step S260-13)
The main CPU 200a determines whether or not a minor winning combination has been won. As a result, when it is determined that a minor winning combination has been won, the process proceeds to step S260-15, and when it is determined that a minor winning combination has not been won, the process proceeds to step S260-35.

(Step S260-15)
The main CPU 200a turns on a winning flag indicating that a minor winning combination has been won.

(Step S260-17)
The main CPU 200a executes payout number setting processing for setting the number of payouts according to the winning minor combination.

(Step S260-19)
The main CPU 200a determines whether it is an advantageous section. As a result, if it is determined that the section is not the advantageous section, the process proceeds to step S270, and if it is determined that the section is the advantageous section, the process proceeds to step S260-21.

(Step S260-21)
The main CPU 200a acquires the value of the advantageous section MY counter that counts the net increase in the number of coins during the advantageous section.

(Step S260-23)
The main CPU 200a adds the payout number to the value of the advantageous section MY counter acquired in step S260-23.

(Step S260-25)
The main CPU 200a acquires the inserted number of the game.

(Step S260-27)
The main CPU 200a subtracts the inserted number from the value added in step S260-23.

(Step S260-29)
The main CPU 200a determines whether the subtraction result in step S260-27 is negative. As a result, if it is determined that the subtraction result is not negative, the process moves to step S260-33, and if it is determined that the subtraction result is negative, the process moves to step S260-31.

(Step S260-31)
The main CPU 200a clears (sets to 0) the value of the advantageous section MY counter.

(Step S260-33)
The main CPU 200a updates the value of the advantageous section MY counter to the value subtracted in step S260-27 or the value cleared in step S260-31.

(Step S260-35)
The main CPU 200a determines whether or not the replay combination has won. As a result, if it is determined that the replay combination has not won, the process proceeds to step S270, and if it is determined that the replay combination has won, the process proceeds to step S260-37.

(Step S260-37)
The main CPU 200a sets the inserted number as the payout number.

(Step S260-39)
The main CPU 200a turns on the replay flag.

(Step S260-41)
The main CPU 200a sets the number of sheets automatically inserted.

(Step S270)
The main CPU 200a executes payout processing for paying out medals. This payout process will be described later.

FIG. 28 is a flow chart for explaining the payout process (S270) in the main control board 200. As shown in FIG.

(Step S270-1)
The main CPU 200a acquires the replaying flag.

(Step S270-3)
The main CPU 200a sets a payout start command indicating that the payout of medals has started in the transmission buffer.

(Step S270-5)
The main CPU 200a determines whether or not the replay combination has been won, based on the replay operation flag acquired in step S270-1. As a result, when it is determined that the replay combination has won, the process moves to step S270-41, and when it is determined that the replay combination has not won, the process moves to step S270-7.

(Step S270-7)
The main CPU 200 a executes a main indicator display process for displaying 0 on the main payout display section 132 .

(Step S270-9)
The main CPU 200a determines that there is no payout (the number of payouts is 0). As a result, when it is determined that there is no payout, the process proceeds to step S270-35, and when it is determined that there is payout, the process proceeds to step S270-11.

(Step S270-11)
The main CPU 200a determines whether the number of stored coins is 50 or more. As a result, if it is determined that the stored number of sheets is 50 or more, the process moves to step S270-13, and if it is determined that the stored number is not 50 or more, the process moves to step S270-15.

(Step S270-13)
The main CPU 200a executes medal payout device control processing to pay out one medal from the medal payout device 142, and shifts the processing to step S270-23.

(Step S270-15)
The main CPU 200a sets a payout start interval timer.

(Step S270-17)
The main CPU 200a determines whether the payout start timer is not 0, that is, whether it is the first payout. As a result, when it is determined that it is the time of the first payout, the process moves to step S270-21, and when it is determined that it is not the time of the first payout, the process moves to step S270-19.

(Step S270-19)
The main CPU 200a executes timer wait processing for waiting until the payout start interval timer reaches zero.

(Step S270-21)
The main CPU 200a increments the stored number by one.

(Step S270-23)
The main CPU 200a sets a payout execution command indicating that one medal has been paid out in the transmission buffer.

(Step S270-25)
The main CPU 200a executes main display pre-display processing for displaying the number of payouts that have already been paid out on the main payout display section 132. FIG.

(Step S270-27)
The main CPU 200a determines whether it is in the bonus game state. As a result, when it is determined that the game is not in the bonus game state, the process proceeds to step S270-31, and when it is determined that the bonus game state is in effect, the process proceeds to step S270-29.

(Step S270-29)
The main CPU 200a increments, by one, the number of medals paid out during bonus operation, which is the number of medals paid out in the bonus game state.

(Step S270-31)
The main CPU 200a determines whether or not the payout of the payout number of medals has been completed. As a result, when it is determined that the payout has not been completed, the process proceeds to step S270-11, and when it is determined that the payout has been completed, the process proceeds to step S270-33.

(Step S270-33)
The main CPU 200a executes payout end processing for ending the payout of medals.

(Step S270-35)
The main CPU 200a determines whether an over error has been detected. As a result, if it is determined that no over error has been detected, the process proceeds to step S270-41, and if it is determined that an over error has been detected, the process proceeds to step S270-37.

(Step S270-37)
The main CPU 200a sets an error code "E5" indicating an over error.

(Step S270-39)
The main CPU 200a performs error display, request for warning sound, and error wait processing for waiting for error recovery.

(Step S270-41)
The main CPU 200a sets a payout end command indicating that the payout of medals has ended in the transmission buffer.

(Step S280)
The main CPU 200a executes a game transition process for transitioning a game state, managing an advantageous interval, and the like. This game transition processing will be described later.

FIG. 29 is a flow chart for explaining game transition processing (S280) in the main control board 200. As shown in FIG.

(Step S280-1)
The main CPU 200a acquires a replay flag and turns on or off a bit corresponding to a replay indicator (not shown) indicating that the next game is a replay based on the acquired replay flag. For this purpose, the stop indicator output bit off (output image) is set, and replay indicator control processing is executed to update the output bit of the set output image.

(Step S280-3)
When a bonus combination is won, the main CPU 200a executes a role product actuation symbol display process for setting various parameters for controlling the bonus game state.

(Step S281)
The main CPU 200a executes state-specific module execution processing for executing modules for each effect state and section state. In addition, in the state-specific module execution process, the module (process) corresponding to the transferred effect state is read from the main ROM 200b and executed.

(Step S280-5)
The main CPU 200a executes a bonus operation end process for shifting the game state to a non-internal game state when the number of coins acquired during bonus operation reaches a predetermined number in the bonus game state.

(Step S280-7)
The main CPU 200a executes advantageous section update processing for managing advantageous sections.

(Step S280-9)
The main CPU 200a determines whether or not the next game is in the AT effect state. As a result, when it is determined that the next game is not in the AT effect state, the process is shifted to step S280-15, and when it is determined that the next game is in the AT effect state, the process is shifted to step S280-11.

(Step S280-11)
The main CPU 200a determines whether it is in the bonus game state. As a result, when it is determined that the game is not in the bonus game state, the process proceeds to step S280-15, and when it is determined that the bonus game state is in effect, the process proceeds to step S280-13.

(Step S280-13)
The main CPU 200a sets on an advantageous lamp flag for lighting the section indicator 160. FIG.

(Step S280-15)
The main CPU 200a executes an effect command setting process for setting an effect command, which is a command relating to the advantageous section, in the transmission buffer.

(Step S280-17)
The main CPU 200a sets a game end command indicating that one game has ended in the transmission buffer.

(Step S280-19)
The main CPU 200a executes terminal board signal output processing for outputting an external signal.

(Step S280-21)
The main CPU 200a determines whether or not the effect wait timer set when ending the advantageous section in step S280-7 is zero. As a result, when it is determined that the effect wait timer is not 0, the processing is shifted to step S280-21, and when it is determined that the effect wait timer is 0, the processing is shifted to step S280-23.

(Step S280-23)
The main CPU 200a sets a game state command indicating the game state in the transmission buffer.

(Step S280-25)
The main CPU 200a sets a game start command indicating the start of the next game in the transmission buffer, and shifts the process to step S200.

One game is executed through a series of processes from step S200 to step S280. Thereafter, steps S200 to S280 are repeated.

Next, save processing and timer interrupt processing in the main control board 200 will be described.

(Evacuation processing when main control board 200 is powered off)
FIG. 30 is a flow chart for explaining the power-off saving process in the main control board 200 . The main CPU 200a monitors the power-off detection circuit, and when the power supply voltage drops below a predetermined value, it interrupts and executes the saving process at power-off.

(Step S300-1)
When the power-off warning signal is input, the main CPU 200a saves the register.

(Step S300-3)
The main CPU 200a checks for a power-off warning signal.

(Step S300-5)
The main CPU 200a determines whether a power-off warning signal is detected. As a result, when it is determined that the power cut warning signal is detected, the process is moved to step S300-11, and when it is determined that the power cut warning signal is not detected, the process is moved to step S300-7. .

(Step S300-7)
The main CPU 200a restores the register.

(Step S300-9)
The main CPU 200a performs processing for permitting an interrupt, and terminates the power-off save processing.

(Step S300-11)
The main CPU 200a executes output port clear processing to stop the output of the output port.

(Step S300-13)
The main CPU 200a executes save processing for the separate area when the power is turned off.

(Step S300-15)
The main CPU 200a executes RAM protection setting processing necessary to prohibit access to the main RAM 200c.

(Step S300-17)
The main CPU 200a sets the counter value of the loop counter to the predetermined number of power failure detection signal detections in order to set the power failure occurrence monitoring time.

(Step S300-19)
The main CPU 200a subtracts 1 from the value of the loop counter set in step S300-17.

(Step S300-21)
The main CPU 200a determines whether or not the counter value of the loop counter is zero. As a result, if it is determined that the counter value is not 0, the process proceeds to step S300-19, and if it is determined that the counter value is 0, the above-described CPU initialization process (step S1000) is performed.

It should be noted that if the power is actually turned off, the operation of the slot machine 100 is stopped during the loop of steps S300-19 to S300-21.

(Timer interrupt processing of main control board 200)
FIG. 31 is a flowchart for explaining timer interrupt processing in the main control board 200. As shown in FIG. The main control board 200 is provided with a reset clock pulse generation circuit that generates a clock pulse at a predetermined cycle (1.49 milliseconds in the simultaneous rotation reference example, hereinafter referred to as "1.49 ms"). Then, when a clock pulse is generated by the reset clock pulse generation circuit, it interrupts and the following timer interrupt processing is executed.

(Step S400-1)
The main CPU 200a saves the register.

(Step S400-3)
The main CPU 200a clears the interrupt flag.

(Step S400-5)
The main CPU 200a reads various input port images and executes port input processing for accurately acquiring the latest switch status.

(Step S400-7)
The main CPU 200a outputs the set output image to the output port, the main credit display section 130, the main payout display section 132, the input number display, the start display, the display of the stop switches 120a, 120b, and 120c, and the replay display. dynamic port output processing for controlling the lighting of the section indicator 160.

(Step S400-9)
The main CPU 200a updates the timer interrupt processing phase. The timer interrupt processing phase is one of 0 to 3. Here, when the timer interrupt processing phase is 0, 1, or 2, 1 is added, and when the timer interrupt processing phase is 3, is changed to 0.

(Step S400-11)
The main CPU 200 a performs sub-command transmission processing for transmitting the command stored in the transmission buffer to the sub-control board 202 .

(Step S400-13)
The main CPU 200 a executes stepping motor control processing for controlling the stepping motor 152 .

(Step S400-15)
The main CPU 200 a executes output port image output processing for outputting an output image to be output to the medal payout device 142 .

(Step S400-17)
The main CPU 200a executes random number update processing for updating various random numbers.

(Step S400-19)
The main CPU 200a executes fraud monitoring processing for detecting errors in order to output external signals (external signals 4 and 5) corresponding to errors to the outside.

(Step S400-21)
The main CPU 200a executes a module (subroutine) corresponding to the timer interrupt processing phase updated in step S400-9. Here, the timer interrupt processing phase is set to one of 0 to 3, and one module corresponding to each of the timer interrupt processing phases 0 to 3 is provided (four in total). One module will be executed once every four timer interrupt processing (every 5.96 ms). For example, a module that executes time monitoring processing for subtracting various timers is associated with one timer interrupt processing phase.

(Step S400-23)
The main CPU 200a executes test signal output processing for outputting the test signal to the outside.

(Step S400-25)
The main CPU 200a reads various input port images and executes port input processing for accurately acquiring the latest switch status.

(Step S400-27)
The main CPU 200a restores the register.

(Step S400-29)
The main CPU 200a permits the interrupt and terminates the timer interrupt process.

<Configuration around the CPU of the main control board>
FIG. 32 is a diagram for explaining electrical connections around the main CPU 200a. The main CPU 200 a includes a CPU core 700 and a bus controller 702 . The CPU core 700 controls the bus controller 702 through a bus control signal (Bus Cont) output from the BC terminal, reads data from the main ROM 200b, the main RAM 200c, or the input/output unit 704, or reads data from the main RAM 200c or the input/output unit 704. Data is written to the portion 704 . Here, as the main CPU 200a, a microprocessor based on the Z80 series CPU sold by LETech is used.

For example, when reading data from the main ROM 200b, the main RAM 200c, or the input/output unit 704, the bus controller 702 outputs a 16-bit address (A[16]) signal and outputs the main ROM 200b, Either the main RAM 200c or the input/output unit 704 is specified, and the read (RD) signal is controlled to read the data (D[8]) signal from the main ROM 200b, the main RAM 200c, or the input/output unit 704. . When data is written to the main RAM 200c or the input/output unit 704, the bus controller 702 outputs an address (A[16]) signal and a data (D[8]) signal to the main RAM 200c through decoders 706b and 706c. , or specifies one of the input/output units 704 and controls the write (WR) signal to write the data (D[8]) signal to the main RAM 200 c or the input/output unit 704 .

Here, as will be described later, the address space of the input/output unit 704 is integrated with the address spaces of the main ROM 200b and the main RAM 200c. Therefore, conventionally, a memory request (MREQ) terminal and an I/O request (IORQ) terminal for outputting a signal for specifying whether to access memory or I/O are not provided. By reassigning these two terminals to arbitrary other signals, the degree of freedom in program development can be increased.

The CPU core 700 also includes an interrupt/wait (INT/WAIT) signal that triggers the start of interrupt processing, a non-maskable interrupt (NMI) signal that allows interrupt processing to be executed with the highest priority, and bus signals that are set to high impedance. An external signal such as a transitionable bus request (BUSREQ) signal is also input.

FIG. 33 is a block diagram showing the internal configuration of the CPU core 700. As shown in FIG. CPU core 700 includes external input unit 710 , state control unit 712 , central control unit 714 , register unit 716 and arithmetic logic unit (ALU) 718 . The external input unit 710 receives external signals and outputs control information based on the external signals to the state control unit 712 and the central control unit 714 .

State control unit 712 manages and transitions internal states (RESET, instruction fetch, instruction decode, operation, memory load, memory store, HALT, etc.) based on input control information to change the operating state of CPU core 700. It determines and outputs control information to the central control unit 714 based on its operating state.

Central control unit 714 extracts an operation code (instruction) from input data (DI[8]) input via bus controller 702 and controls ALU 718 based on the command decoded by the instruction decoder. Also, the central control unit 714 acquires necessary information from each register of the register unit 716 and updates each register according to the decoded command.

Register unit 716 includes selector ports 722 a , 722 b , 722 c , input bank selector 724 , first register bank 726 , second register bank 728 , output bank selector 730 , address port 732 and individual registers 734 . The individual register 734 includes a 16-bit program counter (PC) indicating the address of the next program to be executed, an 8-bit interrupt (I) register used in interrupt mode, and an 8-bit counter for counting opcode fetch cycles. It includes a bit refresh (R) register and an 8-bit interrupt enable (IFF) register that controls interrupt enable/disable.

In addition, the register unit 716 has a random number generator for obtaining various random numbers (jackpot determination random number, winning pattern random number, reach group determination random number, reach mode determination random number, variation pattern random number, winning determination random number) related to the big win lottery. A device (not shown) is associated with the input port (FE73h-FE9Ch) to obtain the latched random value.

The random number generator operates with a system clock (a clock obtained by dividing an external input by two) and generates random numbers less than a predetermined maximum value. The random number generator is a random number generator capable of setting the maximum value of random numbers. A configurable random number generator is provided with eight channels. Here, the 16-bit maximum value setting random number generator can select the random number update period within the range of 32 to 47 clocks, and the maximum value setting range can be set within the range of 256 to 65,535. In addition, the 8-bit maximum value setting random number generator can select the random number update period in the range of 16 to 31 clocks, and the maximum value setting range can be set in the range of 16 to 255 for 4 channels. It can be set in the range of 64-255. In addition, as a random number generator with a fixed maximum value of random numbers, a random number generator capable of setting a maximum value of 16 bits has four channels and a random number generator capable of setting a maximum value of 8 bits. The instrument is prepared for 8 channels. Here, the 16-bit fixed maximum value random number generator has a fixed random number update cycle of 1 clock and a maximum value of 65,535. The 8-bit fixed maximum value random number generator has a fixed random number update cycle of 1 clock and a maximum value of 255.

If the number of types of random numbers is insufficient, the random numbers obtained from the hardware random number generator (random number generator) are multiplied by a predetermined number in the program, or divided to generate other random numbers (software random number generator).

FIG. 34 is a diagram illustrating the configuration of registers. The register unit 716 is provided with a first register bank (bank 0) 726 and a second register bank (bank 1) 728 paired with the first register bank 726 . The first register bank 726 is provided with a main register group (front register group) 726a and a sub-register group (back register group) 726b paired with the main register group 726a. A main register group 728a and a sub-register group 728b paired with the main register group 728a are provided. The main register group 726a and sub-register group 726b of the first register bank 726 and the main register group 728a and sub-register group 728b of the second register bank 728 are both 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY). However, unlike the sub-register groups 726b and 728b, the main register groups 726a and 728a further include an 8-bit register (U) and a 16-bit register (SP). The main CPU 200a switches between the first register bank 726 and the second register bank 728 and can access only one of the register banks indicated by the register bank designation register RB in the F register, which will be described later. The other register bank cannot be accessed simultaneously.

Among the registers shown in FIG. 34, the Q registers are 8-bit registers that are provided in two sets in each register bank as extended registers and store the high-order bytes of addresses used in some commands. If, for example, F0h is set as the value of the Q register, the main CPU 200a can use the Q register to access F000h to F0FFh of the main RAM 200c. The U register is an 8-bit register that is provided in each register bank as an extension register and stores the upper byte of the address used in some commands. If, for example, FEh is set as the value of the U register, the main CPU 200a controls internal devices (timers, random number generators, external input/output circuits, etc.) connected to the input/output unit 704 for FE00h to FEFFh. A U register is available for access. The A register is a general-purpose register that also functions as an 8-bit accumulator used for arithmetic processing and data transfer. The F register is an 8-bit flag register that holds various calculation results. Here, as shown in FIG. 34, each bit of the F register is from the most significant bit (MSB: Most Significant Bit) to the least significant bit (LSB: Least Significant Bit), and S is 1 when the operation result is negative. , Z is a zero flag (first zero flag) that is set to 1 when all bits are 0 as a result of the operation, and TZ is a data transfer instruction (LD; load) executed by , is a specific bit flag (second zero flag) of extended specifications for gaming machines, which is set to 1 (value changes) when all bits are 0, and is sometimes called a teeze flag. H is a half-carry flag that cannot be touched by the programmer, and RB (register bank designation register) is a register bank monitor that indicates the current register bank (first register bank 726=0, second register bank 728=1). , P/V is a parity overflow flag, N is an addition/subtraction flag that cannot be touched by the programmer, and C is a carry flag that is set to 1 when a carry or borrow occurs as a result of an operation. The F register constitutes the A register and the pair register AF.

The B register, C register, D register, E register, H register, and L register are two sets of 8-bit general-purpose registers provided in each register bank, each of which is a predetermined combination of 16-bit pairs. Registers (eg, registers BC, DE, HL, and multiple combinations exist) are configured and utilized. The IX and IY registers are 16-bit general-purpose registers used for index addressing. The SP (stack pointer) register is 16 bits and stores an address that serves as a stack pointer. Q' register, A' register, F' register, B' register, C' register, D' register, E' register, H' register, L' register, IX' register, IY' register are Q register, A register , F register, B register, C register, D register, E register, H register, L register, IX register, and IY register. Possible sub-register groups 726b, 728b, where the A' and F' registers form a pair register AF', the B' and C' registers form a pair register BC', and the D' and E' registers. constitute a pair register DE', and the H' register and L' register constitute a pair register HL'. Note that the pair registers are not limited to BC', DE', and HL', and there are other combinations. On the other hand, one set of U register and SP register is provided for each register bank.

By the way, as described above, in the main control board 200, the main CPU 200a controls the progress of the game in cooperation with the main RAM 200c based on the programs stored in the main ROM 200b. Programs for executing these functional units are arranged in predetermined areas (used areas) of the main ROM 200b and the main RAM 200c.

FIG. 35 is an explanatory diagram showing a memory map. A memory space of 0000h to 3FFFh (12 kbytes) is allocated to the main ROM 200b, a memory space of F000h to F3FFh (1 kbyte) is allocated to the main RAM 200c, and a memory space of FE00h to FEFFh (256 bytes) is allocated to the input/output unit 704. Allocated memory space. The instruction code of the program is written in assembler language. Here, the program is composed of instruction codes, is read by a computer, and can realize predetermined processing in cooperation with data and a work area.

A memory space from 0000h to 1DF3h of the main ROM 200b is allocated a usable area. The use area is an area for storing programs and data for executing game control processing for controlling the progress of the game. Specifically, initialization means 300, betting means 302, winning type lottery means 304, reel control means 306, determination means 308, payout control The instruction code of the program for executing the game control process that controls the progress of the game by making the means 310, the game state control means 312, the effect state control means 314, and the command transmission means 316 function is stored, and 1200h to 1DF3h (3 0 kbytes), data used for the game control processing program is stored in the memory space (data area). A comment area is allocated to the memory space of 1E00h to 1FFFh, and a program management area is allocated to the memory space of 3FC0h to 3FFFh. Another area (unused area) is allocated to the memory space from 2000h to 3FBFh. The separate area is an area for storing programs and data that are not specified to be stored in the use area, as will be described later. Specifically, in the memory space from 2000h to 3FBFh, some or all of the game machine test processing and security-related processing that do not affect the progress of the game (hereinafter simply referred to as non-game control processing) is stored) and the instruction code and program data of the program that executes the

In addition, the memory space of F000h to F1FFh of the main RAM 200c is allocated with a use area. Specifically, the memory space of F000h to F13Fh is assigned a work area for the game control process, and is used for variable management such as timers, counters, and flags. A stack area for the game control process is assigned to the memory space of F1C0h to F1FFh. Another area is allocated to the memory space of F200h to F3FFh of the main RAM 200c. More specifically, the memory spaces F210h to F22Fh are allocated work areas for some or all of the security-related processes, and are used for managing variables such as timers, counters, and flags. A stack area for part or all of the security-related processing is allocated to the memory spaces F230h to F246h.

An input/output unit 704 is assigned to the memory space of FE00h to FEFFh. Conventionally, in order to access the device corresponding to the input/output unit 704, an I/O space of 256 bytes was provided independently of the memory space. On the other hand, in this embodiment, the MREQ and IORQ signals are eliminated, and access to the memory and the input/output unit 704 is made common and performed by the RD and WR signals. A U register is provided as hardware for designating the upper 8-bit address for accessing the device connected to the input/output unit 704, and the 8-bit upper address is designated in advance. As a result, the I/O space provided independently of the memory space is integrated into the memory space to form one address space, and when the IN instruction and the OUT instruction are executed, the input/output unit 704 is assigned to the memory space. On the other hand, the upper 8 bits are specified by the U register, and the lower 8 bits can be accessed using the lower 8 bits specified by the operands of the IN and OUT instructions.

In this embodiment, the LDQ instruction uses the value of the Q register to access the memory space (mainly the data area and work area), and the IN and OUT instructions use the U register to access the device (timer, random number generator, external It becomes possible to describe a program so as to access I/O of an input/output circuit, etc.). Such a configuration makes it easier to grasp the program at the time of design. In addition, memory and I/O that have been accessed by specifying them with 16-bit addresses can now be accessed with lower 8-bit operands, and the program capacity can be compressed. Furthermore, by having a plurality of high-order designated registers such as the Q register, Q' register, and U register, the number of exchanges due to reuse of the high-order register is reduced compared to when there is only one high-order register, and the program capacity is further compressed. be able to.

Although the memory space corresponding to the I/O space is accessed by the IN instruction and the OUT instruction in the above example, the memory space may be directly accessed by the IN instruction and the OUT instruction. For example, when accessing three 256-byte areas on the memory, the upper 8 bits are specified in the Q register, Q' register, and U register, respectively, and the LDQ, IN, and OUT instructions This can be achieved by accessing the area of

<Reference to various tables>
The main CPU 200a refers to the table in which necessary information is arranged in each process shown in FIGS. 9 to 31, and extracts various information required for the progress of the game. Here, specific processing for extracting information will be described using various tables such as an area data table, an internal lottery offset table, a number acquisition table, and a symbol bit offset table as examples.

(internal lottery offset table)
The main CPU 200a refers to the area-specific data table ("T_CMD_SET") in the winning combination group setting process S230-5 in the symbol code setting process S230 of FIG. Based on, the winning hand group is determined. Then, the command transmission means (information transmission means) 316 of the main CPU 200a transmits the determined winning combination group (group information) to the sub control board 202 as a winning information command every game. The value of the winning area is determined by the winning type lottery means 304 corresponding to each of the plurality of winning types. Therefore, the winning type lottery means 304 also functions as a winning area lottery means for determining a winning area by lottery.

FIG. 36 is a program code showing specific processing of the winning combination group setting processing S230-5. The index "GET_ARD:" on the first line in FIG. 36(a) indicates the start address of the winning combination group setting process. The command "LD HL, T_CMD_SET" on the second line sets the top address ("T_CMD_SET") of the data table for each area in the HL register. A command "RST CALADRS" on the third line calls a subroutine "CALADRS" for register addition processing. At this time, an identification number (hereinafter simply referred to as a winning area value or a winning area) that can identify the winning area acquired in the gaming state setting process S230-1 is set in the A register. Note that the values of the winning regions are indicated by serial numbers from 0 to 36. FIG. In the subroutine "CALADRS", the value of the HL register and the value of the A register are added, and the contents of the address indicated by the added value in the data table for each area ("T_CMD_SET") are set in the A register. Then, the command "RET" on the fourth line returns to the calling process.

In the data table by area ("T_CMD_SET") shown in FIG. 36(b), the winning area and the value of the winning combination group in the winning type table shown in FIG. 6 are associated with each other. In addition, the order of description is arranged in serial numbers so that the values (0 to 36) of the winning areas are in ascending order. Therefore, by using the value of the winning area as an offset value to the address where the data is stored in the data table for each area, it is possible to specify the address where the data indicating the value of the winning combination group is stored. can. For example, if the winning area is "0", the command "RST CALADRS" on the third line in FIG. “T_CMD_SET”+winning area “0”) is specified, and “0” is set in the A register as the value of the winning hand group. If the winning area is "10", the command "RST CALADRS" on the 3rd line of FIG. “T_CMD_SET”+winning area “10”) is specified, and “4” is set in the A register as the value of the winning hand group. In this way, the main CPU 200a can acquire the value of the winning combination group and transmit the winning information command (_HIT_CMD) indicating the winning combination group to the sub control board 202. FIG.

Here, the winning hand group is defined by the type of winning hand (replay hand, small hand, bonus hand), function in the progress of the game, or game profit (advantage section transition, CZ effect state transition, AT effect state transition, etc.). This is a grouping of a plurality of winning areas with the same probability of being awarded. According to FIG. 6, for example, the winning area 4 to the winning area 15 are grouped as the winning combination group 4 with the same function as the winning type "batting order bell". Here, when the winning type "Battering order bell B1" of the winning area 10 is won, the main CPU 200a does not provide the information indicating the winning type "Battering order Bell B1" capable of grasping the correct operation mode, but the winning corresponding to the winning area 10. Information indicating the hand group 4 is transmitted to the sub control board 202 . Further, the main CPU 200a transmits a command capable of grasping the correct operation mode to the sub control board 202 separately from the winning hand group 4 in the AT effect state, and does not transmit such a command in the non-AT effect state. With such a configuration, it is possible to prevent the player from illegally awarding the correct combination in the non-AT effect state.

Also, in the lottery data acquisition process S220-15 in the internal lottery process S220 of FIG. The lottery data (number), which is a numerical value indicating the winning range of the predetermined winning area, is obtained.

FIG. 37 is a program code showing specific processing of the lottery data acquisition process S220-15, and FIG. 38 is a program code showing an internal lottery offset table. In the internal lottery offset table of FIG. 38, the winning area is associated with the offset value to the lottery data group. In addition, the order of description is arranged in serial numbers so that the values (1 to 36) of the winning areas are in ascending order. Therefore, by using the value of the winning area as the offset value to the address where the data is stored in the internal lottery offset table, the address where the data indicating the offset value to the lottery data group is specified. be able to. Here, the lottery data group is a data group in which the lottery data (numbers) corresponding to the winning areas are arranged singly or collectively in ascending order of set values.

The index "LOTDATA:" on the first line in FIG. 37 indicates the start address of the lottery data acquisition process. The command "LD A, B" on the second line copies the value (0 to 36) of the winning area set in the B register to the A register. The command "LD HL, T_MAP_NML-1" on the third line sets the head address ("T_MAP_NML")-1 of the internal lottery offset table in the HL register. Here, the reason why 1 is subtracted is to match the winning areas 1 to 36 with the address of the offset value to the lottery data group. The subroutine "CALADRS" is called by the command "RST CALADRS" on the fourth line, the value of the HL register and the value of the A register are added, and the added value in the internal lottery offset table ("T_MAP_NML") of FIG. The content of the indicated address (the offset value in the internal lottery offset table) is set in the A register. In this way, the offset values to the lottery data group corresponding to the winning area values (1 to 36) are extracted.

For example, if the winning area is "4", the address obtained by adding "4" to the head address "T_MAP_NML"-1 of the internal lottery offset table, that is, the value described in the fifth line of FIG. , the offset value "T_SEL_NML_AT1-$" is doubled, and a value with bit 0 set to 0 is set in the A register. If the winning area is "20", the address obtained by adding "20" to the top address "T_MAP_NML"-1 of the internal lottery offset table, that is, the offset value " T_SEL_NML_BA2-$” is doubled and the value with bit 0 set to 0 is set in the A register. Note that "$" indicates the value of the address itself where the code is described.

Subsequently, the value of the A register is shifted by 1 bit by the command "SRL" on the fifth line in FIG. Thus, only the offset value to the lottery data group remains in the A register. If the bit 0 of the value referred to from the internal lottery offset table "T_MAP_NML" is 1 by the command "JR NC, LOTDATA01" on the sixth line, that is, if the bonus type is not confirmed, the process of the seventh line is performed. without jumping to the index "LOTDATA01" on the 8th line. If the bit-shifted carry is 0, the command "RTQ Z, (LOW_BNS_KND)" on the 7th line sets the value of the Q register to the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "_BNS_KND" to If the value (bonus type) stored in the memory area indicated by the lower 1 byte of the address is 0, the process returns to the caller.

The subroutine "CALADRS" is called by the command "RST CALADRS" on the ninth line in FIG. In ("T_MAP_NML"), the content of the address indicated by the added value is set in the A register. For example, if the winning area is "4", the address obtained by adding the offset value "T_SEL_NML_AT1-$" to the top address "T_MAP_NML" of the internal lottery offset table, that is, the 39th to 46th lines in FIG. Of the lottery data group shown, "@RNK_FLG+@LOT_OFS_NHT" described in the 40th line is set in the A register. If the winning area is "20", the address obtained by adding the offset value "T_SEL_NML_BA2-$" to the top address "T_MAP_NML" of the internal lottery offset table, that is, the 48th to 50th lines in FIG. Of the lottery data group shown, "@BYT_FLG+@YME_FLG+@LOT_OFS_1FK" described in the 49th line is set in the A register.

The command "LD C, A" on the 10th line in FIG. 37 temporarily saves the value of the A register to the C register, and the command "AND 0FH" on the 11th line masks the lower 4 bits of the A register, triggering A role type is generated. By the command "LDQ (LOW_TRG_KND), A" on the 12th line, the value of the A register (the generated trigger role type) is set to the value of the Q register as the upper 1 byte of the address and the lower 1 byte of the address "_TRG_KND". The value is stored in the memory area indicated by the 2-byte address with the lower 1 byte of the address. The command "INC HL" on line 13 increments the value of the HL register by one.

If the bit "@YME_BIT" of the C register is 1 by the command "JBIT NZ, @YME_BIT, C, LOTDATA02" on line 14 of FIG. jumps to the index "LOTDATA02" on the 17th line without performing the processing of . Also, by the command "JTQ NZ, (LOW_YRI_KND), LOTDATA02" on the 15th line, the value of the Q register is set as the upper 1 byte of the address, and the value of the lower 1 byte of the address "_YRI_KND" is set as the lower 1 byte of the address. If the value stored in the memory area indicated by the 2-byte address, that is, if the advantageous section type is not 0, the process of the 16th line is skipped and the process jumps to the index "LOTDATA02" on the 17th line. If the conditions of the commands on the 14th and 15th lines are not satisfied, the command "CLRQ (LOW _TRG_KND)" on the 16th line sets the value of the Q register to the upper 1 byte of the address and the lower 1 byte of the address "_TRG_KND". is stored as the lower 1 byte of the address, 0 is stored, and the trigger role type is cleared.

The command "LDQ A, (LOW_GAM_RNK)" on the 18th line in FIG. The value stored in the memory area indicated by , that is, the set value data (0 to 5) is set in the A register. According to the command "JBIT NZ, @RNK_BIT, C, LOTDATA03" on the 19th line, if the bit "@RNK_BIT" of the C register is 1, that is, if there is a setting difference, the processing of the 20th line is performed. without jumping to the index "LOTDATA03" on the 21st line. The command "XOR A" on line 20 sets the A register to 0 if the bit "@RNK_BIT" in the C register is 0, ie if there is no set difference. Thus, the set value data is set to 0 when there is no set difference.

The command "BIT @BYT_BIT, C" on the 22nd line in FIG. JR NZ, LOTDATA04", if the bit checked is 1, that is, if the data size is 1 byte, then the index "LOTDATA04" in line 29 is processed without processing lines 24-28. jump to If the confirmed bit is 0, that is, if the data size is 2 bytes, the command "ADD A, A" doubles the value of the A register, and the command "RST CALADRS" on the 25th line calls the subroutine "CALADRS", adds the value of the HL register and the value of the A register, and produces the result shown in FIG. The content (lottery data) of the address indicated by the added value in the internal lottery offset table ("T_MAP_NML") is set in the A register. For example, if the winning area is "4" and the set value is "2", the HL register incremented on the 13th line will have the A register value of 2 (the value "1" indicating the set value "2" x The address to which the offset value "2") has been added, that is, the lower 1 byte of the lottery data "3218" described in the 42nd line in the lottery data group shown in the 39th to 46th lines in FIG. The value "92H" is set in the A register.

Subsequently, the value of the HL register is incremented by one by the command "INC HL" on line 26 in FIG. The value stored in the memory area at the address indicated by the HL register is set in the H register by the command "LD H, (HL)" on the 27th line. For example, if the winning area is "4" and the set value is "2", the upper 1-byte value "0CH" of the lottery data "3218" described in the 42nd line of FIG. set. The command "JR LOTDATA05" on the 28th line in FIG. 37 jumps to the index "LOTDATA05" on the 32nd line.

Subsequently, the subroutine "CALADRS" is called by the command "RST CALADRS" on the 30th line of FIG. 37, the value of the HL register and the value of the A register are added, and the internal lottery offset table ("T_MAP_NML") of FIG. , the content of the address indicated by the added value (lottery data) is set in the A register. For example, if the winning area is "20" and there is no set difference, the address obtained by adding the value 0 of the A register to the HL register incremented in line 13 of FIG. Of the lottery data group shown in the 1st to 50th lines, the lottery data "16" described in the 50th line is set in the A register. Then, 0 is set in the H register by the command "LD H, 0" on the 31st line in FIG.

The command "LD L, A" on the 33rd line in FIG. 37 sets the value of the A register to the L register. Thus, lottery data is set in the HL register. The command "OR H" on the 34th line calculates the logical sum of the A register and the H register, and if both registers are 0, the value of the A register is set to 0 (the zero flag is established). be done. Then, the command "RET" on the 35th line returns to the calling process.

As described above, here, by executing the lottery data acquisition process S220-15 in a state in which the value of the winning area (1 to 36) is set in the B register as an argument, the lottery data is stored in the HL register as a result. Data can be captured. Specifically, as shown in the 2nd to 37th rows of FIG. 38, the main CPU 200a uses the same number of internal lottery offset tables as the winning areas to determine the lottery values (1 to 36) corresponding to the winning areas. Extract the offset value into the data group. Then, based on the extracted offset value, one lottery is drawn from a plurality of lottery data groups (for example, 39th to 46th rows, 48th to 50th rows) in which lottery data corresponding to the winning area is determined. A data group is specified, and one lottery data corresponding to the winning area is determined based on whether there is a setting difference in the winning area and whether the data size of the lottery data is 1 byte or 2 bytes. identified.

By the way, lottery data (lottery data group) may be common in a plurality of winning areas. For example, as can be understood with reference to FIG. 38, for winning areas 4 to 15 described in lines 5 to 16 in FIG. ) is extracted, and for the winning areas 16 to 18 described in the 17th to 19th lines of FIG. .

In this way, the main CPU 200a refers to common lottery data for winning areas 4-15. Separately from this, as can be understood with reference to FIGS. 6 and 36, winning regions 4 to 15 have the same winning hand group value of "4". Therefore, it can be said that, at least, the winning areas in which the winning combination group is common also have the lottery data in common. Here, the internal lottery offset table is simplified by using the winning combination group "4" instead of the winning areas 4 to 15, taking advantage of the fact that the lottery data is also common in the winning areas with the same winning combination group. It is possible to

More specifically, as described with reference to FIG. 36, in the winning combination group setting process S230-5, an area-by-area data table ("T_CMD_SET") in which winning areas and values of winning combination groups are associated is used. A winning combination group is specified based on the winning area, and the winning combination group is transmitted to the sub-control board 202 as a winning information command. Therefore, by the winning combination group setting process S230-5, a winning combination group formed by grouping a part of the winning area has already been specified. Here, in the lottery data acquisition process S220-15 shown in FIG. 37, the winning combination groups 1 to 23 are set as arguments in the B register instead of the winning areas 1 to 36, and the lottery data acquisition process S220-15 is executed. can be executed, and as a result the lottery data can be loaded into the HL register.

FIG. 39 is program code showing another example of the internal lottery offset table. In the internal lottery offset table of FIG. 39, the winning combination group is associated with the offset to the lottery data group. The order of description is arranged in serial numbers from 1 to 23 so that the identification numbers that can specify the winning combination group (hereinafter simply referred to as the value of the winning combination group or the winning combination group) are in ascending order. there is Therefore, by using the value of the winning hand group as the offset value to the address where the data is stored in the internal lottery offset table, the address where the data indicating the offset value to the lottery data group is specified. can do.

For example, if the winning area is "4", the winning combination group "4" is specified by the winning combination group setting process S230-5. The command "RST CALADRS" on the fourth line in the lottery data acquisition process S220-15 of FIG. A value in which bit 1 is set to 0 by doubling the offset "T_SEL_NML_AT1-$", which is the value described in the row, is set in the A register. Then, the command "RST CALADRS" on the ninth line in FIG. "@RNK_FLG+@LOT_OFS_NHT" is set in the A register. If the set value is "2", the address obtained by adding the A register value 2 (the value "1" x 2 indicating the set value "2") to the HL register incremented on the 13th line in FIG. That is, the lower 1-byte value "92H" of the lottery data "3218" described on the 29th line in FIG. 39 is set in the A register, and the command "LD H, (HL)" on the 27th line in FIG. As a result, the upper 1-byte value "0CH" of the lottery data "3218" described in the 29th line of FIG. 39 is set in the H register. In this way, the lottery data "3218" corresponding to the winning area 4 (winning combination group 4) can be obtained.

Further, when the winning area is "20", the winning combination group "7" is specified by the winning combination group setting process S230-5. The command "RST CALADRS" on the fourth line in the lottery data acquisition process S220-15 in FIG. A value in which bit 1 is set to 0 by doubling the offset "T_SEL_NML_BA2-$", which is the value described in the row, is set in the A register. Then, the command "RST CALADRS" on the 9th line in FIG. LOT_OFS_1FK" is set in the A register. Since such lottery data has no setting difference, the address obtained by adding the value 0 of the A register to the HL register incremented in the 13th line of FIG. 37, that is, the lottery data " 16" is set in the A register, and 0 is set in the H register by the command "LD H, 0" on the 31st line in FIG. Thus, the lottery data "16" corresponding to the winning area 20 (winning combination group 5) can be obtained.

Comparing the internal lottery offset table of FIG. 38 with the internal lottery offset table of FIG. 39, the internal lottery offset table of FIG. , the difference between the winning areas 1 to 36 and the winning combination groups 1 to 23, that is, 13 bytes can be reduced.

Here, one or a plurality of winning combination groups (group information) are determined by grouping part of the plurality of winning areas 0 to 36, for example, the winning areas 4 to 15, and the determined winning areas are included. The subject (function of the main CPU 200a) that identifies the winning combination group is the group identification unit. In addition, the entity (function of the main ROM 200b) in which the internal lottery offset table (table) in which the lottery data (information about the winning area) is arranged is used as a storage means. Also, lottery data is derived using the top address "T_MAP_NML" of the internal lottery offset table as a reference and the value of the winning hand group corresponding to the lottery data (identification number that can specify group information: 1 to 23) as the offset value. Let the subject be information derivation means. Also, in the internal lottery offset table, the lottery data are arranged so that the winning combination group values (1 to 23) corresponding to the lottery data are arranged in ascending order. Also, the identification number is sufficient as long as it is identification information that can be identified from others, and various numerical values can be applied. In the above description, the lottery data is arranged in the internal lottery offset table so that the values of the winning combination groups corresponding to the lottery data are arranged in ascending order. The values of the winning combination groups corresponding to the lottery data may be arranged in descending order according to the definition of the addresses (leading address or trailing address).

In this way, here, it is assumed that the winning combination group including the determined winning area is specified, and the specified winning combination group is transmitted to the sub control board 202. is effectively used to specify the lottery data from the internal lottery offset table. With such a configuration, lottery data can be specified appropriately without generating grouped information anew, that is, while suppressing an increase in new programs and processing load. In addition, instead of the winning area, the lottery data is extracted using a smaller number of winning hand groups than the winning area as the offset value, so as described above, it is possible to greatly reduce the memory capacity of the internal lottery offset table. becomes.

(Number of sheets acquisition table)
In the above-described embodiment, an example has been given in which the memory capacity of the internal lottery offset table is reduced by using the winning combination group setting process S230-5 required for converting the winning combination into the winning combination group. In the following, using the winning combination group setting process S230-5, a new parameter is generated by grouping different from the winning combination group, thereby reducing the memory capacity of the table.

For example, as described above, in the present embodiment, the difference number management is performed in the AT effect state. In order to prevent an unintended extension of the AT effect state in the difference number management, when the assist effect is executed, regardless of whether or not the player actually follows the assist effect, when the player follows the assist effect, The available difference number is counted (subtracted). Therefore, the difference number in the AT effect state can be uniquely obtained from the winning area. For example, if the player wins the winning type "batting order bell A1" in the winning area 4 and the auxiliary effect of the correct operation mode (batting order 1) that allows winning of the winning combination "seven-card combination" is executed, the player does not participate in the auxiliary effect. Regardless of whether it is actually followed or not, the difference number of 7 cards that can be obtained when the auxiliary effect is followed is uniquely specified, and the 7 cards are counted. Here, the subtraction number acquisition process for acquiring the difference number to be subtracted based on the winning area will be described.

FIG. 40 is a program code showing specific processing of the subtraction number acquisition processing. The command "LDQ A, (LOW_HIT_NUM)" on the first line of FIG. The value stored in the memory area indicated by the address, that is, the value of the winning area (stop control number) is set in the A register. The command "LD HL, T_CLC_MDL" on the second line sets the head address ("T_CLC_MDL") of the number acquisition table in the HL register. The command "ADDWB HL, A" on the third line updates the value of the HL register by adding the value of the A register to the value of the HL register. The value stored in the memory area at the address indicated by the HL register is read into the A register by the command "LD A, (HL)" on the fourth line.

In the number acquisition table ("T_CLC_MDL") of FIG. 40(b), the winning area is associated with the difference number to be subtracted. In addition, the order of description is arranged in serial numbers so that the values (0 to 36) of the winning areas are in ascending order. Therefore, by using the value of the winning area as an offset value to the address where the data is stored in the number acquisition table, it is possible to specify the address where the data indicating the difference number is stored. For example, if the winning area is "0", the second row ("T_CLC_MDL"+winning area "0") in FIG. is set in the A register. Also, if the winning area is "10", in the subtraction number acquisition process, the 12th line ("T_CLC_MDL" + winning area "10") in FIG. 40B is specified as the address, and the difference number is "7". is set in the A register.

As described above, here, by setting the winning area value (0 to 36) in the A register as an argument and executing the subtraction number acquisition process, the difference number can be set in the A register as a result. . Specifically, the main CPU 200a, as shown in the 2nd to 38th rows of FIG. are extracted. It should be noted that here, in some winning areas, the difference number is common. For example, as can be understood with reference to FIG. 40, for the winning areas 0 to 3 described in the 2nd to 5th lines of FIG. 40, and for the winning areas 4 to 15 described in the 6th to 17th lines of FIG. 40, the same difference number "7" is extracted in common. Therefore, by grouping the winning areas with the common difference number to make a difference number group that can uniquely identify the difference number, for example, by using the difference number group instead of the winning areas 0 to 36, the number acquisition table is created. Simplification is possible.

The difference number group is 0 to 4 (@MDL_000, @MDL_001, @MDL_003, @MDL_007, @MDL_015) for each difference number "0", "1", "3", "7", and "15". assigning a value. Then, the process of acquiring the difference number group based on the winning area is executed using the winning combination group setting process S230-5 necessary for converting the winning area into the winning combination group. Specifically, in this embodiment, the winning combination group is determined in the range of 0-23. That is, a 5-bit area is required to identify the winning hand group. In other words, only 5 bits out of 1 byte (8 bits), which is unit data prepared in the area-specific data table, are used for identifying the winning hand group. Therefore, 3 bits that are not used for identifying the winning hand group are used to describe the difference number groups 0 to 4. FIG. Then, the main CPU 200a extracts the difference number group together with the winning combination group by the winning combination group setting process S230-5.

FIG. 41 is a program code showing another example of the winning combination group setting process S230-5. The index “GET_ARD:” on the first line in FIG. 41(a) indicates the start address of the winning combination group setting process. The command "LD HL, T_CMD_SET" on the second line sets the top address ("T_CMD_SET") of the data table for each area in the HL register. The command "RST CALADRS" on the third line calls a subroutine "CALADRS" that performs register addition processing, adds the value of the HL register and the value of the A register, and adds the value in the area-specific data table ("T_CMD_SET"). The content of the address indicated by the value (difference number group x 32 + winning combination group) is set in the A register. The lower 5 bits are masked by the command "AND 00011111B" on the fourth line, leaving only the winning hand group in the A register. Then, the command "RET" on the fifth line returns to the calling process.

In the area-by-area data table ("T_CMD_SET") of FIG. 41(b), in addition to the value of the winning combination group, the value of the difference number group is associated with the winning area. In addition, the order of description is arranged in serial numbers so that the values (0 to 36) of the winning areas are in ascending order. Therefore, by using the value of the winning area as it is as an offset value to the address where the data is stored in the data table for each area, the difference number group and the winning combination group can be specified. For example, if the winning area is "0", the subroutine "CALADRS" specifies the second line ("T_CMD_SET"+winning area "0") in FIG. A certain “@MDL — 000” (equivalent to 0) and “0” which is the value of the winning hand group are set. If the winning area is "10", the subroutine "CALADRS" specifies the 12th line ("T_CMD_SET"+winning area "10") in FIG. @MDL — 007” (corresponding to “3”) and “4”, which is the winning hand group, are set.

Thus, by using the winning combination group setting process S230-5 for acquiring the winning combination group based on the winning area, it is possible to acquire the difference number group based on the winning area. Subsequently, subtraction number acquisition processing is performed in a manner different from that in FIG. 40 using the acquired difference number group.

FIG. 42 is a program code showing another example of subtraction number acquisition processing. The subroutine "GET_HTD" is called by the command "CALLF GET_HTD" on the first line of FIG. is set to The value stored in the memory area of the address indicated in the HL register by the command "XOR (HL)" on the second line, that is, the HL register set by the command "RST CALADRS" on the third line in FIG. The value stored in the memory area of the address indicated by (difference number group×32+winning combination group) and the value of A register (winning combination group) are derived by exclusive OR. In this way, the lower 5 bits are cleared to 0, leaving only the upper 3-bit difference number group (difference number group x 32). The command "SRLA 5" on the third line in FIG. 42(a) shifts the value of the A register to the right by 5 bits. Thus, only the value of the difference number group remains in the A register. The command "LD HL, T_CLC_MDL" on the fourth line sets the top address ("T_CLC_MDL") of the number acquisition table in the HL register. The command "ADDWB HL, A" on the fifth line updates the value of the HL register by adding the value of the A register to the value of the HL register. The value stored in the memory area at the address indicated by the HL register is read into the A register by the command "LD A, (HL)" on the sixth line.

In the number acquisition table (“T_CLC_MDL”) of FIG. 42B, the difference number group and the difference number to be subtracted are associated. The order of description is arranged in serial numbers from 0 to 4 so that the identification numbers that can specify the difference number group (hereinafter simply referred to as the value of the difference number group or the difference number group) are in ascending order. . Therefore, by using the value of the difference number group as it is as an offset value to the address where the data is stored in the number acquisition table, the difference number can be specified.

For example, if the winning area is "0", the difference number group is "0". is specified, and "0" is set as the difference number. In addition, when the winning area is "10", the difference number group is "3", and in the subtraction number acquisition process, the ninth line ("T_CLC_MDL" + difference number group "3") in FIG. is specified, and "7" is set as the difference number.

Comparing the number acquisition table of FIG. 40 and the number acquisition table of FIG. 42, the number acquisition table of FIG. , 4 bytes of commands in the 3rd row are added, but the memory capacity can be reduced by the difference between the winning areas 0 to 36 and the difference number groups 0 to 4, that is, 32 bytes. Therefore, in total, it is possible to reduce the memory capacity of 28 bytes.

In this way, here, on the premise that the winning combination group including the determined winning area is specified and the specified winning combination group is transmitted to the sub-control board 202, the process of specifying the winning combination group is used. Then, the difference number group is specified by using the above method, and the difference number is specified from the number acquisition table based on the difference number group thus specified. In addition, in the data table for each area, the winning combination group and the difference number group are combined and expressed as unit data (1 byte). With such a configuration, it is possible to appropriately specify the difference number of sheets while suppressing an increase in new programs and processing load. In addition, instead of the winning area, the difference number group 0 to 4, which is smaller in number than the winning area 0 to 36, is used as an offset value to extract the difference number. can be reduced.

(Design bit offset table)
Another example of reducing the memory capacity of the table by generating new parameters by grouping different from the winning combination group and the difference number group using the winning combination group setting process S230-5 will be given below. explain.

In the symbol code initial setting process S230-7 in the symbol code setting process S230 of FIG. 18, the main CPU 200a refers to the symbol bit offset table and transfers the symbol arrangement data related to the stop control to the stop control RWM.

FIG. 43 is a program code showing specific processing of the symbol code initialization process S230-7, and FIG. 44 is a program code showing a symbol bit offset table (T_JUG_OFS). In the symbol bit offset table (T_JUG_OFS) of FIG. 44, the winning area is associated with the offset value to the symbol array data group. In addition, the order of description is arranged in serial numbers so that the values (0 to 36) of the winning areas are in ascending order. Therefore, by using the value of the winning area as the offset value to the address where the data is stored in the symbol bit offset table as it is, the address where the data indicating the offset value to the symbol array data group is specified. can do. Here, the symbol array data group is a data group in which the symbol array data corresponding to the winning areas are collectively arranged.

The command "LDQ A, (LOW_HIT_NUM)" on the first line in FIG. 43 sets the value of the Q register as the upper 1 byte of the address and the value of the lower 1 byte of the address "_HIT_NUM" as the lower 1 byte of the address. The value stored in the memory area indicated by , that is, the value of the winning area (stop control number) is set in the A register. The top address ("T_JUG_OFS") of the symbol bit offset table is set in the HL register by the command "LD HL, T_JUG_OFS" on the second line. The subroutine "CALADRS" is called by the command "RST CALADRS" on the third line, the value of the HL register and the value of the A register are added, and the added value in the symbol bit offset table ("T_JUG_OFS") of FIG. The content of the indicated address (offset value to the pattern array data group) is set in the A register. For example, if the winning area is "0", the address obtained by adding "0" to the address "T_JUG_OFS", that is, the offset value "T_JUG_DRW_000-$" described in the second line of FIG. set. The command "ADDWB HL, A" on the fourth line in FIG. 43 updates the value of the HL register by adding the value of the A register to the value of the HL register.

The command "LDQ DE, LOW _JUG_BIT" on the fifth line in FIG. 43 sets the value of the Q register to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_JUG_BIT" to the lower 1 byte of the address. The value stored in the memory area, that is, the address of the destination stop control RWM is set in the DE register. Then, the index "GET_DAT" on the eighth line is called as a subroutine by the command "CALLF GET_DAT" on the sixth line.

The index "GET_DAT:" on line 8 of FIG. 43 indicates the top address of the symbol code initial setting process. The command "LD B, 7" on the ninth line sets the loop count "7" in the B register. The contents of the address indicated by the HL register are set in the C register by the command "LD C, (HL)" on the 10th line. For example, if the winning area is "0", the value obtained by adding the offset "T_JUG_DRW_000-$" described in the second line of FIG. 44 to the HL register value ("T_JUG_OFS") is set in the HL register. 44, and the symbol management bit (here, "1111100B") described in the 41st line of FIG. For example, the symbol management bit "1111100B" transfers a significant value to the address corresponding to the position where the bit is set. Therefore, the symbol array data to be handled by the symbol management bit "1111100B" is 5 bytes. The command "EX DE, HL" on the 11th line in FIG. 43 switches the contents of the DE and HL registers, the DE register manages the transfer source address, and the HL register manages the transfer destination address. .

The command "XOR A" on the 13th line in FIG. 43 clears the A register, and the command "SRL C" on the 14th line shifts the value of the C register to the right by one bit. If the command "JR NC, GET_DAT02" on the 15th line is shifted by 1 bit and the carry is not set, that is, if the bit 0 before the shift is "0", the index "GET_DAT02" on the 18th line to jump If carry is set as a result of shifting by 1 bit, the value of the DE register (transfer source address) is incremented by 1 by the command "INC DE" on the 16th line. The command "LD A, (DE)" on the 17th line sets the value (symbol array data) stored in the memory area at the address indicated by the DE register to the A register. For example, when the winning area is "0", as a result of repeating the 1-bit shift of the symbol management bit "1111100B" shown in the 41st line of FIG. is set in the A register.

The command "LD (HL), A" on the 19th line in FIG. 43 sets the value of the A register (symbol array data) to the transfer destination address indicated by the HL register. The value of the HL register (transfer destination address) is incremented by one by the command "INC HL" on the 20th line. The command "DJNZ GET_DAT01" on the 21st line decrements the value of the B register by 1, jumps to the index "GET_DAT01" on the 12th line until the value of the B register becomes 0, and continues until the value of the B register becomes 0. Then move on to the next command. That is, the processing from the 12th line to the 21st line is repeated seven times. Then, the command "RET" on the 22nd line returns to the calling process.

As described above, here, the winning area value (0 to 36) is set in the A register as an argument, and the symbol array data is transferred to the stop control RWM by executing the symbol code initial setting process S230-7. be able to. Specifically, as shown in the 2nd to 38th rows of FIG. 44, the main CPU 200a uses the same number of symbol bit offset tables as the winning areas 0 to 36 to set the values (0 to 36) of the winning areas. A corresponding offset value to the pattern array data group is extracted. Then, based on the extracted offset value, a plurality of symbol data groups (for example, 40th to 43rd rows, 45th to 48th rows, 50th rows) in which the symbol array data corresponding to the winning area are determined 53rd line), one group is specified, and pattern arrangement data is transferred based on the pattern management bit.

It should be noted that the data size of the pattern array data group may be common in a plurality of winning areas. For example, as can be understood with reference to FIG. 44, the data size of the pattern array data defined in the 45th to 48th lines corresponding to the winning area 1 described in the 3rd line, and the data size of the pattern array data defined in the 4th line It is equal to the data size of the pattern array data defined in the 50th to 53rd lines corresponding to the described winning area 2 .

Here, although not shown, combinations of the winning area 0, the winning areas 1 to 15, the winning areas 16 to 18, the winning areas 19 to 22, the winning areas 23 to 35, and the winning area 36 have a common data size. Therefore, it is possible to simplify the symbol bit offset table by grouping the winning areas having the same data size to form a data size group, and using the data size group instead of the winning areas 0 to 36, for example. .

The data size group assigns values of 0 to 5 to data sizes "5", "4", "2", "1", "2" and "3". Here, since the winning areas having the same data size are grouped together, if the data sizes of the consecutive winning areas are different, the data size group is also changed. Also, as described above, different data size groups may have the same data size (for example, "2").

Then, the process of acquiring the data size group based on the winning area is executed using the winning combination group setting process S230-5 necessary for converting the winning area into the winning combination group. More specifically, data size groups 0 to 5 are described using 3 bits that are not occupied (used) by the winning hand groups, instead of the difference number groups 0 to 4 described with reference to FIG. Then, by the winning combination group setting process S230-5, the data size group is extracted together with the winning combination group.

FIG. 45 is a program code showing another example of the winning combination group setting process S230-5. The index "GET_ARD:" on the first line in FIG. 45(a) indicates the start address of the winning combination group setting process. The command "LD HL, T_CMD_SET" on the second line sets the top address ("T_CMD_SET") of the data table for each area in the HL register. A command "RST CALADRS" on the third line calls a subroutine "CALADRS" for register addition processing. At this time, the value of the winning area obtained in step S230-1 is set in the A register. In such "CALADRS", the value of the HL register and the value of the A register are added, and the content of the address indicated by the added value (data size group x 32 + winning combination group) in the data table for each area ("T_CMD_SET") is A Set in a register. The lower 5 bits are masked by the command "AND 00011111B" on the fourth line, leaving only the winning hand group in the A register. Then, the command "RET" on the fifth line returns to the calling process.

In the area-specific data table (“T_CMD_SET”) of FIG. 45(b), in addition to the values of the winning combination group, the values of the data size group are associated with the winning areas. In addition, the order of description is arranged in serial numbers so that the values (0 to 36) of the winning areas are in ascending order. Therefore, the values of the data size group and the winning hand group can be specified by using the value of the winning area as the offset value to the address where the data is stored in the data table for each area. For example, if the winning area is "0", the subroutine "CALADRS" specifies the second line ("T_CMD_SET"+winning area "0") in FIG. A certain "0" and the value of the winning hand group "0" are set. If the winning area is "10", the subroutine "CALADRS" specifies the 12th line ("T_CMD_SET"+winning area "10") in FIG. A value of "1" and the value of the winning combination group of "4" are set.

Thus, using the winning combination group setting process S230-5 for acquiring the winning combination group based on the winning area, the data size group can also be acquired based on the winning area. Subsequently, using the acquired data size group, the pattern code setting process S230 is performed in a manner different from that shown in FIG.

FIG. 46 is program code showing another example of the symbol code initialization process S230-7, and FIG. 47 is program code showing another example of the symbol bit offset table. In the symbol bit offset table (T_JUG_OFS) of FIG. 47, data size groups are associated with offset values to symbol array data groups. The order of description is arranged in serial numbers from 0 to 5 so that the identification numbers that can specify the data size groups (hereinafter simply referred to as data size group values or data size groups) are in ascending order. there is Therefore, by using the value of the data group as the offset value to the address where the data is stored in the pattern bit offset table as it is, the address where the data indicating the offset value to the pattern array data group is specified. can do.

The command "LDQ A, (LOW_HIT_NUM)" on the first line in FIG. 46 sets the value of the Q register as the upper 1 byte of the address and the value of the lower 1 byte of the address "_HIT_NUM" as the lower 1 byte of the address. The value stored in the memory area indicated by , that is, the value of the winning area (stop control number) is set in the A register. The value of the A register is saved in the D register by the command "LD D, A" on the second line. The command "LD HL, T_CMD_SET" on the third line sets the top address ("T_CMD_SET") of the area-specific data table in the HL register. The command "RST CALADRS" on the 4th line calls the subroutine "CALADRS" that performs register addition processing, adds the value of the HL register and the value of the A register, and performs the addition in the area data table ("T_CMD_SET"). The content of the address indicated by the value is set in the A register. The command "AND 00011111B" on the fifth line masks the lower 5 bits, leaving only the winning hand group in the A register. 45 ( The value (data size group x 32 + winning combination group) stored in the memory area of the address b) and the value of the A register are derived by exclusive OR. In this way, the lower 5 bits are cleared to 0, leaving only the upper 3-bit difference number group (difference number group x 32). The command "SWP A" on the 7th line in FIG. 46 replaces the upper 4 bits and the lower 4 bits of the A register. Thus, only the doubled value of the data size group remains in the A register.

A command "LD HL, T_JUG_OFS-1" on the eighth line in FIG. 46 sets a value obtained by subtracting 1 from the head address ("T_JUG_OFS") of the symbol bit offset table in the HL register. The command "ADDWB HL, A" on the 9th line updates the value of the HL register by adding the value of the A register to the value of the HL register. By the command "INLD AE, (HL)" on the 10th line, the value stored in the memory area indicated by the address obtained by incrementing the value of the HL register by 1 (the data size of the pattern array data group for each winning area) is stored in the E register. , and the value stored in the memory area indicated by the address obtained by incrementing the value of the HL register by 1 (the offset value up to the pattern array data group) is set in the A register. Therefore, in the command "LD HL, T_JUG_OFS-1" on the eighth line, 1 is subtracted from the start address ("T_JUG_OFS") in advance. For example, if the winning area is "0", the data size group is "0", "5" corresponding to the second line in FIG. 47 is set in the E register, and "(T_JUG_DRW_1-$ )” is set in the A register. When the winning area is "10", the data size group is "1", "4" corresponding to the fifth line in FIG. 47 is set in the E register, and "(T_JUG_DRW_2-$ )-1*4” is set in the A register.

The command "ADDWB HL, A" on the 11th line in FIG. 46 updates the value of the HL register by adding the value of the A register to the value of the HL register. With the command "MUL D, E" on the 12th line, the value of the D register (value of the winning area saved in the second line) is multiplied by the value of the E register (offset value for each winning area) to update the DE register. do. By the command "ADD HL, DE" on the 13th line, the DE register is added to the value of the HL register updated on the 11th line, and the start address of the data size group to be the transfer source is set in the HL register. be. Here, the value of the D register, that is, the value of the winning area is used as it is for the multiplication, so the offset value becomes large. Therefore, for example, like "-1*4" on the 6th line in FIG. 47, the difference is subtracted in advance from the offset value up to the pattern array data group to achieve matching. Here, by calculating the difference in advance, it is possible to reduce the memory capacity and the processing load.

The command "LDQ DE, LOW _JUG_BIT" on the 14th line in FIG. 46 sets the value of the Q register to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_JUG_BIT" to the lower 1 byte of the address. The value stored in the memory area, that is, the address of the destination stop control RWM is set in the DE register. Then, the command "CALLF GET_DAT" on the 15th line calls the index "GET_DAT" on the 17th line as a subroutine.

The index "GET_DAT:" on the 17th line in FIG. 46 indicates the head address of the pattern code initial setting process. The loop count "7" is set in the B register by the command "LD B, 7" on the 18th line. The contents of the address indicated by the HL register are set in the C register by the command "LD C, (HL)" on the 19th line. For example, if the winning area is "0", the symbol management bit (here, "1111100B") shown in the HL register and described in the 21st line of FIG. The second command "EX DE, HL" switches the contents of the DE register and the HL register, the DE register manages the transfer source address, and the HL register manages the transfer destination address.

The command "XOR A" on the 22nd line in FIG. 46 clears the A register, and the command "SRL C" on the 23rd line shifts the value of the C register to the right by one bit. If the command "JR NC, GET_DAT02" on the 24th line is shifted by 1 bit and the carry is not set, that is, if the bit 0 before the shift is "0", the index "GET_DAT02" on the 27th line to jump If carry is set as a result of shifting by 1 bit, the value of the DE register (transfer source address) is incremented by 1 by the command "INC DE" on the 25th line. The command "LD A, (DE)" on the 26th line sets the value (symbol array data) stored in the memory area at the address indicated by the DE register to the A register.

The command "LD (HL), A" on the 28th line in FIG. 46 sets the value of the A register (symbol array data) to the transfer destination address indicated by the HL register. The value of the HL register (transfer destination address) is incremented by one by the command "INC HL" on the 29th line. The command "DJNZ GET_DAT01" on the 30th line decrements the value of the B register by 1, jumps to the index "GET_DAT01" on the 21st line until the value of the B register becomes 0, and continues until the value of the B register becomes 0. Then move on to the next command. That is, the processing from the 21st line to the 30th line is repeated seven times. Then, the command "RET" on the 31st line returns to the calling process.

Comparing the symbol code initial setting process S230-7 in FIG. 43 and the symbol bit offset table in FIG. 44 with the symbol code initial setting process S230-7 in FIG. 46 and the symbol bit offset table in FIG. 2, 3, 5-7, 10-13 lines command 14 bytes are added, but the memory capacity is reduced to the difference between the winning area 0-36 and the data size group 0-5, that is, 31 Bytes can be reduced. Therefore, in total, it is possible to reduce the memory capacity by 17 bytes.

In this way, here, on the premise that the winning combination group including the determined winning area is specified and the specified winning combination group is transmitted to the sub-control board 202, the process of specifying the winning combination group is used. to specify the data size group, and based on the data size group thus specified, the design arrangement data is specified from the design bit offset table. Also, in the data table for each area, the winning combination group and the data size group are combined and expressed as unit data (1 byte). With this configuration, it is possible to appropriately specify the pattern array data while suppressing the increase in new programs and processing load. In addition, instead of the winning area, the data size groups 0 to 5, which are smaller in number than the winning areas 0 to 36, are used as offset values to extract the pattern array data. It is possible to reduce it significantly.

(Other grouping examples of winning areas)
Hereinafter, another example of generating new parameters by using the winning combination group setting process S230-5 and grouping other than the winning combination group, the difference number group, and the data size group will be described.

In the winning combination group setting process S230-5 described with reference to FIG. 36, a winning combination group is generated based on the winning area. The winning combination group is obtained by grouping a plurality of winning combination types having the same winning combination type (replay combination, minor combination, bonus combination), etc., and the generated winning combination group is transmitted to the sub control board 202.例文帳に追加

In addition to such winning areas and winning combination groups, there are cases where processing efficiency and memory capacity reduction can be realized by grouping at the time of predetermined determination. For example, in the present embodiment, in FIG. 6, for the group of the winning type "batting order bell" of the winning areas 4 to 15 and the winning type "common bell" of the winning area 19, the transition to the AT effect state or An arbitrary lottery such as a lottery for continuation (for example, a lottery is executed according to the accumulated amount of points) is performed. In this case, when judging whether or not to perform an arbitrary lottery, it is necessary to judge whether or not the winning area is one of the 13 winning areas 4 to 15 and 19 . 4 to 15 and 19, which are the numbers of the winning areas 4 to 15 and 19, do not have commonality that excludes other numbers. It is necessary to perform a process of extracting one by one and repeatedly comparing with the elected winning areas, and performing a lottery if any of them are equal, and not performing a lottery if they are not equal.

As for the winning areas 4 to 15, the winning combination group is equal to "4", so if the winning combination group is used, the processing load will be reduced. Ultimately, it is necessary to determine whether the winning combination group is one of the winning combination groups 4 and 6, and the processing is still complicated due to the comparison processing performed multiple times.

Similarly, in the present embodiment, on the condition that the group of the winning type "replay 2" of the winning area 33 and the winning type "replay 3" of the winning area 34 in FIG. A player may be prompted to perform a predetermined operation (for example, an operation aimed at stopping a predetermined symbol combination). In this case, when determining whether or not the condition is satisfied, it is necessary to determine whether or not the selected winning area is one of the winning areas 33 and 34 . In the winning areas 33 and 34, the winning combination groups are also different from 20 and 21, respectively. Therefore, even if the winning combination group is adopted for the determination, the winning combination group will not win when it is determined whether or not the conditions are satisfied. It is necessary to determine whether or not it belongs to either of the hand groups 20 and 21, and the processing is still complicated due to the comparison processing repeated multiple times.

Similarly, in the present embodiment, on the condition that the group of the winning type "heart fanning lip 1" in the winning area 30 and the winning type "heart fanning lip 2" in the winning area 31 shown in FIG. Commonly, the player may be prompted to perform a predetermined operation (for example, an operation aiming to stop a predetermined symbol combination). In this case, when determining whether or not the condition is satisfied, it is necessary to determine whether or not the selected winning area is one of the winning areas 30 and 31 . In the winning areas 30 and 31, the winning combination groups are also different from 17 and 18, respectively. Therefore, even if the winning combination group is adopted for the determination, the winning combination group will be the winning combination when it is determined whether or not the conditions are satisfied. It is necessary to determine whether it belongs to either of the hand groups 17 and 18, and the process is still complicated due to the comparison processing performed multiple times.

Similarly, in the present embodiment, the winning type of the winning area 20 in FIG. Winning type of area 25 "middle stage watermelon", winning type of winning area 26 "upper watermelon chanlip", winning type of winning area 27 "middle stage watermelon chanlip", winning type of winning area 28 "heart fanning chanlip 1", winning area 29 If you win a group that corresponds to a so-called strong rare role, such as the winning type "Heart Stirring Chan Lip 2", the winning type "Heart Stirring Lip 1" in the winning area 30, and the winning type "Heart Stirring Lip 2" in the winning area 31, In common, an arbitrary lottery such as a lottery for transition to or continuation of the AT effect state is performed. In this case, when judging whether or not to perform an arbitrary lottery, it is necessary to judge whether the winning area is one of the winning areas 20-22 or 25-31. Since the winning combination groups 7 to 9 and 12 to 18 are included in the winning areas 20 to 22 and 25 to 31, respectively, even if the winning combination group is adopted for determination, it is determined whether or not an arbitrary lottery is performed. Sometimes, it is necessary to determine whether the winning combination group is one of the winning combination groups 7 to 9 and 12 to 18, and the process becomes complicated due to the multiple comparison processes. do not have.

Therefore, these winning areas are grouped separately. For example, the winning type "batting order bell" of the winning areas 4 to 15 and the winning type "common bell" of the winning area 19 are grouped into a bell group and given a specific identification number. Similarly, the winning type "replay 2" of the winning area 33 and the winning type "replay 3" of the winning area 34 are grouped into a bar-aligned group and given a specific identification number. Also, the winning type ``heart fanning Lip 1'' in the winning region 30 and the winning type ``heart fanning Lip 2'' in the winning region 31 are grouped into a heart aligned group and given a specific identification number. In addition, the winning type of the winning area 20 "strong bell 1", the winning type of the winning area 21 "strong bell 2", the winning type of the winning area 22 "chance eye", the winning type of the winning area 25 "middle row watermelon", the winning area 26 winning type "upper watermelon chanlip", winning type 27 "middle watermelon chanlip", winning type 28 "heart fanning chanlip 1", winning type 29 "heart fanning chanlip 2", winning region The 30 winning types "Heart stirring Lip 1" and the winning type "Heart stirring Lip 2" in the winning area 31 are grouped to form a strong rare group and given a specific identification number.

Here, the bell group, the bar-aligned group, the heart-aligned group, and the strong rare group (hereinafter referred to as the bell group, the bar-aligned group, the heart-aligned group, and the strong rare group are collectively used as information for determining the transition of the production state, (sometimes abbreviated as effect determination group) can be assigned to numerical values in ascending order. For example, bell group = "0", bar group = "1", heart group = "2", strong rare group = "3", and so on. By doing so, all effect determination groups can be represented by 2 bits.

However, for example, the winning type ``heart fanning Lip 1'' in the winning area 30 and the winning type ``heart fanning Lip 2'' in the winning area 31 are included in both the heart-aligned group and the strong rare group. Therefore, if the numbers are assigned in ascending order as described above, even if the winning area 30 or 31 is won, it can only be specified that the winning area is included in one of the effect determination groups. Therefore, in the present embodiment, bits that can be specified independently from others are assigned to the effect determination groups (bell group, bar group, heart group, strong rare group). Therefore, 4 bits are required to express 4 effect determination groups.

Here, similarly to the difference number group and the data size group described above, the allocation of the effect determination group described above to the area-by-area data table will be considered. By doing so, it is possible to execute the process of acquiring the effect determination group based on the winning area by using the winning combination group setting process S230-5 necessary for converting the winning area into the winning combination group. becomes.

By the way, since both the difference number group and the data size group require only 3 bits, they could be allocated to the remaining 3 bits of the winning combination group represented by 5 bits, but the effect judgment group requires 4 bits. , the remaining 3 bits of the winning hand group represented by 5 bits. Therefore, of the 8 bits allowed in the data table for each area, 4 bits are occupied by the effect determination group, and the remaining 4 bits are used for the winning hand group to specify by other means.

FIG. 48 is an explanatory diagram for explaining the winning type lottery table, and FIG. 49 is a program code showing another example of the winning combination group setting process S230-5. Specifically, for the effect determination group, for example, the bell group=bit 7, the bar group=bit 6, the heart group=bit 5, and the strong rare group=bit 4 are assigned to the upper 4 bits. In this way, each effect determination group can be determined using 1-bit information.

Also, for the winning combination group, the winning combination group is identified by including the upper 4 bits in addition to the lower 4 bits. For example, "0" is assigned to the lower 4 bits in common to the winning areas 0, 4 to 15, 20, and 30. Here, "0000B" is assigned to the upper 4 bits of the winning area 0, "1000B" is assigned to the upper 4 bits of the winning areas 4 to 15, and "0001B" is assigned to the upper 4 bits of the winning area 20. Since "0011B" is assigned to the upper 4 bits of the winning area 30, the winning area 0, the winning areas 4 to 15, the winning area 20, the winning area 30, and other winning areas are set as a winning combination group. It is possible to distinguish

In addition, "1" is assigned to the lower 4 bits in common to the winning areas 1, 19, 21, 31, and 33. Here, "0000B" is assigned to the upper 4 bits of the winning area 1, "1000B" is assigned to the upper 4 bits of the winning area 19, and "0001B" is assigned to the upper 4 bits of the winning area 21. "0011B" is assigned to the upper 4 bits of 31, and "0100B" is assigned to the upper 4 bits of the winning area 33. , the winning area 33 and other winning areas can be distinguished as a winning combination group.

In addition, "2" is assigned to the lower 4 bits in common to the winning areas 2, 22, and 34. Here, "0000B" is assigned to the upper 4 bits of the winning area 2, "0001B" is assigned to the upper 4 bits of the winning area 22, and "0100B" is assigned to the upper 4 bits of the winning area 34. , the winning area 2, the winning area 22, the winning area 34, and other winning areas can be distinguished as a winning combination group.

Also, "3" is assigned to the lower 4 bits in common to the winning areas 3 and 25. FIG. Here, since "0000B" is assigned to the upper 4 bits of the winning area 3 and "0001B" is assigned to the upper 4 bits of the winning area 2, the winning area 3, the winning area 25, and other winning areas can be distinguished as a winning combination group.

Also, "4" is assigned to the lower 4 bits in common to the winning areas 16 to 18 and 26. FIG. Here, since "0000B" is assigned to the upper 4 bits of the winning areas 16 to 18 and "0001B" is assigned to the upper 4 bits of the winning area 26, the winning areas 16 to 18, the winning area 26, It is possible to distinguish other winning areas as a winning combination group.

Also, "5" is assigned to the lower 4 bits in common to the winning areas 23 and 27 . Here, since "0000B" is assigned to the upper 4 bits of the winning area 23 and "0001B" is assigned to the upper 4 bits of the winning area 27, the winning area 23, the winning area 27, and other winning areas can be distinguished as a winning combination group.

In this embodiment, there are 23 winning hand groups, but since up to 16 groups can be identified with only the lower 4 bits, some of the winning hand groups are uniquely identified in the lower 4 bits with respect to the winning area. Assign an identifiable number. For example, 6, 7, 8, 9, 10 and 11 represented by the lower four bits are assigned to the winning areas 24, 28, 29, 32, 35 and 36, respectively. In this way, the winning area 24, the winning area 28, the winning area 29, the winning area 32, the winning area 35, and the winning area 36 can be distinguished as a winning combination group by at least the lower 4 bits. .

Here, the value of the winning combination group is determined by the following procedure. First, the same numerical value, for example, "0", is assigned to winning combination groups that can be identified by the upper 4 bits determined by the effect determination group. By repeating this up to a predetermined value (here, "5"), the lower 4 bits can be shared. Then, when the number of remaining winning combination groups becomes equal to or less than the number that can be identified by the lower 4 bits, the winning area is identified by the lower 4 bits only.

When such an identifier is reflected in the data table for each area, it becomes as shown in FIG. 49, and instead of the difference number group and the data size group, the effect determination group can be assigned to the data table for each area. By doing so, it is possible to execute the process of acquiring the effect determination group based on the winning area by using the winning combination group setting process S230-5 necessary for converting the winning area into the winning combination group. becomes.

In this case, while identifying the effect determination group by the upper 4 bits, the winning combination group can be identified by including the upper 4 bits in addition to the lower 4 bits, so that the memory can be effectively used. As a result, the memory capacity can be reduced.

Here, a part of the plurality of winning areas 0 to 36, for example, a plurality of effect determination groups (first group information) obtained by grouping the winning areas 4 to 15 and 19, and a plurality of winning areas 0 to 36 , for example, among a plurality of specific identifiers (second group information) grouping the winning regions 4 to 15, an entity that specifies the effect determination group and the specific identifier that includes the determined winning region (main CPU 200a function) as the group identification part. Also, based on the effect determination group, the main body that executes the process (first process) for determining whether or not the lottery related to transition to or continuation to the AT effect state is performed is defined as the first process execution unit. Further, a second process is executed for determining whether or not the player is subject to a lottery regarding transition to or continuation of the AT effect state based on the combination of the effect determination group and the identifier, that is, the winning hand group. part. Also, here, the effect determination group and the specific identifier are arranged exclusively within one byte (unit data).

In this way, here, on the premise that the winning combination group including the determined winning area is specified and the specified winning combination group is transmitted to the sub-control board 202, the process of specifying the winning combination group is used. Then, the determination process is executed based on whether the specified effect determination group, that is, the predetermined bit is 1 or 0. With such a configuration, it is possible to appropriately execute the determination process while suppressing new programs and an increase in processing load. In addition, since the specific identifier cannot identify all the winning combination groups, the combination of the specific identifier and the effect determination group distinguishes the winning combination group. It becomes possible to express with data (1 byte).

In addition, for each of the production judgment groups (bell group, bar group, heart group, strong rare group), the information that the winning area is the winning area that is the target of the production judgment and the target winning area information that is not grouped into any. For example, in the bell group, winning areas 4 to 15 and 19 are associated with bits "1" indicating that they are bell groups, and other winning areas are associated with "0" indicating that they are not bell groups. there is

Also, here, as can be understood with reference to FIG. 48, it is sufficient that the winning combination group in which the performance determination group and the specific identifier are combined has a numerical value exclusive to the other winning combination groups, and serial numbers are used. don't need to be Further, the specific identifier is sufficient if it can be distinguished from others by combining with the effect determination group, and the number of bits is not limited to 4 bits, and may be any of 1 to 7 bits.

Although the preferred embodiments of the present invention have been described above with reference to the accompanying drawings, it goes without saying that the present invention is not limited to such embodiments. It is obvious that a person skilled in the art can conceive of various modifications or modifications within the scope of the claims, and it should be understood that these also belong to the technical scope of the present invention. be done.

For example, in the above-described embodiment, a winning combination group is given as a plurality of group information obtained by grouping a part of a plurality of winning areas, and a plurality of first group information obtained by grouping a part of a plurality of winning areas are produced. The judgment group (bell group, bar matching group, heart matching group, strong rare group) was given and explained. However, the group information or the first group information may include any of the winning hand group, the number difference group, the data size group, and the effect determination group (bell group, bar group, heart group, strong rare group). may be adopted.

In the above-described embodiment, a specific identifier is used as a plurality of second group information obtained by grouping a part of a plurality of winning areas, and the combination of the first group information and the second group information, that is, the winning combination group However, it suffices if the specific identifier can be distinguished from others by combining it with the first group information. In addition to the groups, any of the winning combination group, the difference number group, the data size group, and the performance determination group (bell group, bar alignment group, heart alignment group, strong rare group) may be adopted.

Further, in the above-described embodiment, as the first process and the second process, the process of determining whether or not a lottery related to transition to or continuation to the AT effect state is targeted has been described. As processing and second processing, transition to any of a plurality of processing based on first group information or second group information, or extract predetermined information from a table based on first group information or second group information. , the first group information and the second group information are subject to calculation, and the first group information and the second group information are displayed on a predetermined display unit. can be applied.

Further, in the above-described embodiment, the main control board 200 and the sub control board 202 are arranged so as to share the function part for progressing the game, but the function part of the main control board 200 is transferred to the sub control board 202. Alternatively, the functional units of the sub-control board 202 may be arranged on the main control board 200, or all the functional units may be collectively arranged on one control board.

Further, in the above-described embodiment, the game is played using medals as game value, but the game value may be electrical information (so-called medalless). In this case, when the winning combination wins, the amount of value corresponding to the winning combination may be given to the player as electrical information.

Further, each process performed by the main control board 200 and the sub control board 202 described above does not necessarily have to be processed in time series according to the order described as the flowchart, and may include parallel or subroutine processing.

100 slot machine (gaming machine)
110 reel 116 bet switch 118 start switch 120 stop switch 124 liquid crystal display section 132 main payout display section 304 winning type lottery means 306 reel control means 314 effect state control means 334 effect control means

Claims (1)

winning type lottery means for determining by lottery one of the winning regions corresponding to each of a plurality of winning types;
The determined winning area is included among a plurality of first group information obtained by grouping a part of the plurality of winning areas and a plurality of second group information obtained by grouping a part of the plurality of winning areas. a group identification unit that identifies the first group information and the second group information,
a first process execution unit that executes a first process based on the first group information;
a second process execution unit that executes a second process based on a combination of the first group information and the second group information;
A game machine with

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