JP2022118464A - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Abstract

To provide an SiC semiconductor device that suppresses lateral expansion of an impurity layer formed by ion implantation.SOLUTION: A defect introduced portion 21 is formed when an electric field blocking layer 4 is formed in a JFET portion 3 by ion implantation, such that a p-type impurity in a p-type ion implanted portion 20 is trapped in a defect during the activation annealing. As a result, the finally formed electric field blocking layer 4 can be configured with a substantially constant width.SELECTED DRAWING: Figure 1

Description

The present invention relates to a SiC semiconductor device having a semiconductor element made of silicon carbide (hereinafter referred to as SiC) and a method for manufacturing the same.

Conventionally, when a semiconductor device is formed, an impurity layer of a desired conductivity type is formed in a silicon substrate by implanting ions into the underlying silicon substrate. It is desired to form an impurity layer without spreading to the inside. As a method of forming an impurity layer while suppressing such lateral expansion, there is an ion implantation method disclosed in Patent Document 1, for example. In this ion implantation method, a mask having openings is placed on a silicon substrate, and ions are implanted through the mask under desired conditions to form an impurity doping region. Specifically, the silicon substrate is cooled to an extremely low temperature, and an ion beam is vertically implanted so that most of the ions are channeled. This causes the ions to be introduced into the crystal in a directionally oriented manner with the motion forced to fix the direction of travel in the main crystallographic axis channel in the low-index plane orientation. Therefore, it is possible to form an impurity doping region without going around the region under the mask during ion implantation.

JP-A-6-252082

In recent years, researches on semiconductor devices using SiC are progressing. Since SiC is harder than silicon, ion implantation with high energy is required. At present, there are facilities capable of accelerating to 5 MeV, for example, implanting to a depth of ~8 μm when aluminum (Al) is used as a dopant. However, ions repeatedly collide with interstitial Si or C during implantation, which causes the problem that the dopant spreads laterally as the depth increases. In the case of SiC, since step-flow growth is performed, an off-substrate having an off-angle is used for crystal growth, so the main surface of the grown SiC also has an off-angle. Therefore, even if the ion implantation is performed perpendicularly to the main surface of SiC, the ions repeatedly collide with Si or C between the lattices during the implantation. If the dopant spreads laterally, the formation range of the impurity layer formed by ion implantation will not be within the desired range, which will affect the semiconductor characteristics.

For example, in the case of a superjunction (hereinafter referred to as SJ) structure, the width of the lower portion of the n-type pillar, which serves as a channel for carriers, is narrowed due to the lateral expansion of the lower portion of the p-pillar formed by ion implantation.

Also, in order to maintain a low saturation current while achieving a low on-resistance, there is a structure in which JFET portions and electric field blocking layers of different conductivity types are alternately arranged in stripes to form a saturation current suppressing layer. In the case of this structure, when ions are implanted into the p-type epitaxial layer below the device structure such as the trench gate to form the n-type impurity layers at regular intervals, the lower portion of the n-type impurity layer is laterally displaced. It spreads and forms. As a result, the depletion layer extending from the p-type epitaxial layer toward the n-type impurity layer does not stretch enough to pinch off, resulting in an increase in saturation current.

SUMMARY OF THE INVENTION In view of the above points, it is an object of the present invention to provide a SiC semiconductor device and a method of manufacturing the same that suppress lateral expansion of an impurity layer formed by ion implantation.

In order to achieve the above object, the invention according to claim 1 is a SiC semiconductor device comprising a SiC substrate (1) and an epitaxially grown film formed on the SiC substrate, and having a first conductivity type and a a first impurity layer (3) of one of the second conductivity type; and a configured second impurity layer (4). The second impurity layer has the first conductivity type and the second conductivity type contained in the second impurity layer on both sides in the width direction perpendicular to the thickness direction of the SiC substrate. The impurity concentration of the other region of the mold is higher than that of other regions of the second impurity layer, and the width of the second impurity layer is set to a predetermined width.

In this way, the structure is such that the impurity concentration is higher on both sides in the width direction of the second impurity layer than in other regions of the second impurity layer. In other words, when the second impurity layer is formed by ion implantation into the first impurity layer, the defect introduced portion (21) is formed, and the impurities in the ion-implanted portion are trapped in the defects during the activation annealing. A second impurity layer is formed as follows. As a result, the finally formed second impurity layer can be formed with a predetermined width, for example, a substantially constant width.

According to a seventh aspect of the invention, there is provided a method for manufacturing a SiC semiconductor device, comprising: preparing a SiC substrate (1); forming a first impurity layer (3) composed of a first impurity layer (3); and a second impurity layer (4) composed of the other of the first conductivity type and the second conductivity type at a desired position of the first impurity layer by ion implantation. forming a Then, in forming the second impurity layer, the defect-introduced portion in which defects are formed on both sides in the width direction of the region to be formed of the second impurity layer, with the direction perpendicular to the thickness direction of the SiC substrate being the width direction. (21) is formed, an impurity ion implantation portion (20) is formed by implanting impurity ions into a region where the second impurity layer is to be formed, and activation annealing of the impurity is performed by heat treatment. and forming a second impurity layer having a predetermined width by trapping impurities in the defect in the region where the defect introduced portion is formed.

In this manner, defect introduction portions are formed on both sides in the width direction of the region where the second impurity layer is to be formed. Therefore, impurities in the ion-implanted portion can be trapped in the defect during activation annealing. As a result, lateral expansion of the second impurity layer can be suppressed, and the second impurity layer can be formed with a predetermined width, for example, a substantially constant width.

It should be noted that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and specific components etc. described in the embodiments described later.

It is a figure which shows the cross-sectional structure of the SiC semiconductor device concerning 1st Embodiment. FIG. 2 is a perspective cross-sectional view showing a part of the SiC semiconductor device shown in FIG. 1; 4 is an enlarged cross-sectional view of the saturation current suppression layer on a plane parallel to the XZ plane passing through the electric field blocking layer; FIG. 3 is a perspective cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG. 2; FIG. 4B is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device continued from FIG. 4A; FIG. 4C is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 4B; FIG. 4D is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 4C; FIG. 4D is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 4D; FIG. 4F is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 4E; FIG. 4F is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 4F; FIG. 4B is a cross-sectional view showing details of the process shown in FIG. 4B; FIG. FIG. 5B is a cross-sectional view showing a step following FIG. 5A; FIG. 5C is a cross-sectional view showing a step following FIG. 5B; FIG. 10 is a diagram showing a simulation result of lateral expansion when Al ions are implanted at an acceleration energy of 500 eV without forming a defect-introduced portion; FIG. 10 is a diagram showing a simulation result of lateral expansion when Al ions are implanted at an acceleration energy of 1000 eV without forming a defect-introduced portion; FIG. 10 is a diagram showing a simulation result of lateral expansion when Al ions are implanted at an acceleration energy of 2000 eV without forming a defect-introduced portion; FIG. 10 is a diagram showing a simulation result of lateral expansion when Al ions are implanted at an acceleration energy of 3000 eV without forming a defect-introduced portion; FIG. 4 is a diagram showing changes in p-type impurity concentration after ion implantation and after activation annealing. It is a perspective sectional view showing a part of the SiC semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view showing a step of forming an electric field blocking layer described in the third embodiment; FIG. 9B is a cross-sectional view showing a step of forming an electric field blocking layer subsequent to FIG. 9A; FIG. 9B is a cross-sectional view showing the step of forming an electric field blocking layer following FIG. 9B; FIG. 9B is a cross-sectional view showing a step of forming an electric field blocking layer subsequent to FIG. 9A;

An embodiment of the present invention will be described below with reference to the drawings. In addition, in each of the following embodiments, portions that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment will be described. In the SiC semiconductor device according to the present embodiment, an inverted vertical MOSFET having a trench gate structure having a saturation current suppressing layer shown in FIGS. 1 and 2 is formed as a semiconductor element. The vertical MOSFETs shown in these figures are formed in the cell region of the SiC semiconductor device, and the SiC semiconductor device is configured by forming the peripheral breakdown voltage structure so as to surround the cell region. Only vertical MOSFETs are shown here. 1 and 2, the depth direction of the vertical MOSFET is the X direction, the width direction of the vertical MOSFET crossing the X direction is the Y direction, and the thickness direction or depth direction of the vertical MOSFET is The horizontal direction, that is, the direction normal to the XY plane will be described as the Z direction.

A vertical MOSFET is formed as a semiconductor element in the cell portion. FIG. 2 is a perspective cross-sectional view showing a cut-out part of the cell portion, but the configuration of the SiC semiconductor device is partially omitted in order to make the layout of each portion easier to see.

As shown in FIGS. 1 and 2, an SiC semiconductor device uses an n ⁺ -type substrate 1 made of SiC as a semiconductor substrate. The n ⁺ -type substrate 1 is, for example, 4H—SiC, and has a principal surface with a predetermined tilt angle with respect to the (0001) plane. An off-substrate with a

An n ⁻ -type layer 2 forming part of the drift layer is formed on the main surface of the n ⁺ -type substrate 1 . The n ⁺ -type substrate 1 has, for example, an n-type impurity concentration of 5.9×10 ¹⁸ /cm ³ and a thickness of 100 μm. The n ⁻ -type layer 2 is composed of an epitaxially grown SiC film with an impurity concentration lower than that of the n ⁺ -type substrate 1 . The n ⁻ -type layer 2 has, for example, an n-type impurity concentration of 7.0×10 ¹⁵ to 1.0×10 ¹⁶ /cm ³ and a thickness of 8.0 μm.

An n-type JFET portion 3 and a p-type electric field blocking layer 4 forming part of a drift layer made of SiC are formed on the n ⁻ -type layer 2. The n ⁻ -type layer 2 is an n ⁺ It is connected to the JFET portion 3 at a position away from the mold substrate 1 .

The JFET portion 3 and the electric field blocking layer 4 constitute a saturation current suppression layer, both extend in the X direction, and are alternately and repeatedly arranged in the Y direction. That is, when viewed from the direction normal to the main surface of n ⁺ -type substrate 1, at least a portion of JFET portion 3 and electric field blocking layer 4 are each formed in a plurality of strips, in other words, in a striped shape. It is considered to be a layout arranged side by side.

In this embodiment, the JFET portion 3 is formed below the electric field blocking layer 4 . For this reason, the striped portions of the JFET portion 3 are connected under the electric field blocking layer 4 , but each striped portion is located between the plurality of electric field blocking layers 4 . It is placed.

Each striped portion of the JFET portion 3, that is, each strip-shaped portion, has a width of, for example, 0.1 to 0.6 μm, preferably a narrower width of 0.1 μm. For example, it is set to 0.6 to 2.0 μm. The JFET portion 3 has a thickness of 1.5 μm, for example, and an n-type impurity concentration higher than that of the n ⁻ -type layer 2, for example, 5.0×10 ¹⁷ to 2.0×10 ¹⁸ . / cm ³ . In this embodiment, the JFET portion 3 has a constant n-type impurity concentration in the depth direction.

The electric field blocking layer 4 is composed of a p-type impurity layer. As described above, the electric field blocking layer 4 is striped, and each strip-shaped portion of the striped electric field blocking layer 4 has a width of, for example, 0.15 to 1.4 μm and a thickness of, for example, 1 μm. 0.4 μm. The electric field blocking layer 4 has a P-type impurity concentration of, for example, 3.0×10 ¹⁷ to 1.0×10 ¹⁸ /cm ³ . In the case of this embodiment, the electric field blocking layer 4 has a constant p-type impurity concentration in the depth direction. The electric field blocking layer 4 is composed of an ion-implanted layer formed by ion-implanting p-type impurities into the JFET portion 3, as will be described later. Further, as shown in FIG. 5A and the like, the electric field blocking layer 4 is formed with a defect introduced portion 21 in which a defect for suppressing lateral spread is introduced in addition to the p-type impurity. . For this reason, the electric field blocking layer 4 has a substantially constant width in the depth direction, and the lower portion, that is, the skirt portion on the n ⁻ -type layer 2 side has substantially the same width as the upper portion. However, in the defect-introduced portion 21, the defects are recovered by the activation heat treatment of the p-type ions implanted for the formation of the electric field blocking layer 4, and the SiC semiconductor device is in a state in which no or almost no defects remain. It is in a state where it is not The surface of the electric field blocking layer 4 opposite to the n ⁻ -type layer 2 is flush with the surface of the JFET portion 3 .

More specifically, the saturation current suppression layer has a cross-sectional shape as shown in FIG. It has a structure of Each electric field blocking layer 4 is composed of an activated region that is activated after ion implantation of p-type impurities. It is formed by activating impurities. At this time, activation annealing is performed in a state in which the defect-introduced portion 21 shown in FIG. 5A is formed in addition to the p-type ion-implanted portion 20, so that the activated region has a substantially constant width. The reason why such effects are obtained will be described later.

Furthermore, on the JFET portion 3 and the electric field blocking layer 4, an n-type current spreading layer 6 forming part of the drift layer made of SiC is formed. The n ^- type current spreading layer 6 is a layer that allows the current flowing through the channel to diffuse in the Y direction, as will be described later. In this embodiment, the n-type current spreading layer 6 has an n-type impurity concentration equal to or higher than that of the JFET section 3 and a thickness of 0.5 μm.

In this embodiment, the n ⁻ -type layer 2, the JFET portion 3, and the n ^- type current spreading layer 6 constitute the drift layer, but the configuration of the drift layer is arbitrary. and the n ⁺ -type substrate 1 may be provided with a buffer layer.

A p-type base region 7 made of SiC is formed on the n-type current spreading layer 6 . An n ⁺ -type source region 8 made of SiC is formed on the p-type base region 7 . The n ⁺ -type source region 8 is formed on a portion of the p-type base region 7 corresponding to the n-type current spreading layer 6 .

The p-type base region ⁷ is thinner than the electric field blocking layer ⁴ and has a lower p-type impurity concentration. 3 μm. The n ⁺ -type source region 8 has a higher n-type impurity concentration than the n-type current spreading layer 6, and has a thickness of 0.5 μm, for example.

A plurality of p-type coupling layers 9 are formed from the surface of n ⁺ -type source region 8 through p-type base region 7 and n-type current spreading layer 6 to reach electric field blocking layer 4 . In the present embodiment, the p-type coupling layer 9 has a strip-like shape whose longitudinal direction is the direction intersecting the longitudinal direction of the striped portion of the JFET portion 3 and the electric field blocking layer 4, here the Y direction. , are laid out in a stripe shape by arranging a plurality of them in the X direction. Through this p-type coupling layer 9, the p-type base region 7 and the electric field blocking layer 4 are electrically connected. In this embodiment, a deep trench 9a is formed from the surface of the n ⁺ -type source region 8 through the p-type base region 7 and the n-type current spreading layer 6 to reach the electric field blocking layer 4. A p-type coupling layer 9 is formed so as to be embedded. The formation pitch of the p-type coupling layer 9 is set independently of the cell pitch, which is the formation interval of the trench gate structure, which will be described later. Therefore, it is set so that it can be suppressed. In the case of this embodiment, the distance between each p-type coupling layer 9 is, for example, 30 to 100 μm, and the width of each p-type coupling layer 9 is, for example, 0.4 to 1.0 μm.

Furthermore, the p-type base region 7 and the n ⁺ -type source region 7 have a width of, for example, 0.4 μm and a depth of 0.4 μm so as to reach the n-type current spreading layer 6 through the p-type base region 7 and the n ⁺ -type source region 8 . A gate trench 10 is formed which is 0.2 to 0.4 μm deeper than the total film thickness of . The p-type base region 7 and the n ⁺ -type source region 8 are arranged so as to be in contact with the side surfaces of the gate trench 10 . The gate trench 10 has a strip-shaped layout in which the width direction is the Y direction in FIG. formed. As shown in FIGS. 1 and 2, the gate trenches 10 are formed in a striped shape in which a plurality of gate trenches 10 are arranged at regular intervals in the Y direction, with the p-type base region 7 and the n ⁺ -type gate trench 10 interposed therebetween. A source region 8 is arranged.

For example, as will be described later, the cell pitch, which is the interval between trench gate structures formed in the gate trenches 10, that is, the cell pitch, which is the interval between adjacent gate trenches 10, is 0.6 to 2.0 μm. Although the width of the gate trench 10 is arbitrary, it is smaller than the cell pitch. In addition, the JFET pitch, which is the arrangement interval of the JFET portions 3, in other words, the arrangement interval of the electric field blocking layers 4, can be set independently of the cell pitch, and the JFET portions 3 are pinched off as described later. It is sufficient if it is set under the condition that In this embodiment, the cell pitch and the JFET pitch are different as shown in FIGS. 1 and 2, but they may be equal.

The portion of the p-type base region 7 located on the side surface of the gate trench 10 is used as a channel region connecting between the n ⁺ -type source region 8 and the n-type current spreading layer 6 during operation of the vertical MOSFET. An inner wall surface of gate trench 10 is covered with a gate insulating film 11 . A gate electrode 12 made of doped Poly-Si is formed on the surface of the gate insulating film 11, and the inside of the gate trench 10 is filled with the gate insulating film 11 and the gate electrode 12 to form a trench gate structure. It is

Further, as shown in FIG. 1, a source electrode 14 and the like are formed on the surface of the n ⁺ -type source region 8 and the surface of the gate electrode 12 with an interlayer insulating film 13 interposed therebetween. The source electrode 14 is composed of a plurality of metals such as Ni/Al. Of the plurality of metals, at least the n-type SiC, specifically, the portion in contact with the n ⁺ -type source region 8 and the gate electrode 12 in the case of n-type doping is composed of a metal capable of ohmic contact with the n-type SiC. there is In addition, at least the p-type SiC among the plurality of metals, specifically, the portion in contact with the p-type coupling layer 9 is made of a metal capable of making ohmic contact with the p-type SiC. Although the source electrode 14 is electrically insulated from the SiC portion by being formed on the interlayer insulating film 13, the contact holes formed in the interlayer insulating film 13 allow the n ⁺ -type source region 8 and the p + -type source region 8 to pass through. It is in electrical contact with the mold coupling layer 9 .

On the other hand, a drain electrode 15 electrically connected to the n ⁺ -type substrate 1 is formed on the back side of the n ⁺ -type substrate 1 . With such a structure, a vertical MOSFET having an n-channel type inverted trench gate structure is formed. A cell portion is configured by arranging a plurality of cells of such vertical MOSFETs.

In a SiC semiconductor device having a vertical MOSFET configured in this manner, for example, a gate voltage Vg of 20 V is applied to the gate electrode 12 with a source voltage Vs of 0 V and a drain voltage Vd of 1 to 1.5 V. It is operated by applying voltage. That is, when the gate voltage Vg is applied, the vertical MOSFET performs an operation in which a channel region is formed in the p-type base region 7 in contact with the gate trench 10 and current flows between the drain and source.

At this time, the JFET portion 3 and the electric field blocking layer 4 function as a saturation current suppressing layer, and by exhibiting a saturation current suppressing effect, it is possible to maintain a low saturation current while achieving a low on-resistance. Specifically, since the striped portion of the JFET portion 3 and the electric field blocking layer 4 are alternately and repeatedly formed, the following operation is performed.

First, when the drain voltage Vd is a voltage applied during normal operation, such as 1 to 1.5 V, the depletion layer extending from the electric field blocking layer 4 side to the JFET portion 3 is formed in a stripe shape in the JFET portion 3. It stretches only to a width smaller than the width of the part that has been made. Therefore, even if the depletion layer extends into the JFET portion 3, a current path is secured. Further, since the n-type impurity concentration of the JFET portion 3 is higher than that of the n ⁻ -type layer 2 and the current path can be configured to have a low resistance, a low on-resistance can be achieved.

Further, when the drain voltage Vd becomes higher than the voltage during normal operation due to a load short circuit or the like, the depletion layer extending from the electric field blocking layer 4 side to the JFET portion 3 extends beyond the width of the striped portion of the JFET portion 3. . Then, the JFET portion 3 is immediately pinched off before the n-type current spreading layer 6 is. At this time, the relationship between the drain voltage Vd and the width of the depletion layer is determined based on the width of the striped portion of the JFET portion 3 and the n-type impurity concentration. Therefore, the width of the striped portion of the JFET portion 3 and the n-type impurity concentration are set so that the JFET portion 3 is pinched off when the voltage becomes slightly higher than the drain voltage Vd during normal operation. do. This makes it possible to pinch off the JFET portion 3 even at a low drain voltage Vd. In particular, in this embodiment, the width of each striped JFET portion 3 is substantially constant in the thickness direction, and the width at the lower position is substantially the same as that at the upper position. Therefore, it is possible to accurately pinch off the JFET portion 3 over the entire thickness direction. In this way, by immediately pinching off the JFET unit 3 when the drain voltage Vd becomes higher than the voltage during normal operation, it is possible to maintain a low saturation current and prevent the SiC from being damaged by a load short circuit or the like. It is possible to improve the tolerance of the semiconductor device.

In this way, the JFET portion 3 and the electric field blocking layer 4 function as a saturation current suppressing layer, exhibiting a saturation current suppressing effect, thereby providing a SiC semiconductor device capable of achieving both a low on-resistance and a low saturation current. becomes possible.

Furthermore, by providing the electric field blocking layers 4 so as to sandwich the JFET section 3, a structure is formed in which the striped portions of the JFET section 3 and the electric field blocking layers 4 are alternately and repeatedly formed. Therefore, even if the drain voltage Vd becomes a high voltage, the extension of the depletion layer extending from below to the n ⁻ -type layer 2 is suppressed by the electric field blocking layer 4, and extension to the trench gate structure can be prevented. can. Therefore, the electric field suppressing effect of reducing the electric field applied to the gate insulating film 11 can be exhibited, and the destruction of the gate insulating film 11 can be suppressed. . Since the depletion layer can be prevented from extending to the trench gate structure in this way, the n-type impurity concentration of the n ⁻ -type layer 2 and the JFET portion 3 can be made relatively high, and the on-resistance can be reduced. becomes.

Therefore, it is possible to provide a SiC semiconductor device having a vertical MOSFET with low on-resistance and high reliability.

On the other hand, the SiC semiconductor device of this embodiment is a normally-off semiconductor element in which no current flows between the drain and the source because the channel region is not formed when the gate voltage Vg is not applied. Further, the JFET portion 3 is of a normally-on type because it does not pinch off unless the drain voltage Vd is higher than the voltage during normal operation even when the gate voltage Vg is not applied.

An example of the thickness, depth, and impurity concentration of each component of the vertical MOSFET has been described, but these are only examples, and other thicknesses and depths can be used as long as the above operations are performed. Alternatively, it may be the impurity concentration.

For example, the width of the JFET portion 3, that is, the dimension in the arrangement direction in which the plurality of JFET portions 3 are arranged may be set so as to obtain the effect of suppressing the saturation current.

Further, the width of the electric field blocking layer 4, that is, the dimension in the arrangement direction of the plurality of electric field blocking layers 4 may be set in consideration of low on-resistance and electric field suppression effect. If the width of the electric field blocking layer 4 is increased, the formation ratio of the JFET portion 3 is relatively decreased, which causes an increase in the JFET resistance. When the depletion layer spreads also from the side surface, the electric field suppression effect is reduced. Therefore, the width of the electric field blocking layer 4 should be set in consideration of the realization of low on-resistance by reducing the JFET resistance and the effect of suppressing the electric field.

Next, a method for manufacturing a SiC semiconductor device having a vertical MOSFET having an n-channel type inverted trench gate structure according to the present embodiment will be described with reference to cross-sectional views during manufacturing steps shown in FIGS. 4A to 4G. explain.

[Steps shown in FIG. 4A]
First, as a semiconductor substrate, an n ⁺ -type substrate 1 made of, for example, 4H—SiC, having a (0001) Si surface and an off angle of 4° with respect to the [11-20] direction is prepared. . Then, an n ⁻ -type layer 2 made of SiC is formed on the main surface of n ⁺ -type substrate 1 by epitaxial growth using a CVD (chemical vapor deposition) apparatus (not shown). At this time, a so-called epi-substrate having an n ⁻ -type layer 2 grown in advance on the main surface of the n ⁺ -type substrate 1 may be used. Then, a JFET portion 3 made of SiC is epitaxially grown on the n ⁻ -type layer 2 .

Epitaxial growth is performed by introducing an n-type dopant such as nitrogen (N ₂ ) in addition to silane and propane, which are source gases for SiC.

[Steps shown in FIG. 4B]
An electric field blocking layer 4 is formed in a predetermined region of the JFET portion 3 . At this time, the electric field blocking layer 4 is formed by a technique that suppresses the lateral spread of the electric field blocking layer 4 . This will be described with reference to FIGS. 5A-5C.

First, the step of forming the defect introduced portion 21 is performed as the step shown in FIG. 5A. After disposing a mask 16 made of an oxide film or the like, desired positions of the mask 16 are opened. Specifically, assuming that the region indicated by the thick dashed line in the drawing is the target width of the region where the electric field blocking layer 4 is to be formed, the mask 16 is opened on both sides of the region where the electric field blocking layer 4 is to be formed.

Then, irradiation of a substance for defect formation is performed from above the mask 16 . For example, electron beam irradiation, ion irradiation (ion implantation) using a cyclotron, or the like is performed. By this material injection, defect introduction portions 21 are formed in which defects are introduced on both sides of the formation planned region of the electric field blocking layer 4 where the mask 16 is open. Defects are formed at the desired depth by adjusting the acceleration energy while increasing the dose of the electron beam in the case of electron beam irradiation or increasing the dose of ions in the case of ion implantation. can. In the case of ion implantation, ions that do not become impurities, such as silicon (Si) and carbon (C), can be used.

Further, here, although the mask 16 is used to perform material irradiation, defects can also be formed by applying heat by laser irradiation. In the case of laser irradiation, a defect can be formed at a desired depth position by scanning the laser at a place to be irradiated and adjusting the irradiation energy and focal position.

Although the defect density of the defect introduced portion 21 is arbitrary, it is preferably the same amount as the p-type impurity implanted into the p-type ion implantation portion 20, or may be different. For example, it is desirable that the defect density in the defect introduced portion 21 is higher than the amount of p-type impurity when forming the p-type ion implanted portion 20 .
Subsequently, as shown in FIG. 5B, after the mask 16 is removed, a mask 17 is placed again, and the area of the mask 17 where the electric field blocking layer 4 is to be formed is opened. Then, by ion-implanting, for example, Al as a p-type impurity, a p-type ion-implanted portion 20 corresponding to an impurity ion-implanted portion is formed. Thereafter, after removing the mask 17, as shown in FIG. 5C, the implanted p-type impurity is activated by performing heat treatment with the surface covered with a carbon film 18, for example, so that the electric field blocking layer 4 is formed. Form.

At this time, activation annealing is performed in a state in which the defect-introduced portions 21 are formed on both sides of the p-type ion-implanted portion 20 in the width direction perpendicular to the thickness direction (Z direction) of the n ⁺ -type substrate 1 . done. Therefore, in the region of the p-type ion-implanted portion 20 where the defect-introduced portion 21 is formed, the lateral spread of the p-type impurity is suppressed. That is, when the p ^- type impurity is implanted, it repeatedly collides with interstitial Si or C and spreads laterally. The p-type impurity is distributed outside the target width. However, if the activation annealing is performed in a state in which the defect introduction portion 21 is formed, the p-type impurity laterally spreading in the defect included in the defect introduction portion 21 is trapped, and the lateral spreading of the p-type impurity is prevented. Suppressed. As a result, the electric field blocking layer 4 formed by the activated portion of the p-type ion implanted portion 20 has a substantially constant width, as indicated by the thick line in FIG. 5C, and has a rectangular shape in the YZ plane. Become.

By simulation, Al was simply ion-implanted into SiC by changing the acceleration energy, and the lateral spread was confirmed without forming the defect-introduced portion 21. As a result, the results shown in FIGS. 6A to 6D were obtained. was taken. 6A to 6D are simulations in which the acceleration energy is changed to 500 eV, 1000 eV, 2000 eV, and 3000 eV, and ions are implanted so that the normal direction of the main surface of the wafer matches the ion implantation direction. In the simulation, Al ions are implanted into SiC after limiting the implantation position by arranging a mask. In all cases of FIGS. 6A to 6D, the dose amount is set to 2.5×10 ¹⁵ cm ⁻² . In each figure, the vertical axis X indicates the depth from the ion-implanted surface, and the horizontal axis Y indicates the lateral expansion amount of the ion implantation. Also, the impurity concentration after ion implantation has a magnitude relationship indicated by hatching shades as shown on the right side of each figure.

As can be seen from FIGS. 6A to 6D, when the activation annealing is performed without forming the defect introduced portion 21, the Al ions spread in the lateral direction, and the more the acceleration energy is increased, the deeper the Al ions are implanted. , the lateral expansion amount is larger. This is because the ions collide with the interstitial atoms forming SiC before being deeply implanted, and the ions spread laterally.

On the other hand, SIMS (secondary ion mass spectroscopy) was used to examine the p-type impurity concentration profile before and after the activation annealing after the ion implantation when the defect introduced portion 21 was formed. Here, the defect introducing portion 21 is formed at a position with a depth of about 0.2 μm, ion implantation is performed with a range from the surface to a position with a depth of 0.2 μm, and the p-type impurity concentration is 1×10. A simulation was performed assuming formation of a p-type impurity layer of ²⁰ cm ⁻³ . Although the defect introduced portion 21 is formed at a predetermined depth, it can be considered that checking the state in which the p-type impurity is trapped in the defect is similar to checking the lateral spread of the p-type impurity. FIG. 7 shows the results.

As shown by the dashed line in the figure, the impurity concentration of the p-type impurity is higher at a depth of about 0.2 μm after activation annealing than before activation annealing after ion implantation. This means that the p-type impurities are trapped and segregated in the defects included in the defect introduced portion 21 .

From this result, it can be seen that the lateral spread of the p-type impurity can be suppressed by performing the activation annealing with the defect introduced portions 21 formed on both sides of the p-type ion implanted portion 20 as in the present embodiment. is possible. Also from this fact, if the electric field blocking layer 4 is formed by performing the activation annealing in the state where the defect introduced portion 21 is formed as in the present embodiment, the electric field blocking layer 4 can be formed with a substantially constant width. It can be said that it is possible. If the defect introduced portion 21 is formed when the electric field blocking layer 4 is formed as in the present embodiment, the p-type impurity concentration on both sides of the electric field blocking layer 4 in the width direction will be different from that of the electric field blocking layer 4. The electric field blocking layer 4 can be formed with a constant width while having a structure higher than the region.

Although the defects are repaired and the crystallinity is recovered during the activation annealing, if the defect density is high, the crystallinity is not completely recovered and the defect-introduced portion 21 partially remains.

[Steps shown in FIG. 4C]
Subsequently, an n-type current spreading layer 6 is formed by epitaxially growing n-type SiC on the JFET portion 3 and the electric field blocking layer 4 using a CVD apparatus (not shown).

[Steps shown in FIG. 4D]
Furthermore, a p-type base region 7 and an n ⁺ -type source region 8 are epitaxially grown on the n-type current spreading layer 6 .

[Steps shown in FIG. 4E]
A mask (not shown) having an opening corresponding to the p-type coupling layer 9 is formed on the n ⁺ -type source region 8 . Then, anisotropic etching such as RIE (Reactive Ion Etching) is performed using the mask to sequentially remove the n ⁺ -type source region 8, the p-type base region 7, and the n-type current spreading layer 6, thereby removing the JFET portion. 3 and the electric field blocking layer 4, a deep trench 9a is formed. Then remove the mask.

[Steps shown in FIG. 4F]
Using a CVD apparatus (not shown), p-type SiC is epitaxially grown so as to fill the deep trenches 9a. Then, the p-type coupling layer 9 is formed by leaving the p-type SiC only in the deep trenches 9a by etching back.

[Steps shown in FIG. 4G]
After forming a mask (not shown) on the n ⁺ -type source region 8 and the like, a region of the mask where the gate trench 10 is to be formed is opened. Then, anisotropic etching such as RIE is performed using a mask to form the gate trench 10 .

Thereafter, after removing the mask, a gate insulating film 11 is formed by, for example, thermal oxidation, and covers the inner wall surface of the gate trench 10 and the surface of the n ⁺ -type source region 8 with the gate insulating film 11 . Then, after depositing Poly-Si doped with p-type or n-type impurities, this is etched back to leave Poly-Si at least in the gate trench 10, thereby forming the gate electrode 12. Next, as shown in FIG. This completes the trench gate structure.

Although not shown, the following steps are performed. That is, an interlayer insulating film 13 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 12 and the gate insulating film 11 . A contact hole is formed in the interlayer insulating film 13 using a mask (not shown) to expose the n ⁺ -type source region 8 and the p-type coupling layer 9 . Then, after forming an electrode material composed of, for example, a laminated structure of a plurality of metals on the surface of the interlayer insulating film 13, the source electrode 14 is formed by patterning the electrode material. Furthermore, a drain electrode 15 is formed on the back side of the n ⁺ -type substrate 1 . Thus, the SiC semiconductor device according to this embodiment is completed.

As described above, in the SiC semiconductor device of the present embodiment, when the electric field blocking layer 4 is formed in the JFET section 3 by ion implantation, the defect introduced section 21 is formed, so that activation annealing is performed. The p-type impurity of the p-type ion implantation part 20 can be trapped in the defect. As a result, the finally formed electric field blocking layer 4 can be configured with a substantially constant width. Therefore, in the structure including the saturation current suppressing layer, it is possible to suppress the width reduction of the JFET portion 3 due to the lateral expansion of the electric field blocking layer 4 . Therefore, it is possible to suppress an increase in on-resistance due to the reduction in the width of the JFET portion 3 .

(Modified example of the first embodiment)
(1) In the first embodiment, the electric field blocking layer 4 is formed of an ion-implanted layer, that is, the electric field blocking layer 4 is formed by ion-implanting the p-type impurity after the JFET section 3 is formed. made it On the other hand, the JFET portion 3 is formed by ion-implanting an n-type impurity after the electric field blocking layer 4 is epitaxially grown on the n ⁻ -type layer 2 so that the JFET portion 3 is composed of an ion-implanted layer. may be formed.

In that case, when forming the n-type ion implanted portion for the electric field blocking layer 4, by forming the defect introducing portions 21 on both sides of the n-type ion implanted portion in the width direction, the lateral direction of the JFET portion 3 is reduced. The spread can be suppressed, and the JFET portion 3 can be formed with a substantially constant width.

As described above, the electric field blocking layer 4 may be formed first, and then the JFET portion 3 may be formed by ion implantation. In this case, since the width of the JFET portion 3 can be made substantially constant, it is possible to suppress the reduction in the width of the electric field blocking layer 4 due to the width of the JFET portion 3 expanding at the lower position. Become. Therefore, it is possible to prevent pinch-off from occurring due to insufficient extension of the depletion layer from the electric field blocking layer 4 to the JFET portion 3 side, thereby suppressing an increase in the saturation current.

(2) In the first embodiment, the longitudinal direction of the JFET portion 3 and the electric field blocking layer 4 having one longitudinal direction is the same as the longitudinal direction of the trench gate structure. They may be in the crossing direction.

(Second embodiment)
A second embodiment will be described. The present embodiment has an SJ structure in comparison with the first embodiment, and is otherwise the same as the first embodiment, so only the parts different from the first embodiment will be described.

As shown in FIG. 8, an n-type pillar 50 and a p-type pillar 51 forming an SJ structure are formed on the n ⁻ -type layer 2 . Both the n-type pillars 50 and the p-type pillars 51 extend in the Y direction and are alternately and repeatedly arranged in the X direction. That is, when viewed from the direction normal to the main surface of the n ⁺ -type substrate 1, each of the n-type pillars 50 and the p-type pillars 51 has a plurality of strips, in other words, stripes, and are arranged alternately. It is said to be a layout. The widths and impurity concentrations of the n-type pillar 50 and the p-type pillar 51 are set in a charge-balanced manner.

A saturation current suppressing layer composed of a JFET portion 3 and an electric field blocking layer 4 is formed on the SJ structure, and each portion constituting the vertical MOSFET described in the first embodiment is formed.

In this way, unlike the first embodiment, the SJ structure is provided between the n ⁻ -type layer 2 and the saturation current suppressing layer. With such an SJ structure, the depletion layer can be widened between the n-type pillar 50 and the p-type pillar 51, and the breakdown voltage can be ensured. can be reduced.

The SJ structure can be formed, for example, by epitaxially growing either the n-type pillar 50 or the p-type pillar 51 on the n ⁻ -type layer 2 and then ion-implanting the other. In this case as well, when the n-type or p-type impurity is implanted into the epitaxially grown impurity layer, the defect introducing portions 21 are formed on both sides in the width direction of the ion implanted portion. As a result, lateral expansion of the n-type pillar 50 and the p-type pillar 51 can be suppressed, and the n-type pillar 50 and the p-type pillar 51 can be formed with substantially constant widths.

(Modification of Second Embodiment)
(1) When the SJ structure is provided as in the second embodiment, the arrangement direction of the n-type pillars 50 and the p-type pillars 51 constituting the SJ structure is the off direction, that is, the main surface and the (0001) plane have an off angle. You may make it become a direction along the provided direction.

(2) In the second embodiment, the longitudinal direction of the n-type pillar 50 and the p-type pillar 51 that constitute the SJ structure is perpendicular to the longitudinal direction of the JFET portion 3 and the electric field blocking layer 4 that constitute the saturation current suppression layer. is not limited to In other words, different directions such as intersecting directions and the same direction may be used instead of the vertical direction. When they are arranged in the same direction, for example, the pitches of the n-type pillar 50 and the JFET section 3 are matched so that the JFET section 3 is arranged above the n-type pillar 50 . Also, the pitches of the p-type pillars 51 and the electric field blocking layers 4 are matched so that the electric field blocking layers 4 are formed above the p-type pillars 51 . The widths of the n-type pillar 50 and the p-type pillar 51 are determined in consideration of the charge balance suitable for constructing the SJ structure, and the widths of the JFET portion 3 and the electric field blocking layer 4 are determined in consideration of the saturation current suppressing layer. shall be suitable for

In such a configuration, the SJ structure is formed by epitaxially growing one of the n-type pillar 50 and the p-type pillar 51 and implanting ions into the epitaxially grown one. Similarly, the saturation current suppression layer is also formed by epitaxially growing one of the JFET portion 3 and the electric field blocking layer 4 and implanting ions into the epitaxially grown layer. In this case, the effect of the first embodiment can be obtained by forming the defect-introduced portion 21 at the time of ion implantation for forming the SJ structure or at the time of ion implantation for forming the saturation current suppressing layer. can get.

Here, since the n-type pillar 50 and the JFET portion 3 are connected to each other, and the p-type pillar 51 and the electric field blocking layer 4 are connected to each other, the pitch between the n-type pillar 50 and the JFET portion 3 is set to I try to match. However, if the JFET portion 3 is formed below the electric field blocking layer 4 and has a structure in which the electric field blocking layer 4 and the p-type pillar 51 are not connected, the n-type pillar 50 and the JFET portion 3 are not always connected. You don't have to match the pitch.

(3) In the second embodiment, the structure includes both the SJ structure and the saturation current suppressing layer, but the structure may include only the SJ structure without the saturation current suppressing layer.

(Third embodiment)
A third embodiment will be described. This embodiment differs from the first and second embodiments in that the ion implantation method is different from that of the first and second embodiments, and the rest is the same as in the first and second embodiments. Only part will be explained.

In the present embodiment, when the impurity layer is formed by ion implantation, the relationship between the formation positions of the defect introduction portions 21 formed on both sides in the width direction of the impurity layer and the formation position of the impurity layer is set in a self-aligning manner. make it Specifically, in the first and second embodiments, ion implantation for forming impurity layers is performed as shown in FIGS. 9A to 9D. Here, the case where ion implantation is performed for forming the electric field blocking layer 4 for the JFET portion 3 will be described as an example. is formed by ion implantation.

First, as shown in FIG. 9A, after disposing a mask 40 corresponding to a first mask made of an oxide film or the like, desired positions of the mask 40 are opened. Specifically, an opening 40a corresponding to the first opening is formed in the formation planned region of the p-type ion implantation portion 20 described in the first embodiment of the mask 40, and the formation planned region of the defect introduced portion 21 is formed. An opening 40b corresponding to the second opening is formed in the . At this time, since the openings are formed in the mask 40 at the same time, it is possible to form the openings 40a and 40b at regular intervals without positional deviation.

Then, as shown in FIG. 9B, after applying a resist 41 corresponding to a second mask so as to cover the mask 40 and the openings 40a and 40b, a resist 41 is formed on the openings 40a of the resist 41 by exposure and development. The opening part 40b is exposed, leaving a part such as a flat part. Then, the defect-introducing portion 21 is formed by irradiating a defect-forming substance from above the mask 40 and the resist 41 .

Subsequently, after removing the resist 41, a resist 42 corresponding to a third mask is applied again as shown in FIG. , to expose the opening 40a. Then, as shown in FIG. 9D, a p-type ion implantation portion 20 is formed by ion-implanting, for example, Al as a p-type impurity. After that, the electric field blocking layer 4 is formed by activating the implanted ions by heat treatment.

At this time as well, since the activation is performed in a state in which the defect introduced portions 21 are formed on both sides of the p-type ion implanted portion 20 in the width direction, the vicinity of the defect introduced portion 21 in the p-type ion implanted portion 20 As for, the lateral spread of the p-type impurity is suppressed. As a result, the electric field blocking layer 4 formed by the activated portion of the p-type ion implanted portion 20 has a substantially constant width as shown in FIG. 5C described in the first embodiment.

When the electric field blocking layer 4 is formed in this manner, since the openings 40a and 40b are formed without being misaligned, the p-type ion implantation portion 20 and the defect introduction portion 21 are positioned It can be formed in an accurate positional relationship without deviation. That is, the p-type ion implanted portion 20 and the defect introduced portion 21 can be formed in a self-aligned manner. Therefore, it becomes possible to form the electric field blocking layer 4 with higher accuracy.

(Other embodiments)
Although the present disclosure has been described based on the above embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.

(1) For example, in each of the above-described embodiments, the width of the impurity layer formed by ion implantation is reduced to approximately An example of making it constant has been given and explained. However, this is only an example, and a first impurity layer of one conductivity type composed of an epitaxially grown film is formed on the SiC substrate, and a second impurity layer of the other conductivity type is formed on the first impurity layer. The present invention can be applied to a device in which an impurity layer is formed of an ion-implanted layer with a predetermined width. That is, when the second impurity layer is formed by ion implantation into the first impurity layer, the defect-introducing portions 21 may be formed on both sides in the width direction of the second impurity layer. In each of the above-described embodiments, the second impurity layer is configured to have a substantially constant width. However, when it is desired to control the width of the second impurity layer to a desired predetermined width, the defect introducing portion 21 is formed. do it.

By forming the second impurity layer under such conditions, the lateral expansion of the second impurity layer at the lower position can be suppressed, and the width of the second impurity layer can be made substantially constant. Device characteristics can be stabilized.

In each of the above embodiments, the p-type ion-implanted portion 20 corresponding to the impurity ion-implanted portion is formed after the defect-introduced portion 21 is formed, but the order may be reversed.

(2) Also in the modified example of the first embodiment and the modified example of the second embodiment, the structure may be such that the JFET portion 3 is deeper than the electric field blocking layer 4 . in short. Even in the case of forming the electric field blocking layer 4 and then forming the JFET portion 3 by ion implantation, the JFET portion 3 can be made to have the same depth as the electric field blocking layer 4, It is also possible to make the JFET portion 3 deeper than the electric field blocking layer 4 .

By making the JFET portion 3 deeper than the electric field blocking layer 4 in this way, it is possible to suppress the extension of the two-dimensional depletion layer extending two-dimensionally from the electric field blocking layer 4 toward the n ⁻ -type layer 2 side. That is, it is possible to further suppress the depletion layer extending from the electric field blocking layer 4 side into the n ⁻ -type layer 2 from entering below the JFET section 3 . Therefore, it is possible to suppress the constriction of the current outlet in the JFET portion 3, and it is possible to reduce the on-resistance.

(3) Further, various dimensions such as the impurity concentration, thickness, and width of each portion constituting the SiC semiconductor device shown in each of the above embodiments are merely examples. Furthermore, although 4H was mentioned as an example of the crystal polymorph, SiC substrates of other crystal polymorphs, such as 6H, may also be used.

(4) In each of the above-described embodiments, an n-channel type vertical MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. may be a p-channel type vertical MOSFET obtained by inverting . Further, in the above description, a vertical MOSFET is used as an example of a semiconductor element, but the present invention can also be applied to an IGBT having a similar structure. In the case of an n-channel type IGBT, the conductivity type of the n ⁺ -type substrate 1 is simply changed from n-type to p-type in each of the above-described embodiments, and other structures and manufacturing methods are the same as in each of the above-described embodiments. is. Moreover, although the trench gate structure is mentioned as an example, a planar MOSFET or IGBT may be used, or an element other than a MOSFET or IGBT may be used.

(5) In addition, when indicating crystal orientation etc., a bar (-) should be attached above the desired number, but since there are restrictions on expression based on electronic filing, in this specification shall precede the desired number with a bar.

Reference Signs List 1 n ⁺ type substrate 3 JFET section 4 electric field blocking layer 20 p-type ion implantation section 21 defect introduction section 40 mask 40a, 40b opening 41, 42 resist 50 n-type pillar 51 p-type pillar

Claims (8)

A silicon carbide semiconductor device,
a silicon carbide substrate (1);
a first impurity layer (3) composed of an epitaxially grown film formed on the silicon carbide substrate and composed of one of a first conductivity type and a second conductivity type;
a second impurity layer (4) formed at a desired position of the first impurity layer, composed of an ion-implanted layer and composed of the other of a first conductivity type and a second conductivity type;
The second impurity layer has a first conductivity type and a second The silicon carbide semiconductor device, wherein the impurity concentration of the other conductivity type is higher than that of the other region of the second impurity layer, and the width of the second impurity layer is set to a predetermined width. 2 . The silicon carbide semiconductor device according to claim 1 , wherein defect introduction portions ( 21 ) in which defects are formed are included on both sides of said second impurity layer in said width direction. 3. The silicon carbide semiconductor device according to claim 1, wherein said second impurity layer has a constant width. having an inverted semiconductor element,
the silicon carbide substrate of the first or second conductivity type;
a first conductivity type layer (2) formed on the silicon carbide substrate and made of first conductivity type silicon carbide having an impurity concentration lower than that of the silicon carbide substrate;
an electric field blocking layer (4) formed on the first conductivity type layer and made of silicon carbide of the second conductivity type in which a plurality of layers are arranged in a stripe shape with one direction being the longitudinal direction; and saturation current suppression layers (3, 4) comprising a JFET portion (3) made of silicon carbide of the first conductivity type and having portions in which a plurality of stripes are arranged alternately with the electric field blocking layers in a direction;
a current spreading layer (6) formed on the saturation current suppression layer and made of first conductivity type silicon carbide having a first conductivity type impurity concentration higher than that of the first conductivity type layer;
a base region (7) made of second conductivity type silicon carbide formed on the current spreading layer;
a source region (8) formed on the base region and made of first conductivity type silicon carbide having a first conductivity type impurity concentration higher than that of the first conductivity type layer;
a gate insulating film (11) formed on the surface of the base region between the source region and the current spreading layer;
a gate electrode (12) disposed on the gate insulating film and formed with one direction as a longitudinal direction;
an interlayer insulating film (13) covering the gate electrode and the gate insulating film and having a contact hole formed therein;
a source electrode (14) electrically connected to the source region through the contact hole;
a drain electrode (15) formed on the back surface side of the silicon carbide substrate,
4. The silicon carbide semiconductor device according to claim 1, wherein one of said JFET portion and said electric field blocking layer is said first impurity layer and the other is said second impurity layer. A plurality of stripes of first conductivity type pillars (50) and second conductivity type pillars (51) extending with one direction as a longitudinal direction are alternately arranged between the first conductivity type layer and the saturation current suppression layer. 5. The silicon carbide semiconductor device according to claim 4, further comprising a superjunction structure (50, 51) arranged in a pattern. having an inverted semiconductor element,
the silicon carbide substrate of the first or second conductivity type;
a first conductivity type layer (2) formed on the silicon carbide substrate and made of first conductivity type silicon carbide having an impurity concentration lower than that of the silicon carbide substrate;
A plurality of first-conductivity-type pillars (50) and second-conductivity-type pillars (51) formed on the first-conductivity-type layer and extending with one direction as a longitudinal direction are alternately arranged in stripes. a superjunction structure (50, 51) composed of
a current spreading layer (6) formed on the superjunction structure and made of first conductivity type silicon carbide having a first conductivity type impurity concentration higher than that of the first conductivity type layer;
a base region (7) made of second conductivity type silicon carbide formed on the current spreading layer;
a source region (8) formed on the base region and made of first conductivity type silicon carbide having a first conductivity type impurity concentration higher than that of the first conductivity type layer;
a gate insulating film (11) formed on the surface of the base region between the source region and the current spreading layer;
a gate electrode (12) disposed on the gate insulating film and formed with one direction as a longitudinal direction;
an interlayer insulating film (13) covering the gate electrode and the gate insulating film and having a contact hole formed therein;
a source electrode (14) electrically connected to the source region through the contact hole;
a drain electrode (15) formed on the back surface side of the silicon carbide substrate,
4. The silicon carbide semiconductor according to claim 1, wherein one of said first conductivity type pillar and said second conductivity type pillar is said first impurity layer and the other is said second impurity layer. Device. A method for manufacturing a silicon carbide semiconductor device,
preparing a silicon carbide substrate (1);
forming a first impurity layer (3) composed of one of a first conductivity type and a second conductivity type by epitaxial growth on the silicon carbide substrate;
forming a second impurity layer (4) composed of the other of the first conductivity type and the second conductivity type at a desired position of the first impurity layer by ion implantation;
By forming the second impurity layer,
forming a defect introduction portion (21) in which defects are formed on both sides of the region in which the second impurity layer is to be formed in the width direction, with the direction perpendicular to the thickness direction of the silicon carbide substrate being the width direction; ,
forming an impurity ion-implanted portion (20) by implanting impurity ions into the region where the second impurity layer is to be formed;
performing activation annealing of the impurity by heat treatment to trap the impurity in the defect in the region where the defect introduced portion is formed, thereby forming the second impurity layer having a predetermined width. A method for manufacturing a silicon semiconductor device. Forming the defect introduction portion and forming the impurity ion implantation portion include:
forming a first mask (40) on the first impurity layer;
Forming a first opening (40a) in the formation scheduled region of the impurity ion implantation portion of the first mask and forming a second opening (40b) in the formation scheduled region of the defect introduction portion;
A second mask (41) is placed to cover the first opening while exposing the second opening, and the defect introduced portion is formed by irradiating a substance from above the first mask and the second mask. and
A third mask (42) is placed to expose the first opening while covering the second opening, and impurity ions are implanted from above the first mask and the third mask, thereby implanting the impurity ions. 8. The method of manufacturing a silicon carbide semiconductor device according to claim 7, comprising forming a portion.

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