JP2022110938A - Read-out circuit and optical sensor - Google Patents

Abstract

To provide a read-out circuit and an optical sensor, in which power consumption of the read-out circuit can be suppressed.SOLUTION: A read-out circuit 2 is an apparatus to convert an analog signal that is one of a plurality of detection signals into a digital signal including a bit string according to the voltage of the analog signal. The read-out circuit includes: upper bit string generators hbg1-hbgN to generate upper bit strings hbs1-hbsN of a bit string by comparing boundaries between a plurality of subranges obtained by dividing a predetermined voltage range and the voltages of the analog signals a1-aN; lower bit string generators lbg1-lbgN which are units to generate lower bit strings lbs1-lbsN of the bit string by any of a plurality of analog-to-digital converters, each of the plurality analog-to-digital converters generating the lower bit strings when the voltages of the analog signals are within a subrange assigned to each analog-to-digital converter; and a digital signal generator 4 to generate the digital signal based on the upper bit strings and the lower bit strings.SELECTED DRAWING: Figure 2

Description

The present invention relates to readout circuits and photosensors.

A CMOS (Complementary Metal-Oxide Semiconductor) image sensor has a photodiode array and a readout circuit that converts the output of the photodiodes into digital signals and sequentially outputs the digital signals. An important component of the readout circuit is the Analog-to-digital Converter, which converts the photodiode output to a digital signal.

An SS-ADC (Single Slope Analog-to-Digital Converter) with a simple circuit configuration is used for the analog-to-digital converter (hereinafter referred to as an AD converter) of the readout circuit (see, for example, Patent Documents 1 and 2). . The SS-ADC converts the input voltage to a digital signal by the number of clock signals counted by a counter until the monotonically increasing (or decreasing) ramp voltage exceeds (or falls below) the input voltage.

The SS-ADC has a problem that the power consumption of the counter cannot be ignored when the conversion speed is increased. In order to solve this problem, a number of techniques have been proposed for generating the upper bits and lower bits of a digital signal obtained by analog-to-digital conversion (hereinafter referred to as AD conversion) using separate circuits (for example, Patent Document 1). 2).

In these techniques, the high-order bits of the digital signal are produced by comparison circuits and logic circuits, and the low-order bits of the digital signal are produced by the SS-ADC. With this circuit configuration, the number of lower bits generated by the SS-ADC is reduced, so the clock frequency of the counter can be reduced. Since the power consumption of the counter greatly depends on the clock frequency, the power consumption of the SS-ADC can be suppressed according to the above technique.

SS-ADC generates only the lower bits The above techniques differ in the range in which the ramp voltage monotonically increases (or decreases) and the number of ramp voltages, but they can be used for analog-to-digital conversion of analog signals. They have in common that only one SS-ADC is used.

JP 2010-183405 A Japanese Patent Publication No. 2010-503253

A CMOS image sensor is a device that captures an image of visible light. On the other hand, an infrared image sensor is a device that captures an infrared image (a so-called thermal image).

Silicon photodiodes have no sensitivity in the infrared wavelength region except for a portion of the near-infrared wavelength region. For this reason, infrared image sensors have photodiode arrays (ie, infrared sensor arrays) made of materials different from silicon. The infrared image sensor also has a readout circuit formed on the silicon chip. The infrared image sensor converts an infrared image formed on the infrared sensor array into an image signal by this readout circuit and outputs the image signal.

Specifically, the infrared image sensor uses a readout circuit to generate an analog signal (e.g., a voltage corresponding to the integrated value of the photocurrent) from the output of the infrared sensor array (e.g., photocurrent) and output the generated analog signal. do. The output analog signal is converted into a digital signal by an analog-to-digital converter (hereinafter referred to as an external AD converter) provided on the same circuit board as the infrared image sensor.

In this configuration, the analog signal (that is, the image signal) output from the infrared image sensor is disturbed by the mixture of external noise on the line transmitted to the analog-to-digital converter. Therefore, as in the case of CMOS image sensors, a technique of mounting an SS-ADC in a readout circuit to suppress the mixing of external noise is being studied.

However, when the SS-ADC is mounted on the readout circuit of the infrared image sensor, the following problems occur. An infrared image sensor is a device that detects a target object with a minute temperature difference against a normal temperature background. Therefore, an analog-to-digital converter with a higher resolution than the SS-ADC of the CMOS image sensor is used for the external AD converter of the infrared image sensor. For example, the resolution of the external AD converter of the infrared image sensor is 14 bits. On the other hand, the resolution of the SS-ADC of the CMOS image sensor is 11 bits.

If the SS-ADC achieves the same high resolution (ie, 14 bits) as that of an external AD converter, the count number of the counter increases significantly (eg, 8 times). Therefore, if an infrared image sensor equipped with an SS-ADC is used to achieve the frame rate of an infrared image sensor that uses an external AD converter, the count speed (that is, operation speed) of the counter increases significantly.

An increase in count rate is achieved by an increase in clock frequency, so increasing the count rate increases the clock frequency. As a result, the power consumption of the counter increases and the counter generates heat. If the infrared sensor is a thermal sensor (for example, a bolometer or the like), heat generated by the counter increases the temperature of the thermal sensor, making it difficult to capture an infrared image. If the infrared sensor is a cooled sensor (e.g., a HgCdTe infrared detector or a type II superlattice infrared detector), heat generated by the counter will make it difficult to cool the cooled sensor, resulting in difficulty in capturing an infrared image. Become.

The SS-ADC compares an analog signal and a ramp voltage to generate a digital signal, and a counter is also used to generate the ramp voltage. Therefore, if an SS-ADC equipped with a readout circuit is used to achieve a high resolution for capturing an infrared image, the counter of the ramp voltage source will also generate heat, making capturing an infrared image even more difficult. As the infrared image sensor has a higher frame rate and higher definition, the problem caused by the heat generation of the counter becomes more serious.

Then, this invention makes it a subject to solve such a problem.

In one embodiment, the readout circuit outputs a first analog one of the plurality of first detection signals for each of the plurality of first detection signals generated from the outputs of the plurality of first photodetectors. A readout circuit for performing analog-to-digital conversion for converting a signal into a first digital signal including a first bit string according to the voltage of the first analog signal, the readout circuit performing analog-to-digital conversion from a first voltage to a second voltage different from the first voltage. by comparing the voltage of the first analog signal with the boundary between a plurality of sub-ranges obtained by dividing the voltage range up to A portion of the first bit string other than the first high-order bit string by one of a first high-order bit string generator for generating a first high-order bit string signal including a first high-order bit string and a plurality of first analog-to-digital converters wherein each of the plurality of first analog-to-digital converters is configured such that the voltage of the first analog signal is within a specific first sub-range of the plurality of sub-ranges a first low-order bit string generating section for generating the first low-order bit string signal when the voltages of the plurality of first analog-to-digital converters are different from each other in the first sub-ranges; the first high-order bit string signal; and a digital signal generator that generates the first digital signal based on the first lower bit string signal.

According to one aspect of the present invention, power consumption of a readout circuit equipped with an analog-to-digital converter can be suppressed.

FIG. 1 is an example of a functional block diagram of a readout circuit 2 according to the first embodiment. FIG. 2 is a diagram showing the flow of signals in the readout circuit 2. As shown in FIG. FIG. 2 is a diagram showing the flow of signals in the readout circuit 2. As shown in FIG. FIG. 3 is a diagram illustrating an example of signals generated by the first high-order bit string generator hbg1 and the first low-order bit string generator lbg1. FIG. 4 is a diagram showing an example of the hardware configuration of the readout circuit 2. As shown in FIG. FIG. 5 is a diagram showing an example of the hardware configuration of the reference voltage generation circuit 6. As shown in FIG. FIG. 6 is a diagram showing an example of the hardware configuration of the ramp voltage generation circuit 8. As shown in FIG. FIG. 7 is a diagram showing an example of the hardware configuration of the first upper and lower bit string generation circuit bgc1. FIG. 8 is a diagram showing an example of the hardware configuration of the digital signal generation circuit 10. As shown in FIG. FIG. 9 is a flow chart showing an example of the operation of readout circuit 2. Referring to FIG. FIG. 10 is a diagram illustrating an example of signal flow in the first upper and lower bit string generation circuit bgc1 (see FIG. 4). FIG. 11 is a diagram showing temporal changes in the lamp voltages generated by the plurality of lamp voltage sources 16. As shown in FIG. FIG. 12 is an example of the truth table 38 of the processing performed by the determination circuit 26 on the first analog signal a1. FIG. 13 is an example of a functional block diagram of the photosensor 100 according to the second embodiment. FIG. 14 is a diagram showing signal flow in the optical sensor 100. As shown in FIG. FIG. 15 is an example of a functional block diagram of readout circuit 102 of the second embodiment. FIG. 16 is a diagram showing the flow of signals in readout circuit 102. Referring to FIG. FIG. 17 is an example of a perspective view of the optical sensor 100 according to the second embodiment. FIG. 18 is a plan view showing an example of the structure of the sensor chip 109. FIG. FIG. 19 is a diagram showing an example of the hardware configuration of the readout circuit 102. As shown in FIG. FIG. 20 is a plan view showing an example of the structure of the analog signal generation circuit 110. As shown in FIG. FIG. 21 is a circuit diagram showing an example of the pixel circuit 115. As shown in FIG. FIG. 22 is a diagram showing an example of the hardware configuration of the first ramp voltage source R1. FIG. 23 shows the signal flow in the first ramp voltage source R1. FIG. 24 is a diagram showing an example of the hardware configuration of SS-ADC1. FIG. 25 is a diagram showing signal flow in the SS-ADC1.

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to matters described in the claims and equivalents thereof. Parts having the same structure are denoted by the same reference numerals even if the drawings are different, and the description thereof will be omitted.

(Embodiment 1)
(1) Structure (1-1) Functional Block FIG. 1 is an example of a functional block diagram of the readout circuit 2 of the first embodiment. FIG. 2 is a diagram showing the flow of signals in the readout circuit 2. As shown in FIG. The readout circuit 2 outputs one of the plurality of first detection signals D1 for each of the plurality of first detection signals D1 (see FIG. 2) generated from the outputs of the plurality of first photodetectors (not shown). is a circuit that performs AD conversion for converting a first analog signal a1 into a first digital signal d1.

The plurality of first photodetectors are, for example, a plurality of type II superlattice infrared detectors arranged in tandem. The plurality of first photodetectors may be a plurality of HgCdTe infrared detectors arranged in a column or a plurality of silicon photodiodes arranged in a column.

The readout circuit 2 (see FIG. 1) has a first high-order bit string generator hbg1, a first low-order bit string generator lbg1, and a digital signal generator 4. FIG. FIG. 3 is a diagram illustrating an example of signals generated by the first high-order bit string generator hbg1 and the first low-order bit string generator lbg1.

The first digital signal d1 generated by AD conversion performed by the readout circuit 2 is a signal including a bit string (hereinafter referred to as a first bit string BS1) corresponding to the voltage of the first analog signal a1. A first high-order bit string generator hbg1 (see FIG. 2) generates a signal (hereinafter referred to as a first high-order bit string signal hbs1) including a high-order bit string (hereinafter referred to as first high-order bit string HBS1) of the first bit string BS1 (see FIG. 3). call). The first high-order bit string HBS1 is a bit string that includes the most significant bit MSB and does not include the least significant bit LSB of the first bit string BS1 (the same applies hereinafter).

A first low-order bit string generator lbg1 (see FIG. 2) generates a signal (hereinafter referred to as a first low-order bit string signal lbs1) including a low-order bit string of the first bit string BS1 (hereinafter referred to as a first low-order bit string LBS1). . The first lower bit string LBS1 is the portion of the first bit string BS1 other than the first upper bit string HBS1.

The digital signal generator 4 (see FIG. 2) generates the first digital signal d1 based on the first upper bit string signal hbs1 and the first lower bit string signal lbs1.

-Second high-order bit string generator hbg2, second low-order bit string generator lbg2, etc.-
For each of the i-th detection signals generated from the i-th photodetectors (i is an integer equal to or greater than 2, the same shall apply hereinafter) different from the plurality of first photodetectors, the readout circuit 2 further , performs AD conversion. AD conversion for each of the i-th plurality of detection signals converts the i-th analog signal, which is one of the i-th plurality of detection signals, into a signal containing a bit string corresponding to the voltage of the i-th analog signal (hereinafter referred to as i It is the process of converting to the second digital signal). The multiple first detection signals D1 (see FIG. 2) described above are the first multiple detection signals. The "bit string corresponding to the voltage of the i-th analog signal" is hereinafter referred to as the i-th bit string.

For example, the readout circuit 2 detects one of the plurality of second detection signals D2 for each of the plurality of second detection signals D2 generated from the outputs of the plurality of second photodetectors different from the plurality of first photodetectors. A/D conversion is performed to convert the second analog signal a2, which is the second analog signal a2, into a second digital signal d2. The second digital signal d2 is a signal containing a second bit string corresponding to the voltage of the second analog signal a2. Note that "N" in the code "DN" shown in FIG. 2 is an integer of 2 or more (the same applies hereinafter).

The readout circuit 2 has an i-th high-order bit string generation section (for example, a second high-order bit string generation section hbg2) different from the first high-order bit string generation section hbg1. The reading circuit 2 further includes an i-th lower bit string generator (for example, a second lower bit string generator lbg2) different from the first lower bit string generator lbg1.

The i-th high-order bit string generator is a circuit that generates a signal including the high-order bit string of the i-th bit string (hereinafter referred to as the i-th high-order bit string signal). "High-order bit string of i-th bit string" (hereinafter referred to as i-th high-order bit string) is a bit string that includes the most significant bit and does not include the least significant bit of the i-th bit string.

For example, the second high-order bit string generation unit hbg2 generates a signal (hereinafter referred to as a second high-order bit string signal hbs2). The second high-order bit string is a bit string that includes the most significant bit and does not include the least significant bit of the second bit string.

The i-th low-order bit string generator is a circuit that generates a signal (hereinafter referred to as an i-th low-order bit string signal) including a portion of the i-th bit string other than the i-th high-order bit string. "A portion of the i-th bit string other than the i-th upper bit string" is hereinafter referred to as the i-th lower bit string.

For example, the second low-order bit string generator lbg2 generates a signal (hereinafter referred to as a second low-order bit string signal lbs2) including a portion of the second bit string other than the second high-order bit string. The number of digits of the i-th bit string is the same as the number of digits of the first bit string BS1. The number of digits of the i-th high-order bit string is the same as the number of digits of the first high-order bit string HBS1.

The digital signal generator 4 generates the i-th digital signal based on the i-th upper bit string signal and the i-th lower bit string signal. For example, the digital signal generator 4 generates the second digital signal d2 based on the second high-order bit string signal hbs2 and the second low-order bit string signal lbs2.

(1-2) Hardware Configuration FIG. 4 is a diagram showing an example of the hardware configuration of the readout circuit 2. As shown in FIG.

As shown in FIG. 4, the readout circuit 2 includes a reference voltage generation circuit 6, a ramp voltage generation circuit 8, a first upper and lower bit string generation circuit bgc1 to an Nth upper and lower bit string generation circuit bgcN, a digital signal generation circuit 10, and a control circuit 12 . The control circuit 12 is a circuit (for example, a logic circuit) that controls the ramp voltage generation circuit 8 and the like.

The j-th (j is an integer equal to or greater than 1, hereinafter the same) high-order bit string generator (see FIG. 1) is realized by the reference voltage generation circuit 6, the j-th upper and lower bit string generation circuit, and the control circuit 12. For example, the first high-order bit string generator hbg1 (see FIG. 1) is realized by the reference voltage generation circuit 6 (see FIG. 4), the first upper and lower bit string generation circuit bgc1, and the control circuit 12.

Similarly, the j-th low-order bit string generator is realized by the reference voltage generation circuit 6, the ramp voltage generation circuit 8, the j-th upper and lower bit string generation circuit, and the control circuit 12. FIG. For example, the first lower bit string generation unit lbg1 (see FIG. 1) is realized by the reference voltage generation circuit 6 (see FIG. 4), the ramp voltage generation circuit 8, the first upper and lower bit string generation circuit bgc1, and the control circuit 12. be done.

The digital signal generator 4 (see FIG. 1) is implemented by a digital signal generator circuit 10 . The first to N-th upper and lower bit string generation circuits are so-called column AD converters.

-Reference Voltage Generation Circuit 6-
FIG. 5 is a diagram showing an example of the hardware configuration of the reference voltage generation circuit 6. As shown in FIG. As shown in FIG. 5, the reference voltage generating circuit 6 has, for example, a plurality of resistors 13 connected in series and a plurality of buffer circuits 14 having input terminals connected between adjacent resistors 13 .

A first voltage VL is connected to one end E1 of the resistors 13 connected in series. A second voltage VH different from the first voltage VL is connected to the other ends E2 of the resistors 13 connected in series. Unless otherwise specified, the second voltage VH is higher than the first voltage VL in the following description. However, the second voltage VH may be lower than the first voltage VL.

A plurality of buffer circuits 14 divide a voltage range [VL, VH] from a first voltage VL to a second voltage VH (hereinafter referred to as an ADC range) to divide a plurality of subrange boundaries (hereinafter referred to as called the boundary voltage). In the example shown in FIG. 5, the boundary voltages are the output V1 of the first buffer circuit B1, the output V2 of the second buffer circuit B2 and the output V3 of the third buffer circuit B3.

In the following description, the resistance values of the multiple resistors 13 are equal to each other, and the multiple sub-ranges are ranges obtained by equally dividing the ADC range.

- Ramp voltage generation circuit 8 -
FIG. 6 is a diagram showing an example of the hardware configuration of the ramp voltage generation circuit 8. As shown in FIG. The ramp voltage generator circuit 8 has a plurality of ramp voltage sources 16 each scanning a separate voltage range.

Each ramp voltage source 16 has two input terminals. One of the two input terminals is connected to the first voltage VL or one of the plurality of buffer circuits 14 (see FIG. 5). Another buffer circuit 14 or a second voltage VH is connected to the other of the two input terminals. Each ramp voltage source 16 outputs a ramp voltage that changes from one of two voltages input to two input terminals to the other. Each ramp voltage source 16 also has a control terminal (not shown) connected to the control circuit 12 .

In the example shown in FIG. 6, the first voltage VL and the output terminal of the first buffer circuit B1 are connected to the two input terminals of the first ramp voltage source R1. Thus, the first ramp voltage source R1, for example, outputs a ramp voltage that increases from one end (eg, first voltage VL) of the sub-range [VL, V1] toward the other end (eg, boundary voltage V1).

Similarly, two input terminals of the second ramp voltage source R2 are connected to the output terminal of the first buffer circuit B1 and the output terminal of the second buffer circuit B2. Thus, the second ramp voltage source R2, for example, outputs a ramp voltage that increases from one end (eg, boundary voltage V1) of the sub-range [V1, V2] to the other end (eg, boundary voltage V2).

Two input terminals of the third ramp voltage source R3 are connected to the output terminal of the second buffer circuit B2 and the output terminal of the third buffer circuit B3. Thus, the third ramp voltage source R3, for example, outputs a ramp voltage that increases from one end (eg, boundary voltage V2) of the sub-range [V2, V3] to the other end (eg, boundary voltage V3).

Two input terminals of the fourth ramp voltage source R4 are connected to the output terminal of the third buffer circuit B3 and the second voltage VH. Therefore, the fourth ramp voltage source R4, for example, outputs a ramp voltage that increases from one end (eg, boundary voltage V3) of the sub-range [V3, VH] toward the other end (eg, second voltage VH).

-First upper and lower bit string generation circuit bgc1-
FIG. 7 is a diagram showing an example of the hardware configuration of the first upper and lower bit string generation circuit bgc1 (see FIG. 4). The hardware configuration of each of the second upper and lower bit string generation circuit bgc2 to the Nth upper and lower bit string generation circuit bgcN is substantially the same as the hardware configuration of the first upper and lower bit string generation circuit bgc1. Therefore, description of the second upper and lower bit string generation circuit bgc2 to the Nth upper and lower bit string generation circuit bgcN is omitted.

The first upper and lower bit string generation circuit bgc1 has a load transistor 20 connected to a pixel circuit (not shown), which will be described later, and a noise elimination capacitor 22 connected in parallel to the load transistor 20 .

The first upper and lower bit string generation circuit bgc1 further includes a plurality of analog-to-digital converters (hereinafter referred to as first analog-to-digital converters) 18 . One end of the load transistor 20 on the pixel circuit side is connected to an input terminal (hereinafter referred to as an analog signal terminal) of each first analog-to-digital converter 18 . Another input terminal (hereinafter referred to as a ramp voltage terminal) of each first analog-to-digital converter 18 is connected to one of the output terminals of the plurality of ramp voltage sources 16 (see FIG. 6).

The number of first analog-to-digital converters 18 is equal to the number of sub-ranges, and each first analog-to-digital converter 18 is assigned a separate sub-range. In the example shown in FIG. 7, the plurality of first analog-to-digital converters 18 are four SS-ADCs (Single Slope Analog-to-Digital Converters).

The output terminal of the first ramp voltage source R1 is connected to the ramp voltage terminal of the first SS-ADC (hereinafter referred to as SS-ADC1). The output terminal of the second ramp voltage source R2 is connected to the ramp voltage terminal of the second SS-ADC (hereinafter referred to as SS-ADC2). The output terminal of the third ramp voltage source R3 is connected to the ramp voltage terminal of the third SS-ADC (hereinafter referred to as SS-ADC3). The output terminal of the fourth ramp voltage source R4 is connected to the ramp voltage terminal of the fourth SS-ADC (hereinafter referred to as SS-ADC4).

The first upper and lower bit string generation circuit bgc 1 further has a plurality of comparators 24 . One end of the load transistor 20 on the pixel circuit side is connected to the non-inverting input terminal of each comparator.

An output terminal of one of a plurality of buffer circuits 14 (see FIG. 5) is connected to the inverting input terminal of each comparator. In the example shown in FIG. 7, the plurality of comparators 24 are three operational amplifiers.

The output terminal of the first buffer circuit B1 (see FIG. 5) is connected to the inverting input terminal of the first comparator C1 (hereinafter referred to as the first comparator). The output terminal of the second buffer circuit B2 is connected to the inverting input terminal of the second comparator C2 (hereinafter referred to as the second comparator). The output terminal of the third buffer circuit B3 is connected to the inverting input terminal of the third comparator C3 (hereinafter referred to as the third comparator).

The first upper and lower bit string generation circuit bgc 1 further has a determination circuit 26 . The decision circuit 26 is, for example, an ethics circuit. The function of the determination circuit 26 will be described later (see "(2-2) Hardware Operation").

The determination circuit 26 has a plurality of input terminals. In the example shown in FIG. 7, the determination circuit 26 has three input terminals. The first input terminal is connected to the output terminal of the first comparator C1. The output terminal of the second comparator C2 is connected to the second input terminal. The third input terminal is connected to the output terminal of the third comparator C3.

The determination circuit 26 has a plurality of output terminals. In the example shown in FIG. 7, the determination circuit 26 has five output terminals. The first output terminal is connected to an input terminal of the SS-ADC 1 that is different from the lamp voltage terminal and the analog signal terminal (hereinafter referred to as an EN terminal). The EN terminal of SS-ADC2 is connected to the second output terminal. The EN terminal of SS-ADC3 is connected to the third output terminal. The EN terminal of SS-ADC 4 is connected to the fourth output terminal. One of the input terminals of the digital signal generation circuit 10 (see FIG. 4) is connected to the fifth output terminal.

The decision circuit 26 also has a control terminal (not shown) connected to the control circuit 12 .

-Digital signal generation circuit 10-
FIG. 8 is a diagram showing an example of the hardware configuration of the digital signal generation circuit 10. As shown in FIG. The digital signal generation circuit 10 has an upper and lower bit string coupling circuit 28 and a memory 30 (for example, Static Random Access Memory). The upper and lower bit string coupling circuit 28 is, for example, a logic circuit.

A plurality of input terminals of the upper and lower bit string coupling circuit 28 are connected to the output terminal of the determination circuit 26 and the output terminals of the SS-ADCs 1 to 4, respectively. An input terminal of the memory 30 is connected to an output terminal of the upper and lower bit string coupling circuit 28 . An output terminal of the memory 30 is connected to an output port of the readout circuit 2 .

The function of the upper and lower bit string coupling circuit 28 will be described later (see "(2-2) Hardware Operation").

(2) Operation (2-1) Operation of Readout Circuit FIG. 9 is a flowchart showing an example of the operation of the readout circuit 2 . FIG. 9 is a flowchart showing an example of a procedure in which the readout circuit 2 AD-converts each of the plurality of first detection signals D1.

-Step S2-
The readout circuit 2 first compares the boundary voltage between a plurality of subranges obtained by dividing the ADC range with the first analog signal a1 to obtain the first upper bit string HBS1 of the first bit string BS1 (see FIG. 3). generates a first high-order bit string signal hbs1 containing The first bit string BS1 is a bit string corresponding to the voltage of the first analog signal a1.

The ADC range is the voltage range described with reference to FIG. 5 (see "-reference voltage generation circuit 6-"). The minimum value of the ADC range (that is, the first voltage VL) is preferably the minimum value of voltages that the plurality of first detection signals D1 can take (for example, ground potential). The maximum value of the ADC range (that is, the second voltage VH) is preferably the maximum value of voltages that the plurality of first detection signals D1 can take (for example, a reset voltage of a pixel circuit, which will be described later).

If the ADC range does not match this preferred range, problems may occur, such as not AD converting part of the analog signal. However, such a problem can be ignored depending on the state of use and purpose of use of the readout circuit 2 . For example, the maximum value of the ADC range (that is, the second voltage VH) may be higher than the maximum possible voltage value of the plurality of first detection signals D1. Similarly, the minimum value of the ADC range (that is, the first voltage VL) may be lower than the minimum possible voltage value of the plurality of first detection signals D1.

Step S2 is executed by the first high-order bit string generator hbg1 (see FIG. 2).

-Step S4-
After step S2, readout circuit 2 generates first lower bit string signal lbs1 including first lower bit string LBS1 of first bit string BS1 by one of the plurality of first analog-to-digital converters 18 (see FIG. 7). .

Step S4 is executed by the first lower bit string generator lbg1.

-Step S6-
After step S4, readout circuit 2 generates first digital signal d1 based on first upper bit string signal hbs1 (see FIG. 2) and first lower bit string signal lbs1. The readout circuit 2 outputs the generated first digital signal d1.

Step S6 is executed by the digital signal generator 4 .

After step S6, readout circuit 2 returns to step S2 and executes steps S2 to S6 for the new first analog signal a1.

AD conversion performed by the readout circuit 2 on each of the i-th detection signals Di (for example, the plurality of second detection signals D2) is substantially the same as the AD conversion described with reference to FIG. Specifically, the description of the AD conversion for the plurality of first detection signals D1 is converted to the description of the AD conversion for the plurality of detection signals Di by performing the following replacement.

The “plurality of first detection signals D1” should be read as “the i-th plurality of detection signals Di”. Further, "first analog signal a1" is read as "i-th analog signal ai". The "first digital signal d1" is read as "i-th digital signal di".

The "first bit string BS1" is read as "i-th bit string". The "first high-order bit string HBS1" should be read as "i-th high-order bit string". The “first high-order bit string generation unit hbg1” is read as “i-th high-order bit string generation unit hbgi”.

The "plurality of first analog-to-digital converters 18" is read as "the i-th plurality of analog-to-digital converters". The "first low-order bit string" is read as "i-th low-order bit string". The “first low-order bit string generation unit lbg1” is read as “i-th low-order bit string generation unit lbgi”. The “first low-order bit string generation unit lbg1” is read as “i-th low-order bit string generation unit lbgi”.

(2-2) Hardware Operation FIG. 10 is a diagram illustrating an example of signal flow in the first upper and lower bit string generation circuit bgc1 (see FIG. 4). Here, the operation performed by the first upper and lower bit string generation circuit bgc1 will be described. However, the first digital signal d1 generated by the readout circuit 2 is assumed to be a 6-bit digital signal. The first high-order bit string is assumed to be a 2-bit bit string. The first lower bit string is assumed to be a 4-bit bit string. The operations of the second upper and lower bit string generation circuit bgc2 to the Nth upper and lower bit string generation circuit bgcN are substantially the same as the operations of the first upper and lower bit string generation circuit bgc1.

When the readout circuit 2 is activated, the first voltage VL is connected to one end E1 of the plurality of resistors 13 of the reference voltage generation circuit 6 (see FIG. 5). The first voltage VL is, for example, the ground potential (that is, 0V). On the other hand, the second voltage VH is connected to the other ends E2 of the resistors 13 . The second voltage VH is, for example, the reset voltage of the pixel circuit (see Embodiment 2). In the following description, the first voltage VL is assumed to be 0V.

When the first voltage VL and the second voltage VH are connected (that is, applied) across the plurality of resistors 13, the first buffer circuit B1 transfers the boundary voltage V1 (=VH/4) to the first comparator C1 ( (see FIG. 10). The second buffer circuit B2 inputs the boundary voltage V2 (=2·VH/4) to the inverting terminal of the second comparator C2. The third buffer circuit B3 inputs the boundary voltage V3 (=3·VH/4) to the inverting terminal of the third comparator C3.

For example, the control circuit 12 (see FIG. 4) controls an analog signal generation circuit (not shown) (see Embodiment 2) in response to a read request from the outside of the read circuit 2 to generate a plurality of first light beams. A plurality of first detection signals D1 are generated from the output of the detector. The control circuit 12 further controls the analog signal generation circuit to input the analog signal 32, which is one of the generated first detection signals D1, to the non-inverting terminals of the comparators C1 to C3. The analog signal 32 is the first analog signal a1 described above. The first analog signal a1 is, for example, an analog signal sequentially selected from a plurality of first detection signals D1 generated from outputs of a plurality of first photodetectors.

The first comparator C1 outputs a signal with a high signal level (that is, a high level signal) when the voltage of the input analog signal 32 is equal to or higher than the boundary voltage V1. On the other hand, when the voltage of the input analog signal 32 is lower than the boundary voltage V1, the first comparator C1 outputs a signal with a low signal level (that is, a low level signal). The same applies to the second to third comparators C2 and C3.

―Generation of upper bit string―
Outputs 34 of the first to third comparators C 1 to C 3 (see FIG. 10) are input to the decision circuit 26 . The determination circuit 26 generates a first high-order bit string signal hbs1 containing the first high-order bit string HBS1 of the first bit string BS1 (see FIG. 3) based on the outputs 34 of the first comparator C1 to the third comparator C3. The generated first high-order bit string signal hbs1 is input to the upper and lower bit string coupling circuit 28 of the digital signal generation circuit 10 (see FIG. 8).

―Generation of low-order bit string―
The decision circuit 26 (see FIG. 10) further selects one of the SS-ADCs 1 to 4 (for example, SS-ADC3) based on the outputs 34 of the first comparators C1 to third comparators C3.

The control circuit 12 then sends control signals to the plurality of ramp voltage sources 16 (see FIG. 6) and the decision circuit 26 . The control signal sent to the multiple ramp voltage sources 16 is hereinafter referred to as the first control signal. The control signal sent to the decision circuit 26 is hereinafter referred to as the second control signal.

A plurality of ramp voltage sources 16 each output a ramp voltage in response to the first control signal. FIG. 11 is a diagram showing temporal changes in the lamp voltages generated by the plurality of lamp voltage sources 16. As shown in FIG. The horizontal axis is the elapsed time from when the plurality of lamp voltage sources 16 received the first control signal (hereinafter referred to as sweep time). The origin of the sweep time is the time when the plurality of lamp voltage sources 16 start outputting lamp voltages all at once. The vertical axis is the magnitude of the lamp voltage (ie voltage).

As shown in FIG. 11, the first ramp voltage source R1 (see FIG. 6) increases stepwise from one end (first voltage VL) of the sub-range [VL, V1] to the other end (boundary voltage V1). A ramp voltage RV1 is generated. The generated ramp voltage RV1 is input to SS-ADC1.

The ramp voltage RV1 is increased by the number of times (here, 15 times) corresponding to the number of bits (here, 4 bits) of the low-order bit string (that is, the first low-order bit string) of the first digital signal d1. Reach V1. The voltage per step of the ramp voltage RV1 is a voltage obtained by equally dividing the width (=V1 ^- VL) of the sub-range [VL, V1] by 24. The same applies to lamp voltages RV2 to RV3, which will be described later.

Similarly, the second ramp voltage source R2 generates a ramp voltage RV2 that increases stepwise from one end (boundary voltage V1) of the sub-range [V1, V2] to the other end (boundary voltage V2). The generated ramp voltage RV2 is input to SS-ADC2. Similarly, the third ramp voltage source R3 generates a ramp voltage RV3 that increases stepwise from one end (boundary voltage V2) to the other end (boundary voltage V3) of the sub-range [V2, V3]. The generated ramp voltage RV3 is input to SS-ADC3. Similarly, the fourth ramp voltage source R4 generates a ramp voltage RV4 that increases stepwise from one end (boundary voltage V3) of the sub-range [V3, VH] to the other end (second voltage VH). The generated ramp voltage RV4 is input to SS-ADC4.

On the other hand, when the decision circuit 26 receives the second control signal (not shown), the SS-ADC (for example, SS-ADC3) selected based on the outputs 34 of the first to third comparators is set to high level. Send ADC select signal 36 . On the other hand, a low-level ADC selection signal 36 is sent to the SS-ADCs that have not been selected (eg, SS-ADCs 1, 2, 4).

The SS-ADC (for example, SS-ADC3) that has received the high-level ADC selection signal 36 generates the first lower bit string signal lbs1 based on the ramp voltage (for example, the ramp voltage RV3) and sends it to the digital signal generation circuit 10. Send. The SS-ADCs (eg, SS-ADCs 1, 2, 4) that have received the low-level ADC selection signal 36 do not perform AD conversion.

The upper and lower bit string coupling circuit 28 (see FIG. 8) of the digital signal generation circuit 10 generates the first digital signal d1 based on the received first upper bit string signal hbs1 and the received first lower bit string signal lbs1. Specifically, the first high-order bit string HBS1 (see FIG. 3) included in the first high-order bit string signal hbs1 and the first low-order bit string LBS1 included in the first low-order bit string signal lbs1 are combined to form the first digital signal d1. generated. The generated first digital signal d1 is recorded in the memory 30. FIG.

By the same procedure, the control circuit 12, the i-th upper and lower bit string generation circuit (i is an integer of 2 or more and N or less), and the digital signal generation circuit 10 cooperate to generate an analog signal, which is one of the plurality of detection signals Di. Generate the i-th digital signal di from the signal ai. The generated i-th digital signal di is recorded in the memory 30 .

After that, the control circuit 12 causes the memory 30 to sequentially output the first digital signal d1 to the Nth digital signal dN.

Steps S2 to S6 are repeated until AD conversion for each of a plurality of detection signals Dj (j is an integer from 1 to N) is completed.

If the number of bits of the first digital signal d1 is n, the voltage width ΔV of the first analog signal a1 corresponding to the minimum unit "1b" of the first digital signal d1 is (VH−VL)/ ²ⁿ . . A voltage corresponding to the minimum value "0b" of the first digital signal d1 is VL. The voltage corresponding to the maximum value "11 . . . 1b" of the first digital signal d1 is VH-ΔV.

-Truth Table 38 of Judgment Circuit 26-
FIG. 12 is an example of the truth table 38 of the processing performed by the determination circuit 26 on the first analog signal a1. The first column of the truth table 38 lists the signal level of the output 34 of the first comparator C1. The same applies to the second and third columns of the truth table 38 as well. "H" written in the truth table 38 indicates that the signal level is high. "L" indicates that the signal level is low.

The fourth column of the truth table 38 describes the signal level of the ADC selection signal 36 sent to the SS-ADC1. The same applies to the 5th to 7th columns of the truth table 38 .

The eighth and ninth columns of the truth table 38 describe the first high-order bit string HBS1 included in the first high-order bit string signal hbs1 generated by the determination circuit 26. FIG. The eighth column of the truth table 38 describes the most significant bit of the first high-order bit string HBS1. The ninth column of the truth table 38 describes the least significant bit of the first high-order bit string HBS1. In the example shown in FIG. 12, the number of digits of the first high-order bit string HBS1 is 2 bits.

The second row 40 from the bottom of the truth table 38 indicates that when the outputs 34 of the first and second comparators C1 and C2 are high and the output 34 of the third comparator C3 is low, the ADC selection signal 36 is It shows that only the signal transmitted to SS-ADC 3 is at high level. That is, the second row 40 from the bottom indicates that only the ADC selection signal 36 sent to the SS-ADC 3 is at a high level when the voltage of the first analog signal a1 is higher than the boundary voltage V2 and lower than the boundary voltage V3. showing.

In other words, the second row 40 from the bottom indicates that the SS-ADC 3 generates the first lower bit string signal lbs1 if the voltage of the first analog signal a1 is within a specific sub-range [V2, V3]. indicates that The same applies to rows other than the second from the bottom (that is, the 1st, 3rd and 4th rows from the bottom).

That is, in FIG. 12, each of the plurality of first analog-to-digital converters 18 converts the first low-order bit string signal to lbs1 is generated (see step S4).

FIG. 12 further shows that the specific sub-ranges (hereinafter referred to as first sub-ranges) of each of the plurality of first analog-to-digital converters 18 are different from each other. For example, the fourth row from the bottom of FIG. 12 shows that the first sub-range of SS-ADC1 is [VL, V1], and the third row from the bottom shows that the first sub-range of SS-ADC2 is [V1 , V2]. The second row from the bottom shows that the first sub-range of SS-ADC3 is [V2, V3] and the first row from the bottom shows that the first sub-range of SS-ADC4 is [V3, VH]. It is shown that.

The same applies to a plurality of analog-to-digital converters (hereinafter referred to as a plurality of second analog-to-digital converters) included in the second upper and lower bit string generation circuits bgc2 and the like (see FIG. 4). For example, the second upper and lower bit string generation circuit bgc2 includes a plurality of second analog-to-digital converters, and generates the second lower-order bit string signal lbs2 by any one of the plurality of second analog-to-digital converters. Each of the plurality of second analog-to-digital converters generates a second lower bit string signal lbs2 when the voltage of the second analog signal a2 is within a specific second sub-range of the plurality of sub-ranges. The second sub-ranges of each of the plurality of second analog-to-digital converters are ranges different from each other. The plurality of second analog-to-digital converters is a device different from the plurality of first analog-to-digital converters (that is, the plurality of first analog-to-digital converters included in the first upper and lower bit string generation circuit bgc1).

The second row 40 from the bottom of the truth table 38 further states that when the outputs 34 of the first and second comparators C1 and C2 are high and the output 34 of the third comparator C3 is low, the decision circuit 26 , to generate a first high-order bit string signal hbs1 containing the bit string "10". Other rows of the truth table 38 also show the contents of the first high-order bit string signal hbs1 (that is, the first high-order bit string HBS1) generated by the decision circuit 26 based on the outputs of the first to third comparators C1, C2, and C3. is shown. 12, the determination circuit 26 compares the voltage of the first analog signal a1 with the boundaries V1, V2, and V3 between a plurality of sub-ranges obtained by dividing the ADC range, thereby determining the first high-order bit string signal (see step S2). The same applies to the determination circuit included in the second upper and lower bit string generation circuit bgc2 and the like (see FIG. 4). For example, the determination circuit 26 of the second upper and lower bit string generation circuit bgc2 compares the boundaries V1, V2, and V3 between a plurality of sub-ranges obtained by dividing the ADC range with the voltage of the second analog signal a2. A second high-order bit string signal hbs2 is generated.

By the way, in the example described with reference to FIG. 11 and the like, the number of bits of the first digital signal d1 is 6 bits. On the other hand, the number of bits of the first lower bit string signal lbs1 generated by the plurality of SS-ADCs 18 is 4 bits. Therefore, the frequency of the clock received by the plurality of SS-ADCs 18 (hereinafter referred to as the clock frequency) is the clock frequency of the SS-ADC (hereinafter referred to as the single conversion SS-ADC) that AD-converts the first analog signal a1 independently. can be made much lower. However, it is assumed that the AD conversion speed of the readout circuit 2 (hereinafter referred to as the AD conversion speed) is the same as the AD conversion speed of the single conversion SS-ADC.

The power consumption of the SS-ADC (especially the power consumption of the counter) increases non-linearly as the clock frequency increases. Therefore, the power consumption of multiple SS-ADCs 18 is lower than that of a single conversion SS-ADC. The same applies to the power consumption when AD-converting the second analog signal a2 and the like.

Furthermore, in Embodiment 1, only one of the plurality of SS-ADCs 18 operates when AD-converting the first analog signal a1 (fourth to seventh columns of the truth table 38). reference). Therefore, according to the readout circuit 2 of the first embodiment, power consumption can be further suppressed when AD-converting the plurality of first detection signals D1.

Alternatively, if the clock frequency of the plurality of SS-ADCs 18 is the same as the clock frequency of the single conversion SS-ADC, the AD conversion speed of the readout circuit 2 can be significantly faster than the AD conversion speed of the single conversion SS-ADC. That is, the frame frequency of readout circuit 2 can be significantly increased.

(3) Modification (3-1) Modification 1
In the above example, each of the plurality of first analog-to-digital converters 18 operates only when the voltage of the first analog signal a1 is within a respective specific sub-range (eg, [VL, V1]). However, the plurality of first analog-to-digital converters 18 may operate regardless of whether the voltage of the first analog signal a1 is within their particular sub-range (ie, within the first sub-range).

In this case, the upper and lower bit string combination circuit 28 (see FIG. 8) selects one of the plurality of signals output from the plurality of first analog-to-digital converters 18 based on the first upper bit string signal hbs1 input by the determination circuit 26. to extract the first lower bit string signal lbs1 from . The upper and lower bit string combining circuit 28 combines the extracted first lower bit string included in the first lower bit string signal lbs1 and the first upper bit string included in the first higher bit string signal hbs1 to generate a first digital signal d1.

Even in this case, the power consumption of the SS-ADC increases nonlinearly with respect to the clock frequency. The power consumption of multiple SS-ADCs 18 is low.

(3-2) Modification 2
In the above example, the number of bits of the first high-order bit string HBS1 is 2 bits. However, the number of bits of the first high-order bit string HBS1 may be other than 2 bits. The same applies to the number of bits of the second high-order bit string and the like.

In this case, if the number of bits of the first high-order bit string or the like is m bits ( ^m is an integer other than 2), the number of divisions of the ADC range is 2m. If m is 3 or more, the number of bits of the digital signals generated by the plurality of first analog-to-digital converters 18 is further reduced. Therefore, the power consumption of the readout circuit 2 is further reduced.

If m is 1, the number of first analog-to-digital converters 18 is two, so the configuration of readout circuit 2 is simplified.

(3-3) Modification 3
In the above example, the ADC range is divided equally. However, the ADC range may be divided unevenly. For example, even if the width of the first sub-region when the ADC range is divided equally and the width of the first sub-region when the ADC range is divided unevenly are not equal, the difference between them is the first digital signal d1. is less than 1 bit, the conversion error is less than 1 bit. Therefore, if a conversion error of 1 bit or less is allowed, there is no problem even if the non-uniform division is performed. If the allowed conversion error is larger, even more non-uniform partitioning is not a problem.

According to Modification 3, the degree of freedom in designing the readout circuit 2 is increased.

In the example described with reference to FIG. 11 and the like, the first digital signal d1 to the Nth digital signal dN are 6-bit digital signals. However, the first digital signal d1 to the Nth digital signal dN may be digital signals other than 6-bit digital signals (for example, 14-bit digital signals).

In the above example, the readout circuit 2 has the second upper bit string generator hbg2 through the Nth upper bit string generator hbgN and the second lower bit string generator lbg2 through the Nth lower bit string generator lbgN. However, the readout circuit 2 may not have these units.

The readout circuit 2 of the first embodiment detects, for example, the first high-order bit string HBS1 of the first digital signal d1 with a plurality of comparators 24 and the first low-order bit string LBS1 with a plurality of SS-ADCs 18 . Therefore, since the number of digits of the bit string detected by the plurality of SS-ADCs 18 is reduced, according to the first embodiment, the clock frequency of the plurality of SS-ADCs 18 is reduced to suppress the power consumption of the readout circuit 2. becomes possible.

(Embodiment 2)
The photosensor of the second embodiment is a device having a readout circuit substantially the same as the readout circuit 2 of the first embodiment. Therefore, descriptions of the same configurations and the like as in the first embodiment are omitted or simplified.

(1) Functional Blocks and Operations FIG. 13 is an example of a functional block diagram of optical sensor 100 according to the second embodiment. FIG. 14 is a diagram showing signal flow in the optical sensor 100. As shown in FIG. The photosensor 100 has a first photodetector array pda1 in which a plurality of first photodetectors 101a are arranged in a line, and a readout circuit 102 connected to the first photodetector array pda1. The optical sensor 100 further includes a photodetector array pda (for example, a It has a second photodetector array pda2). The multiple first photodetectors 101a are the multiple photodetectors described in the first embodiment. The same applies to the plurality of second photodetectors 101b and the like.

FIG. 15 is an example of a functional block diagram of readout circuit 102 of the second embodiment. FIG. 16 is a diagram showing the flow of signals in readout circuit 102. Referring to FIG. The readout circuit 102 of the second embodiment has an analog signal generator 107 that generates a plurality of first detection signals D1 from the outputs 105a of the plurality of first photodetectors 101a.

The analog signal generator 107 further generates a plurality of detection signals D (for example, a plurality of to generate a second detection signal D2).

The functional blocks of readout circuit 102 are substantially the same as those of readout circuit 2 of the first embodiment (see FIG. 1), except that readout circuit 102 has analog signal generating section 107 .

(2) Hardware Configuration (2-1) Perspective View of Photosensor 100 FIG. 17 is an example of a perspective view of the photosensor 100 according to the second embodiment. Optical sensor 100 has sensor chip 109 , bumps 111 and readout circuit chip 113 . An image (for example, an infrared image) is formed on the surface of the sensor chip 109 .

(2-2) Sensor chip 109
FIG. 18 is a plan view showing an example of the structure of the sensor chip 109. FIG. As shown in FIG. 18, the sensor chip 109 has a plurality of photodetector arrays pda1 and pda parallel to each other. The multiple photodetector arrays pda1 and pda are multiple one-dimensional sensor arrays arranged such that each photodetector 101 is positioned at a grid point on the sensor chip 109 . That is, sensor chip 109 is a two-dimensional photosensor array.

(2-3) Readout circuit chip 113
(2-3-1) Analog signal generation circuit 110
A read circuit 102 is provided in the read circuit chip 113 (see FIG. 17). FIG. 19 is a diagram showing an example of the hardware configuration of the readout circuit 102. As shown in FIG. The hardware configuration of readout circuit 102 is substantially the same as that of readout circuit 2 of the first embodiment, except that readout circuit 102 includes analog signal generation circuit 110 . However, the control circuit 12 of the second embodiment also controls the analog signal generation circuit 110 in addition to the first upper and lower bit string generation circuit bgc1 and the like.

The analog signal generation section 107 (see FIG. 15) is implemented by the analog signal generation circuit 110 .

-Structure of Analog Signal Generation Circuit 110-
FIG. 20 is a plan view showing an example of the structure of the analog signal generation circuit 110. As shown in FIG. The analog signal generation circuit 110 has a plurality of pixel circuits 115 arranged at grid points on a readout circuit chip 113 (see FIG. 17). A plurality of pixel circuits 115 are arranged to face the photodetectors 101a and 101 (see FIG. 18), respectively, and are connected to the photodetectors 101a and 101 via bumps 111 (see FIG. 17). In FIG. 20, positions of photodetector arrays pda1 and pda including a plurality of photodetectors 101a and 101 are indicated by dashed lines.

The analog signal generation circuit 110 further has a vertical scanning circuit 117 and a plurality of row wirings 119 connected to the vertical scanning circuit 117 . The analog signal generating circuit 110 further has a plurality of column wirings 121 connected to the first upper and lower bit string generating circuit bgc1 to the Nth upper and lower bit string generating circuit bgcN (see FIG. 19). The analog signal generation circuit 110 further has a control line 123 that connects the control circuit 12 (see FIG. 19) and the pixel circuit 115 .

FIG. 21 is a circuit diagram showing an example of the pixel circuit 115. As shown in FIG. Pixel circuit 115 has bias transistor 125 , reset transistor 127 and output transistor 129 . Pixel circuit 115 further includes row select transistor 131 and capacitor 133 .

Also shown in FIG. 21 are photodetectors 101a and 101 located on sensor chip 109. FIG. The output transistor 129 is connected to the load transistor 20 (see FIG. 7) through the row select transistor 131 and the column wiring 121 (see FIG. 21). Output transistor 129 and load transistor 20 form a source follower circuit.

-Operation of Analog Signal Generation Circuit 110-
First, a ground potential (ie, a reference potential) is applied by the control circuit 12 to the gate of the bias transistor 125 (see FIG. 21). The bias transistor 125 then becomes non-conductive, electrically disconnecting the pixel circuit 115 from the photodetectors 101a, 101a. In this state, reset transistor 127 conducts in response to a signal from control circuit 12 (see FIG. 19). Capacitor 133 is then charged to reset potential VR via reset transistor 127 .

Due to this charging, the potential of the capacitor 133 on the reset transistor 127 side becomes substantially the reset potential VR. Thereafter, the signal from control circuit 12 to reset transistor 127 ceases and reset transistor 127 becomes non-conductive.

A bias signal output by control circuit 12 is applied to the gate of bias transistor 125 after reset transistor 127 becomes non-conductive. The voltage of the bias signal is a voltage (=V _B +V _th ) obtained by adding the threshold V _th of the bias transistor 125 to the bias voltage V _B applied to the photodetectors 101 a and 101 . The application of the bias signal causes the bias transistor 125 to conduct, and the bias voltage V _B (=(V _B +V _th )−V _th ) is applied to the photodetectors 101a and 101a.

Then, the charge stored in the capacitor 133 gradually decreases due to the currents output from the photodetectors 101a and 101a. The bias signal continues for a certain period of time and then stops, the control circuit 12 applies the ground potential to the gate of the bias transistor 125 again, and the bias transistor 125 becomes non-conductive.

Charge is lost from capacitor 133 corresponding to the time integral of the current output by photodetectors 101a and 101a while bias transistor 125 is conducting. As a result, a potential corresponding to the intensity of the photocurrent output from the photodetectors 101 a and 101 is generated on the reset transistor 127 side of the capacitor 133 . Specifically, the voltage obtained by subtracting the potential Vc of the reset transistor 127 side of the capacitor 133 from the reset potential VR (=VR-Vc) is approximately proportional to the magnitude of the current output from the photodetectors 101a and 101. .

After bias transistor 125 is rendered non-conductive, row select transistor 131 is rendered conductive by a signal input from vertical scanning circuit 117 via row wiring 119 (see FIG. 20). Output transistor 129 is then connected to load transistor 20 (see FIG. 10) and operates as a source follower transistor. As a result, the potential Vc of the capacitor 133 on the reset transistor 127 side (hereinafter referred to as capacitor voltage Vc) is amplified and input to the first upper and lower bit string generation circuits bgc1 to Nth upper and lower bit string generation circuits bgcN (see FIG. 19). be.

A plurality of pixel circuits 115 (see FIG. 20) are connected to each row wiring 119 . The pixel circuits 115 connected to the same row wiring 119 are respectively connected to separate photodetectors 101a and 101 (see FIG. 18). The output of the amplified capacitor voltage Vc to the column wiring 121 is sequentially performed for each of the plurality of photodetectors 101 a and 101 connected to the same row wiring 119 .

The outputs 105a of the plurality of first photodetectors 101a described with reference to FIG. 14 and the like are currents output by the photodetectors 101a. The multiple first detection signals D1 described with reference to FIG. 16 and the like are the outputs of the pixel circuit 115 (that is, the capacitor voltage Vc amplified by the output transistor 129). The output of pixel circuit 115 is hereinafter referred to as the pixel output. The same applies to the outputs 105b of the plurality of second photodetectors 101b and the like, and the plurality of second detection signals D2 and the like.

The pixel outputs are, for example, generated simultaneously by each pixel circuit 115 of the readout circuit chip 113 (ie, global shutter). A pixel output may be generated sequentially for each of a plurality of pixel circuits 115 connected to the same row wiring 119 (ie rolling shutter).

(2-3-2) Circuits other than the analog signal generation circuit 110 Circuits other than the analog signal generation circuit 110 (see FIG. 19) (for example, the reference voltage generation circuit 6) are implemented as described with reference to FIGS. is substantially the same circuit as the circuit of form 1 of . Here, an example of the hardware configuration of the ramp voltage source 16 (see FIG. 6) and the SS-ADC 1, which were not described in the first embodiment, will be described.

―Hardware Configuration of Ramp Voltage Source―
FIG. 22 is a diagram showing an example of the hardware configuration of the first ramp voltage source R1. FIG. 23 shows the signal flow in the first ramp voltage source R1.

The first ramp voltage source R1 has a counter 137 with the control circuit 12 connected to an enable terminal 135 . The first ramp voltage source R1 further comprises a digital-to-analog converter 139 (hereinafter DAC 139) connected to the counter 137, the first voltage VL and the first buffer circuit B1.

When the first control signal CS1 (see "Embodiment 1") from the control circuit 12 is input to the enable terminal 135, the counter 137 starts counting the clock CR generated by the clock circuit (not shown). . The counter 137 counts the clock CR until the count number CNT reaches ²ⁿ . n is the number of digits such as the first lower bit string LBS1.

The DAC 139 generates a ramp voltage RV1 (see FIG. 11) that increases from the first voltage VL to just before the boundary voltage V1 based on the first voltage VL, the output V1 of the first buffer circuit B1, and the count number CNT of the counter 137. to generate Ramp voltage RV1 is, for example, VL+(CNT-1)*(V1-VL)/ ²ⁿ .

The hardware configuration and operation of the ramp voltage sources other than the first ramp voltage source R1 are substantially the same as the hardware configuration and operation of the first ramp voltage source R1.

-Hardware configuration of SS-ADC1-
FIG. 24 is a diagram showing an example of the hardware configuration of SS-ADC1. FIG. 25 is a diagram showing signal flow in the SS-ADC1.

As shown in FIG. 24, the SS-ADC1 has a comparator 141 whose non-inverting input terminal is connected to the column wiring 121 (see FIG. 21) and whose inverting terminal is connected to the first ramp voltage source R1. The SS-ADC1 further has a counter 143 with an enable terminal 149 connected to the output terminal of the comparator 141 . SS-ADC1 further comprises a switch circuit 145 interposed between the counter 143 and a clock circuit (not shown).

The control circuit 12 (see FIG. 19) controls the SS-ADC 1 via the determination circuit 26 (see FIG. 10) and the like. The control circuit 12 first controls the pixel circuit 115 (see FIG. 20) and the vertical scanning circuit 117 to generate the pixel output po. A pixel output po (see FIG. 25) is input to the non-inverting terminal of the comparator 141 via the column wiring 121 . In the example shown in FIG. 25, the pixel output po is the first analog signal a1.

The control circuit 12 (see FIG. 19) further transmits a second control signal (see "Embodiment 1") to the determination circuit 26 (see FIG. 10) to convert the plurality of first analog-to-digital converters 18 (see FIG. 10). reference). The decision circuit (see FIG. 10) 26 sends a high-level ADC selection signal 36 to the selected first analog-to-digital converter 18, and sends a low-level ADC selection signal 36 to the other first analog-to-digital converters 18. Send. Selection of the first analog-to-digital converter 18 is performed, for example, based on the truth table shown in FIG. Here, it is assumed that the high-level ADC selection signal 36 is sent to SS-ADC1.

The ADC selection signal 36 (see FIG. 25) sent to the SS-ADC1 is input to the switch circuit 145. FIG. When the high level ADC selection signal 36 is input, the switch circuit 145 is closed to connect the counter 143 to the clock circuit.

The control circuit 12 further sends a first control signal CS1 (see FIG. 23) to each of the plurality of ramp voltage sources 16. FIG. A plurality of ramp voltage sources 16 respectively generate ramp voltages RV1 to RV4 in response to the first control signal CS1. The control circuit 12 transmits the first and second control signals so that the timing at which the ramp voltages RV1 to RV4 start to be generated coincides with the timing at which the counter 143 starts counting the clock CR.

The generated ramp voltage RV1 is input to the inverting terminal of the comparator 141 of SS-ADC1. The output 147 of the comparator 141 (hereinafter referred to as the comparator output) remains high until the ramp voltage RV1 exceeds the pixel output po. When ramp voltage RV1 exceeds pixel output po, comparator output 147 goes low.

Counter 143 responds to comparator output 147 by counting clocks CR until ramp voltage RV1 exceeds pixel output po. When the ramp voltage RV1 exceeds the pixel output po, the counter 143 finishes counting the clock CR.

When the ramp voltage RV1 finishes increasing, the counter 143 inputs to the memory 30 a signal containing a bit string (for example, the count number CNT in binary notation) corresponding to the count number CNT at the time when the ramp voltage RV1 exceeds the pixel output po. do. This signal is the first low-order bit string signal lbs1 (see FIG. 10) containing the low-order bit string (that is, the first low-order bit string LBS1) of the first digital signal d1. As is clear from the above description, the first lower bit string LBS1 is, for example, binary notation of the count number CNT at the time when the ramp voltage RV1 exceeds the pixel output po.

The hardware configuration and operation of SS-ADC2 to SS-ADC4 other than SS-ADC1 are also substantially the same as the hardware configuration and operation of SS-ADC1.

As is clear from the above description, the optical sensor 100 (see FIG. 17) of the second embodiment has the readout circuit 102 substantially the same as the readout circuit 2 of the first embodiment. Power consumption of the sensor 100 can be suppressed.

Although the embodiments of the present invention have been described above, the first and second embodiments are illustrative and not restrictive. For example, in Embodiments 1 and 2, the plurality of first analog-to-digital converters 18 are SS-ADCs. However, the plurality of first analog-to-digital converters 18 may be analog-to-digital converters other than SS-ADCs.

For example, the plurality of first analog-to-digital converters 18 are any of a delta-sigma analog-to-digital converter, a successive approximation analog-to-digital converter, a cyclic analog-to-digital converter, and a combination analog-to-digital converter. can be The same applies to the plurality of second analog-to-digital converters and the like.

Furthermore, in Embodiments 1 and 2, the plurality of SS-ADS 18 convert the first analog signal a1 etc. to the first digital signal d1 etc. based on the monotonically increasing ramp voltage. However, the plurality of SS-ADS 18 may convert the first analog signal a1 etc. to the first digital signal d1 etc. based on the monotonically decreasing ramp voltage.

The following additional remarks are disclosed with respect to the first and second embodiments described above.

(Appendix 1)
For each of a plurality of first detection signals generated from outputs of a plurality of first photodetectors, a first analog signal, which is one of the plurality of first detection signals, is set to the voltage of the first analog signal. A reading circuit that performs analog-to-digital conversion for converting into a first digital signal containing a corresponding first bit string,
comparing the voltage of the first analog signal with a boundary between a plurality of sub-ranges obtained by dividing a voltage range from a first voltage to a second voltage different from the first voltage to obtain the first bit string; a first high-order bit string generator for generating a first high-order bit string signal including a first high-order bit string that includes the most significant bit and does not include the least significant bit;
A unit for generating a first lower bit string signal including a portion of said first bit string other than said first upper bit string by any one of a plurality of first analog-to-digital converters, said plurality of first analog-to-digital converters Each converter generates the first lower bit string signal when the voltage of the first analog signal is within a specific first sub-range of the plurality of sub-ranges, and the plurality of first analog a first low-order bit string generator in which the first sub-ranges of each of the digital converters are different from each other;
and a digital signal generator that generates the first digital signal based on the first high-order bit string signal and the first low-order bit string signal.

(Appendix 2)
wherein the first voltage is equal to or lower than the minimum voltage that the plurality of first detection signals can take;
The readout circuit according to appendix 1, wherein the second voltage is equal to or higher than the maximum voltage value that the plurality of first detection signals can take.

(Appendix 3)
Clause 1 or 2, wherein each of said plurality of first analog-to-digital converters is configured to operate only when the voltage of said first analog signal is within said respective first sub-range. The readout circuit described in .

(Appendix 4)
Each of the plurality of first analog-to-digital converters generates the first lower bit string signal based on a ramp voltage that varies from one end to the other end of the first sub-range. 4. The readout circuit according to any one of 3.

(Appendix 5)
Further, for each of the plurality of second detection signals generated from the outputs of the plurality of second photodetectors different from the plurality of first photodetectors, the second detection signal, which is one of the plurality of second detection signals, A reading circuit that performs analog-to-digital conversion for converting two analog signals into a second digital signal that includes a second bit string according to the voltage of the second analog signal,
Furthermore, by comparing the voltage of the second analog signal with the boundary between the plurality of sub-ranges, a second bit string including a second upper bit string including the most significant bit and excluding the least significant bit of the second bit string is obtained. a second high-order bit string generating section, different from the first high-order bit string generating section, for generating a 2 high-order bit string signal;
A unit for generating a second lower bit string signal including a portion of the second bit string other than the second upper bit string by one of a plurality of second analog to digital converters different from the plurality of first analog to digital converters. wherein each of the plurality of second analog-to-digital converters converts the second lower bit string when the voltage of the second analog signal is within a specific second sub-range among the plurality of sub-ranges a second lower bit string generator different from the first lower bit string generator for generating a signal, wherein the second sub-ranges of each of the plurality of second analog-to-digital converters are different from each other;
5. The digital signal generation unit further generates the second digital signal based on the second high-order bit string signal and the second low-order bit string signal. readout circuit.

(Appendix 6)
a plurality of first photodetectors; generating a plurality of first detection signals from outputs of the plurality of first photodetectors; and generating the plurality of first detection signals for each of the generated plurality of first detection signals a readout circuit that performs analog-to-digital conversion for converting a first analog signal, which is one of the signals, into a first digital signal that includes a first bit string according to the voltage of the first analog signal,
The readout circuit has an analog signal generator, a first upper bit string generator, a first lower bit string generator, and a digital signal generator,
The analog signal generator generates the plurality of first detection signals,
The first high-order bit string generation unit divides a voltage range from a first voltage to a second voltage different from the first voltage, and divides the boundaries between a plurality of sub-ranges and the voltage of the first analog signal. generating a first high-order bit string signal including a first high-order bit string including the most significant bit and excluding the least significant bit of the first bit string by comparison;
The first low-order bit string generator generates a first low-order bit string signal including a portion of the first bit string other than the first high-order bit string by one of a plurality of first analog-to-digital converters,
Each of the plurality of first analog-to-digital converters generates the first lower bit string signal when the voltage of the first analog signal is within a specific first sub-range of the plurality of sub-ranges. , the first sub-ranges of each of the plurality of first analog-to-digital converters are different from each other;
The optical sensor, wherein the digital signal generator generates the first digital signal based on the first high-order bit string signal and the first low-order bit string signal.

2, 102: readout circuit 4: digital signal generator 18: first analog-to-digital converter 100: optical sensor 101a: first photodetector 101b: second photodetector 102: readout circuit 107: analog signal generator BS1: First bit string D1: First detection signal D2: Second detection signal HBS1: First upper bit string LBS1: First lower bit string a1: First analog signal a2: Second analog signal d1: First digital signal d2: Second digital Signal hbg1: first high-order bit string generator hbg2: second high-order bit string generator lbg1: first low-order bit string generator lbg2: second low-order bit string generator

Claims (5)

For each of a plurality of first detection signals generated from outputs of a plurality of first photodetectors, a first analog signal, which is one of the plurality of first detection signals, is set to the voltage of the first analog signal. A reading circuit that performs analog-to-digital conversion for converting into a first digital signal containing a corresponding first bit string,
comparing the voltage of the first analog signal with a boundary between a plurality of sub-ranges obtained by dividing a voltage range from a first voltage to a second voltage different from the first voltage to obtain the first bit string; a first high-order bit string generator for generating a first high-order bit string signal including a first high-order bit string that includes the most significant bit and does not include the least significant bit;
A unit for generating a first lower bit string signal including a portion of said first bit string other than said first upper bit string by any one of a plurality of first analog-to-digital converters, said plurality of first analog-to-digital converters Each converter generates the first lower bit string signal when the voltage of the first analog signal is within a specific first sub-range of the plurality of sub-ranges, and the plurality of first analog a first low-order bit string generator in which the first sub-ranges of each of the digital converters are different from each other;
and a digital signal generator that generates the first digital signal based on the first high-order bit string signal and the first low-order bit string signal. 2. The method of claim 1, wherein each of said plurality of first analog-to-digital converters is configured to operate only when the voltage of said first analog signal is within said respective first sub-range. Readout circuit as described. 2. Each of the plurality of first analog-to-digital converters generates the first low-order bit string signal based on a ramp voltage varying from one end to the other end of the first sub-range. 3. or the readout circuit according to 2. Further, for each of the plurality of second detection signals generated from the outputs of the plurality of second photodetectors different from the plurality of first photodetectors, the second detection signal, which is one of the plurality of second detection signals, A reading circuit that performs analog-to-digital conversion for converting two analog signals into a second digital signal that includes a second bit string according to the voltage of the second analog signal,
Furthermore, by comparing the voltage of the second analog signal with the boundary between the plurality of sub-ranges, a second bit string including a second upper bit string including the most significant bit and excluding the least significant bit of the second bit string is obtained. a second high-order bit string generating section, different from the first high-order bit string generating section, for generating a 2 high-order bit string signal;
A unit for generating a second lower bit string signal including a portion of the second bit string other than the second upper bit string by one of a plurality of second analog to digital converters different from the plurality of first analog to digital converters. wherein each of the plurality of second analog-to-digital converters converts the second lower bit string when the voltage of the second analog signal is within a specific second sub-range among the plurality of sub-ranges a second lower bit string generator different from the first lower bit string generator for generating a signal, wherein the second sub-ranges of each of the plurality of second analog-to-digital converters are different from each other;
4. The digital signal generator according to any one of claims 1 to 3, wherein the digital signal generator further generates the second digital signal based on the second high-order bit string signal and the second low-order bit string signal. readout circuit. a plurality of first photodetectors; generating a plurality of first detection signals from outputs of the plurality of first photodetectors; and generating the plurality of first detection signals for each of the generated plurality of first detection signals a readout circuit that performs analog-to-digital conversion for converting a first analog signal, which is one of the signals, into a first digital signal that includes a first bit string according to the voltage of the first analog signal,
The readout circuit has an analog signal generator, a first upper bit string generator, a first lower bit string generator, and a digital signal generator,
The analog signal generator generates the plurality of first detection signals,
The first high-order bit string generation unit divides a voltage range from a first voltage to a second voltage different from the first voltage, and divides the boundaries between a plurality of sub-ranges and the voltage of the first analog signal. generating a first high-order bit string signal including a first high-order bit string including the most significant bit and excluding the least significant bit of the first bit string by comparison;
The first low-order bit string generator generates a first low-order bit string signal including a portion of the first bit string other than the first high-order bit string by one of a plurality of first analog-to-digital converters,
Each of the plurality of first analog-to-digital converters generates the first lower bit string signal when the voltage of the first analog signal is within a specific first sub-range of the plurality of sub-ranges. , the first sub-ranges of each of the plurality of first analog-to-digital converters are different from each other;
The optical sensor, wherein the digital signal generator generates the first digital signal based on the first high-order bit string signal and the first low-order bit string signal.

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