JP2022107114A - Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus - Google Patents

Abstract

To achieve a high-power semiconductor device with excellent linearity.SOLUTION: A semiconductor device 1A includes: an electron transit layer 10; and an electron supply layer 20 provided on one surface 10a of the electron transit layer 10. A gate electrode 30 is provided on an opposite surface 20a side to the electron transit layer 10 side, of the electron supply layer 20. A dielectric layer 40A comprising a dielectric section 40a and a dielectric section 40b with different thicknesses is provided between the surface 20a of the electron supply layer 20 and the gate electrode 30. Thereby, there can be obtained the semiconductor device 1A in which a plurality of types of transistor structures having different characteristics such as thresholds and mutual conductance are combined. This enables processing of the electron supply layer 20 and the like, and suppresses reduction in output caused by the processing, and thus, achieves combination of transistor structures with different characteristics by the dielectric layer 40A having portions with different thicknesses. Therefore, the mutual conductance of the semiconductor device 1A is flattened to improve the linearity.SELECTED DRAWING: Figure 3

Description

The present invention relates to semiconductor devices, methods for manufacturing semiconductor devices, and electronic devices.

A GaN-based heterostructure field effect transistor (HFET) using a nitride semiconductor such as GaN (gallium nitride) or AlGaN (aluminum gallium nitride) is known. As GaN-based HFETs, in addition to an insulating gate HFET using an insulating film such as SiO (silicon oxide) or SiN (silicon nitride), an insulating gate HFET using a two-layer insulating film in which AlO (aluminum oxide) is laminated on SiN is available. Are known.

Japanese Unexamined Patent Publication No. 2004-311961

By the way, a semiconductor device using a nitride semiconductor such as GaN for the electron traveling layer and a nitride semiconductor such as AlGaN for the electron supply layer, for example, an electric field effect of a high electron mobility transistor (HEMT) or the like. Regarding a transistor, linearity is one of the indexes showing its performance. For example, in a semiconductor device used for amplification, by enhancing its linearity, distortion of the signal after amplification can be suppressed, and deterioration of signal quality can be suppressed.

As a technique for obtaining good linearity, a technique for combining a plurality of transistor structures having different characteristics such as threshold value and transconductance is known. For example, in a semiconductor device in which a gate electrode is provided on an electron supply layer laminated on an electron traveling layer, a technique of providing a plurality of regions having different thicknesses of the electron supply layer under the gate electrode, or an electron traveling layer under the gate electrode. And a technique for providing a plurality of regions having different widths of the electron supply layer is known.

However, with the conventional techniques, it may be difficult to realize a semiconductor device having sufficient linearity and output, for example, the output may be reduced by adopting the technique.
In one aspect, the present invention aims to realize a high output semiconductor device having excellent linearity.

In one embodiment, the electron traveling layer, the electron supply layer provided on the first surface side of the electron traveling layer, and the electron supplying layer are provided on the second surface side of the electron traveling layer opposite to the electron traveling layer side. A first dielectric portion provided between the gate electrode and the second surface of the electron supply layer and the gate electrode, and having a first thickness in the first direction from the second surface toward the gate electrode. A semiconductor device including a dielectric layer including a second dielectric portion having a second thickness thicker than the first thickness in the first direction is provided.

In another aspect, a method for manufacturing a semiconductor device as described above and an electronic device including the semiconductor device as described above are provided.

On one side, it is possible to realize a high output semiconductor device having excellent linearity.

It is a figure (the 1) explaining the example of the linearity improvement technique of a semiconductor device. It is a figure (the 2) explaining the example of the linearity improvement technique of a semiconductor device. It is a figure explaining an example of the semiconductor device which concerns on 1st Embodiment. It is a figure (the 1) explaining an example of the combination of a transistor structure. It is a figure (the 2) explaining an example of the combination of a transistor structure. It is a figure (the 1) explaining an example of the forming method of the semiconductor device which concerns on 1st Embodiment. It is a figure (the 2) explaining an example of the forming method of the semiconductor device which concerns on 1st Embodiment. FIG. 3 is a diagram (No. 3) for explaining an example of a method for forming a semiconductor device according to the first embodiment. It is a figure (the 4) explaining an example of the forming method of the semiconductor device which concerns on 1st Embodiment. FIG. 5 is a diagram (No. 5) for explaining an example of a method for forming a semiconductor device according to the first embodiment. It is a figure explaining another configuration example of the semiconductor device which concerns on 1st Embodiment. It is a figure explaining an example of the semiconductor device which concerns on 2nd Embodiment. It is a figure (the 1) explaining an example of the forming method of the semiconductor device which concerns on 2nd Embodiment. It is a figure (the 2) explaining an example of the forming method of the semiconductor device which concerns on 2nd Embodiment. FIG. 3 is a diagram (No. 3) for explaining an example of a method for forming a semiconductor device according to a second embodiment. It is a figure (the 4) explaining an example of the forming method of the semiconductor device which concerns on 2nd Embodiment. FIG. 5 is a diagram (No. 5) for explaining an example of a method for forming a semiconductor device according to a second embodiment. It is a figure explaining an example of the semiconductor device which concerns on 3rd Embodiment. It is a figure explaining an example of the semiconductor package which concerns on 4th Embodiment. It is a figure explaining an example of the power factor improvement circuit which concerns on 5th Embodiment. It is a figure explaining an example of the power supply device which concerns on 6th Embodiment. It is a figure explaining an example of the amplifier which concerns on 7th Embodiment.

Semiconductor devices using nitride semiconductors have been developed as high withstand voltage and high output devices by utilizing features such as high saturated electron velocity and wide band gap. As a semiconductor device using a nitride semiconductor, many reports have been made on field effect transistors such as HEMTs.

As one of the HEMTs, a HEMT using an AlGaN layer as an electron supply layer (also referred to as a "barrier layer") and a GaN layer as an electron traveling layer (also referred to as a "channel layer") is known. In such a HEMT, due to the spontaneous polarization of the AlGaN layer and the piezo polarization generated in the AlGaN layer due to the strain caused by the difference in lattice constant with the GaN layer, the GaN layer near the junction interface with the AlGaN layer has a high concentration of two dimensions. Two Dimensional Electron Gas (2DEG) is generated to realize a high power device. Therefore, HEMTs using GaN-based nitride semiconductors are expected to be applied to high-power amplifiers for communication and the like.

Linearity is one of the performances required for high-power amplifiers for communication. If an amplifier with poor linearity is used, the amplified signal will be distorted, resulting in deterioration of communication quality. By improving the linearity of the HEMT used for amplification, distortion of the signal after amplification can be suppressed, and deterioration of communication quality can be suppressed.

Flattening the transconductance is effective in obtaining good linearity. As a technique for flattening transconductance and obtaining good linearity, a technique (derivative superposition technique) for combining a plurality of transistor structures having different characteristics such as threshold value and transconductance is known.

1 and 2 are diagrams for explaining an example of a technique for improving the linearity of a semiconductor device. FIG. 1 schematically shows an example of the relationship between the gate voltage and the transconductance. FIG. 2A schematically shows a cross-sectional view of a main part of an example of a semiconductor device adopting the first linearity improving technique. FIG. 2B schematically shows a cross-sectional view of a main part of an example of a semiconductor device adopting the second linearity improving technique.

FIG. 1 schematically shows an example of the relationship between the gate voltage of three types of transistor structures P, Q, and R having different thresholds and transconductance and the transconductance. Here, the transistor structure P (dotted line P in FIG. 1) has a relatively low threshold value and a relatively large transconductance. The transistor structure Q (dotted line Q in FIG. 1) has a higher threshold value in the positive direction than the transistor structure P and a smaller transconductance than the transistor structure P. The transistor structure R (dotted line R in FIG. 1) has a higher threshold value in the positive direction than the transistor structure Q and a smaller transconductance than the transistor structure P. When the transistor structures P, Q, and R are combined, the combination (solid line P + Q + R in FIG. 1) is such that the transconductance is flattened as compared with the case where the respective transistor structures P, Q, and R are adopted alone. Become. That is, in the combination of the transistor structures P, Q, and R, the half width of the relationship between the gate voltage and the transconductance is widened, and the region where the transconductance becomes higher than a certain level with respect to the gate voltage becomes wider.

As a structure of a semiconductor device in which three types of transistor structures P, Q, and R having different threshold values and transconductances are combined, for example, there is one as shown in FIG. 2 (A).
The semiconductor device 100 shown in FIG. 2 (A) is an example of HEMT. The semiconductor device 100 includes an electron traveling layer 110, an electron supply layer 120 provided on the electron traveling layer 110, and a gate electrode 130 provided on the electron supply layer 120. The gate electrode 130 is provided between the source electrode and the drain electrode (not shown) separately from them. FIG. 2A schematically shows a cross section along a direction in which the gate electrode 130 extends (a direction orthogonal to the gate length direction (gate width direction), which is a direction in which the source electrode and the drain electrode face each other). Is.

In the semiconductor device 100, a nitride semiconductor such as GaN is used for the electron traveling layer 110, and a nitride such as AlGaN having a larger bandgap than the nitride semiconductor used for the electron traveling layer 110 is used for the electron supply layer 120. Semiconductors are used. In the semiconductor device 100, the electrons in the vicinity of the junction interface with the electron supply layer 120 due to the spontaneous polarization of the electron supply layer 120 and the piezo polarization generated in the electron supply layer 120 due to the strain caused by the difference in lattice constant from the electron traveling layer 110. 2DEG300 is generated in the traveling layer 110. In the semiconductor device 100, the amount of electric charge of the 2DEG 300 passing under the gate electrode 130 is controlled by the electric field effect due to the gate voltage applied to the gate electrode 130, and the magnitude of the output drain current is controlled.

The semiconductor device 100 has a structure in which a plurality of stepped regions having different thicknesses of the electron supply layer 120 in the stacking direction of the electron traveling layer 110 and the electron supply layer 120 are provided under the gate electrode 130. The structure of such a semiconductor device 100 is also referred to as a "multi-stage gate recess type". In the semiconductor device 100, the region where the thickness of the electron supply layer 120 is the minimum (region P in FIG. 2A) corresponds to the region of the transistor structure P. The region where the thickness of the electron supply layer 120 is intermediate (region Q in FIG. 2A) corresponds to the region of the transistor structure Q. The region where the thickness of the electron supply layer 120 is maximum (region R in FIG. 2A) corresponds to the region of the transistor structure R. By providing a plurality of stepped regions having different thicknesses of the electron supply layer 120 in this way, for example, three types of transistor structures P, Q, and R having different characteristics are provided, and flattened transconductance (FIG. A semiconductor device 100 having a solid line P + Q + R) of 1 is realized.

Further, as another structure of the semiconductor device in which three types of transistor structures P, Q, and R having different threshold values and transconductances are combined, for example, there is one as shown in FIG. 2 (B).
The semiconductor device 200 shown in FIG. 2B is an example of a HEMT. The semiconductor device 200 includes an electron traveling layer 210, an electron supply layer 220 provided on the electron traveling layer 210, and a gate electrode 230 provided on the electron supply layer 220. The gate electrode 230 is provided between the source electrode and the drain electrode (not shown) separately from the source electrode and the drain electrode (not shown). FIG. 2B schematically shows a cross section along the direction in which the gate electrode 230 extends (the gate width direction orthogonal to the gate length direction).

In the semiconductor device 200, a nitride semiconductor such as GaN is used for the electron traveling layer 210, and a nitride semiconductor such as AlGaN is used for the electron supply layer 220. In the semiconductor device 200, the electrons in the vicinity of the junction interface with the electron supply layer 220 due to the spontaneous polarization of the electron supply layer 220 and the piezo polarization generated in the electron supply layer 220 due to the strain caused by the difference in lattice constant with the electron traveling layer 210. 2DEG300 is generated in the traveling layer 210. In the semiconductor device 200, the amount of electric charge of the 2DEG 300 passing under the gate electrode 230 is controlled by the electric field effect due to the gate voltage applied to the gate electrode 230, and the magnitude of the output drain current is controlled.

The semiconductor device 200 has a structure in which a part of the surface layer of the electron traveling layer 210 and a plurality of fin-shaped regions having different widths of the electron supply layer 220 laminated on the surface layer are provided under the gate electrode 230. The structure of such a semiconductor device 200 is also referred to as a "fin type". In the semiconductor device 200, a part of the surface layer of the electron traveling layer 210 and the region where the width of the electron supply layer 220 laminated on the surface layer is the smallest (region P in FIG. 2B) corresponds to the region of the transistor structure P. .. A part of the surface layer of the electron traveling layer 210 and a region (region Q of FIG. 2B) in which the width of the electron supply layer 220 laminated on the surface layer is intermediate corresponds to the region of the transistor structure Q. A part of the surface layer of the electron traveling layer 210 and the region where the width of the electron supply layer 220 laminated therewith is maximum (region R in FIG. 2B) corresponds to the region of the transistor structure R. By providing a part of the surface layer of the electron traveling layer 210 and a plurality of fin-shaped regions having different widths of the electron supply layer 220 laminated thereto, for example, three types of transistor structures P and Q having different characteristics are provided. , R, and a semiconductor device 200 having flattened transconductance (solid line P + Q + R in FIG. 1) is realized.

Regarding the linearity of semiconductor devices, for example, techniques described in International Publication No. 2019/077784 Pamphlet, International Publication No. 2019/077781 Pamphlet and the like are also known.

However, the semiconductor device 100 adopting the multi-stage gate recess type structure and the semiconductor device 200 adopting the fin type structure as described above have the following problems, respectively.
In the semiconductor device 100 (FIG. 2A) that employs a multi-stage gate recess type structure, the electron supply layer 120 is provided with a plurality of stepped regions having different thicknesses, and the electron supply layer 120 is provided with the electron traveling layer 110. It needs to be processed after epitaxial growth to the top. In the semiconductor device 100, the output of the semiconductor device 100 may decrease due to the damage introduced into the electron supply layer 120 during this processing. Further, in the semiconductor device 100, variations in the processing depth of the electron supply layer 120 of several nm affect the characteristics of the semiconductor device 100, so that sufficient manufacturing reproducibility may not be obtained.

Further, in the semiconductor device 200 (FIG. 2B) adopting the fin-type structure, epitaxially grown electron traveling is provided in order to provide a plurality of fin-shaped regions having different widths of the electron traveling layer 210 and the electron supply layer 220. It is necessary to process the layer 210 and the electron supply layer 220. In the semiconductor device 200, the output of the semiconductor device 200 may decrease due to the damage introduced into the electron traveling layer 210 and the electron supply layer 220 during this processing. Further, in the semiconductor device 200, by dividing the electron traveling layer 210 and the electron supply layer 220 into a plurality of fin-shaped regions, the effective channel width is reduced, which causes a decrease in the output of the semiconductor device 200. There is a fear.

With conventional linearity improvement techniques, it has sometimes been difficult to realize a semiconductor device having sufficient linearity and output.
In view of the above points, here, a configuration as shown in the following embodiments is adopted to realize a high-output semiconductor device having excellent linearity.

[First Embodiment]
FIG. 3 is a diagram illustrating an example of a semiconductor device according to the first embodiment. FIG. 3A schematically shows a plan view of a main part of an example of the semiconductor device according to the first embodiment. FIG. 3B schematically shows a cross-sectional view of a main part of an example of the semiconductor device according to the first embodiment. FIG. 3B is a schematic cross-sectional view taken along the line III-III of FIG. 3A.

The semiconductor device 1A shown in FIGS. 3 (A) and 3 (B) is an example of HEMT. The semiconductor device 1A includes an electron traveling layer 10, an electron supply layer 20, a dielectric layer 40A, a gate electrode 30, a source electrode 50, and a drain electrode 60.

A nitride semiconductor, for example, GaN is used for the electron traveling layer 10. In addition to GaN, a nitride semiconductor such as AlGaN or InGaN (indium gallium nitride) may be used for the electron traveling layer 10. The electron traveling layer 10 may have a single-layer structure of one kind of nitride semiconductor, or may have a laminated structure of one kind or two or more kinds of nitride semiconductors. The electron traveling layer 10 is predetermined by using, for example, the Metal Organic Chemical Vapor Deposition (MOCVD or Metal Organic Vapor Phase Epitaxy; MOVPE) method or the Molecular Beam Epitaxy (MBE) method. It is formed on the base substrate (not shown) of. The base substrate on which the electronic traveling layer 10 is formed includes a substrate such as SiC (silicon carbide), Si (silicon), sapphire, GaN, AlN (aluminum nitride), diamond, or AlN, GaN, AlGaN, etc. on the substrate. A substrate on which an initial layer having a single-layer structure or a laminated structure of two or more of them is formed can be used.

A nitride semiconductor, for example, AlGaN is used for the electron supply layer 20. In addition to AlGaN, nitride semiconductors such as InAlN (indium aluminum nitride), InAlGaN (indium aluminum gallium nitride), AlN, and ScAlN (scandium aluminum nitride) may be used for the electron supply layer 20. The electron supply layer 20 may have a single-layer structure of one type of nitride semiconductor, or may have a laminated structure of one type or two or more types of nitride semiconductors. The electron supply layer 20 is provided on one surface 10a side of the electron traveling layer 10 by using the MOVPE method or the like.

Here, nitride semiconductors having different band gaps are used for the electron traveling layer 10 and the electron supply layer 20. By providing the electron supply layer 20 using a nitride semiconductor having a band gap larger than that on the electron traveling layer 10, a heterojunction structure having a band discontinuity is formed. By setting the Fermi level above the conduction band (high energy side) of the junction interface between the electron traveling layer 10 and the electron supply layer 20, 2DEG) 70 is generated in the electron traveling layer 10 near the junction interface. Will be done. 2DEG70 is generated in the electron traveling layer 10 near the bonding interface by the spontaneous polarization of the nitride semiconductor used in the electron supply layer 20 and the piezoelectric polarization generated due to its lattice constant. For the electron traveling layer 10 and the electron supply layer 20, a nitride semiconductor having a combination such that such 2DEG70 is generated is used in the vicinity of the junction interface of the electron traveling layer 10 with the electron supply layer 20.

Although not shown here, a spacer layer using a nitride semiconductor such as AlGaN, InGaN, or AlN may be interposed between the electron traveling layer 10 and the electron supply layer 20. Further, a cap layer using a nitride semiconductor such as GaN may be provided on the electron supply layer 20.

The dielectric layer 40A is provided on the surface 20a side of the electron supply layer 20 opposite to the electron traveling layer 10 side. The dielectric layer 40A includes a plurality of insulating films, in this example, a two-layer insulating film of the insulating film 41 and the insulating film 42 laminated on the insulating film 41. For the insulating film 41 and the insulating film 42, for example, insulating materials different from each other are used.

The insulating film 41 of the dielectric layer 40A is provided in a part of the region on the electron supply layer 20. For example, the insulating film 41 is provided so as to have one or two or more (here, four as an example) openings 41a leading to the electron supply layer 20. The insulating film 41 includes, for example, one or a mixture of two or more of SiN, AlO, AlN, SiO, HfO (hafnium oxide), ZrO (zirconium oxide), LaO (lanthanum oxide), and TaO (tantalum oxide). Is used.

The insulating film 42 of the dielectric layer 40A is provided in a part of the region on the insulating film 41. For example, the insulating film 42 is provided so as to have one or two or more (here, four as an example) openings 42a leading to the insulating film 41 and the electron supply layer 20. The opening 42a of the insulating film 42 is provided so as to include, for example, the opening 41a of the insulating film 41 and a part of the insulating film 41 outside the opening 41a in a plan view. For the insulating film 42, for example, one or a mixture of two or more of SiN, AlO, AlN, SiO, HfO, ZrO, LaO, and TaO is used. For the insulating film 42, for example, an insulating material different from the insulating material used for the insulating film 41 is used.

The insulating film 41 and the insulating film 42 are formed by using a plasma chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, or the like, depending on the type of insulating material used therein. It is formed. The insulating film 41 is formed by selective etching to obtain a high etching selectivity with respect to the electron supply layer 20, and is provided in a part of the region on the electron supply layer 20. The insulating film 42 is formed by selective etching with which a high etching selectivity can be obtained with respect to the electron supply layer 20 and the insulating film 41, or with respect to the insulating film 41 among them, and a part of the insulating film 41 is formed on the insulating film 41. Provided in the area. For the selective etching of the insulating film 41 and the insulating film 42, dry etching or wet etching can be used depending on the type of insulating material used therein and the nitride semiconductor of the electron supply layer 20.

The dielectric layer 40A is provided with the electron traveling layer 10 and electrons by means of an insulating film 41 provided in a part of the electron supply layer 20 and an insulating film 42 provided in a part of the insulating film 41. The dielectric portions 40a and the dielectric portions 40b having different thicknesses in the stacking direction D1 of the layer 20 (the direction from the surface 20a of the electron supply layer 20 toward the gate electrode 30) are formed. That is, the dielectric layer 40A includes a dielectric portion 40a having a single-layer film of the insulating film 41 and a dielectric portion 40b having a laminated film of the insulating film 41 and the insulating film 42. The dielectric portion 40a has a thickness corresponding to the thickness of the single-layer insulating film 41, and the dielectric portion 40b has a thickness corresponding to the total thickness of the laminated insulating film 41 and the insulating film 42. Has. In this example, the dielectric portion 40b is thicker than the dielectric portion 40a by the thickness of the insulating film 42.

The gate electrode 30, the source electrode 50, and the drain electrode 60 are provided on the surface 20a side of the electron supply layer 20 in which the dielectric layer 40A is provided. A gate electrode 30 is provided between the source electrode 50 and the drain electrode 60, which are provided so as to be separated from each other and face each other, separated from the source electrode 50 and the drain electrode 60. A metal material is used for the gate electrode 30, the source electrode 50, and the drain electrode 60. For the gate electrode 30, for example, a laminate of Ni (nickel) and Au (gold) provided on the Ni (nickel) is used. For the source electrode 50 and the drain electrode 60, for example, a laminate of Ti (titanium) and Al (aluminum) provided on the Ti (titanium) is used. The gate electrode 30, the source electrode 50, and the drain electrode 60 are formed by using a vapor deposition method or the like.

In the semiconductor device 1A, for example, as shown in FIG. 3A, a so-called asymmetric structure is adopted in which the distance between the gate electrode 30 and the drain electrode 60 is wider than the distance between the gate electrode 30 and the source electrode 50. You may. By adopting the asymmetric structure, the electric field between the gate electrode 30 and the drain electrode 60 can be relaxed and the withstand voltage can be improved.

In the semiconductor device 1A, the source electrode 50 and the drain electrode 60 are provided so as to function as ohmic electrodes. The source electrode 50 and the drain electrode 60 may be connected to the electron supply layer 20 or may be connected to the electron traveling layer 10 through the electron supply layer 20 as long as they function as ohmic electrodes. A contact layer (re-growth layer) using a nitride semiconductor such as n-type GaN or n-type AlGaN is provided in the electron supply layer 20 or the electron traveling layer 10 to which the source electrode 50 and the drain electrode 60 are connected. It may be provided.

The gate electrode 30 is an electron supply of the dielectric layer 40A on the dielectric portions 40a (the insulating film 41) and the dielectric portions 40b (the insulating film 42) having different thicknesses, and on which the dielectric layer 40A is not provided. It is provided on the layer 20 (its surface 20a). The dielectric layer 40A is a cross-sectional view of the gate electrode 30 and the electron supply layer 20 in the gate width direction D3 orthogonal to the gate length direction D2 (the direction in which the source electrode 50 and the drain electrode 60 face each other). A dielectric portion 40a and a dielectric portion 40b having different thicknesses are provided between them. As shown in FIG. 3A, for example, the edge of the gate electrode 30 is from the edge of the opening 41a of the insulating film 41 of the dielectric layer 40A and the edge of the opening 42a of the insulating film 42 in the gate length direction D2. Is provided in a size that is inside.

The surface 20a of the electron supply layer 20 in the region overlapping the gate electrode 30 has high flatness and is parallel to the surface 10a of the electron traveling layer 10 on which the electron supply layer 20 is laminated. The surface 20a of 20 is not provided with recesses such as steps and holes.

In the region 80 where the gate electrode 30 is provided on the electron supply layer 20 in which the dielectric layer 40A is not provided, the electron supply layer 20 and the gate electrode 30 are in contact with each other, and the gate electrode 30 is shotkey connected. It becomes an area. When another nitride semiconductor such as a cap layer is provided on the electron supply layer 20, the nitride semiconductor and the gate electrode 30 are in contact with each other, and the gate electrode 30 is Schottky connected. The region 81 in which the gate electrode 30 is provided on the electron supply layer 20 via the dielectric portion 40a and the region 82 in which the gate electrode 30 is provided on the electron supply layer 20 via the dielectric portion 40b are MIS (Metal Insulator). Semiconductor) It becomes the area of the gate. As described above, in the semiconductor device 1A, the region 80 of the Schottky gate in which the gate electrode 30 is provided in contact with the electron supply layer 20 and the dielectric portions 40a and the dielectric portions 40b having different thicknesses are provided on the electron supply layer 20. It has a region 81 and a region 82 of the MIS gate on which the gate electrode 30 is provided. That is, the semiconductor device 1A is provided with a combination of three types of transistor structures having different characteristics from each other.

In the semiconductor device 1A, a transistor structure exhibiting different current-voltage characteristics from each other in a region 80 in which the dielectric layer 40A is not provided, and a region 81 and a region 82 in which the dielectric portions 40a and the dielectric portions 40b having different thicknesses are interposed. Is realized. For example, in the semiconductor device 1A, a transistor structure in which the threshold value and the transconductance are different from each other is realized by the region 80, the region 81, and the region 82. In the semiconductor device 1A, by providing a combination of transistor structures having different characteristics from each other, it is possible to flatten the transconductance and thereby improve the linearity. In the case of combination, the area ratio occupied by each of the region 80 (the electron supply layer 20), the region 81 (the insulating film 41) and the region 82 (the laminated film of the insulating films 41 and 42) with respect to the gate electrode 30 is It will be adjusted. This adjusts the degree of flattening of the transconductance and the degree of improvement in linearity.

Here, the combination of transistor structures will be described.
4 and 5 are diagrams for explaining an example of a combination of transistor structures. FIG. 4A schematically shows an example of the relationship between the gate voltage and the transconductance of a transistor structure having a Schottky gate. FIG. 4B schematically shows an example of the relationship between the gate voltage and the transconductance of a transistor structure having a MIS gate. FIG. 4C schematically shows another example of the relationship between the gate voltage and the transconductance of a transistor structure having a MIS gate. FIG. 5 schematically shows an example of the relationship between the gate voltage and the transconductance when a combination of transistor structures having different characteristics is assumed.

FIG. 4A is an example of the relationship between the gate voltage and the transconductance of a transistor structure having a Schottky gate in which a dielectric layer is not interposed between the gate electrode and the electron supply layer. FIG. 4B shows an example of the relationship between the gate voltage and the transconductance of a transistor structure having a MIS gate in which a single layer film of SiN having a thickness of 8 nm is interposed between the gate electrode and the electron supply layer. be. FIG. 4C shows a MIS gate in which a laminated film (AlO / SiN) of AlO having a thickness of 2 nm and SiN having a thickness of 8 nm laminated on the gate electrode is interposed between the gate electrode and the electron supply layer. This is an example of the relationship between the gate voltage and the transconductance of the transistor structure having the above.

From FIGS. 4 (A) to 4 (C), it can be seen that the threshold value of the transistor structure having the MIS gate is shifted in the negative direction as compared with the transistor structure having the Schottky gate. This is because the distance from the gate electrode to the 2DEG generated in the electron traveling layer near the junction interface with the electron supply layer is longer in the transistor structure having the MIS gate than in the transistor structure having the Schottky gate. In addition, the increase in the carrier density of 2DEG has an effect. Further, when comparing the threshold values of the two types of transistor structures having the MIS gate from FIGS. 4 (B) and 4 (C), the AO / SiN stacking is compared with that of the SiN single layer film (FIG. 4 (B)). It can be seen that the threshold value of the membrane (FIG. 4 (C)) is shifted in the positive direction. It is considered that this is because the threshold value is shifted in the positive direction as a result of the generation of positive fixed charges due to the oxygen vacancies in AlO.

Assuming a combination of these three types of transistor structures, that is, a transistor structure having a Schottky gate and two types of transistor structures having a MIS gate, an example of the result of adding the characteristics of the three types of transistor structures is shown in the figure. Shown in 5. In the combination, the area ratio of each transistor structure is 20% for the transistor structure having a shotkey gate, 30% for the transistor structure having a MIS gate using a single layer film of SiN, and MIS using a laminated film of AlO / SiN. The transistor structure having a gate is 50%.

From FIG. 5, when a transistor structure having a shotkey gate and two types of transistor structures having a MIS gate are combined in a predetermined area ratio, the transconductance is relatively flattened as compared with the case of each transistor structure alone. You can see that. The smaller the value of the second derivative of transconductance, the better the value of the third-order intercept point, which is an index of linearity. From the characteristics of FIG. 5, when three types of transistor structures are combined, the value of the quadratic differential of the transconductance is 100 mS / V ^2. mm, and the transistor structure having a Schottky gate is 600 mS / V ^2. mm. The value is lower than that of 200 mS / V ^2. mm of two types of transistor structures having a MIS gate. Therefore, it can be said that the linearity can be improved by combining a transistor structure having a Schottky gate and two types of transistor structures having a MIS gate in a predetermined area ratio.

In the semiconductor device 1A, a shotkey gate is formed in a region 80 in which the dielectric layer 40A is not interposed between the electron supply layer 20 and the gate electrode 30. MIS gates are formed in the regions 81 and 82 in which the dielectric portions 40a and the dielectric portions 40b having different thicknesses are interposed, respectively. As a result, the semiconductor device 1A is provided with a combination of three types of transistor structures having different characteristics from each other. In such a semiconductor device 1A, the area ratio of the region 80 (the electron supply layer 20), the region 81 (the insulating film 41) and the region 82 (the laminated film of the insulating films 41 and 42) is adjusted by adjusting the area ratio. Flattening of transconductance and thereby improved linearity is achieved.

In the semiconductor device 1A, a dielectric portion 40a and a dielectric portion 40b having different thicknesses are provided in the region 81 and the region 82, which are the MIS gates, respectively. The dielectric portions 40a and the dielectric portions 40b having different thicknesses can be formed by depositing and selective etching the insulating film 41 and the insulating film 42 contained therein, respectively. The thickness of the insulating film 41 and the insulating film 42 can be controlled with high accuracy by the deposition technique, and therefore, the thickness of the dielectric portion 40a of the region 81 and the thickness of the dielectric portion 40b of the region 82 Can be controlled with high accuracy. Further, by selective etching of the insulating film 41 and the insulating film 42, the area of the insulating film 41 and the insulating film 42, and therefore the area of the dielectric portion 40a of the region 81 and the area of the dielectric portion 40b of the region 82 can be made highly accurate. It is possible to control. As a result, each structure of the region 80, the region 81, and the region 82 can be precisely created, and the flattening of the transconductance by the combination thereof and the improvement of the linearity by the combination can be performed with high accuracy.

In the semiconductor device 1A, the transistor structures of the region 80, the region 81, and the region 82 are separately formed by depositing and selective etching the insulating film 41 and the insulating film 42. By providing the dielectric layer 40A having the dielectric portions 40a and the dielectric portions 40b having different thicknesses between the electron supply layer 20 and the gate electrode 30, a combination of transistor structures having different characteristics is realized. Therefore, in order to realize a transistor structure having different characteristics, it is not necessary to process the electron supply layer 20 or the electron traveling layer 10 and to provide recesses such as steps and holes in the electron supply layer 20 and the like by processing. Therefore, the effects such as a decrease in output due to damage caused by processing of the electron supply layer 20 and the like, a decrease in manufacturing reproducibility due to variation in processing depth, and a decrease in output due to a decrease in effective channel width due to region division are effective. It becomes possible to suppress the target. As a result, it is possible to suppress a decrease in output, realize a combination of transistor structures having different characteristics, flatten the transconductance, and improve the linearity.

According to the above configuration, it is possible to realize a high-output semiconductor device 1A having excellent linearity.
Subsequently, a method for forming the semiconductor device 1A having the above configuration will be described.

6 to 10 are views for explaining an example of a method for forming a semiconductor device according to the first embodiment. Hereinafter, an example of the forming method will be described in order with reference to FIGS. 6 to 10.
FIG. 6 is a diagram illustrating an example of a nitride semiconductor layer forming step. FIG. 6A schematically shows a plan view of a main part of an example of the nitride semiconductor layer forming step. FIG. 6B schematically shows a cross-sectional view of a main part of an example of the nitride semiconductor layer forming step. FIG. 6B is a schematic cross-sectional view taken along the line VI-VI of FIG. 6A.

For example, as shown in FIGS. 6A and 6B, the initial layer 3 is laminated on the base substrate 2, the electron traveling layer 10 and the electron supply layer 20 are laminated on the initial layer 3. The structure is prepared. As the base substrate 2, a substrate such as SiC, Si, sapphire, GaN, AlN, or diamond is used. The base substrate 2 may have a single-layer structure of one type of substrate, or may have a laminated structure of one type or two or more types of substrates. The initial layer 3, the electron traveling layer 10, and the electron supply layer 20 are epitaxially grown on the base substrate 2 by using, for example, the MOVPE method. As the initial layer 3, a nitride semiconductor having a single layer structure such as AlN, GaN, AlGaN, or a laminated structure of two or more of them is grown. Nitride semiconductors such as GaN and AlGaN are grown on the initial layer 3 as the electron traveling layer 10. On the electron traveling layer 10 (the surface 10a thereof), a nitride semiconductor having a single layer structure such as AlGaN, InAlN, InAlGaN, AlN, ScAlN or a laminated structure of two or more of them is grown as the electron supply layer 20. To. 2DEG70 is generated in the vicinity of the junction interface between the electron traveling layer 10 and the electron supply layer 20.

After the initial layer 3, the electron traveling layer 10 and the electron supply layer 20 are formed on the base substrate 2, an element separation region (not shown) is formed. For example, first, a resist pattern having an opening is formed in a region forming an element separation region by a photolithography technique. Then, using the formed resist pattern as a mask, Ar (argon) ions are injected into the nitride semiconductor at the opening to form an element separation region. The device separation region may be formed by removing the nitride semiconductor at the opening of the resist pattern by dry etching such as reactive ion etching (RIE) using Cl (chlorine) gas. .. After forming the element separation region, the resist pattern used as a mask is removed by using an organic solvent or the like.

FIG. 7 is a diagram illustrating an example of a process of forming a source electrode and a drain electrode. FIG. 7A schematically shows a plan view of a main part of an example of the source electrode and drain electrode forming steps. FIG. 7B schematically shows a cross-sectional view of a main part of an example of the process of forming the source electrode and the drain electrode. FIG. 7B is a schematic cross-sectional view taken along the line VII-VII of FIG. 7A.

After the initial layer 3, the electron traveling layer 10 and the electron supply layer 20 are formed on the base substrate 2, and the element separation region (not shown) is formed, as shown in FIGS. 7 (A) and 7 (B). , The source electrode 50 and the drain electrode 60 are formed. For example, first, a resist pattern having an opening is formed in a region forming the source electrode 50 and the drain electrode 60 by a photolithography technique. Then, the metal material is vapor-deposited on the resist pattern and in the opening thereof by the vacuum vapor deposition method. As an example, Ti having a thickness of 2 nm to 50 nm is vapor-deposited, and Al having a thickness of 100 nm to 300 nm is vapor-deposited on the Ti. After the metal material is deposited, the lift-off technique removes the resist pattern along with the metal material deposited on it. As a result, the source electrode 50 and the drain electrode 60 are formed. After that, heat treatment (alloying treatment) is performed at 500 ° C. to 900 ° C. in a nitrogen atmosphere to establish ohmic connection between the source electrode 50 and the drain electrode 60.

FIG. 8 is a diagram illustrating an example of the first insulating film forming step. FIG. 8A schematically shows a plan view of a main part of an example of the first insulating film forming step. FIG. 8B schematically shows a cross-sectional view of a main part of an example of the first insulating film forming step. FIG. 8B is a schematic cross-sectional view taken along the line VIII-VIII of FIG. 8A.

After the formation of the source electrode 50 and the drain electrode 60, as shown in FIGS. 8A and 8B, the first insulating film 41 having the opening 41a is formed. For example, first, AlO having a thickness of 2 nm to 10 nm is formed on the electron supply layer 20 (the surface 20a thereof) by using the ALD method. Next, a resist pattern having an opening is formed in the region where AlO is removed by the photolithography technique. The opening of the resist pattern is provided in a region where a part of the electron supply layer 20 is exposed from the first insulating film 41. Then, using the formed resist pattern as a mask, AlO at the opening is removed by wet etching using, for example, tetra-Methyl-Ammonium Hydroxide (TMAH). As a result, the first insulating film 41 using AlO having an opening 41a leading to a part of the electron supply layer 20 is formed. After the first layer of the insulating film 41 is formed, the resist pattern used as a mask is removed by using an organic solvent or the like.

In addition to being able to etch the AlO of the first insulating film 41, TMAH suppresses the etching of AlGaN and the like of the underlying electron supply layer 20 and introduces damage to the electron supply layer 20. It can be suppressed. Therefore, TMAH is suitable as an etchant for selective etching when AlO is used for the first layer insulating film 41. However, for etching the first layer insulating film 41 using AlO, not only TMAH but also other alkaline chemicals and dry etching such as RIE using F (fluorine) gas can be used. be.

FIG. 9 is a diagram illustrating an example of the second insulating film forming step. FIG. 9A schematically shows a plan view of a main part of an example of the second insulating film forming step. FIG. 9B schematically shows a cross-sectional view of a main part of an example of the second insulating film forming step. 9 (B) is a schematic cross-sectional view of IX-IX of FIG. 9 (A).

After the formation of the first-layer insulating film 41, the second-layer insulating film 42 having the opening 42a is formed as shown in FIGS. 9A and 9B. For example, first, SiN having a thickness of 2 nm to 20 nm is formed on the AlO of the first insulating film 41 and on the electron supply layer 20 exposed from the opening 41a by using the plasma CVD method. Here, it is desirable that the total thickness of the AlO of the first-layer insulating film 41 and the SiN of the second-layer insulating film 42 laminated thereto is 30 nm or less from the viewpoint of high-frequency characteristics. For example, by setting the AlO of the first layer insulating film 41 to a thickness of 2 nm to 10 nm and the SiN of the second layer insulating film 42 to a thickness of 2 nm to 20 nm, the total thickness of these AlO and SiN is 4 nm. It is set in the range of ~ 30 nm. Following the formation of SiN in the second layer insulating film 42, a resist pattern having an opening in the region where SiN is removed is formed by a photolithography technique. The opening of the resist pattern is formed in a region of the first insulating film 41 that includes an opening 41a in which a part of the electron supply layer 20 is exposed and a part of the insulating film 41 outside the opening 41a. It is provided. Then, using the formed resist pattern as a mask, SiN at the opening is removed by dry etching such as RIE using an F-based gas. As a result, a second insulating film 42 using SiN having an opening 42a leading to a part of the first insulating film 41 and a part of the electron supply layer 20 is formed. After forming the second insulating film 42, the resist pattern used as a mask is removed by using an organic solvent or the like.

Dry etching using F-based gas can etch SiN of the second insulating film 42, and also suppresses etching of AlGaN or the like of the electron supply layer 20 which is a part of the base. , The introduction of damage to the electron supply layer 20 can be suppressed. Further, in the dry etching using the F-based gas, the etching rate of the first layer insulating film 41, which is a part of the base of the second layer insulating film 42, with respect to AlO is much slower than the etching rate with respect to SiN. .. Therefore, according to dry etching using an F-based gas, the SiN of the second layer insulating film 42 can be etched with a high selectivity.

In this way, the first AlO insulating film 41 having the opening 41a in which a part of the electron supply layer 20 is exposed is formed, and a part of the insulating film 41 and a part of the electron supply layer 20 are formed on the insulating film 41 of the first layer. A second-layer SiN insulating film 42 having a communicating opening 42a is formed, and a dielectric layer 40A is formed.

FIG. 10 is a diagram illustrating an example of a gate electrode forming step. FIG. 10A schematically shows a plan view of a main part of an example of the gate electrode forming step. FIG. 10B schematically shows a cross-sectional view of a main part of an example of the gate electrode forming step. FIG. 10B is a schematic cross-sectional view taken along the line XX of FIG. 10A.

After the formation of the second insulating film 42, as shown in FIGS. 10A and 10B, it is exposed from a part of the second insulating film 42 and the opening 42a of the insulating film 42. The gate electrode 30 is formed on a part of the first insulating film 41 and a part of the electron supply layer 20. For example, first, a resist pattern having an opening is formed in a region forming the gate electrode 30 by a photolithography technique. The opening of the resist pattern corresponds to a part of the second insulating film 42, a part of the first insulating film 41 exposed from the opening 42a of the insulating film 42, and a part of the electron supply layer 20. It is provided in the area to be used. Then, the metal material is vapor-deposited on the resist pattern and in the opening thereof by the vacuum vapor deposition method. As an example, Ni having a thickness of 5 nm to 30 nm is vapor-deposited, and Au having a thickness of 100 nm to 300 nm is vapor-deposited on the Ni. After the metal material is deposited, the lift-off technique removes the resist pattern along with the metal material deposited on it. As a result, the gate electrode 30 is formed. A heat treatment may be performed after the formation of the gate electrode 30.

Through the above steps, the semiconductor device 1A having the configurations shown in FIGS. 10 (A) and 10 (B) is formed.
A region 80 in which neither the insulating film 41 nor the insulating film 42 is interposed and a region 81 in which the single-layer film of the insulating film 41 is interposed between the electron supply layer 20 of the semiconductor device 1A and the gate electrode 30 above the electron supply layer 20. And a region 82 in which the insulating film 41 and the laminated film of the insulating film 42 are interposed are provided. In the region 80 in which neither the insulating film 41 nor the insulating film 42 is interposed, that is, in the region 80 in which the dielectric layer 40A is not interposed, the electron supply layer 20 and the gate electrode 30 are in contact with each other, and the gate electrode 30 is Schottky connected. In the region 81 in which the single-layer film of the insulating film 41 is interposed, the insulating film 41 functions as a relatively thin dielectric portion 40a in the dielectric layer 40A. In the region 82 in which the insulating film 41 and the laminated film of the insulating film 42 are interposed, the insulating film 41 and the insulating film 42 function as a relatively thick dielectric portion 40b in the dielectric layer 40A. As a result, in the semiconductor device 1A, different transistor structures are formed in the region 80, the region 81, and the region 82, respectively.

That is, a shot key gate is formed in the region 80 in which the dielectric layer 40A is not interposed between the electron supply layer 20 and the gate electrode 30. A MIS gate is formed in a region 81 in which a relatively thin dielectric portion 40a of the dielectric layer 40A is interposed between the electron supply layer 20 and the gate electrode 30. A MIS gate having a configuration different from that of the MIS gate in the region 81 is formed in the region 82 in which the relatively thick dielectric portion 40b of the dielectric layer 40A is interposed between the electron supply layer 20 and the gate electrode 30. As a result, the semiconductor device 1A is formed by combining three types of transistor structures having different characteristics from each other.

In the semiconductor device 1A, the area ratio of each part of the dielectric layer 40A in the region 80, the region 81, and the region 82 with respect to the gate electrode 30 is adjusted to flatten the transconductance and thereby improve the linearity. To. In the formation of the semiconductor device 1A, the size of the opening 41a of the first insulating film 41 (the size of the electron supply layer 20 exposed from the opening 41a) of the first layer 41 and the size of the second layer so as to obtain desired transconductance and linearity. The size of the opening 42a of the insulating film 42 (the size of the insulating film 41 and the electron supply layer 20 exposed from the opening 42a) is set. Further, the size of the gate electrode 30 in the gate length direction D2 is set so as to obtain the desired transconductance and linearity. For example, in this way, the area of the electron supply layer 20 overlapping the gate electrode 30, the area of the insulating film 41 (dielectric portion 40a) overlapping the gate electrode 30, and the insulating film 41 and the insulating film overlapping the gate electrode 30. The area of 42 (dielectric portion 40b) is adjusted. In order to obtain desired mutual conductance and linearity, the type and thickness of the nitride semiconductor of the electron supply layer 20, the combination of the nitride semiconductors of the electron supply layer 20 and the electron traveling layer 10 and the like are appropriately set. ..

In the semiconductor device 1A, the transistor structures having different characteristics of the region 80, the region 81, and the region 82 are created separately by the deposition and selective etching of the insulating film 41 and the insulating film 42. When the opening 41a of the first insulating film 41 on the electron supply layer 20 is formed, the introduction of damage to the electron supply layer 20 is suppressed by selective etching on the electron supply layer 20. At the time of forming the opening 42a of the second insulating film 42 on the first insulating film 41 and the electron supply layer 20, electrons are selectively etched on the electron supply layer 20 (and the first insulating film 41). The introduction of damage to the supply layer 20 is suppressed. According to the above-mentioned forming method of the semiconductor device 1A, in order to realize a transistor structure having different characteristics, the electron supply layer 20 or the electron traveling layer 10 is further processed, and the electron supply layer 20 or the like is processed to have steps, holes, or the like. It is not necessary to provide a recess. Therefore, the effects such as a decrease in output due to damage caused by processing of the electron supply layer 20 and the like, a decrease in manufacturing reproducibility due to variation in processing depth, and a decrease in output due to a decrease in effective channel width due to region division are effective. Can be suppressed.

In the description of the above-mentioned forming method of the semiconductor device 1A, an example in which the first-layer insulating film 41 is AlO and the second-layer insulating film 42 is SiN is shown, but the insulation of the two-layer insulating film 41 and the insulating film 42 is shown. The combination of materials is not limited to this example. The first layer insulating film 41 is formed and the opening 41a is formed by selective etching (FIG. 8), the second layer insulating film 42 is formed therein, and the opening 42a is formed by selective etching (FIG. 8). If it can be done in FIG. 9), various combinations of insulating materials can be adopted.

FIG. 11 is a diagram illustrating another configuration example of the semiconductor device according to the first embodiment. 11 (A) to 11 (D) schematically show cross-sectional views of main parts of the first to fourth configuration examples of the semiconductor device according to the first embodiment, respectively.

In the semiconductor device 1A, the area ratio of the dielectric portion 40a and the dielectric portion 40b of the dielectric layer 40A interposed between the electron supply layer 20 and the gate electrode 30 so as to obtain desired transconductance and linearity. May be set. For example, in the semiconductor device 1A, as shown in FIG. 11A, the forming region of the first insulating film 41 of the dielectric layer 40A interposed between the electron supply layer 20 and the gate electrode 30, and the region thereof. The forming region of the second layer insulating film 42 laminated on the upper layer may be set respectively. The width of the single-layer film portion (dielectric portion 40a) of the insulating film 41 and the width of the laminated film portion (dielectric portion 40b) of the insulating film 41 and the insulating film 42 may be the same. It may be different.

Further, in the semiconductor device 1A, the area ratios of the dielectric portions 40a and the dielectric portions 40b so as to obtain desired mutual conductance and linearity are as shown in FIGS. 11B and 11C. It may be configured. That is, as shown in FIGS. 11B and 11C, one end of the forming region of the second layer insulating film 42 is aligned with one end of the forming region of the first insulating film 41. You may. Alternatively, as shown in FIG. 11C, a continuous forming region of the first layer insulating film 41 may be provided between the pair of forming regions of the second layer insulating film 42.

Further, the semiconductor device 1A is not limited to a combination of three types of transistor structures of a Schottky gate and two types of MIS gates. For example, as shown in FIG. 11 (D), the dielectric portions 40a having different thicknesses and the dielectric portions 40a having different thicknesses are provided without providing a shotky gate region in which the dielectric layer 40A is not interposed between the electron supply layer 20 and the gate electrode 30. It is also possible to provide only two types of MIS gate regions in which the dielectric portion 40b is interposed. In the case of the configuration as shown in FIG. 11D, the insulating film 41 of the first layer has an ultra-thin thickness such that the tunnel effect is exhibited, for example, a thickness of less than 2 nm, and the region of the dielectric portion 40a. Can also effectively function as a shot key gate.

Further, in the semiconductor device 1A, it is not always necessary to provide the Schottky gate and each of the two types of MIS gates at a plurality of locations. The area ratio of the dielectric portion 40a and the dielectric portion 40b of the dielectric layer 40A can be set so as to obtain the desired mutual conductance and linearity, and the insulating film 41 and the insulating film 41 and the insulation can be set so as to have the area ratio. The formation region of the film 42 can be set respectively.

[Second Embodiment]
FIG. 12 is a diagram illustrating an example of a semiconductor device according to the second embodiment. FIG. 12A schematically shows a plan view of a main part of an example of the semiconductor device according to the second embodiment. FIG. 12B schematically shows a cross-sectional view of a main part of an example of the semiconductor device according to the second embodiment. 12 (B) is a schematic cross-sectional view of XII-XII of FIG. 12 (A).

The semiconductor device 1B shown in FIGS. 12A and 12B is an example of HEMT. The semiconductor device 1B includes an electron traveling layer 10, an electron supply layer 20, a dielectric layer 40B, a gate electrode 30, a source electrode 50, and a drain electrode 60. The semiconductor device 1B has a configuration in which a third insulating film 43 is further provided as the dielectric layer 40B in addition to the first insulating film 41 and the second insulating film 42. The semiconductor device 1B is different from the semiconductor device 1A described in the first embodiment in this respect.

The dielectric layer 40B is provided on the surface 20a side of the electron supply layer 20 opposite to the electron traveling layer 10 side. The dielectric layer 40B includes an insulating film 41, an insulating film 42 laminated on the insulating film 41, and an insulating film 43 laminated on the insulating film 42.

The first insulating film 41 has an opening 41a leading to a part of the electron supply layer 20. The second-layer insulating film 42 includes an opening 41a of the insulating film 41 and a part of the insulating film 41 outside the insulating film 41, and includes an opening 42a leading to a part of the insulating film 41 and a part of the electron supply layer 20. Have. The third-layer insulating film 43 includes the opening 42a of the insulating film 42 and a part of the insulating film 42 outside the insulating film 42, and the opening 41a of the insulating film 41 and a part of the insulating film 41 outside the opening 41a. It has an opening 43a leading to a part of the insulating film 42, a part of the insulating film 41, and a part of the electron supply layer 20.

For the insulating film 41, the insulating film 42, and the insulating film 43, for example, one or a mixture of two or more of SiN, AlO, AlN, SiO, HfO, ZrO, LaO, and TaO is used. For example, different types of insulating materials are used for the insulating film 41, the insulating film 42, and the insulating film 43. Alternatively, different types of insulating materials are used for the first-layer insulating film 41 and the second-layer insulating film 42, and different types of insulating materials are used for the second-layer insulating film 42 and the third-layer insulating film 43. An insulating material is used, and the same type of insulating material may be used for the first-layer insulating film 41 and the third-layer insulating film 43. The insulating film 41, the insulating film 42, and the insulating film 43 are formed by using a plasma CVD method, an ALD method, or the like, depending on the type of insulating material used therein.

The dielectric layer 40B includes an insulating film 41 provided in a part of the electron supply layer 20, an insulating film 42 provided in a part of the area above the insulating film 41, and an insulating film 42 provided in a part of the area above the insulating film 41. The film 43 forms a dielectric portion 40a, a dielectric portion 40b, and a dielectric portion 40c having different thicknesses in the stacking direction D1. That is, the dielectric layer 40B is insulated from the dielectric portion 40a having a single-layer film of the insulating film 41, the dielectric portion 40b having a laminated film of the insulating film 41 and the insulating film 42, and the insulating film 41 and the insulating film 42. The dielectric portion 40c having a laminated film with the film 43 is included. The dielectric portion 40a has a thickness corresponding to the thickness of the insulating film 41, and the dielectric portion 40b has a thickness corresponding to the total thickness of the insulating film 41 and the insulating film 42, and is a dielectric. The portion 40c has a thickness corresponding to the total thickness of the insulating film 41, the insulating film 42, and the insulating film 43. In this example, the dielectric portion 40b is thicker than the dielectric portion 40a by the thickness of the insulating film 42, and the dielectric portion 40c is thicker than the dielectric portion 40b by the thickness of the insulating film 43.

The gate electrode 30 is formed on a dielectric portion 40a (the insulating film 41 thereof) having a different thickness of the dielectric layer 40B, on the dielectric portion 40b (the insulating film 42), and on the dielectric portion 40c (the insulating film 43). Further, it is provided on the electron supply layer 20 (the surface 20a thereof) on which the dielectric layer 40B is not provided. The dielectric layer 40B is a dielectric portion 40a and a dielectric having different thicknesses between the gate electrode 30 and the electron supply layer 20 in a cross-sectional view in the gate width direction D3 orthogonal to the gate length direction D2 of the gate electrode 30. A portion 40b and a dielectric portion 40c are provided. As shown in FIG. 12A, for example, the gate electrode 30 has an edge 41a of the insulating film 41 of the dielectric layer 40B, an opening 42a of the insulating film 42, and an insulating film in the gate length direction D2. The size is provided so as to be inside the edge of the opening 43a of 43.

The surface 20a of the electron supply layer 20 in the region overlapping the gate electrode 30 has high flatness and is parallel to the surface 10a of the electron traveling layer 10 on which the electron supply layer 20 is laminated. The surface 20a of 20 is not provided with recesses such as steps and holes.

The region 80 in which the gate electrode 30 is provided on the electron supply layer 20 in which the dielectric layer 40B is not provided is a region of the shot key gate. A region 81 in which the gate electrode 30 is provided on the electron supply layer 20 via the dielectric portion 40a, a region 82 in which the gate electrode 30 is provided via the dielectric portion 40b, and a gate electrode 30 via the dielectric portion 40c. The provided region 83 is a region of the MIS gate. As described above, the semiconductor device 1B has a Schottky gate region 80 in which the gate electrode 30 is provided on the electron supply layer 20 in contact with the gate electrode 30 and the gate electrode 30 is Schottky connected. When another nitride semiconductor such as a cap layer is provided on the electron supply layer 20, a gate electrode 30 is provided in contact with the nitride semiconductor, and the gate electrode 30 is Schottky connected. Further, the semiconductor device 1B further includes a region 81, a region 82, and a region 83 of the MIS gate in which the gate electrode 30 is provided on the electron supply layer 20 via the dielectric portions 40a, the dielectric portions 40b, and the dielectric portions 40c having different thicknesses. Has. That is, the semiconductor device 1B is provided with a combination of four types of transistor structures having different characteristics.

In the semiconductor device 1B, the region 80 in which the dielectric layer 40B is not provided, and the region 81, the region 82, and the region 83 in which the dielectric portions 40a, the dielectric portions 40b, and the dielectric portions 40c having different thicknesses are interposed form each other. Transistor structures with different current-voltage characteristics are realized. For example, in the semiconductor device 1B, a transistor structure in which the threshold value and the transconductance are different from each other is realized by the region 80, the region 81, the region 82, and the region 83. In the semiconductor device 1B, by providing a combination of transistor structures having different characteristics from each other, it is possible to flatten the transconductance and thereby improve the linearity. At the time of combination, the area 80 (the electron supply layer 20), the area 81 (the insulating film 41), the area 82 (the laminated film of the insulating films 41 and 42) and the area 83 (the insulating film) with respect to the gate electrode 30. The area ratio occupied by each of the 41, 42, and 43 laminated films) is adjusted. This adjusts the degree of flattening of the transconductance and the degree of improvement in linearity.

In the semiconductor device 1B, by using the three-layer insulating film 41, the insulating film 42, and the insulating film 43 as the dielectric layer 40B, it is possible to combine four types of transistor structures including a region in which the dielectric layer 40B is not provided. become. Therefore, the transconductance and linearity of the semiconductor device 1B can be brought closer to the desired transconductance and linearity with higher accuracy.

In the semiconductor device 1B, the transistor structures of the region 80, the region 81, the region 82, and the region 83 are separately formed by depositing and selective etching the insulating film 41, the insulating film 42, and the insulating film 43. By providing a dielectric layer 40B having a dielectric portion 40a, a dielectric portion 40b, and a dielectric portion 40c having different thicknesses between the electron supply layer 20 and the gate electrode 30, a combination of transistor structures having different characteristics can be obtained. Realize. Therefore, in order to realize a transistor structure having different characteristics, it is not necessary to process the electron supply layer 20 or the electron traveling layer 10 and to provide recesses such as steps and holes in the electron supply layer 20 and the like by processing. Therefore, the effects such as a decrease in output due to damage caused by processing of the electron supply layer 20 and the like, a decrease in manufacturing reproducibility due to variation in processing depth, and a decrease in output due to a decrease in effective channel width due to region division are effective. It becomes possible to suppress the target. As a result, it is possible to suppress a decrease in output, realize a combination of transistor structures having different characteristics, flatten the transconductance, and improve the linearity.

According to the above configuration, it is possible to realize a high-output semiconductor device 1B having excellent linearity.
Subsequently, a method for forming the semiconductor device 1B having the above configuration will be described.

13 to 17 are views for explaining an example of a method for forming a semiconductor device according to the second embodiment. In the method for forming the semiconductor device according to the second embodiment, the steps of FIG. 6 (nitride semiconductor layer forming step) and the steps of FIG. 7 (source electrode and drain electrode forming) described in the first embodiment are described. The process) can be the same. In the following, the steps after the steps of FIGS. 6 and 7 will be described in order with reference to FIGS. 13 to 17.

FIG. 13 is a diagram illustrating an example of an insulating film forming step. FIG. 13A schematically shows a plan view of a main part of an example of the insulating film forming step. FIG. 13B schematically shows a cross-sectional view of a main part of an example of the insulating film forming step. 13 (B) is a schematic cross-sectional view of XIII-XIII of FIG. 13 (A).

After the formation of the initial layer 3, the electron traveling layer 10 and the electron supply layer 20 on the base substrate 2 (FIG. 6), and the formation of the source electrode 50 and the drain electrode 60 (FIG. 7), FIG. 13 (A) and As shown in FIG. 13B, the insulating film 41, the insulating film 42, and the insulating film 43 are formed. For example, first, SiN having a thickness of 2 nm to 10 nm is formed on the electron supply layer 20 as the first insulating film 41 by using a plasma CVD method. Next, AlO having a thickness of 2 nm to 10 nm is formed as the second insulating film 42 on the SiN of the first insulating film 41 by using the ALD method. Next, SiO having a thickness of 2 nm to 10 nm is formed on the AlO of the second-layer insulating film 42 as the third-layer insulating film 43 by using the plasma CVD method. Here, the total thickness of the SiN of the first-layer insulating film 41, the AlO of the second-layer insulating film 42 laminated on the SiN, and the SiO of the third-layer insulating film 43 laminated on the SiN is a high frequency. From the viewpoint of characteristics, it is desirable that the thickness is 30 nm or less. For example, by setting the SiN of the first-layer insulating film 41, the AlO of the second-layer insulating film 42, and the SiO of the third-layer insulating film 43 to a thickness of 2 nm to 10 nm, these SiN, AlO, and SiN, respectively. The total thickness of is set in the range of 6 nm to 30 nm.

FIG. 14 is a diagram illustrating an example of the first etching step. FIG. 14A schematically shows a plan view of a main part of an example of the first etching step. FIG. 14B schematically shows a cross-sectional view of a main part of an example of the first etching step. 14 (B) is a schematic cross-sectional view of XIV-XIV of FIG. 14 (A).

After the insulating film 41, the insulating film 42, and the insulating film 43 are formed, the SiO of the third layer insulating film 43 is first etched as shown in FIGS. 14 (A) and 14 (B). For example, a resist pattern having an opening is formed in a region of the third layer insulating film 43 from which SiO is removed by a photolithography technique. Then, using the formed resist pattern as a mask, the SiO in the opening is removed by dry etching such as RIE using an F-based gas. As a result, the third-layer insulating film 43 using SiO is formed, which has an opening 43a leading to a part of the second-layer insulating film 42. After forming the third layer insulating film 43, the resist pattern used as a mask is removed by using an organic solvent or the like.

In dry etching using an F-based gas, in addition to being able to etch the SiO of the third layer insulating film 43, the etching rate of the underlying second layer insulating film 42 with respect to AlO is the etching rate with respect to SiO. Very slow compared to. Therefore, according to dry etching using an F-based gas, the SiO of the third-layer insulating film 43 can be etched with respect to the AlO of the second-layer insulating film 42 at a high selectivity.

FIG. 15 is a diagram illustrating an example of the second etching step. FIG. 15A schematically shows a plan view of a main part of an example of the second etching step. FIG. 15B schematically shows a cross-sectional view of a main part of an example of the second etching step. 15 (B) is a schematic cross-sectional view of XV-XV of FIG. 15 (A).

After etching the SiO of the third layer insulating film 43, the AlO of the second layer insulating film 42 is etched as shown in FIGS. 15A and 15B. For example, a resist pattern having an opening is formed in a region for removing a part of the second-layer insulating film 42 exposed in the opening 43a of the third-layer insulating film 43 by a photolithography technique. Then, using the formed resist pattern as a mask, AlO of the second layer insulating film 42 of the opening is removed by wet etching using TMAH or the like. As a result, the second-layer insulating film 42 using AlO having an opening 42a leading to a part of the first-layer insulating film 41 is formed. After forming the second insulating film 42, the resist pattern used as a mask is removed by using an organic solvent or the like.

In addition to being able to etch AlO of the second layer insulating film 42, TMAH can suppress etching of SiN of the first layer insulating film 41 under the TMAH. Therefore, according to wet etching using TMAH, the AlO of the second-layer insulating film 42 can be etched with a high selectivity with respect to the SiN of the first-layer insulating film 41.

FIG. 16 is a diagram illustrating an example of a third etching step. FIG. 16A schematically shows a plan view of a main part of an example of the third etching step. FIG. 16B schematically shows a cross-sectional view of a main part of an example of the third etching step. 16 (B) is a schematic cross-sectional view of XVI-XVI of FIG. 16 (A).

After etching the AlO of the second layer insulating film 42, the SiN of the first layer insulating film 41 is etched as shown in FIGS. 16A and 16B. For example, a resist pattern having an opening is formed in a region for removing a part of the first-layer insulating film 41 exposed in the opening 42a of the second-layer insulating film 42 by a photolithography technique. Then, using the formed resist pattern as a mask, the SiN of the first layer insulating film 41 of the opening is removed by dry etching such as RIE using an F-based gas. As a result, the first insulating film 41 using SiN having an opening 41a leading to a part of the electron supply layer 20 is formed. After the first layer of the insulating film 41 is formed, the resist pattern used as a mask is removed by using an organic solvent or the like.

In dry etching using an F-based gas, in addition to being able to etch SiN of the first insulating film 41, it is possible to suppress etching of AlGaN or the like of the underlying electron supply layer 20 and to suppress the etching of the electron supply layer. The introduction of damage to 20 can be suppressed. According to dry etching using an F-based gas, the SiN of the first insulating film 41 can be etched with a high selectivity with respect to AlGaN or the like of the electron supply layer 20.

In this way, the first-layer SiN insulating film 41, the second-layer AlO insulating film 42, and the third-layer SiO insulating film 43 are laminated, and the opening 43a and the opening 42a are sequentially selected and etched from the upper layer. And the opening 41a is formed, and the dielectric layer 40B is formed.

FIG. 17 is a diagram illustrating an example of a gate electrode forming step. FIG. 17A schematically shows a plan view of a main part of an example of the gate electrode forming step. FIG. 17B schematically shows a cross-sectional view of a main part of an example of the gate electrode forming step. FIG. 17B is a schematic cross-sectional view of XVII-XVII of FIG. 17A.

After etching the insulating film 43, the insulating film 42, and the insulating film 41, the gate electrode 30 is formed as shown in FIGS. 17 (A) and 17 (B). That is, a part on the third-layer insulating film 43, a part on the second-layer insulating film 42 exposed from the opening 43a, and a part on the first-layer insulating film 41 exposed from the opening 42a. The gate electrode 30 is formed in a part and a part on the electron supply layer 20. For example, first, a resist pattern having an opening is formed in a region forming the gate electrode 30 by a photolithography technique. Then, the metal material is vapor-deposited on the resist pattern and in the opening thereof by the vacuum vapor deposition method. As an example, Ni having a thickness of 5 nm to 30 nm is vapor-deposited, and Au having a thickness of 100 nm to 300 nm is vapor-deposited on the Ni. After the metal material is deposited, the lift-off technique removes the resist pattern along with the metal material deposited on it. As a result, the gate electrode 30 is formed. A heat treatment may be performed after the formation of the gate electrode 30.

Through the above steps, the semiconductor device 1B having the configurations shown in FIGS. 17 (A) and 17 (B) is formed.
A region 80 in which none of the insulating film 41, the insulating film 42, and the insulating film 43 is interposed is formed between the electron supply layer 20 of the semiconductor device 1B and the gate electrode 30. In this region 80, the gate electrodes 30 are Schottky connected to form a Schottky gate. Between the electron supply layer 20 and the gate electrode 30 of the semiconductor device 1B, a region 81 in which a single-layer film of the insulating film 41 is interposed and a region 82 in which a laminated film of the insulating film 41 and the insulating film 42 is interposed are further interposed. , And a region 83 in which a laminated film of the insulating film 41, the insulating film 42, and the insulating film 43 is interposed is formed. In the region 81, the insulating film 41 functions as the thinnest dielectric portion 40a in the dielectric layer 40B, and a MIS gate is formed. In the region 82, the insulating film 41 and the insulating film 42 function as a dielectric portion 40b having an intermediate thickness in the dielectric layer 40B, and a MIS gate is formed. In the region 83, the insulating film 41, the insulating film 42, and the insulating film 43 function as the thickest dielectric portion 40c in the dielectric layer 40B, and a MIS gate is formed. As a result, the semiconductor device 1B is formed by combining four types of transistor structures having different characteristics in the region 80, the region 81, the region 82, and the region 83. In the semiconductor device 1B, the area ratio of each part of the dielectric layer 40B in the region 80, the region 81, the region 82, and the region 83 with respect to the gate electrode 30 is adjusted to flatten the transconductance and thereby improve the linearity. Is realized.

In the semiconductor device 1B, the transistor structures having different characteristics of the region 80, the region 81, and the region 82 are created separately by the deposition and selective etching of the insulating film 41, the insulating film 42, and the insulating film 43. When the opening 41a of the first insulating film 41 on the electron supply layer 20 is formed, the introduction of damage to the electron supply layer 20 is suppressed by selective etching on the electron supply layer 20. According to the above-mentioned forming method of the semiconductor device 1B, in order to realize a transistor structure having different characteristics, the electron supply layer 20 or the electron traveling layer 10 is further processed, and the electron supply layer 20 or the like is processed to have steps, holes, or the like. It is not necessary to provide a recess. Therefore, the effects such as a decrease in output due to damage caused by processing of the electron supply layer 20 and the like, a decrease in manufacturing reproducibility due to variation in processing depth, and a decrease in output due to a decrease in effective channel width due to region division are effective. Can be suppressed.

In the description of the above-mentioned forming method of the semiconductor device 1B, an example is shown in which the first-layer insulating film 41 is SiN, the second-layer insulating film 42 is AlO, and the third-layer insulating film 43 is SiO. The combination of the insulating film 41, the insulating film 42, and the insulating material of the insulating film 43 is not limited to this example. After laminating the three layers of the insulating film 41, the insulating film 42 and the insulating film 43 (FIG. 13), the opening 43a, the opening 42a and the opening 41a are formed by selective etching in order from the upper layer (FIGS. 14 to 16). If possible, various combinations of insulating materials can be adopted.

Further, in the description of the above-mentioned forming method of the semiconductor device 1B, after laminating the three layers of the insulating film 41, the insulating film 42 and the insulating film 43 (FIG. 13), the opening 43a, the opening 42a and the opening 42a are sequentially etched from the upper layer. An example in which the opening 41a is formed (FIGS. 14 to 16) and the dielectric layer 40B is formed is shown. In addition, the dielectric layer 40B including the three-layer insulating film 41, the insulating film 42, and the insulating film 43 can also be formed according to the example of the forming method described in the first embodiment. That is, the first-layer insulating film 41 is formed to form the opening 41a, the second-layer insulating film 42 is formed on the first-layer insulating film 41 to form the opening 42a, and the third layer is formed on the second-layer insulating film 42. The insulating film 43 may be formed to form the opening 43a.

In the first embodiment for forming the dielectric layer 40A including the two-layer insulating film 41 and the insulating film 42, the formation of the dielectric layer 40A is described in the second embodiment. It can also be formed according to an example of the method. That is, after the second insulating film 42 is laminated on the first insulating film 41, the opening 42a and the opening 41a are formed in order from the upper layer by selective etching to form the dielectric layer 40A. May be good.

[Third Embodiment]
FIG. 18 is a diagram illustrating an example of a semiconductor device according to the third embodiment. FIG. 18A schematically shows a plan view of a main part of an example of the semiconductor device according to the third embodiment. FIG. 18B schematically shows a cross-sectional view of a main part of an example of the semiconductor device according to the third embodiment. FIG. 18B is a schematic cross-sectional view of XVIII-XVIII of FIG. 18A.

The semiconductor device 1C shown in FIGS. 18 (A) and 18 (B) is an example of HEMT. The semiconductor device 1C includes an electron traveling layer 10, an electron supply layer 20, a dielectric layer 40A, a gate electrode 30, a source electrode 50, and a drain electrode 60. In the semiconductor device 1C, in the Schottky gate region 80, the end 31 of the gate electrode 30 in the gate length direction D2, which is the direction in which the source electrode 50 and the drain electrode 60 face each other, is located on the dielectric layer 40A. It has a structure. The semiconductor device 1C is different from the semiconductor device 1A described in the first embodiment in that it has such a configuration.

Generally, in HEMT in which a GaN-based nitride semiconductor is used for an electron traveling layer and an electron supply layer, a current collapse phenomenon may occur in which a drain current decreases when a high voltage is applied. 2DEG electrons with high energy due to electric field concentration near the gate electrode are captured at the surface defect level of the electron supply layer, and the electron traveling layer is depleted by the electric field of the captured electrons, increasing the channel resistance and drain current. It is believed that a decrease will be caused.

In the semiconductor device 1C, in addition to the MIS gate region 81 and the region 82, a configuration is adopted in which the end 31 of the gate electrode 30 in the gate length direction D2 is located on the dielectric layer 40A in the Schottky gate region 80. .. As a result, in the semiconductor device 1C, the electric field concentration at the end 31 of the gate electrode 30 is relaxed, the occurrence of the current collapse phenomenon when a high voltage is applied, and the decrease in the drain current due to the phenomenon are suppressed.

According to the above configuration, it is possible to realize a high-output semiconductor device 1C having excellent linearity.
Here, the dielectric layer 40A including the two-layer insulating film 41 and the insulating film 42 as described in the first embodiment is taken as an example. In addition, when the dielectric layer 40B including the three-layer insulating film 41, the insulating film 42, and the insulating film 43 as described in the second embodiment is used, the gate electrode 30 is similarly in the gate length direction. It is possible to adopt a configuration in which the end portion 31 of D2 is located on the dielectric layer 40B.

The first to third embodiments have been described above.
In the above description, as the dielectric layer provided between the electron supply layer 20 and the gate electrode 30, the dielectric layer 40A including the two-layer insulating film 41 and the insulating film 42, and the three-layer insulating film 41 and the insulating film The dielectric layer 40B including the 42 and the insulating film 43 has been exemplified. The number of layers of the insulating film contained in the dielectric layer provided between the electron supply layer 20 and the gate electrode 30 is not limited to the above example, and a dielectric layer containing four or more insulating films is used. You can also do it. As the number of insulating film layers contained in the dielectric layer is increased, the types of transistor structures to be combined can be increased, and the transconductance and linearity obtained by the combination can be obtained with higher accuracy and desired transconductance and linearity. It becomes possible to approach.

Further, the semiconductor devices 1A, 1B, 1C and the like having the configurations as described in the first to third embodiments can be applied to various electronic devices. As an example, a case where a semiconductor device having the above configuration is applied to a semiconductor package, a power factor improving circuit, a power supply device, and an amplifier will be described below.

[Fourth Embodiment]
Here, an example of application of a semiconductor device having the above configuration to a semiconductor package will be described as a fourth embodiment.

FIG. 19 is a diagram illustrating an example of a semiconductor package according to the fourth embodiment. FIG. 19 schematically shows a plan view of a main part of an example of the semiconductor package according to the fourth embodiment.

The semiconductor package 400 shown in FIG. 19 is an example of a discrete package. The semiconductor package 400 includes, for example, the semiconductor device 1A (FIG. 3 and the like) described in the first embodiment, the lead frame 410 on which the semiconductor device 1A is mounted, and the resin 420 that seals them.

The semiconductor device 1A is mounted on the die pad 410a of the lead frame 410 using a die attach material or the like (not shown). The semiconductor device 1A is provided with a pad 30a connected to the gate electrode 30, a pad 50a connected to the source electrode 50, and a pad 60a connected to the drain electrode 60. The pad 30a, the pad 50a, and the pad 60a are each connected to the gate lead 411, the source lead 412, and the drain lead 413 of the lead frame 410 by using a wire 430 such as Al. The lead frame 410, the semiconductor device 1A mounted on the lead frame 410, and the wire 430 connecting them are sealed with the resin 420 so that each part of the gate lead 411, the source lead 412, and the drain lead 413 is exposed.

For example, the semiconductor device 1A described in the first embodiment is used, and a semiconductor package 400 having such a configuration can be obtained. Here, the semiconductor device 1A is taken as an example, but a similar semiconductor package 400 can be obtained by using other semiconductor devices 1B, 1C, and the like.

As described above, in the semiconductor devices 1A, 1B, 1C and the like, the dielectric layers 40A and 40B having different thickness portions are provided between the electron supply layer 20 and the gate electrode 30, so that the threshold value and the transconductance Transistor structures having different characteristics such as the above are combined and provided. This makes it possible to flatten the transconductance and thereby improve the linearity. Further, in the semiconductor devices 1A, 1B, 1C, etc., it is possible to suppress the processing of the electron supply layer 20 and the like for providing the transistor structures having different characteristics in combination and the damage caused by the processing, resulting in a decrease in output and manufacturing reproduction. Deterioration of sex is suppressed. Therefore, high-output semiconductor devices 1A, 1B, 1C and the like having excellent linearity are stably realized. Such semiconductor devices 1A, 1B, 1C and the like are used to realize a high-performance semiconductor package 400.

[Fifth Embodiment]
Here, an example of application of the semiconductor device having the above configuration to the power factor improving circuit will be described as the fifth embodiment.

FIG. 20 is a diagram illustrating an example of a power factor improving circuit according to the fifth embodiment. FIG. 20 shows an equivalent circuit diagram of an example of the power factor improving circuit according to the fifth embodiment.
The Power Factor Correction (PFC) circuit 500 shown in FIG. 20 includes a switch element 510, a diode 520, a choke coil 530, a capacitor 540, a capacitor 550, a diode bridge 560 and an alternating current power supply 570 (AC).

In the PFC circuit 500, the drain electrode of the switch element 510, the anode terminal of the diode 520, and one terminal of the choke coil 530 are connected. The source electrode of the switch element 510 is connected to one terminal of the capacitor 540 and one terminal of the capacitor 550. The other terminal of the capacitor 540 and the other terminal of the choke coil 530 are connected. The other terminal of the capacitor 550 and the cathode terminal of the diode 520 are connected. A gate driver is connected to the gate electrode of the switch element 510. An AC power supply 570 is connected between both terminals of the capacitor 540 via a diode bridge 560, and a direct current power supply (DC) is taken out from both terminals of the capacitor 550.

For example, the semiconductor devices 1A, 1B, 1C and the like are used for the switch element 510 of the PFC circuit 500 having such a configuration.
As described above, in the semiconductor devices 1A, 1B, 1C and the like, the dielectric layers 40A and 40B having different thickness portions are provided between the electron supply layer 20 and the gate electrode 30, so that the threshold value and the transconductance Transistor structures having different characteristics such as the above are combined and provided. This makes it possible to flatten the transconductance and thereby improve the linearity. Further, in the semiconductor devices 1A, 1B, 1C, etc., it is possible to suppress the processing of the electron supply layer 20 and the like for providing the transistor structures having different characteristics in combination and the damage caused by them, resulting in a decrease in output and manufacturing reproduction. Deterioration of sex is suppressed. Therefore, high-output semiconductor devices 1A, 1B, 1C and the like having excellent linearity are stably realized. Such semiconductor devices 1A, 1B, 1C and the like are used to realize a high-performance PFC circuit 500.

[Sixth Embodiment]
Here, an example of application of the semiconductor device having the above configuration to the power supply device will be described as the sixth embodiment.

FIG. 21 is a diagram illustrating an example of a power supply device according to a sixth embodiment. FIG. 21 shows an equivalent circuit diagram of an example of the power supply device according to the sixth embodiment.
The power supply device 600 shown in FIG. 21 includes a primary side circuit 610 and a secondary side circuit 620, and a transformer 630 provided between the primary side circuit 610 and the secondary side circuit 620.

The primary side circuit 610 includes an inverter circuit connected between both terminals of the PFC circuit 500 as described in the fifth embodiment and the capacitor 550 of the PFC circuit 500, for example, a full bridge inverter circuit 640. Is done. The full-bridge inverter circuit 640 includes a plurality of (four as an example here) switch element 641, a switch element 642, a switch element 643, and a switch element 644.

The secondary circuit 620 includes a plurality of (three as an example here) switch elements 621, switch elements 622, and switch elements 623.
For example, the semiconductor devices 1A, 1B, 1C are attached to the switch elements 510 of the PFC circuit 500 included in the primary side circuit 610 and the switch elements 641 to 644 of the full bridge inverter circuit 640 of the power supply device 600 having such a configuration. Etc. are used. For example, a normal MIS gate FET using Si is used for the switch elements 621 to 623 of the secondary circuit 620 of the power supply device 600.

As described above, in the semiconductor devices 1A, 1B, 1C and the like, the dielectric layers 40A and 40B having different thickness portions are provided between the electron supply layer 20 and the gate electrode 30, so that the threshold value and the transconductance Transistor structures having different characteristics such as the above are combined and provided. This makes it possible to flatten the transconductance and thereby improve the linearity. Further, in the semiconductor devices 1A, 1B, 1C, etc., it is possible to suppress the processing of the electron supply layer 20 and the like for providing the transistor structures having different characteristics in combination and the damage caused by the processing, resulting in a decrease in output and manufacturing reproduction. Deterioration of sex is suppressed. Therefore, high-output semiconductor devices 1A, 1B, 1C and the like having excellent linearity are stably realized. Such semiconductor devices 1A, 1B, 1C and the like are used to realize a high-performance power supply device 600.

[7th Embodiment]
Here, an example of application of a semiconductor device having the above configuration to an amplifier will be described as a seventh embodiment.

FIG. 22 is a diagram illustrating an example of an amplifier according to the seventh embodiment. FIG. 22 shows an equivalent circuit diagram of an example of the amplifier according to the seventh embodiment.
The amplifier 700 shown in FIG. 22 includes a digital predistortion circuit 710, a mixer 720, a mixer 730, and a power amplifier 740.

The digital pre-distortion circuit 710 compensates for the non-linear distortion of the input signal. The mixer 720 mixes the input signal SI and the AC signal in which the non-linear distortion is compensated. The power amplifier 740 amplifies the signal in which the input signal SI is mixed with the AC signal. In the amplifier 700, for example, the output signal SO can be mixed with the AC signal by the mixer 730 and sent to the digital predistortion circuit 710 by switching the switch. The amplifier 700 can be used as a high frequency amplifier or a high output amplifier.

The semiconductor devices 1A, 1B, 1C and the like are used for the power amplifier 740 of the amplifier 700 having such a configuration.
As described above, in the semiconductor devices 1A, 1B, 1C and the like, the dielectric layers 40A and 40B having different thickness portions are provided between the electron supply layer 20 and the gate electrode 30, so that the threshold value and the transconductance Transistor structures having different characteristics such as the above are combined and provided. This makes it possible to flatten the transconductance and thereby improve the linearity. Further, in the semiconductor devices 1A, 1B, 1C, etc., it is possible to suppress the processing of the electron supply layer 20 and the like for providing the transistor structures having different characteristics in combination and the damage caused by them, resulting in a decrease in output and manufacturing reproduction. Deterioration of sex is suppressed. Therefore, high-output semiconductor devices 1A, 1B, 1C and the like having excellent linearity are stably realized. Such semiconductor devices 1A, 1B, 1C and the like are used to realize a high-performance amplifier 700.

Various electronic devices to which the semiconductor devices 1A, 1B, 1C, etc. are applied (semiconductor package 400, PFC circuit 500, power supply device 600, amplifier 700, etc. described in the fourth to seventh embodiments) are various electronic devices. Alternatively, it can be mounted on an electronic device. For example, it can be mounted on various electronic devices or electronic devices such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio devices, measuring devices, inspection devices, manufacturing devices, etc. It is possible.

The following additional notes will be further disclosed with respect to the embodiments described above.
(Appendix 1) Electronic traveling layer and
An electron supply layer provided on the first surface side of the electron traveling layer and
A gate electrode provided on the second surface side of the electron supply layer opposite to the electron traveling layer side, and
A first dielectric portion provided between the second surface of the electron supply layer and the gate electrode and having a first thickness in the first direction from the second surface toward the gate electrode, and the first dielectric portion. A semiconductor device including a dielectric layer including a second dielectric portion having a second thickness thicker than the first thickness in the direction.

(Appendix 2) A source electrode and a drain electrode are provided on the second surface side of the electron traveling layer so as to be separated from each other and face each other.
The gate electrode is provided between the source electrode and the drain electrode separately from the source electrode and the drain electrode.
The dielectric layer is a cross-sectional view of the gate electrode along a third direction orthogonal to the second direction in which the source electrode and the drain electrode face each other, and the second surface of the electron supply layer and the gate. The semiconductor device according to Appendix 1, wherein the first dielectric portion and the second dielectric portion are provided between the electrodes.

(Appendix 3) The dielectric layer is provided in a part of the first region between the second surface of the electron supply layer and the gate electrode.
Note 1 or 2, wherein the gate electrode is Schottky-connected in a second region different from the first region between the second surface of the electron supply layer and the gate electrode. The semiconductor device described.

(Appendix 4) The dielectric layer is
A first insulating film containing a first portion and a second portion different from the first portion.
The first insulating film includes a second insulating film laminated on the second portion of the first insulating film.
The first dielectric portion of the dielectric layer includes the first portion of the first insulating film.
The second dielectric portion of the dielectric layer includes the second portion of the first insulating film and at least a part of the second insulating film laminated on the second portion. The semiconductor device according to any one of Supplementary note 1 to 3.

(Appendix 5) The dielectric layer has a third thickness thicker than the second thickness of the second dielectric portion in the first direction from the second surface of the electron supply layer toward the gate electrode. The semiconductor device according to any one of Supplementary note 1 to 4, wherein the semiconductor device includes a third dielectric portion.

(Appendix 6) The dielectric layer is
The second insulating film including the third portion and the fourth portion different from the third portion.
Including a third insulating film laminated on the fourth portion of the second insulating film,
The second dielectric portion of the dielectric layer includes the second portion of the first insulating film and the third portion of the second insulating film laminated on the second portion.
The third dielectric portion of the dielectric layer is formed on the second portion of the first insulating film, the fourth portion of the second insulating film laminated on the second portion, and the fourth portion. The semiconductor device according to Appendix 5, wherein the semiconductor device includes at least a part of the laminated third insulating film.

(Appendix 7) A step of forming a dielectric layer on the second surface side of the electron supply layer provided on the first surface side of the electron traveling layer, which is opposite to the electron traveling layer side.
A step of forming a gate electrode on the second surface side of the electron supply layer so that the dielectric layer is provided between the second surface and the second surface is included.
The step of forming the dielectric layer is
A step of forming a first dielectric portion having a first thickness in the first direction from the second surface toward the gate electrode, and
A method for manufacturing a semiconductor device, which comprises a step of forming a second dielectric portion having a second thickness thicker than the first thickness in the first direction.

(Appendix 8) A step of forming a source electrode and a drain electrode which are separated from each other and provided to face each other on the second surface side of the electron traveling layer is included.
The gate electrode is formed between the source electrode and the drain electrode separately from the source electrode and the drain electrode.
The dielectric layer is a cross-sectional view of the gate electrode along a third direction orthogonal to the second direction in which the source electrode and the drain electrode face each other, and the second surface of the electron supply layer and the gate. The method for manufacturing a semiconductor device according to Appendix 7, wherein the first dielectric portion and the second dielectric portion are provided between the electrodes.

(Appendix 9) The step of forming the dielectric layer includes a step of forming the dielectric layer in a part of the first region on the second surface side of the electron supply layer.
In the step of forming the gate electrode, the gate electrode is formed on the second surface side of the electron supply layer, the first region on which the dielectric layer is formed, and a second region different from the first region. Including the process of forming in
The method for manufacturing a semiconductor device according to Appendix 7 or 8, wherein the gate electrode is Schottky-connected in the second region.

(Appendix 10) The step of forming the dielectric layer is
A step of forming a first insulating film including a first portion and a second portion different from the first portion.
Including a step of forming a second insulating film laminated on the second portion of the first insulating film.
In the step of forming the first dielectric portion of the dielectric layer, the first dielectric portion including the first portion of the first insulating film is formed.
In the step of forming the second dielectric portion of the dielectric layer, the second portion of the first insulating film and at least a part of the second insulating film laminated on the second portion are included. The method for manufacturing a semiconductor device according to any one of Supplementary note 7 to 9, wherein a second dielectric portion is formed.

(Appendix 11) Electronic traveling layer and
An electron supply layer provided on the first surface side of the electron traveling layer and
A gate electrode provided on the second surface side of the electron supply layer opposite to the electron traveling layer side, and
A first dielectric portion provided between the second surface of the electron supply layer and the gate electrode and having a first thickness in the first direction from the second surface toward the gate electrode, and the first dielectric portion. An electronic device comprising a dielectric layer including a second dielectric portion having a second thickness thicker than the first thickness in the direction.

1A, 1B, 1C, 100,200 Semiconductor device 2 Base substrate 3 Initial layer 10,110,210 Electron traveling layer 10a, 20a Surface 20,120,220 Electron supply layer 30,130,230 Gate electrode 30a, 50a, 60a Pad 31 End 40A, 40B Dielectric layer 40a, 40b, 40c Dielectric part 41, 42, 43 Insulating film 41a, 42a, 43a Opening 50 Source electrode 60 Drain electrode 70, 300 2DEG
80, 81, 82, 83 Region 400 Semiconductor Package 410 Lead Frame 410a Die Pad 411 Gate Lead 412 Source Lead 413 Drain Lead 420 Resin 430 Wire 500 PFC Circuit 510, 621, 622, 623, 641, 642, 643, 644 Switch Element 520 Diode 530 Choke coil 540,550 Capacitor 560 Diode bridge 570 AC power supply 600 Power supply 610 Primary side circuit 620 Secondary side circuit 630 Transformer 640 Full bridge Inverter circuit 700 Amplifier 710 Digital predistortion circuit 720, 730 Mixer 740 Power amplifier D1 Stacking direction D2 Gate length direction D3 Gate width direction

Claims (7)

Electronic traveling layer and
An electron supply layer provided on the first surface side of the electron traveling layer and
A gate electrode provided on the second surface side of the electron supply layer opposite to the electron traveling layer side, and
A first dielectric portion provided between the second surface of the electron supply layer and the gate electrode and having a first thickness in the first direction from the second surface toward the gate electrode, and the first dielectric portion. A semiconductor device including a dielectric layer including a second dielectric portion having a second thickness thicker than the first thickness in the direction. A source electrode and a drain electrode provided on the second surface side of the electron traveling layer so as to be separated from each other and opposed to each other are included.
The gate electrode is provided between the source electrode and the drain electrode separately from the source electrode and the drain electrode.
The dielectric layer is a cross-sectional view of the gate electrode along a third direction orthogonal to the second direction in which the source electrode and the drain electrode face each other, and the second surface of the electron supply layer and the gate. The semiconductor device according to claim 1, wherein the first dielectric portion and the second dielectric portion are provided between the electrodes. The dielectric layer is provided in a part of the first region between the second surface of the electron supply layer and the gate electrode.
Claim 1 or 2 characterized in that the gate electrode is Schottky-connected in a second region different from the first region between the second surface of the electron supply layer and the gate electrode. The semiconductor device described in 1. The dielectric layer is
A first insulating film containing a first portion and a second portion different from the first portion.
The first insulating film includes a second insulating film laminated on the second portion of the first insulating film.
The first dielectric portion of the dielectric layer includes the first portion of the first insulating film.
The second dielectric portion of the dielectric layer includes the second portion of the first insulating film and at least a part of the second insulating film laminated on the second portion. The semiconductor device according to any one of claims 1 to 3. A step of forming a dielectric layer on the second surface side of the electron supply layer provided on the first surface side of the electron traveling layer, which is opposite to the electron traveling layer side.
A step of forming a gate electrode on the second surface side of the electron supply layer so that the dielectric layer is provided between the second surface and the second surface is included.
The step of forming the dielectric layer is
A step of forming a first dielectric portion having a first thickness in the first direction from the second surface toward the gate electrode, and
A method for manufacturing a semiconductor device, which comprises a step of forming a second dielectric portion having a second thickness thicker than the first thickness in the first direction. The step of forming the dielectric layer includes a step of forming the dielectric layer in a part of the first region on the second surface side of the electron supply layer.
In the step of forming the gate electrode, the gate electrode is formed on the second surface side of the electron supply layer, the first region on which the dielectric layer is formed, and a second region different from the first region. Including the process of forming in
The method for manufacturing a semiconductor device according to claim 5, wherein the gate electrode is Schottky-connected in the second region. Electronic traveling layer and
An electron supply layer provided on the first surface side of the electron traveling layer and
A gate electrode provided on the second surface side of the electron supply layer opposite to the electron traveling layer side, and
A first dielectric portion provided between the second surface of the electron supply layer and the gate electrode and having a first thickness in the first direction from the second surface toward the gate electrode, and the first dielectric portion. An electronic device comprising a dielectric layer including a second dielectric portion having a second thickness thicker than the first thickness in the direction.

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