JP2022107067A - Encoding circuit and semiconductor device, encoding method, data transmission system, and decoding circuit - Google Patents

Abstract

To provide an encoding scheme with reduced overhead.SOLUTION: An encoding circuit 100 converts 9-bit input data S1 into a 10-bit symbol S2. A conversion circuit 110 converts the 9-bit input data S1 into a 10-bit symbol S2 having a disparity of 0, ±2, or ±4. A disparity controller 120 selects the polarity of the disparity for the current symbol on the basis of the history of disparities over multiple past times.SELECTED DRAWING: Figure 1

Description

The present invention relates to a coding circuit.

8b10b encoding is widely used as an encoding method in serial data communication. 8b10b coding converts 8-bit data into 10-bit data and embeds a clock in the serial data to transmit the data and the clock with the same wiring.

In 8b10b coding, the 8-bit transmission data word is divided into upper 3 bits and lower 5 bits, the upper 3 bit data word is converted into a 4-bit symbol based on the 3b4b conversion table, and the lower 5 bit data word is converted. It is converted into a 6-bit symbol based on the 5b6b conversion table, and the converted 4-bit symbol and 6-bit symbol are combined to obtain a 10-bit encoded symbol.

In order to improve the DC balance, in 8b10b encoding, symbols are generated based on the concept of running disparity. The disparity represents the difference xy between the number x of 1s x and the number y of 0s included in the 4-bit symbol or the 6-bit symbol. The disparity of the symbol can be obtained as a value obtained by adding the bits [1] to 1 and [0] to -1, for example, when the 4-bit code is [1101], the disparity is 2 and [ The disparity of 0011] is 0. The disparity of a 4-bit or 6-bit symbol can take three values of -2, 0, +2. In each code, two symbols having different disparities (or one symbol having a disparity of 0) are defined.

In 8b10b encoding, the running disparity varies by a binary value of 1 or -1. When the immediately preceding running disparity is -1, if a symbol with a disparity of ± 2 can be selected, a symbol with +2 is selected and the running disparity is updated to +1. When the immediately preceding running disparity is -1, if a symbol with a disparity of 0 is input, the running disparity is maintained at -1.

When the immediately preceding running disparity is 1, if a symbol with a disparity of ± 2 can be selected, the symbol of -2 is selected and the running disparity is updated to -1. If a symbol with a disparity of 0 is input when the immediately preceding running disparity is 1, the running disparity is maintained at 1.

As described above, in 8b10b, the balance of the number of 1s and 0s is maintained based on the running disparity.

In 8b10b encoding, 2 out of 10 bits have no information and have a 20% overhead.

The present invention has been made in such a situation, and one of the exemplary objects of the embodiment is to provide a coding scheme with reduced overhead.

One aspect of the present invention relates to a coding circuit that converts 9-bit input data into 10-bit symbols. The coding circuit is based on a conversion circuit that converts 9-bit input data into a 10-bit symbol whose disparity is 0, ± 2, ± 4, and a history of multiple disparities in the past. , A disparity controller that selects the disparity polarity of the current symbol.

According to this aspect, the overhead per 10 bits of one symbol can be reduced to 1 bit, and the effective transmission rate can be increased as compared with 8b10b coding. Further, the DC balance can be maintained by monitoring the history of disparity over a plurality of times in the past.

The conversion circuit may include a converter capable of outputting a 10-bit symbol having a disparity of either 0, -2, -4, or 0, + 2, + 4. The disparity controller may control whether the symbol is output as it is or bit inverted.

The converter circuit may further include a selector that receives the output of the converter and its inverted code. The disparity controller may switch the state of the selector.

The disparity controller may select the polarity of the disparity of the current symbol based on the combination of the immediately preceding disparity and the previous disparity. Hardware can be simplified by monitoring only two disparities.

The disparity controller may select the polarity of the disparity of the current symbol based on the sum of the previous disparity and the previous disparity.

The disparity controller may select the polarity of the disparity of the current symbol based on the polarity of the previous disparity when the total value is zero.

The disparity controller may include a table that defines the relationship between the total value, the previous disparity, the candidate disparity of the current symbol, and the polarity of the disparity of the current symbol.

Another aspect of the present invention relates to a coding circuit that converts m-bit input data into n-bit symbols (n> m). The coding circuit is a conversion circuit that converts m-bit input data into an n-bit symbol whose disparity is 0, ± 2, ..., ± 2k (k ≧ 2), and the past k times or that. It comprises a disparity controller that selects the disparity polarity of the current symbol based on a history of more disparity.

The conversion circuit may include a converter capable of outputting an n-bit symbol having a disparity of 0, -2, ..., -2k, or 0, + 2, ..., + 2k. .. The disparity controller may control whether the symbol is output as it is or bit inverted.

The converter circuit may further include a selector that receives the output of the converter and its inverted code. The disparity controller may switch the state of the selector.

The disparity controller may select the polarity of the disparity of the current symbol based on the total value of the disparity of the past k times.

The disparity controller may select the polarity of the disparity of the current symbol based on the polarity of the previous disparity when the total value is zero.

The disparity controller may include a table that defines the relationship between the total value, the previous disparity, the candidate disparity of the current symbol, and the polarity of the disparity of the current symbol.

It may be n = m + 1.

Another aspect of the present invention relates to a semiconductor device. The semiconductor device includes a separator that cuts out 9-bit data to be transmitted, the above-mentioned coding circuit that converts 9-bit data into a 10-bit symbol, a serializer that converts the output of the coding circuit into serial data, and serial. It may include a transmitter that transmits data. The semiconductor device may be an image transmission circuit.

The coding circuit may be integrally integrated on one semiconductor substrate. "Integrated integration" includes cases where all the components of a circuit are formed on a semiconductor substrate or cases where the main components of a circuit are integrated integrally, and some of them are used for adjusting circuit constants. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. By integrating the circuit on one chip, the circuit area can be reduced and the characteristics of the circuit element can be kept uniform.

It should be noted that any combination of the above components or components and expressions of the present invention that are mutually replaced between methods, devices, systems, and the like are also effective as aspects of the present invention.

According to an aspect of the present invention, coding with low overhead can be realized.

It is a block diagram of the data transmission system using the coding circuit which concerns on embodiment. It is a figure which shows the flow of 10b coding and 9b10b decoding. It is a figure which shows an example of a part of the 10-bit data symbol used for 9b10b coding. It is a figure which shows an example of the 10-bit symbol for control used for 9b10b coding. FIG. 5A is a diagram for explaining disparity control in 8b10b coding, and FIG. 5B is a diagram showing a state when the polarity of disparity is inverted for each symbol in 9b10b coding. Is. It is a figure explaining the control of running disparity in 9b10b coding. It is a table of an example of the control of running disparity in 9b10b coding. It is a block diagram which shows the structural example of a coding circuit. It is a figure which shows the configuration example of a disparity controller. It is a block diagram of a decoding circuit. It is a table explaining error detection by a disparity error detector. It is a block diagram of an image transmission system using 9b10b coding.

Hereinafter, the present invention will be described with reference to the drawings based on preferred embodiments. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and redundant description will be omitted as appropriate. Further, the embodiment is not limited to the invention, but is an example, and all the features and combinations thereof described in the embodiment are not necessarily essential to the invention.

FIG. 1 is a block diagram of a data transmission system 2 using the coding circuit 100 according to the embodiment. The data transmission system 2 includes a semiconductor device 300 on the transmitting side and a semiconductor device 400 on the receiving side. The semiconductor device 300 and the semiconductor device 400 are connected via a single-ended or differential serial transmission line 4.

The semiconductor device 300 includes a separator 302, a serializer 304, and a transmitter 306 in addition to the coding circuit 100. The separator 302 divides the data to be transmitted to the semiconductor device 400 into the number of bits suitable for the input of the coding circuit 100. In the present embodiment, the coding circuit 100 inputs 9-bit data S1 and outputs 10-bit symbol S2. Following the 8b10b coding, the coding circuit 100 is referred to as a 9b10b encoder, and the coding by the coding circuit 100 is referred to as 9b10b coding.

The serializer 304 converts the 10-bit symbol S2, which is the output of the coding circuit 100, into serial data S3. The transmitter 306 transmits the serial data S3 to the semiconductor device 400. A clock is embedded in the serial data S3 by 9b10b coding.

The semiconductor device 400 receives the serial data S3 from the semiconductor device 300 and processes the signal. The semiconductor device 400 includes a receiver 402, a deserializer 404, and a decoding circuit 200. The receiver 402 receives the serial data S3 from the semiconductor device 300. The receiver 402 includes a CDR (Clock Data Recovery) circuit that reproduces the clock embedded in the serial data and latches each bit of the serial data with the reproduced clock.

The deserializer 404 converts the serial data S4 received by the receiver 402 into 10-bit parallel data S5 (that is, a symbol). The decoding circuit 200 is paired with the coding circuit 100, and restores the original 9-bit data S6 from the 10-bit symbol S5. The decoding circuit 200 is also referred to as a 9b10b decoder.

Subsequently, the coding circuit 100 will be described. The coding circuit 100 includes a 9b10b conversion circuit 110 and a disparity controller 120. The 9b10b conversion circuit 110 converts the 9-bit input data S1 into a 10-bit symbol having a disparity (difference between the number of bits having a value of 1 and the number of bits having a value of 0) of 0, ± 2, ± 4. Convert to S2.

Disparity can be calculated by adding bit 1 contained in the symbol as +1 and bit 0 as -1. For example, the disparity of "0001011000" is -4, and the disparity of the bit-inverted symbol "1110100111" is +4.

The disparity controller 120 selects the polarity CurrentRD of the disparity of the current symbol based on the history of the disparity over a plurality of times in the past. For example, the disparity controller 120 can select the polarity CurrentRD of the disparity of the current symbol based on the combination of the immediately preceding disparity di _-1 and the previous disparity di _-2 .

FIG. 2 is a diagram showing a flow of 9b10b coding and 9b10b decoding. The left side of FIG. 2 shows the coding in the semiconductor device 300 on the transmitting side, and the right side shows the decoding in the semiconductor device 400 on the receiving side. In the present embodiment, a 1-bit control code (K code) is prepared.

In the coding circuit 100, when the K code is 0, the 9-bit transmission data TX [8: 0] (that is, S1) is converted into a 10-bit data symbol based on a code table for ordinary data. When the K code is 1, the 9-bit transmission data TX [8: 0] is converted into a 10-bit control symbol based on a code table that defines a control symbol, which is different from the normal data. Note that the control symbol and the data symbol do not have the same code.

The 10-bit symbol S2 (data symbol or control symbol) is stored in the shift register in the serializer 304, and is converted into serial data S3 by bit shift.

The receiver 402 of the semiconductor device 400 on the receiving side receives the serial data S3 and reproduces the serial data S4 by CDR. In the deserializer 404, the serial data S4 is stored in a 10-bit shift register and converted into parallel data S5.

The decoding circuit 200 determines whether the 10-bit parallel data S5 is a control symbol or a data symbol, and converts the 10-bit parallel data S5 into the original data or the control code. When it is a control symbol, the K code is set to 1, and when it is a data symbol, the K code is set to 0.

The above is the data flow of the data transmission system 2. Subsequently, the 9b10b coding will be described while paying attention to the difference from the 8b10b coding.

-Presence / absence of bit division In 8b10b, an 8-bit input is divided into 3 bits and 5 bits, and these are converted into 4-bit symbols and 6-bit symbols. On the other hand, in 9b10b, the 9-bit input is directly converted into a 10-bit symbol without being divided. That is, 8b10b uses two converters, whereas 9b10b has one converter.

-Symbol disparity In 8b10b, the disparity of each of the 4-bit symbol and the 6-bit symbol is 0, ± 2. On the other hand, in 9b10b, the disparity of the 10-bit symbol can be 0, ± 2, ± 4.

FIG. 3 is a diagram showing a part of a 10-bit data symbol (10B code) used for 9b10b coding. As mentioned above, these symbols are used when K = 0. The disparity of each 10B code (symbol) is 0, -2, or -4, and the disparity of the bit-inverted inverted code (Alternate code) is 0, + 2, + 4. The inversion code of the 10B code whose disparity is 0 is not used and is treated as equivalent to the 10B code. In FIG. 3, the encode class is also shown. The method of determining the 10-bit symbol is not unique and can be arbitrarily determined by the designer.

FIG. 4 is a diagram showing an example of a control 10-bit symbol (10B code) used for 9b10b coding. In the present embodiment, there are nine control codes (225,232,240,450,456,464,113,120,368 in decimal notation). The 10-bit code (control symbol) corresponding to the control code does not overlap with the data symbol of FIG.

-Control of disparity polarity In 8b10b encoding, the disparity polarity is alternately inverted for each symbol in 4-bit symbols and 6-bit symbols. FIG. 5A is a diagram illustrating disparity control in 8b10b encoding. The disparity polarities (+,-) are alternately selected for each symbol, thereby maintaining DC balance.

FIG. 5B is a diagram showing a state when the polarity of disparity is inverted for each symbol in 9b10b coding. The sequence of symbols is random. As shown in FIG. 4B, when symbols having different absolute values of disparity are consecutive and the polarity is inverted for each symbol, the running disparity becomes positively biased and the DC balance is lost. It ends up.

Therefore, in _9b10b coding, the current disparity di is based on the past multiple disparity processes, in other words, at least the immediately preceding disparity di _-1 and the previous disparity di _-2 . Select the polarity. Specifically, the polarity of the current disparity (referred to as Currant RD) is determined based on the polarity of Sum, which is the sum of the disparity di _-1 immediately before and the disparity two times before. For example, when the previous disparity is +2 and the previous disparity is -4, their total value Sum is -2. Therefore, for the polarity CurrentRD of the current symbol, + opposite to the polarity of the total value-is selected. Selecting the positive polarity means outputting the 10b code, and selecting the negative polarity means outputting the inverted code (Alternative code).

For convenience, when the total value Sum is 0, the next polarity Current RD may be determined in consideration of the polarity of the immediately preceding disparity (Preview RD). When the previous disparity di _-2 is -4 and the previous disparity di _-1 is +4, the total value Sum is 0, but since the previous polarity (Previous RD) is +, the current polarity ( The Polar RD) can be determined as-.

If the total value Sum is 0 and the current disparity is 0, the current polarity Current RD shall maintain the previous polarity Preview RD. Note that when the current disparity is 0, the original 10b code is output instead of the inverted code regardless of whether the polarity Current RD is + or-.

FIG. 6 is a diagram illustrating control of running disparity in 9b10b coding. i represents the symbol cycle. _di'is a candidate for the disparity of each symbol before the polarity is determined, and _di is the disparity after the polarity is determined. When the total value Sum is non-zero, the polarity opposite to that polarity becomes the next polarity Current RD. When the total value Sum is zero, the polarity opposite to the current polarity Previous RD becomes the next polarity Current RD.

As shown in the second cycle and the third cycle of FIG. 6, the 9b10b coding differs from the 8b10b coding in that cases in which the same polarity is continuous can occur.

FIG. 7 is a table of an example of control of running disparity in 9b10b coding. Sum is the sum of the immediately preceding disparity di _-1 and the preceding disparity di _-2 . The Preview RD is the polarity of the previous disparity di _-1 , and the Current RD is the _polarity of the disparity di to be selected in the current symbol.

The coding circuit 100 can determine the polarity based on the table of FIG.

FIG. 8 is a block diagram showing a configuration example of the coding circuit 100. The 9b10b conversion circuit 110 includes a converter 112, a selector 114, and a bit inverting device 116.

The converter 112 is configured to be capable of generating a 10-bit symbol having a disparity of 0, -2, or -4. The converter 112 outputs a 10-bit symbol S2a corresponding to the 9-bit input data TX [8: 0]. The converter 112 may be configured to be capable of outputting a 10-bit symbol having a disparity of 0, + 2, + 4. The disparity controller 120 controls whether the output S2a of the converter 112 is output as it is or is bit-inverted and output. The converter 112 may be composed of a combinational circuit (logic circuit), or may include a conversion table, that is, a memory, which holds a correspondence between 9-bit input data and 10-bit symbols.

All bits of the 10-bit symbol are inverted by the bit reverser 116. The disparity of the output S2b of the bit inversion device 116 is one of 0, +2, and +4. However, the output S2b of the bit inversion device 116 when the disparity is 0 is not selected.

The selector 114 receives the output S2a of the converter 112 and the output S2b of the bit reversing device 116, and outputs one specified by the disparity controller 120.

FIG. 9 is a diagram showing a configuration example of the disparity controller 120. The disparity controller 120 includes an adder 122, a register 124, and a table 126. The adder 122 calculates the total value Sum of the disparity di _-1 and di _-2 over the past two times and stores it in the register 124. The register 124 also holds a bit 125 indicating the polarity Preview RD of the past disparity di _-1 . Table 126 selects the current polarity Current RD based on the sum value Sum and the polarity Premier RD. Bit 125 of register 124 is updated by the current polarity Current RD.

The configuration of the disparity controller 120 is not limited to that shown in FIG. 9, and may be configured by a state machine.

Subsequently, the decoding circuit 200 will be described. FIG. 10 is a block diagram of the decoding circuit 200. The decoding circuit 200 includes a conversion circuit 210 and a disparity error detector 220. The conversion circuit 210 includes a converter that converts the 10-bit symbol S5 into the 9-bit code S9. The converter may be composed of a combinational circuit or may include a memory.

In 9b10b coding, the polarity of the disparity is determined based on the table of FIG. In other words, any polarity that does not match this table is an error. Therefore, the decoding circuit 200 of the semiconductor device 400 includes a disparity error detector 220 that detects an error based on the relationship between the past disparity process over a plurality of times and the current disparity.

FIG. 11 is a table for explaining error detection by the disparity error detector 220. This table can be determined based on the table of FIG. The decoding circuit 200 refers to this table and generates a disparity error.

According to 9b10b coding, the overhead per 10 bits per symbol can be reduced to 1 bit, and the effective transmission rate can be increased as compared with 8b10b coding. Further, the DC balance can be maintained by monitoring the history of disparity over a plurality of times in the past.

(Use)
Subsequently, the uses of the coding circuit 100 and the decoding circuit 200 will be described. FIG. 12 is a block diagram of an image transmission system using 9b10b coding. The image transmission system 6 includes a semiconductor device 500 and a semiconductor device 600. The semiconductor device 500 corresponds to the above-mentioned semiconductor device 300, and transmits image data to the semiconductor device 600. For example, the semiconductor device 500 includes a timing controller, a bridge circuit, a repeater circuit, a splitter, a replicator, a selector, a switch, a hub, and the like. In this example, the semiconductor device 500 is a timing controller.

The semiconductor device 600 corresponds to the above-mentioned semiconductor device 400 and receives image data from the semiconductor device 500. For example, the semiconductor device 600 is a source driver and drives a display panel (not shown) based on the received image data. The semiconductor device 600 may be a timing controller, a bridge circuit, a repeater circuit, a splitter, a replicator, a selector, a switch, or a hub.

In this example, the semiconductor device 500 and the semiconductor device 600 are connected via a plurality (4) serial transmission lines 4A to 4D. In the semiconductor device 500 and the semiconductor device 600, each lane is similarly configured.

The semiconductor device 500 includes a lane distributor 502. In the lane distributor 502, the image data includes a plurality of pixels, and each pixel can contain 8-bit data of each subpixel of R, G, and B. The lane distributor 502 divides the image data into 9 bits and assigns them to each lane. Note that the 9 bits are a mixture of bits of different colors.

The CRC (Cyclic Redundancy Check) circuit 510 adds a 9-bit code including a bit for inspection after the image data.

The scrambler 520 scrambles the output data of the CRC circuit 510. The coding circuit 100 converts the scrambled 9-bit code into a 10-bit symbol. The 10-bit symbol is serial-serialized by the serializer 530 and transmitted to the semiconductor device 600.

In the semiconductor device 600, the deserializer 610 converts the received serial data into parallel data (10-bit symbols). The decoding circuit 200 converts the 10-bit symbol into the original 9-bit code. The descrambler 620 descrambles a 9-bit code. The CRC circuit 630 performs a cyclic redundancy check on the 9-bit code after descramble and detects an error.

The above is the use of 9b10b coding. In 8b10b encoding, 8-bit sub-pixel data R, G, B are assigned to one symbol. On the other hand, in the 9b10b coding, the data of a plurality of sub-pixels R, G, and B are mixed in the 9-bit code constituting one symbol. As a result, the effect of scrambling (noise diffusion) by the scramble circuit in the subsequent stage can be enhanced, and there is an advantage that the DC balance in the coding circuit 100 can be easily improved.

The present invention has been described above based on the embodiments. This embodiment is an example, and it will be understood by those skilled in the art that various modifications are possible for each of these components and combinations of each processing process, and that such modifications are also within the scope of the present invention. be. Hereinafter, such a modification will be described.

(Modification example 1)
In the embodiment, the disparity controller 120 is configured by using a table, but the present invention is not limited to this, and the disparity controller 120 may be configured by, for example, a state machine.

(Modification 2)
In the embodiment, the total value Sum of the two most recent disparities di _-1 and di _-2 is calculated, but the total value is not limited to this, and the total value of the most recent three or more times may be calculated.

Alternatively, the disparity controller 120 may cumulatively add the past disparity. That is, the polarity Current RD of the current disparity may be determined in consideration of all the disparity in the past. In this case, the total value may be calculated with -1 or +1 as the initial value. As a result, the total value does not become zero, so that the current polarity Current RD can be determined only by the polarity of the total value.

(Modification example 3)
The disparity controller 120 may determine the current polarity Current RD by the combination of the past two (or three or more times) disparity di _-1 and di _-2 without calculating the total value. ..

(Modification example 4)
In the embodiment, 9b10b coding has been described, but it can be extended to mbnb coding having an arbitrary number of bits (input bit number m, output bit number n). In this case, the conversion circuit 110 converts the m-bit input data into an n-bit symbol having a disparity of 0, ± 2, ..., ± 2k (k ≧ 2). The disparity controller 120 selects the polarity of the disparity of the current symbol based on the past k (or more) combinations of disparity. Preferably m = n + 1, which can reduce overhead.

The conversion circuit may include a converter capable of outputting an n-bit symbol having a disparity of 0, -2, ..., -2k, or 0, + 2, ..., + 2k. .. The disparity controller may control whether the symbol is output as it is or bit inverted.

The disparity controller may select the polarity of the disparity of the current symbol based on the total value of the disparity of the past k times. The disparity controller may select the polarity of the disparity of the current symbol based on the polarity of the previous disparity when the total value is zero.

The disparity controller may include a table that defines the relationship between the total value, the previous disparity, the candidate disparity of the current symbol, and the polarity of the disparity of the current symbol.

2 Data transmission system 4 Serial transmission line 6 Image transmission system 100 Coding circuit 110 9b10b Conversion circuit 112 Converter 114 Selector 116-bit reverser 120 Disparity controller 122 Adder 124 Register 126 Table 200 Decoding circuit 210 Conversion circuit 220 Disparity error Detector 300 Semiconductor device 302 Separator 304 Serializer 306 Transmitter 400 Semiconductor device 402 Receiver 404 Deserializer 500,600 Semiconductor device

Claims (24)

A coding circuit that converts 9-bit input data into 10-bit symbols.
A conversion circuit that converts the 9-bit input data into the 10-bit symbol having a disparity of 0, ± 2, ± 4.
A disparity controller that selects the polarity of the disparity of the current symbol based on the history of disparity over multiple times in the past,
A coding circuit comprising. The conversion circuit includes a converter capable of outputting the 10-bit symbol having a disparity of either 0, -2, -4 or 0, + 2, + 4.
The coding circuit according to claim 1, wherein the disparity controller controls whether the symbol is output as it is or is bit-inverted and output. The conversion circuit further includes an output of the converter and a selector that receives its inversion code.
The coding circuit according to claim 2, wherein the disparity controller switches the state of the selector. The disparity controller according to any one of claims 1 to 3, wherein the disparity controller selects the polarity of the disparity of the current symbol based on a combination of the immediately preceding disparity and the previous disparity. Coding circuit. The code according to claim 4, wherein the disparity controller selects the polarity of the disparity of the current symbol based on the total value of the immediately preceding disparity and the previous disparity. Circuit. The code according to claim 5, wherein the disparity controller selects the disparity polarity of the current symbol based on the polarity of the immediately preceding disparity when the total value is zero. Circuit. The claim is characterized in that the disparity controller includes a table that defines the relationship between the total value, the immediately preceding disparity, the disparity candidate of the current symbol, and the polarity of the disparity of the current symbol. Item 6. The coding circuit according to item 6. A coding circuit that converts m-bit input data into n-bit symbols (n> m).
A conversion circuit that converts the m-bit input data into the n-bit symbol having a disparity of 0, ± 2, ..., ± 2k (k ≧ 2).
A disparity controller that selects the polarity of the disparity of the current symbol based on the history of disparity k times or more in the past,
A coding circuit comprising. The conversion circuit
Includes a converter capable of outputting the n-bit symbol whose disparity is either 0, -2, ..., -2k, or 0, + 2, ..., + 2k.
The coding circuit according to claim 8, wherein the disparity controller controls whether the symbol is output as it is or is bit-inverted and output. The conversion circuit further includes an output of the converter and a selector that receives its inversion code.
The coding circuit according to claim 9, wherein the disparity controller switches the state of the selector. The coding circuit according to claim 10, wherein the disparity controller selects the polarity of the disparity of the current symbol based on the total value of the disparity of the past k times. 11. The coding according to claim 11, wherein the disparity controller selects the disparity polarity of the current symbol based on the polarity of the immediately preceding disparity when the total value is zero. circuit. The claim is characterized in that the disparity controller includes a table that defines the relationship between the total value, the immediately preceding disparity, the disparity candidate of the current symbol, and the polarity of the disparity of the current symbol. Item 12. The coding circuit according to item 12. The coding circuit according to any one of claims 9 to 13, wherein n = m + 1. A separator that cuts out 9 bits of data to be transmitted, and
The coding circuit according to any one of claims 1 to 14, which converts the 9-bit data into a 10-bit symbol.
A serializer that converts the output of the coding circuit into serial data,
The transmitter that transmits the serial data and
A semiconductor device characterized by being provided with. The semiconductor device according to claim 15, wherein the semiconductor device is an image transmission circuit. A data transmission system comprising the semiconductor device according to claim 15 or 16. A decoding circuit that converts a 10-bit symbol into 9-bit data.
The 10-bit symbol is generated by 9b10b coding that converts 9-bit data into the 10-bit symbol having a disparity of 0, ± 2, ± 4, and of each symbol. The polarity of the disparity is determined based on the history of multiple disparities in the past.
The decoding circuit
A conversion circuit that converts the 10-bit symbol into 9-bit data, and
A disparity error detector that detects an error based on the relationship between the past multiple disparity and the current disparity,
A decoding circuit characterized by comprising. A decoding circuit that converts n-bit symbols into m-bit (n> m) data.
The n-bit symbol is generated by 9b10b coding that converts m-bit data into the n-bit symbol having a disparity of 0, ± 2, ± 4, and is generated by each symbol. The polarity of the disparity is determined based on the history of multiple disparities in the past.
The decoding circuit
A conversion circuit that converts the n-bit symbol into m-bit data,
A disparity error detector that detects an error based on the relationship between the past multiple disparity and the current disparity,
A decoding circuit characterized by comprising. A receiver that receives serial data and
A deserializer that converts the serial data received by the receiver into symbols that are 10-bit parallel data, and
The decoding circuit according to claim 18 or 19, which converts the 10-bit symbol into 9-bit data.
A semiconductor device characterized by being provided with. A data transmission system comprising the semiconductor device according to claim 20. The semiconductor device according to claim 15 or 16.
The semiconductor device according to claim 20 and
A data transmission system characterized by being equipped with. A coding method that converts 9-bit input data into 10-bit symbols.
A step of converting the 9-bit input data into a symbol having a disparity of 0, 2, or 4 and
A step of inverting or non-inverting the symbol based on the history of disparity over the past multiple times.
A coding method comprising. A coding method that converts m-bit input data into n-bit symbols (n> m).
A step of converting the m-bit input data into the n-bit symbol having a disparity of 0, 2, ..., 2k (k ≧ 2).
A step of inverting or non-inverting the symbol based on the history of disparity k times or more in the past.
A coding method comprising.

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