JP2022106432A - Digital filter shift register - Google Patents

Abstract

To provide a digital filter shift register capable of simultaneously outputting data of multiple times.SOLUTION: A digital filter shift register includes a plurality of RAMs #1 to #N, a write control unit 110 that writes one piece of input data to the same write address of the plurality of RAMs #1 to #N and increments the write address each time one piece of data is written, and a read control unit 120 that performs control such that data is read simultaneously from different addresses in the plurality of RAMs.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to shift registers of digital filters.

The digital filter needs to acquire and process the data of a plurality of signals whose input signals are delayed at the same time at a certain time. A shift register is a configuration of multiple delay elements. In the method described in Patent Document 1, the shift register function is realized by the RAM inside the LSI (Large Scale Integrated Circuit) to suppress the number of flip-flops used inside the LSI. Generally, the capacity of one RAM is large, and it is possible to hold not only data at a certain time but also data at a plurality of times, which is effective in suppressing the number of flip-flops used. In order to store data in the RAM and output the data from the RAM, write control and read control by specifying an address are required, and one clock (processing unit time) is required for each of the write and read. Therefore, it takes at least 2 clocks from the data input to the data output. Further, the number of writeable and readable data is limited to one per hour. In the method described in Patent Document 1, the time of writing and reading the data of the input signal to the RAM is controlled, and the data is output with a delay of a specific time.

Special Table 2001-520429

However, when the method described in Patent Document 1 is applied to the shift register of the digital filter, only one data can be acquired at one time, so that the data at a plurality of times cannot be output at the same time.

Therefore, an object of the present disclosure is to provide a shift register of a digital filter capable of simultaneously outputting data at a plurality of times.

The shift register of the digital filter of the present disclosure is a write that writes a plurality of RAMs and one input data to the same write address of the plurality of RAMs, and increments the write address each time one data is written. It includes a control unit and a read control unit that controls so that data is read from different addresses of a plurality of RAMs at the same time.

According to the shift register of the digital filter of the present disclosure, data is read from different addresses of a plurality of RAMs at the same time, so that data at a plurality of times can be output at the same time.

FIG. 5 is an overall configuration diagram of a shift register of a digital filter according to the first embodiment. It is a figure which shows the structure of the light control unit 110. It is a flowchart which shows the setting procedure of a write address. It is a flowchart which shows the procedure of a light instruction. It is a figure which shows an example which input data is stored in RAM # 1 to RAM # N. It is a figure which shows the structure of the read control part 120. It is a flowchart which shows the setting procedure of a read address. It is a flowchart which shows the procedure of a read instruction. It is a figure which shows an example which the data stored in RAM # 1 to RAM # N is output. It is a timing chart which shows an example which input data is delayed and is output. It is a figure which shows the structure of the reset control unit 130. It is a flowchart which shows the recording procedure of a written address. It is a flowchart which shows the generation procedure of the initial value mask signal. It is a flowchart which shows the procedure of the initial value mask control.

Hereinafter, embodiments will be described with reference to the drawings.
Embodiment 1.
FIG. 1 is an overall configuration diagram of a shift register of a digital filter according to the first embodiment. The shift register of the digital filter has a configuration in which input data at a plurality of times can be acquired at the same time. The shift register of the digital filter includes a storage unit 100, a write control unit 110, a read control unit 120, a reset control unit 130, and an initial value mask control unit 140.

The storage unit 100 stores and outputs input data. The storage unit 100 includes a first RAM (RAM # 1) 102 (1), a second RAM (RAM # 2) 102 (2), ..., And an Nth RAM (RAM # N) 102 (N).
The write control unit 110 controls the writing of the input data to the storage unit 100.
The read control unit 120 controls the read of the stored data in the storage unit 100.

The reset control unit 130 executes the reset control while the reset is enabled and until the data is written to the storage unit 100.

The initial value mask control unit 140 outputs an initial value as output data according to the reset control of the reset control unit 130.

The storage unit 100 includes RAMs for the number of data that need to be acquired at the same time. In FIG. 1, the storage unit 100 includes N RAMs # 1 to RAM # N. N is 3 or more. Input data is stored in each RAM according to the control of the write control unit 110. The stored data in each RAM is output in a state where a necessary delay amount is added according to the control of the read control unit 120. The delay amount is given by changing the read address of each RAM and the timing of the read instruction.

In general, the data stored in RAM cannot be initialized immediately by resetting. Therefore, in the present embodiment, the output data is replaced with the initial value instead of initializing the data stored in RAM # 1 to RAM # N according to the control of the reset control unit 130 and the initial value mask control unit 140. As a result, initialization by reset is realized.

The write control unit 110 writes one input data to the same write address of a plurality of RAMs # 1 to RAM # N, and increments the write address each time one data is written. The write control unit 110 holds the original value without incrementing the write address when the write enable is invalid. The write control unit 110 returns the write address to the initial value when the reset is effective.

FIG. 2 is a diagram showing the configuration of the light control unit 110.
The write control unit 110 includes a write address setting unit 200 and a write instruction unit 210.
The write address setting unit 200 sets the write addresses of RAMs # 1 to RAM # N for storing the input data.

FIG. 3 is a flowchart showing the procedure for setting the write address.
In step S101, if the reset is valid, the process proceeds to step S102, and if the reset is invalid, the process proceeds to step S103.

In step S102, the write address setting unit 200 returns the write address to the initial value. This is because when the reset is enabled, the written address recorded in the written address recording unit 400, which will be described later, is cleared. Therefore, the write address controlled by the write control unit 110 is also returned to the initial value for matching. This is to take.

In step S103, when write enable is enabled, the process proceeds to step S104. If the write enable is invalid, the process proceeds to step S107.

In step S104, the write address setting unit 200 increments the write address in order to write the input data in order from the initial value of the addresses of RAM # 1 to RAM # N.

In step S105, when the write address exceeds the end of the address of RAM # 1 to RAM # N, the process proceeds to step S106, and when the write address does not exceed the end of the address of RAM # 1 to RAM # N, the process proceeds to step S106. The process proceeds to step S107.

In step S106, the write address setting unit 200 returns the write address to the initial value. As a result, it is possible to cope with the case where the input data is continuously input.

In step S107, the write address setting unit 200 sets the write address in RAM # to RAM # N. The same write address is set for N RAMs # 1 to RAM # N.

In step S103, when the write enable is invalid, the write address setting unit 200 holds the original value without incrementing the write address. As a result, not only the shift register function for continuously input data but also the shift register function for intermittently input data with write enable can be realized.

The write instruction unit 210 gives a write instruction to store input data in RAM # 1 to RAM # N.
FIG. 4 is a flowchart showing the procedure of the light instruction.
In step S201, if the write enable is enabled, the process proceeds to step S202, and if the write enable is disabled, the process proceeds to step S203.

In step S203, the write instruction unit 210 sets the write instruction for RAM # 1 to RAM # N to be invalid. As a result, the input data is not stored in RAM # 1 to RAM # N. The write address setting unit 200 holds the write address when the write enable is invalid. The input data is written to RAM # 1 to RAM # N only when write enable is enabled so that the stored data of the retained address is not overwritten by the input data.

In step S202, the write instruction unit 210 effectively sets the write instruction to RAM # 1 to RAM # N. As a result, the input data is stored in RAM # 1 to RAM # N.

When the write enable is enabled, the write control unit 110 effectively sets the write instruction to the same write address of RAM # 1 to RAM # N. Since the input data to each RAM is the same, the same input data is stored in all the RAMs # 1 to RAM # N constituting the storage unit 100 at the same time. The input data stored in each RAM is stored without missing even if the input data is continuous in time.
FIG. 5 is a diagram showing an example in which input data is stored in RAM # 1 to RAM # N.

First, the write addresses of RAM # 1 to RAM # N are set to the initial value "0", and the input data D (nt-7T) is stored in the set write addresses.

Next, after the time of the clock cycle T elapses, the write addresses of RAM # 1 to RAM # N are incremented to "1", and the input data D (nt-6T) is stored in the set write addresses.

Further, after the time of the clock cycle T elapses, the write addresses of RAM # 1 to RAM # N are incremented to "2", and the input data D (nt-5T) is stored in the set write addresses.

Further, after the time of the clock cycle T elapses, the write addresses of RAM # 1 to RAM # N are incremented to "3", and the input data D (nt-4T) is stored in the set write addresses.

When the input data D (nT-4T) is input, the stored data of RAM # 1 to RAM # N are all the same.

As shown in FIG. 5, the input data D (nT-7T), D (nT-6T), D (nT-5T), and D (nT-4T) are continuously input in time, but are omitted. Not all are stored.

Even for data that is intermittently input, the input data is stored in RAM # 1 to RAM # N without being chipped by the write address setting unit 200 and the write instruction unit 210.

The read control unit 120 controls the plurality of RAMs # 1 to RAM # N so that data is read from different addresses at the same time. The read control unit 120 sets the read addresses of the plurality of RAMs # 1 to RAM # N to a plurality of consecutive addresses. When the read enable is enabled, the read control unit 120 effectively sets the read instruction to the plurality of RAMs # 1 to RAM # N one by one at regular time intervals. The read control unit 120 returns the read addresses of the plurality of RAMs # 1 to RAM # N to the initial values when the reset is effective.

FIG. 6 is a diagram showing the configuration of the lead control unit 120.
The lead control unit 120 includes a setting unit 300 and an indicator unit 310.
The setting unit 300 sets the read addresses of the RAMs # 1 to RAM # N in order to acquire the stored data from the RAMs # 1 to RAM # N constituting the storage unit 100. The setting unit 300 includes a first read address setting unit 302 (1), a second read address setting unit 302 (2), and ..., an Nth read address setting unit 302 (N).
The i-th read address setting unit 302 (i) sets the read address (i) of the RAM # i.

FIG. 7 is a flowchart showing the procedure for setting the read address.
In step S301, if the reset is valid, the process proceeds to step S302, and if the reset is invalid, the process proceeds to step S303.

In step S302, the i-th read address setting unit 302 (i) returns the read address (i) to the initial value. For example, the i-th read address setting unit 302 (i) returns the read address (i) of RAM # i to “0”. However, i = 1 to N. This is for matching the comparison between the written address and the read address performed by the initial value mask signal generation unit 410, which will be described later, when the reset is enabled. If only the written address is returned to the initial value, the comparison with the read address will not be performed correctly. Therefore, the read address (i) is also returned to the initial value for matching.

In step S303, if read enable is enabled, the process proceeds to step S304. If read enable is disabled, processing proceeds to step S308.

In step S304, the first read address setting unit 302 (1) increments the read address (1) of the RAM # 1 in order to sequentially read the stored data starting with the initial value of the address of the RAM # 1.

In step S305, the i-th read address setting unit 302 (i) adjusts the read address (i) of the RAM # i according to the read address (1) of the RAM # 1. However, i = 2 to N.

For example, the i-th read address setting unit 302 (i) uses the address obtained by subtracting (i-1) from the read address (1) of RAM # 1 as the read address (i) of RAM # i. For example, when the read address (1) of the RAM # 1 is "2", the second read address setting unit 302 (2) sets the read address (2) of the RAM # 2 to "1", and the third read address setting unit 302 (2) sets the read address (2) of the RAM # 2 to "1". The read address setting unit 302 (3) sets the read address (3) of RAM # 3 to “0”. This causes a difference in the output data between RAM # 1 and RAM # N. By adjusting the output data and the output timing by the indicator 310, it is possible to simultaneously acquire data at a plurality of times required as a shift register function.

In step S306, when the read address (i) exceeds the end of the address of RAM # i, the process proceeds to step S307, and when the read address (i) does not exceed the end of the address of RAM # i, the process proceeds. The process proceeds to step S308. However, i = 1 to N.

In step S307, the i-th read address setting unit 302 (i) returns the read address (i) of the RAM # i to the initial value. However, i = 1 to N. By returning to the initial value, it is possible to handle the case where the stored data is continuously output.

In step S308, the i-th read address setting unit 302 (i) sets the read address (i) in the RAM # i. However, i = 1 to N.

In step S303, when the read enable is invalid, the first read address setting unit 302 (1) holds the original value without incrementing the read address (1). As a result, the shift register function can be realized not only for the shift register function that continuously outputs the stored data of the RAM but also for the digital filter that processes the data intermittently. Since the shift register function can be realized by adjusting the read control, it is not necessary to increase the number of RAMs.

The instruction unit 310 gives a read instruction to each RAM in order to acquire stored data from each RAM constituting the storage unit 100.

The instruction unit 310 includes a first lead instruction unit 312 (1), a second lead instruction unit 312 (2), ..., And an Nth lead instruction unit 312 (N). The i-th read instruction unit 312 (i) gives a read instruction to output the stored data of the RAM # i.
FIG. 8 is a flowchart showing the procedure of lead instruction.

In step S401, if read enable is enabled, the process proceeds to step S402. If the read enable is invalid, the process proceeds to step S405.

In step S402, the i-th read instruction unit 312 (i) waits for a delay amount corresponding to RAM # i. However, i = 2 to N. For example, the i-th read instruction unit 312 (i) waits for (i-1) clock cycles T. As a result, the read instruction can be given at the timing corresponding to the read address adjusted by the setting unit 300.
When the standby is completed in step S403, the process proceeds to step S404.

In step S404, the i-th read instruction unit 312 (i) effectively sets the read instruction to the RAM # i. However, i = 1 to N.

In step S405, the i-th read instruction unit 312 (i) sets the read instruction to the RAM # i to be invalid. However, i = 1 to N. As a result, the stored data is not read from RAM # i. The setting unit 300 holds the read address even when the read enable is invalid. No read instruction is given in order to repeatedly output the stored data of the retained address so as not to affect the circuit in the subsequent stage.

FIG. 9 is a diagram showing an example in which the data stored in RAM # 1 to RAM # N is output.
The read control unit 120 reads the data stored in RAM # 1 to RAM # N. Unlike write control, read control controls each RAM separately. The data stored in each RAM is the same, but the output data read from each RAM at the same time differs due to the adjustment of the read address and the timing adjustment of the read instruction. Since the output data of each RAM is different, a plurality of delayed data having the same function as the shift register is output.

After the time of the clock cycle T has elapsed, the read instruction of RAM # 1 becomes effective. Further, after the time of the clock cycle T has elapsed, the read instruction of RAM # 2 becomes effective. Further, after the time of the clock cycle T has elapsed, the read instruction of RAM # 3 becomes effective.

When the time of the clock cycle T elapses three times, the read data of RAM # 1 is D (nT-5T), the read data of RAM # 2 is D (nT-6T), and the read data of RAM # N is D (nT). -7T). As a result, continuous delays for three clock cycles are added, and output data can be acquired from the three RAMs at the same time.
FIG. 10 is a timing chart showing an example in which the input data is delayed and output.

In FIG. 10, for convenience of explanation, it is assumed that the storage unit 100 includes three RAMs # 1, RAM # 2, and RAM # 3.

The write instruction S20 of RAM # 1, the write instruction S90 of RAM # 2, and the write instruction S160 of RAM # 3 have the same timing.

The write address S30 of RAM # 1, the write address S100 of RAM # 2, and the write address S170 of RAM # 3 are the same at any time.

On the other hand, a continuous delay is realized by adjusting the timing for enabling the read instruction S60 of RAM # 1, the read instruction S130 of RAM # 2, and the read instruction S200 of RAM # 3. For example, as shown in FIG. 10, it is also possible to acquire the same output data with continuous delays at the same time.

By shifting the first timing at which the RAM # 1 read instruction S60, the RAM # 2 read instruction S130, and the RAM # 3 read instruction S200 become effective by one clock (T), a continuous delay occurs at the same time in the section 5 and thereafter. Three output data with the above are acquired.

For example, in the section 5, the RAM # 1 output data S80, the RAM # 2 output data S150, and the RAM # 3 output data S220 are D (nT-7T), D (nT-6T), and D (nT-5T), respectively. be. Continuous delay can be realized at the same time.

If the data is input intermittently as the target to be input to the shift register of the digital filter, it is possible to store all the input data in the RAM and then sequentially read and process the data. However, the processing time (latency) for storing the input data in the RAM increases. According to the present embodiment, the output data can be acquired by the read control unit 120 immediately after the input data is stored in the RAM, so that the latency is suppressed.

The initial value mask control unit 140 masks the output data of RAM # 1 to RAM # N by replacing the output data of RAM # 1 to RAM # N with the initial value when the reset is enabled.

The initial value mask control unit 140 replaces the output data of RAM # 1 to RAM # N with the initial value when the address of RAM # 1 to RAM # N whose input data is not written is instructed to the read address. Masks the output data of RAM # 1 to RAM # N. This is done because the stored data in the RAM is not initialized by reset.

FIG. 11 is a diagram showing the configuration of the reset control unit 130.
The reset control unit 130 includes a written address recording unit 400 and an initial value mask signal generation unit 410.
The written address recording unit 400 records the written addresses set in RAM # 1 to RAM # N.

FIG. 12 is a flowchart showing the recording procedure of the written address.
In step S501, if the reset is valid, the process proceeds to step S504, and if the reset is invalid, the process proceeds to step S502.

In step S502, the written address recording unit 400 acquires the write address from the write control unit 110.

In step S503, the written address recording unit 400 records the acquired write address as the written address.

In step S504, the written address recording unit 400 clears the recorded written address. As a result, the input data has not been written to RAM # 1 to RAM # N even once.

The initial value mask signal generation unit 410 acquires the written address from the written address recording unit 400 and acquires the read address from the read control unit 120, and enables the initial value mask signal to be valid for the initial value mask control unit 140. Or notify invalidity.

FIG. 13 is a flowchart showing the procedure for generating the initial value mask signal.
In step S601, if the reset is valid, the process proceeds to step S606, and if the reset is invalid, the process proceeds to step S602.

In step S602, the initial value mask signal generation unit 410 acquires the written address from the written address recording unit 400.

In step S603, the initial value mask signal generation unit 410 acquires a read address from the read control unit 120.

In step S604, if the read address is included in the written address, the process proceeds to step S605. If the read address is not included in the written address, the process proceeds to step S606.

In step S605, the initial value mask signal generation unit 410 sets the initial value mask signal for the initial value mask control unit 140 to be invalid.

In step S606, the initial value mask signal generation unit 410 effectively sets the initial value mask signal. The initial value mask signal is valid when the input data is not written in RAM # 1 to RAM # N and the place where the indefinite value or the value before reset is stored is specified as the read address. Also, when reset is enabled, the initial value mask signal is valid regardless of the written address and read address.

The initial value mask control unit 140 either replaces the output data of RAM # 1 to RAM # N with the initial value and masks it based on the state of the initial value mask signal generated by the reset control unit 130, or RAM # 1 to RAM. Switch whether to output the output data of #N as it is. The initial value mask control unit 140 masks the output data of RAM # 1 to RAM # N with the initial value when the initial value mask signal is valid.

FIG. 14 is a flowchart showing the procedure of initial value mask control.
In step S701, when the initial value mask signal is valid, the process proceeds to step S703, and when the initial value mask signal is invalid, the process proceeds to step S702.

In step S703, the initial value mask control unit 140 outputs the value specified as the initial value as the output delay data of RAM # 1 to RAM # N.

In step S702, the initial value mask control unit 140 outputs the data of RAM # 1 to RAN # N as output delay data.

In order to initialize the stored data in RAM # 1 to RAM # N by resetting, it is necessary to write (overwrite) all the stored data in RAM # 1 to RAM # N with the initial values, which takes a considerable amount of time. .. In the present embodiment, the output data of RAM # 1 to RAM # N is masked with the initial value by the initial value mask signal, thereby realizing the function equivalent to the reset. Since the time required for this process is only the time required for comparing the written address and the read address and generating the initial value mask signal, the reset function can be realized in a short time in the present embodiment.

In a system in which RAM is mounted, the RAM is not initialized immediately after startup, and an indefinite value is stored as stored data. If a read instruction is given to the RAM in this state, an indefinite value may be output and a malfunction may occur. In the present embodiment, the written address is not recorded until the input data is written to RAM # 1 to RAM # N, so that the initial value mask signal is valid regardless of which read address is read. Become. As a result, even if the indefinite value is output from RAM # 1 to RAM # N, the indefinite value is not processed by the initial value mask control unit 140 replacing the indefinite value with the initial value.

According to the present embodiment, as shown in the operation example of the timing chart of FIG. 10, output data to which a continuous delay amount is given can be acquired at the same time at the same time. Therefore, it is possible to continuously process the continuously input data.

Even when data is input intermittently instead of continuously input data, the shift register function can be realized without changing the number of RAMs by adjusting the read address by the setting unit 300. Further, although the input data is intermittent, the shift register function can be realized without changing the number of RAMs even when the data is continuously output.

When the data that is continuously input is thinned out and the data is processed intermittently, it can be realized by adjusting the read address by the setting unit 300. Further, since it is sufficient that RAM # 1 to RAM # N exist for the number of data that need to be acquired at the same time at the same time, the RAM can be used efficiently.

If the output data of the RAM is used as the input of the RAM in the subsequent stage, one clock (processing unit time) is required for each of the write and the read, so that a continuous delay amount cannot be given. When trying to give a continuous delay amount, for example, it is necessary to use two or more sets of the same configuration, and the number of RAMs used increases. In the configuration of this embodiment, since a continuous delay amount can be added as output data, the number of RAMs used can be reduced.

When the input data is input intermittently, it is conceivable that the input data is temporarily stored in the RAM and then sequentially read to perform the data acquisition process, but the latency until the start of the data acquisition process increases. In the present embodiment, since the data acquisition process can be performed immediately after the input data is input, the latency can be suppressed.

By masking the initial value of the output data of the RAM by the reset control unit 130 and the initial value mask control unit 140, the output data of the RAM can be immediately set as the initial value when the reset is enabled. When it is necessary to process the input data immediately after the initialization by reset, if it takes time to reset, there will be a period during which processing cannot be performed. However, in the present embodiment, since it is initialized immediately, it is processed continuously. Can be carried out.

In the RAM immediately after startup, if a read instruction is given to the RAM while the indefinite value is stored, the indefinite value may be output and a malfunction may occur. In the present embodiment, even if the reset control unit 130 and the initial value mask control unit 140 output an indefinite value, the indefinite value is replaced with the initial value and masked. Therefore, the indefinite value is not processed and a malfunction can be prevented.

It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The scope of the present disclosure is indicated by the scope of claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

100 storage unit, 110 write control unit, 120 read control unit, 130 reset control unit, 140 initial value mask control unit, 200 write address setting unit, 210 write indicator unit, 300 setting unit, 302 (1) 1st read address setting Unit, 302 (2) 2nd read address setting unit, 302 (N) Nth read address setting unit, 310 instruction unit, 312 (1) 1st read instruction unit, 312 (2) 2nd read instruction unit, 312 ( N) Nth read indicator, 400 written address recording unit, 410 initial value mask signal generation unit.

Claims (8)

With multiple RAMs
A write control unit that writes one input data to the same write address of the plurality of RAMs and increments the write address each time the one data is written.
A shift register of a digital filter including a read control unit that controls data to be read from different addresses of the plurality of RAMs at the same time. The shift register of the digital filter according to claim 1, wherein the read control unit sets the read addresses of the plurality of RAMs to a plurality of consecutive addresses. The digital filter according to claim 1 or 2, wherein the read control unit enables read instructions for the plurality of RAMs one by one at regular time intervals when the read enable is enabled. Shift register. The shift register of the digital filter according to any one of claims 1 to 3, wherein the read control unit returns the read addresses of the plurality of RAMs to initial values when the reset is effective. The shift register of the digital filter according to any one of claims 1 to 4, wherein the write control unit holds the original value without incrementing the write address when the write enable is invalid. The shift register of the digital filter according to any one of claims 1 to 5, wherein the write control unit returns the write address to an initial value when reset is effective. A written address recording unit that stores the written addresses set in the plurality of RAMs, and a written address recording unit.
An initial value mask signal generator that enables the initial value mask signal when the read address is not included in the written address,
6. The shift register of the described digital filter. The shift register of the digital filter according to claim 7, wherein the initial value mask signal generation unit further effectively sets the initial value mask signal when reset is effective.

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