JP2022104536A - Display device - Google Patents

Abstract

To control a pixel circuit with less control signals.SOLUTION: A drive circuit controls a pixel circuit with control signal pulses. In a threshold compensation period, a threshold compensation transistor is held ON to write a threshold compensation voltage. In a data write period after the threshold compensation period, a data signal is written. A pulse width of control signal pulses is at least twice as long as the data write period. The drive circuit turns a first transistor ON with a starting edge of a first control pulse before the data write period starts, holds the first transistor ON and turns a second transistor ON with a starting edge of a second control signal pulse after the threshold compensation period ends so as to start the data write period, and turns the first transistor OFF with an ending edge of the first control signal pulse to end the data write period.SELECTED DRAWING: Figure 3

Description

The present disclosure relates to a display device.

Since the OLED (Organic Light-Emitting Diode) element is a current-driven self-luminous element, it does not require a backlight and has advantages such as low power consumption, high viewing angle, and high contrast ratio. It is expected in the development of flat panel displays.

An active matrix (AM) type OLED display device includes a transistor that selects a pixel and a drive transistor that supplies a current to the pixel. The transistor in the OLED display device is a TFT (Thin Film Transistor), and a LTPS (Low Temperature Poly-silicon) TFT is generally used.

TFTs have variations in threshold voltage and charge mobility. Since the drive transistor determines the emission intensity of the OLED display device, variations in such electrical characteristics pose a problem. Therefore, in the pixel circuit of a general OLED display device, a correction circuit for correcting the variation and fluctuation of the threshold voltage of the drive transistor is mounted.

For example, an afterimage may occur in an OLED display device, and this phenomenon is called image retention. For example, if a black and white checkerboard pattern is displayed for a specific time and then an attempt is made to display an intermediate gradation on the entire screen, an afterimage of a checkerboard imitation of a different gradation is displayed for a while.

This is due to the history effect of the drive transistor. The historical effect is a phenomenon in which the drain current when the voltage between the gate and source changes from a high voltage to a low voltage and the drain current when the voltage changes from a low voltage to a high voltage in a field effect transistor are different. Point to.

That is, since the drain current when switching from black to intermediate gradation and the drain current when switching from white to intermediate gradation are different, the emission intensity of the OLED display device is different. Further, since this difference in drain current continues for several frames or more, it is visually recognized as an afterimage.

US Patent Application Publication No. 2019/0156751 US Patent Application Publication No. 2005/0200618

The image retention is caused by the current transient response characteristic due to the history effect of the drive TFT and the characteristic of the threshold voltage compensation of the drive TFT by the pixel circuit. In addition, if the threshold voltage compensation of the drive TFT is insufficient, the image quality may deteriorate. Further, in order to increase the definition and narrow the frame of the display device, it is desirable that the pixel circuit can be controlled with a smaller number of control signals.

The display device of one aspect of the present disclosure includes a display area including a plurality of pixel circuit lines and a drive circuit. Each of the multi-pixel circuit lines includes a multi-pixel circuit. Each of the plurality of pixel circuits is connected in series with a drive transistor that controls the amount of current to the light emitting element, a holding capacity that holds the control voltage of the driving transistor, and a data signal that is transmitted to the holding capacity. It includes a first transistor and a second transistor, and a threshold compensation transistor for writing the threshold compensation voltage of the drive transistor to the holding capacitance. The drive circuit shifts the control signal pulse from the front stage to the rear stage at regular intervals in the multi-pixel circuit line. The pulse width of the control signal pulse is at least twice the fixed period. The drive circuit keeps the threshold compensation transistor ON during the threshold compensation period and writes the threshold compensation voltage to the holding capacitance. In the data writing period after the threshold compensation period, the drive circuit keeps the threshold compensation transistor OFF, the first transistor and the second transistor ON, and writes a data signal to the holding capacitance. The pulse width of the control signal pulse is at least twice the data writing period. The drive circuit controls the first transistor with a first control signal pulse. The drive circuit controls the second transistor with a second control signal pulse different from the first control signal pulse. The drive circuit turns on the first transistor by the start edge of the first control signal pulse before the start of the data write period. After the end of the threshold compensation period, the drive circuit keeps the first transistor ON and turns the second transistor ON by the start edge of the second control signal pulse to start the data write period. The drive circuit turns off the first transistor by the end edge of the first control signal pulse to end the data writing period.

According to one aspect of the present disclosure, the image quality of the display device can be improved.

A configuration example of the OLED display device is schematically shown. A configuration example of a pixel circuit and a control signal according to an embodiment of the present specification is shown. An example of a signal timing chart for controlling the pixel circuit shown in FIG. 2 is shown. Another example of the timing chart of the signal for controlling the pixel circuit shown in FIG. 2 is shown. The layout of the control signal line for transmitting the control signal to the pixel circuit shown in FIG. 2 is schematically shown. Different examples of pixel circuits and control signals are shown. Different examples of pixel circuits and control signals are shown. Different examples of pixel circuits and control signals are shown. Different examples of pixel circuits and control signals are shown. An example of a signal timing chart for controlling the pixel circuit shown in FIG. 9 is shown. The layout of the control signal line for transmitting the control signal to the pixel circuit shown in FIG. 9 is schematically shown. Other configuration examples of the pixel circuit and the control signal are shown. An example of a signal timing chart for controlling the pixel circuit shown in FIG. 12 is shown. The layout of the control signal line for transmitting the control signal to the pixel circuit shown in FIG. 12 is schematically shown. Other configuration examples of the pixel circuit and the control signal are shown. An example of a signal timing chart for controlling the pixel circuit shown in FIG. 15 is shown. Other configuration examples of the pixel circuit and the control signal are shown. A plurality of continuous pixel circuit line areas are schematically shown. Other configuration examples of the pixel circuit and the control signal are shown. Other configuration examples of the pixel circuit and the control signal are shown. A plurality of continuous pixel circuit line areas are schematically shown. Other configuration examples of the pixel circuit and the control signal are shown.

Hereinafter, embodiments will be described with reference to the drawings. The same reference numerals are given to the common configurations in each figure. In order to make the explanation easier to understand, the dimensions and shapes of the illustrated objects may be exaggerated.

Hereinafter, a technique for improving drive current control in a light emitting type display device using a light emitting element that emits light by a drive current, such as an OLED (Organic Light-Emitting Diode) display device, will be disclosed. More specifically, a technique for appropriately compensating the threshold value of the drive transistor by a control signal having a small number of pixel circuits and improving the display quality will be disclosed.

For example, the image retention is caused by the current transient response characteristic due to the history effect of the drive transistor and the threshold voltage compensation characteristic of the drive transistor by the pixel circuit. Not limited to image retention, image quality may deteriorate when the threshold voltage compensation of the drive transistor is insufficient.

The display device according to the embodiment of the present specification writes a data signal to the holding capacity after writing a voltage for compensating the threshold value of the drive transistor to the holding capacity of the pixel circuit. The pixel circuit includes a switch transistor connected in series that transmits a data signal to the holding capacitance. The display device controls these switch transistors by different control signal pulses. The pulse width of these control signal pulses is more than twice the data writing period, and the phases (edge times) are different. By controlling the switch transistors connected in series with control signal pulses having different phases for a predetermined period, the threshold compensation of the drive transistor can be effectively performed with a small number of control signals.

[Display device configuration]
Hereinafter, embodiments of the present specification will be described in more detail. FIG. 1 schematically shows a configuration example of the OLED display device 1. The OLED display device 1 includes a TFT (Thin Film Transistor) substrate 10 on which an OLED element and a pixel circuit are formed, and a thin film encapsulation structure (TFE: Thin Film Encapsulation) 20 for encapsulating an organic light emitting element. Has been done. The thin film sealing structure 20 is one of the sealing structure portions, and as another example, the sealing structure portion joins a sealing substrate for sealing an organic light emitting element, a TFT substrate 10, and a sealing substrate. A joint portion (glass frit seal portion) to be formed can be included. For example, dry air or nitrogen is sealed between the TFT substrate 10 and the sealing substrate.

A scanning driver 31, an emission driver 32, a protection circuit 33, a driver IC 34, and a demultiplexer 36 are arranged around a cathode electrode forming region 14 outside the display region 25 of the TFT substrate 10. The driver IC 34 is connected to an external device via an FPC (Flexible Printed Circuit) 35. These circuits are included in the control circuit that controls the OLED display device 1. Some of these circuits may be omitted.

The scanning driver 31 drives the scanning lines of the TFT substrate 10. The emission driver 32 drives a light emission control line to control the light emission period of each pixel. As will be described later, the emission driver 32 may drive a scanning line for threshold compensation or data writing of the driving transistor in addition to the emission control line. Therefore, the scanning driver 31 may be referred to as a first scanning driver, and the emission driver 32 may be referred to as a second scanning driver. The emission control line is also a scanning line because the pixel circuit lines are sequentially selected. The scanning line and the light emission control line are control lines for controlling the pixel circuit.

The scanning driver 31 and the emission driver 32 are included in the drive circuit that drives the pixel circuit. A circuit that outputs the same control signal as the scanning driver 31 and the emission driver 32 may be arranged only on one side of the display area 25.

The scanning driver 31 and the emission driver 32 are arranged on opposite sides of the display area 25. The scanning lines and the light emission control lines extend in the left-right direction in FIG. 1, and are arranged in the up-down direction, for example. The driver IC 34 is mounted using, for example, an anisotropic conductive film (ACF).

The protection circuit 33 prevents electrostatic destruction of the elements in the pixel circuit. The driver IC 34 supplies a power supply and a timing signal (control signal) to the scanning driver 31 and the emission driver 32. Further, the driver IC 34 supplies a power supply and a data signal to the demultiplexer 36.

The demultiplexer 36 sequentially outputs the output of one pin of the driver IC 34 to d (d is an integer of 2 or more) data lines. The data lines extend in the vertical direction and are arranged in the horizontal direction in FIG. 1, for example. The demultiplexer 36 drives the data line d times the number of output pins of the driver IC 34 by switching the output destination data line of the data signal from the driver IC 34 d times within the scanning period.

As will be described later, each pixel circuit includes a drive TFT (drive transistor) and a holding capacity that holds a signal voltage that determines the drive current of the drive TFT. The data signal transmitted by the data line is corrected according to the threshold value of the drive TFT and stored in the holding capacitance. The voltage of the holding capacitance portion determines the gate voltage (Vgs) of the drive TFT. The corrected data signal changes the conductance of the drive TFT in an analog manner, and supplies a forward bias current corresponding to the emission gradation to the OLED element.

[Pixel circuit configuration]
FIG. 2 shows a configuration example of the pixel circuit 200 and the control signal according to the embodiment of the present specification. The pixel circuit 200 is included in the pixel circuit line of the Nth stage (N is an integer). The pixel circuit 200 includes seven transistors (TFTs) M11-M17 with gates, sources and drains. In this example, all the transistors M11 to M17 are P-type TFTs (the polarity of the transistors is P-type).

The transistor M11 is a drive transistor that controls the amount of current to the OLED element E1. The source of the drive transistor M11 is connected to a power line 241 that transmits the power potential P VDD. The drive transistor M11 controls the amount of current applied from the power supply line 241 to the OLED element E1 according to the voltage held by the holding capacity C10. The holding capacity C10 holds the written voltage throughout one frame period. The cathode of the OLED element E1 is connected to a power line 204 that transmits the power potential PVEE from the cathode power supply.

In the configuration example of FIG. 2, the holding capacity C10 is composed of the capacities C11 and C12 connected in series. One end of the holding capacitance C10 is given an anode power supply potential P VDD, and the other end is connected to the source / drain of the switch transistors M13 and M14. Further, the other end of the holding capacitance C10 is connected to the gate of the drive transistor M11.

More specifically, one end of the capacitance C12 is connected to the power supply line 241. One end of the capacitance C11 is connected to the source / drain of the switch transistors M13 and M14. The intermediate nodes of the capacitances C11 and C12 are connected to the gate of the drive transistor M11.

The voltage of the holding capacitance C10 is the voltage between the gate of the drive transistor M11 and the anode power supply line 241. The source of the drive transistor M11 is connected to the anode power supply line 241 and the source potential is the anode power supply potential P VDD. Therefore, the holding capacitance C10 holds the gate-source voltage of the drive transistor M11. In the configuration example of FIG. 2, the capacitance C12 holds the gate-source voltage of the drive transistor M11.

The transistor M15 is a light emission control switch transistor that controls the supply of a drive current to the OLED element E1 and the ON / OFF of light emission by the supply. The source of the transistor M15 is connected to the drain of the drive transistor M11. The transistor M15 turns on / off the current supply to the OLED element E1 connected to the drain thereof. The gate of the transistor M15 is connected to the control signal line 232A, and the transistor M15 is controlled by the light emission control signal Em_N input to the gate from the emission driver 32. The light emission control signal is a selection signal that controls the light emission of the OLED element E1.

The transistor M16 operates for supplying the reset potential Vrst to the anode of the OLED element E1. One end of the source / drain of the transistor M16 is connected to a power line 242 that transmits the reset potential Vrst, and the other end is connected to the anode of the OLED element E1.

The gate of the transistor M16 is connected to the control signal line 231A, and the transistor M16 is controlled by the selection signal S_N. When the transistor M16 is turned on by the selection signal S_N from the scanning driver 31, the reset potential Vrst transmitted by the power supply line 242 is given to the anode of the OLED element E1. Further, the transistors M15 and M16 give a reset potential Vrst to the gate of the drive transistor M11 via the transistor M12.

The transistor M12 is a switch transistor (threshold compensation transistor) for writing a voltage for performing threshold correction (threshold compensation) of the drive transistor M11 to the holding capacitance C10, and is a transistor for resetting the gate potential of the drive transistor M11. be. The source and drain of the transistor M12 connect the gate and drain of the drive transistor M11. Therefore, when the transistor M12 is ON, the drive transistor M11 is in a diode-connected state.

The transistor M14 is a switch transistor (threshold value compensating transistor) for writing a voltage for performing threshold value compensation for the drive transistor M11 to the holding capacitance C10. The transistor M14 controls whether or not the reference potential Vref is supplied to the holding capacitance C10. One end of the source / drain of the transistor M14 is connected to a power line 202 that transmits the reference potential Vref, and the other end is connected to one end of the capacitance C11. The gate of the transistor M14 is connected to the control signal line 231A, and the transistor M14 is controlled by the selection signal S_N input to the gate from the scanning driver 31.

The transistors M12, M16 and M14 are controlled by the selection signal S_N. Therefore, these transistors M12, M16 and M14 are turned on / off at the same time. During the period in which these are in the ON state, the gate potential of the drive transistor M11 is reset when the transistor M15 is ON. After that, the transistor M15 is turned off. When the transistors M12 and M14 are ON, the transistor M11 constitutes a diode-connected transistor. A threshold compensation voltage is written in the holding capacity C10 between the power supply potential P whether and the reference potential Vrst.

The transistors M13 and M17 connected in series are switch transistors for selecting a pixel circuit for supplying a data signal and writing a data signal (data signal voltage) Vdata to the holding capacitance C10.

One end of the source / drain of the transistor M13 is connected to the holding capacitance C10, and the other end is connected to one end of the source / drain of the transistor M17. More specifically, one end of the source / drain of the transistor M13 is connected to one end of the capacitance C11. The other end of the source / drain of the transistor M17 is connected to a data line 237 that transmits the data signal Vdata.

The gate of the transistor M13 is connected to a control signal line 232B that transmits a light emission control signal Em_N-1 from the emission driver 32. The transistor M13 is controlled by the light emission control signal Em_N-1. The light emission control signal Em_N-1 is a signal that controls the light emission of the pixel circuit line in the (N-1) stage, but the transistor M13 is not a transistor that controls the light emission of the OLED element E1, but data to the holding capacitance C10. It is a switch transistor that controls the supply of the signal Vdata.

The gate of the transistor M17 is connected to the control signal line 231B that transmits the selection signal S_N + 1 from the scanning driver 31. The transistor M17 is controlled by the selection signal S_N + 1. The selection signal S_N + 1 is a signal for selecting the pixel circuit line in the (N + 1) th stage. The transistor M17 controls the supply of the data signal Vdata to the holding capacitance C10.

When the transistors M13 and M17 are ON at the same time, the transistors M13 and M17 give the data signal Vdata supplied from the driver IC 34 via the data line 237 to the holding capacitance C10. As described above, since the transistors M13 and M17 are controlled by the control signals of different pixel circuit lines, the data signal Vdata is set to the holding capacity C10 only during the period when the two control signals S_N + 1 and Em_N-1 are at the low level at the same time. Can be given.

FIG. 3 is an example of a signal timing chart for controlling the pixel circuit 200 shown in FIG. 2, and is an operation of writing the threshold compensation voltage of the drive transistor M11 and the data signal Vdata to the pixel circuit of the Nth stage pixel circuit line. Shows.

Specifically, FIG. 3 shows a selection signal S_N in the Nth stage pixel circuit line for writing the data signal Vdata, a selection signal S_N + 1 in the (N + 1) stage pixel circuit line, and a pixel circuit in the (N-1) stage. The time change of the signal potential level in one frame of the light emission control signal Em_N-1 in the row and the light emission control signal Em_N in the pixel circuit row of the Nth stage is shown. The selection signal is one of the control signals and is also called a scanning signal.

In the timing chart of FIG. 3, the 1H period is a period in which the data signal Vdata is written in the pixel circuit, and is a period in which the transistors M13 and M17 are ON. The threshold compensation period is 1H or more, which is 2H in the example of FIG.

At time T1, the selection signal S_N + 1 is High and the transistor M17 is OFF. Further, the light emission control signal Em_N is Low, and the transistor M15 is ON.

At time T1, the selection signal S_N changes from High to Low, and the light emission control signal Em_N-1 changes from Low to High. Transistors M12, M14 and M16 change from OFF to ON in response to changes in the selection signal S_N. The transistor M13 changes from ON to OFF in response to a change in the light emission control signal Em_N-1.

The transistor M16 is changed to ON, and the supply of the reset potential Vrst to the anode of the OLED element E1 is started. The transistors M12, M15 and M16 are ON, and the supply of the reset potential Vrst to the gate of the drive transistor M11 is started. This state continues from time T1 to time T2. Times T1 to T2 are reset periods of the anode potential of the OLED element E1 and the gate potential of the drive transistor M11. The period length from time T1 to time T2 is 1H. During the reset period, the transistors M13 and M17 are OFF.

At time T2, the selection signal S_N + 1 changes from High to Low. Further, at time T2, the light emission control signal Em_N changes from Low to High. In response to the change in the selection signal S_N + 1, the transistor M17 changes from OFF to ON. The transistor M15 changes from ON to OFF in response to a change in the light emission control signal Em_N. When the transistor M15 changes to OFF, the supply of the reset potential Vrst to the gate of the drive transistor M11 is stopped.

At time T2, the transistors M12, M14, M16, and M17 are ON. Transistors M13 and M15 are OFF. Since the transistors M13 and M15 are OFF and the transistors M12 and M14 are ON, the threshold compensation voltage is written in the holding capacity C10. At time T2, writing of the threshold compensation voltage to the holding capacity C10 starts. As described above, with the start of the threshold compensation period, the transistor M17 is turned on from OFF by the start edge of the selection signal S_N + 1.

From time T2 to time T3, the potential levels of the signals S_N, S_N + 1, Em_N-1, and Em_N are maintained. At time T3, the selection signal S_N changes from Low to High. Further, the light emission control signal Em_N-1 changes from High to Low.

In response to the change in the selection signal S_N, the transistors M12, M14, and M16 change from ON to OFF. Therefore, at time T3, the writing of the threshold compensation voltage to the holding capacity C10 is completed. The period from the time T2 to T3 is the writing period of the threshold compensation voltage to the holding capacity C10, and the length thereof is 2H in the example of FIG.

The transistor M13 changes from OFF to ON in response to a change in the light emission control signal Em_N-1 at time T3. The transistors M13 and M17 are ON, and the data signal Vdata is written to the holding capacitance C10 via the transistors M13 and M17. At time T3, writing of the data signal Vdata to the holding capacity C10 starts. From time T3 to time T4, the potential levels of the signals S_N, S_N + 1, Em_N-1, and Em_N are maintained.

At time T4, the selection signal S_N + 1 changes from Low to High. As a result, the transistor M17 is turned from ON to OFF, and data writing to the Nth pixel circuit line is completed. Times T3 to T4 are data writing periods in the Nth pixel circuit line, and the length thereof is 1H. After the time T4, the selection signal S_N + 1 is maintained at High.

At time T4, the light emission control signal Em_N changes from High to Low. As a result, the transistor M15 changes from OFF to ON. As a result, a drive current is applied to the OLED element E1, and the OLED element starts emitting light.

FIG. 4 is another example of the signal timing chart for controlling the pixel circuit 200 shown in FIG. 2, in which the threshold compensation voltage of the drive transistor M11 and the data signal Vdata are written in the pixel circuit of the Nth stage pixel circuit line. The operation for this is shown. Specifically, FIG. 4 shows the time change of the signal potential level of the selection signal S_N, the selection signal S_N + 1, the light emission control signal Em_N-1, and the light emission control signal Em_N in one frame.

In the timing chart of FIG. 4, the 1H period is a period in which the data signal Vdata is written in the pixel circuit, and is a period in which the transistors M13 and M17 are ON. The threshold compensation period is 1H or more, which is 1H in the example of FIG.

At time T11, the selection signal S_N + 1 is High and the transistor M17 is OFF. Further, the light emission control signal Em_N is Low, and the transistor M15 is ON.

At time T11, the selection signal S_N changes from High to Low, and the light emission control signal Em_N-1 changes from Low to High. Transistors M12, M14 and M16 change from OFF to ON in response to changes in the selection signal S_N. The transistor M13 changes from ON to OFF in response to a change in the light emission control signal Em_N-1.

The transistor M16 is changed to ON, and the supply of the reset potential Vrst to the anode of the OLED element E1 is started. The transistors M12, M15 and M16 are ON, and the supply of the reset potential Vrst to the gate of the drive transistor M11 is started. This state continues from time T11 to time T12. Times T11 to T12 are reset periods of the anode potential of the OLED element E1 and the gate potential of the drive transistor M11. The period length from time T11 to time T12 is 1H.

At time T12, the selection signal S_N + 1 changes from High to Low. Further, at time T12, the light emission control signal Em_N changes from Low to High. In response to the change in the selection signal S_N + 1, the transistor M17 changes from OFF to ON. The transistor M15 changes from ON to OFF in response to a change in the light emission control signal Em_N. When the transistor M15 changes to OFF, the supply of the reset potential Vrst to the gate of the drive transistor M11 is stopped.

At time T12, the transistors M12, M14, M16, and M17 are ON. Transistors M13 and M15 are OFF. Since the transistors M13 and M15 are OFF and the transistors M12 and M14 are ON, the threshold compensation voltage is written in the holding capacity C10. At time T12, writing of the threshold compensation voltage to the holding capacity C10 starts.

From time T12 to time T13, the potential levels of the signals S_N, S_N + 1, Em_N-1, and Em_N are maintained. At time T13, the selection signal S_N changes from Low to High. Further, the light emission control signal Em_N-1 changes from High to Low.

In response to the change in the selection signal S_N, the transistors M12, M14, and M16 change from ON to OFF. Therefore, at time T13, the writing of the threshold compensation voltage to the holding capacity C10 is completed. The period from the time T12 to T13 is the writing period of the threshold compensation voltage to the holding capacity C10, and the length thereof is 1H in the example of FIG.

The transistor M13 changes from OFF to ON in response to a change in the light emission control signal Em_N-1 at time T13. The transistors M13 and M17 are ON, and the data signal Vdata is written to the holding capacitance C10 via the transistors M13 and M17. At time T13, writing of the data signal Vdata to the holding capacity C10 starts. From time T13 to time T14, the potential levels of the signals S_N, S_N + 1, Em_N-1, and Em_N are maintained.

At time T14, the selection signal S_N + 1 changes from Low to High. As a result, the transistor M17 is turned from ON to OFF, and data writing to the Nth pixel circuit line is completed. Times T13 to T14 are data writing periods in the Nth pixel circuit line, and the length thereof is 1H. After the time T14, the selection signal S_N + 1 is maintained at High.

At time T14, the light emission control signal Em_N changes from High to Low. As a result, the transistor M15 changes from OFF to ON. As a result, a drive current is applied to the OLED element E1, and the OLED element starts emitting light.

In the above example, the transistors M13 and M17 are controlled by different control signal pulses. Specifically, the transistor M17 is controlled by the pulse of the control signal S_N + 1, and the transistor M13 is controlled by the pulse of the control signal Em_N-1.

The transistor M17 (example of the first transistor) is turned on by the start edge of the pulse of the control signal S_N + 1 at the time T2 or T12 before the start of the data writing period. The transistor M13 (example of the second transistor) is turned on by the pulse start edge of the control signal Em_N-1 at the start time T3 or T13 of the data writing period. The transistor M17 is turned off by the end edge of the pulse of the control signal S_N + 1 at the end time T4 or T14 of the data writing period.

In the timing chart described with reference to FIG. 4, the pulse width of the control signal is 2H, which is twice the data writing period. The threshold compensation period is the same as the data writing period. In the timing chart described with reference to FIG. 3, the pulse width of the control signal is 3H, which is three times the data writing period. The threshold compensation period is twice the data writing period. The bals width of the control signal pulse can be further increased, which can increase the threshold compensation period.

By controlling the transistors M13 and M17 with different control signal pulses of 2H or more, a threshold compensation period can be formed before the data writing period of 1H with a small number of control signal pulses. Further, by adjusting the pulse width of the control signal pulse, a desired threshold compensation period can be formed.

FIG. 5 schematically shows the layout of a control signal line for transmitting a control signal to the pixel circuit 200. The display area 25 includes a plurality of pixel circuits 200 that control the light emission of the OLED element of each of the plurality of pixels. In FIG. 5, one pixel circuit is designated by reference numeral 200 as an example. In the configuration example of FIG. 5, the pixel circuits 200 are arranged in a matrix. The layout of the pixel circuit is not particularly limited.

In a color OLED display device, each OLED element emits, for example, either red, blue, or green. The plurality of pixel circuits 200 constitute a pixel circuit array. In the configuration example of FIG. 5, one pixel circuit line is composed of a plurality of pixel circuits 200 arranged in the X-axis direction (left-right direction in FIG. 5). Each pixel circuit line is controlled by a common control signal line.

Data lines (not shown) are connected to one pixel circuit column, and each pixel circuit column is connected to one pixel circuit in each pixel circuit row. The data line transmits a data signal that specifies the emission luminance to the pixel circuit of the selected pixel circuit line.

The first shift register 310 is included in the scanning driver 31. The first shift register 310 includes a plurality of connected shift register units 312. The shift register unit 312 is a flip-flop. In FIG. 5, one shift register unit is designated by reference numeral 312 as an example. The shift register unit 312 from the (N-1) stage to the (N + 3) stage is shown as an example. The reference numeral in the shift register unit 312 indicates a control signal output by the shift register unit 312. For example, the shift register unit S_N outputs the selection signal S_N.

The second shift register 320 is included in the emission driver 32. The second shift register 320 includes a plurality of connected shift register units 322. The shift register unit 322 is a flip-flop. In FIG. 5, one shift register unit is designated by reference numeral 322 as an example. The reference numeral in the shift register unit 322 indicates a control signal output by the shift register unit 322. For example, the shift register Em_N outputs a light emission control signal Em_N.

The first shift register 310 drives control signal lines 231A and 231B extending along the X-axis according to a clock signal (not shown). The control signal lines 231A and 231B transmit the same control signal output from each shift register unit 312. In FIG. 5, two control signal lines from one shift register unit 312 are indicated by reference numerals 231A and 231B, respectively, as examples.

The second shift register 320 drives the control signal lines 232A and 232B extending along the X axis according to a clock signal (not shown). The control signal lines 232A and 232B transmit the same control signal output from each shift register unit 322. In FIG. 5, two control signal lines from one shift register unit 322 are indicated by reference numerals 232A and 232B, respectively, as examples.

The control signal line 231A transmits the selection signal S_K output by the shift register unit 312 in the Kth stage (K is an integer) to the pixel circuit line in the Kth stage. The control signal line 231B transmits the selection signal S_K output by the shift register unit 312 in the Kth stage to the pixel circuit line in the (K-1) stage.

The control signal line 232A transmits the light emission control signal Em_K output by the shift register unit 322 in the Kth stage to the pixel circuit line in the Kth stage. The control signal line 232B transmits the light emission control signal Em_K output by the shift register unit 322 in the Kth stage to the pixel circuit line in the (K + 1) stage.

The pixel circuit 200 constituting the pixel circuit line is connected to a common control signal line 231A, 231B, 232A, 232B, and is controlled by the same control signal transmitted by these control signal lines. The control method of the pixel circuit 200 has been described with reference to FIGS. 3 or 4.

The first shift register 310 sequentially outputs signal pulses according to a start pulse signal and a clock signal (not shown). The start pulse signal is a signal having a period of one frame, and has the same pulse width as the pulse output by each control signal line in FIGS. 3 and 4. In the example of the timing chart of FIG. 3, the first shift register 310 shifts a signal pulse having a width of 3H from the front stage to the rear stage every 1H in the connected shift register unit 312. The reference output level of the shift register unit 312 is High, and the potential level of the signal pulse is Low.

In the example of the timing chart of FIG. 4, the first shift register 310 shifts a signal pulse having a width of 2H from the front stage to the rear stage every 1H in the connected shift register unit 312.

The second shift register 320 sequentially outputs signal pulses according to a start pulse signal and a clock signal (not shown). The start pulse signal is a signal having a period of one frame, and has the same pulse width as the pulse output by each control signal line in FIGS. 3 or 4. In the example of the timing chart of FIG. 3, the second shift register 320 shifts a signal pulse having a width of 3H from the front stage to the rear stage every 1H in the connected shift register unit 322.

In this way, the second shift register 320 shifts the signal pulse for the 3H period from the front stage to the rear stage every 1H with respect to the pixel circuit line. The reference output level of the shift register unit 322 is Low, and the signal pulse is High. That is, the polarity of the signal pulse output by the second shift register 320 is opposite to the polarity of the signal pulse output by the first shift register 310.

As shown in FIG. 3, the phases of the signal pulses output by the shift register units of the same stage of the first shift register 310 and the second shift register 320 differ by 1H. The pulse of the second shift register 320 is delayed by 1H from the pulse of the first shift register 310. That is, the shift register unit 312 of the (K-1) stage, the K stage and the (K + 1) stage, and the shift register unit 322 of the (K-2) stage, the (K-1) stage and the K stage are pulsed during the same period. Is output.

In the example of the timing chart of FIG. 4, the second shift register 320 shifts a signal pulse having a width of 2H from the front stage to the rear stage every 1H in the connected shift register unit 322. Other points are the same as the example of FIG.

As described above, the first shift register 310 shifts the control signal pulse of the first polarity (Low) from the front stage to the rear stage at regular intervals in the pixel circuit line. The second shift register 320 shifts the control signal pulse of the opposite polarity (High) of the first polarity from the front stage to the rear stage at regular intervals in the pixel circuit line. The control signal pulse from the first shift register 310 and the control signal pulse from the second shift register 320 are synchronized.

The pixel circuit is controlled by two control signals S_N and S_N + 1 from the first shift register 310 and two control signals Em_N-1 and Em_N from the second shift register 320. By controlling the pixel circuit with two control signals from different shift registers, the layout of the control line becomes easy. The circuit that generates the control signal may include a circuit other than the shift register. Further, the data writing period may be different from the clock period of the control signal pulse, for example, shorter than the clock period. These points are the same in the other configuration examples described below.

FIG. 6 shows different examples of pixel circuits and control signals. The difference from the pixel circuit 200 shown in FIG. 2 will be mainly described. The pixel circuit 210 shown in FIG. 6 includes a holding capacity C20 instead of the holding capacity C10 of the pixel circuit 200 shown in FIG. The holding capacity C20 is composed of the capacities C21 and C22 connected in series between the power supply line 241 transmitting the anode power supply potential P whether and the gate of the drive transistor M11.

A power supply line 241 is connected to one end of the capacity C22. One end of the capacity C21 is connected to the other end of the capacity C22. The gate of the drive transistor M11 is connected to the other end of the capacitance C21. The source / drain of the transistor M14 and the source / drain of the transistor M13 are connected to the intermediate node of the capacitances C21 and C22. The timing chart of the control signal for controlling the pixel circuit 210 is the same as the timing chart shown in FIG. 3 or 4, and the operation of the transistor is also the same.

FIG. 7 shows different examples of pixel circuits and control signals. The difference from the pixel circuit 200 shown in FIG. 2 will be mainly described. The pixel circuit 220 shown in FIG. 7 includes transistors M22 and M24 in place of the transistors M12 and M14 of the pixel circuit 200 shown in FIG. The transistors M22 and M24 are a first threshold value compensating transistor and a second threshold value compensating transistor.

The transistors M22 and M24 are N-type transistors (the polarity of the transistor is N-type). For example, the P-type transistor is a low-temperature polysilicon TFT, and the N-type transistor is an oxide semiconductor TFT. The oxide semiconductor TFT has a smaller leakage current than the low temperature polysilicon TFT, and can more appropriately maintain the charge of the holding capacity.

A light emission control signal Em_N-1 is input to the gate of the transistor M22, and its ON / OFF is controlled. A light emission control signal Em_N-1 is input to the gate of the transistor M24, and its ON / OFF is controlled. The timing chart of the control signal that controls the pixel circuit 220 is the same as the timing chart shown in FIG. 3 or 4.

The operation of the pixel circuit 220 according to the example of the timing chart of FIG. 3 will be described. At time T1, the selection signal S_N + 1 is High and the transistor M17 is OFF. Further, the light emission control signal Em_N is Low, and the transistor M15 is ON.

At time T1, the selection signal S_N changes from High to Low, and the light emission control signal Em_N-1 changes from Low to High. The transistor M16 changes from OFF to ON in response to a change in the selection signal S_N. In response to the change in the light emission control signal Em_N-1, the transistors M22 and M24 change from OFF to ON, and the transistor M13 changes from ON to OFF.

The transistor M16 is changed to ON, and the supply of the reset potential Vrst to the anode of the OLED element E1 is started. The transistors M22, M15 and M16 are ON, and the supply of the reset potential Vrst to the gate of the drive transistor M11 is started. This state continues from time T1 to time T2.

At time T2, the selection signal S_N + 1 changes from High to Low. Further, at time T2, the light emission control signal Em_N changes from Low to High. In response to the change in the selection signal S_N + 1, the transistor M17 changes from OFF to ON. The transistor M15 changes from ON to OFF in response to a change in the light emission control signal Em_N. When the transistor M15 changes to OFF, the supply of the reset potential Vrst to the gate of the drive transistor M11 is stopped.

At time T2, the transistors M22, M24, M16, and M17 are ON. Transistors M13 and M15 are OFF. Since the transistors M13 and M15 are OFF and the transistors M22 and M24 are ON, the threshold compensation voltage is written in the holding capacity C10. At time T2, writing of the threshold compensation voltage to the holding capacity C10 starts.

At time T3, the selection signal S_N changes from Low to High. Further, the light emission control signal Em_N-1 changes from High to Low. The transistor M16 changes from ON to OFF in response to a change in the selection signal S_N. The transistors M22 and M24 change from ON to OFF in response to a change in the light emission control signal Em_N-1. Therefore, at time T3, the writing of the threshold compensation voltage to the holding capacity C10 is completed.

The transistor M13 changes from OFF to ON in response to a change in the light emission control signal Em_N-1 at time T3. The transistors M13 and M17 are ON, and the data signal Vdata is written to the holding capacitance C10 via the transistors M13 and M17. At time T3, writing of the data signal Vdata to the holding capacity C10 starts.

At time T4, the selection signal S_N + 1 changes from Low to High. As a result, the transistor M17 is turned from ON to OFF, and data writing to the Nth pixel circuit line is completed. At time T4, the light emission control signal Em_N changes from High to Low. As a result, the transistor M15 changes from OFF to ON. As a result, a drive current is applied to the OLED element E1, and the OLED element starts emitting light.

FIG. 8 shows different examples of pixel circuits and control signals. The difference from the pixel circuit 200 shown in FIG. 2 will be mainly described. The pixel circuit 230 shown in FIG. 8 includes transistors M22, M23, M24 and M27 in place of the transistors M12, M13, M14 and M17 of the pixel circuit 200 shown in FIG. The transistors M22, M23, M24 and M27 are N-type transistors.

If the leakage currents of the threshold compensation transistors M22 and M24 are large, the gate potential fluctuates during the data retention period, causing flicker. Further, if the leakage currents of the data writing transistors M23 and M27 are large, the data signal leaks to the potential of the holding capacitance, causing crosstalk. On the other hand, the drive transistor M11 is preferably a transistor having high mobility in order to realize high definition and high frequency drive.

Therefore, the drive transistor M11 is a P-type, and the threshold compensation transistors M22 and M24 and the data writing transistors M23 and M27 are N-type. A low-temperature polysilicon TFT with high write capability can be applied to the drive transistor, and an oxide semiconductor TFT with low leakage current can be applied to the threshold compensation transistor and the data write transistor. By combining transistors having different characteristics in this way, there is an effect that high-definition display and high-frequency drive and low-frequency drive that can realize low power consumption can be realized at the same time.

A light emission control signal Em_N-1 is input to the gate of the transistor M22, and its ON / OFF is controlled. A selection signal S_N is input to the gate of the transistor M23, and its ON / OFF is controlled. A light emission control signal Em_N-1 is input to the gate of the transistor M24, and its ON / OFF is controlled. A light emission control signal Em_N is input to the gate of the transistor M27, and its ON / OFF is controlled.

Compared with the control signal of the pixel circuit 200 of FIG. 2, the selection signal S_N + 1 is omitted. The timing chart of the control signal for controlling the pixel circuit 230 is the timing chart shown in FIG. 3 or 4 excluding the selection signal S_N + 1. The layout of the control signal line is the layout shown in FIG. 5 excluding the control signal line 231B.

The operation of the pixel circuit 230 according to the example of the timing chart of FIG. 3 will be described. At time T1, the light emission control signal Em_N is Low, the transistor M27 is OFF, and the transistor M15 is ON.

At time T1, the selection signal S_N changes from High to Low, and the light emission control signal Em_N-1 changes from Low to High. In response to the change in the selection signal S_N, the transistor M23 changes from ON to OFF, and the transistor M16 changes from OFF to ON. The transistors M22 and M24 change from OFF to ON in response to a change in the light emission control signal Em_N-1.

The transistor M16 is changed to ON, and the supply of the reset potential Vrst to the anode of the OLED element E1 is started. The transistors M22, M15 and M16 are ON, and the supply of the reset potential Vrst to the gate of the drive transistor M11 is started. This state continues from time T1 to time T2.

At time T2, the light emission control signal Em_N changes from Low to High. In response to a change in the light emission control signal Em_N, the transistor M27 (example of the first transistor) changes from OFF to ON, and the transistor M15 changes from ON to OFF. When the transistor M15 changes to OFF, the supply of the reset potential Vrst to the gate of the drive transistor M11 is stopped.

At time T2, the transistors M22, M24, M16, and M27 are ON. Transistors M23 and M15 are OFF. Since the transistors M23 and M15 are OFF and the transistors M22 and M24 are ON, the threshold compensation voltage is written in the holding capacity C10. At time T2, writing of the threshold compensation voltage to the holding capacity C10 starts.

At time T3, the selection signal S_N changes from Low to High. Further, the light emission control signal Em_N-1 changes from High to Low. The transistor M16 changes from ON to OFF in response to a change in the selection signal S_N. The transistors M22 and M24 change from ON to OFF in response to a change in the light emission control signal Em_N-1. Therefore, at time T3, the writing of the threshold compensation voltage to the holding capacity C10 is completed.

In response to the change in the selection signal S_N at time T3, the transistor M23 (example of the second transistor) changes from OFF to ON. The transistors M23 and 27 are ON, and the data signal Vdata is written to the holding capacitance C10 via the transistors M23 and 27. At time T3, writing of the data signal Vdata to the holding capacity C10 starts.

At time T4, the light emission control signal Em_N changes from High to Low. As a result, the transistor M27 is turned from ON to OFF, and data writing to the Nth pixel circuit line is completed. Further, the transistor M15 changes from OFF to ON. As a result, a drive current is applied to the OLED element E1, and the OLED element starts emitting light.

FIG. 9 shows different examples of pixel circuits and control signals. The difference from the pixel circuit 200 shown in FIG. 2 will be mainly described. The pixel circuit 240 shown in FIG. 9 includes transistors M22, M23, M24 and M27 in place of the transistors M12, M13, M14 and M17 of the pixel circuit 200 shown in FIG. The transistors M22, M23, M24 and M27 are N-type transistors.

Also in this example, by making the drive transistor M11 P-type and the threshold compensation transistors M22 and M24 and the data writing transistors M23 and M27 N-type, a low-temperature polycarbonate TFT having high write capability is applied to the drive transistor. Oxide semiconductor TFTs with low leakage current can be applied to threshold compensation transistors and data writing transistors. By combining transistors having different characteristics in this way, there is an effect that high-definition display and high-frequency drive and low-frequency drive that can realize low power consumption can be realized at the same time.

A light emission control signal Em_N-1 is input to the gate of the transistor M22, and its ON / OFF is controlled. A light emission control signal Em_N is input to the gate of the transistor M23, and its ON / OFF is controlled. A light emission control signal Em_N-1 is input to the gate of the transistor M24, and its ON / OFF is controlled. A light emission control signal Em_N + 2 is input to the gate of the transistor M27, and its ON / OFF is controlled.

FIG. 10 shows an example of a signal timing chart that controls the pixel circuit 240 shown in FIG. FIG. 10 shows the time change of the selection signal S_N, the light emission control signal Em_N-1, the light emission control signal Em_N, and the light emission control signal Em_N + 2 in one frame. FIG. 10 shows the change in signal potential level.

In the timing chart of FIG. 10, the 1H period is a period in which the data signal Vdata is written in the pixel circuit, and is a period in which the transistors M23 and M27 are ON. The threshold compensation period is 1H or more, and is 2H in the example of FIG.

At time T1, the light emission control signal Em_N + 2 is Low, and the transistor M27 is OFF. Further, the light emission control signal Em_N is Low, the transistor M15 is ON, and the transistor M23 is OFF.

At time T1, the selection signal S_N changes from High to Low, and the light emission control signal Em_N-1 changes from Low to High. The transistor M16 changes from OFF to ON in response to a change in the selection signal S_N. The transistors M22 and M24 change from OFF to ON in response to a change in the light emission control signal Em_N-1.

The transistor M16 is changed to ON, and the supply of the reset potential Vrst to the anode of the OLED element E1 is started. The transistors M22, M15 and M16 are ON, and the supply of the reset potential Vrst to the gate of the drive transistor M11 is started. This state continues from time T1 to time T2. Times T1 to T2 are reset periods of the anode potential of the OLED element E1 and the gate potential of the drive transistor M11. The period length from time T1 to time T2 is 1H.

At time T2, the light emission control signal Em_N changes from Low to High. In response to a change in the light emission control signal Em_N, the transistor M15 changes from ON to OFF, and the transistor M23 (example of the first transistor) changes from OFF to ON. When the transistor M15 changes to OFF, the supply of the reset potential Vrst to the gate of the drive transistor M11 is stopped.

At time T2, the transistors M22, M24, M16, and M23 are ON. Transistors M27 and M15 are OFF. Since the transistors M27 and M15 are OFF and the transistors M22 and M24 are ON, the threshold compensation voltage is written in the holding capacity C10. At time T2, writing of the threshold compensation voltage to the holding capacity C10 starts.

From time T2 to time T3, the potential levels of the signals S_N, Em_N-1, Em_N, Em_N + 2 are maintained. At time T3, the selection signal S_N changes from Low to High. Further, the light emission control signal Em_N-1 changes from High to Low. Further, the light emission control signal Em_N + 2 changes from Low to High.

The transistor M16 changes from ON to OFF in response to a change in the selection signal S_N. The transistors M22 and M24 change from ON to OFF in response to a change in the light emission control signal Em_N-1. Therefore, at time T3, the writing of the threshold compensation voltage to the holding capacity C10 is completed. The period from the time T2 to T3 is the writing period of the threshold compensation voltage to the holding capacity C10, and the length thereof is 2H in the example of FIG.

The transistor M27 (example of the second transistor) changes from OFF to ON in response to a change in the light emission control signal Em_N + 2 at time T3. The transistors M23 and 27 are ON, and the data signal Vdata is written to the holding capacitance C10 via the transistors M23 and 27. At time T3, writing of the data signal Vdata to the holding capacity C10 starts. From time T3 to time T4, the potential levels of the signals S_N, Em_N-1, Em_N, Em_N + 2 are maintained.

At time T4, the light emission control signal Em_N changes from High to Low. As a result, the transistor M23 is turned from ON to OFF, and data writing to the Nth pixel circuit line is completed. Times T3 to T4 are data writing periods in the Nth pixel circuit line, and the length thereof is 1H. After the time T4, the light emission control signal Em_N is maintained at Low.

At time T4, the light emission control signal Em_N changes from High to Low. As a result, the transistor M15 changes from OFF to ON. As a result, a drive current is applied to the OLED element E1, and the OLED element starts emitting light. Then, 2H after the time T4, the light emission control signal Em_N + 2 changes from High to Low.

As a result, the transistor M27 changes from ON to OFF. The light emission of the OLED element E1 is maintained regardless of the state change of the transistor M27. Since both the two transistors M23 and 27 are turned off as compared with the configuration of FIG. 8, it is possible to more effectively reduce the leakage from the holding capacitance to the data line during the light emission period.

FIG. 11 schematically shows the layout of the control signal line for transmitting the control signal to the pixel circuit 240. Differences from the configuration example shown in FIG. 5 will be mainly described. The control signal line 231B is omitted and the control signal line 232C is added to the configuration example shown in FIG. The control signal line 232C transmits the light emission control signal Em_K output by the shift register unit 322 in the Kth stage to the pixel circuit line in the (K-2) stage.

FIG. 12 shows another configuration example of the pixel circuit and the control signal. The element configuration of the pixel circuit 250 shown in FIG. 12 is the same as that of the pixel circuit 200 shown in FIG. The control signal of some transistors of the pixel circuit 250 is different from the control signal of the same transistor of the pixel circuit 200. Specifically, the selection signal S_N + 1 is input to the gate of the transistor M13. Further, the selection signal S_N + 3 is input to the gate of the transistor M17. Other points of the pixel circuit 250 are the same as those of the pixel circuit 200.

FIG. 13 shows an example of a signal timing chart that controls the pixel circuit 250 shown in FIG. FIG. 13 shows the time change of the selection signal S_N, the selection signal S_N + 1, the selection signal S_N + 3, and the light emission control signal Em_N in one frame. FIG. 13 shows the change in signal potential level.

In the timing chart of FIG. 13, the 1H period is a period in which the data signal Vdata is written in the pixel circuit, and is a period in which the transistors M13 and M17 are ON. The threshold compensation period is 1H or more, which is 2H in the example of FIG.

At time T1, the selection signal S_N + 1 is High and the transistor M13 is OFF. The selection signal S_N + 3 is High, and the transistor M17 is OFF. The light emission control signal Em_N is Low, and the transistor M15 is ON.

At time T1, the selection signal S_N changes from High to Low. Transistors M12, M14 and M16 change from OFF to ON in response to changes in the selection signal S_N.

The transistor M16 is changed to ON, and the supply of the reset potential Vrst to the anode of the OLED element E1 is started. The transistors M12, M15 and M16 are ON, and the supply of the reset potential Vrst to the gate of the drive transistor M11 is started. This state continues from time T1 to time T2. Times T1 to T2 are reset periods of the anode potential of the OLED element E1 and the gate potential of the drive transistor M11. The period length from time T1 to time T2 is 1H.

At time T2, the selection signal S_N + 1 changes from High to Low. Further, at time T2, the light emission control signal Em_N changes from Low to High. In response to a change in the selection signal S_N + 1, the transistor M13 (example of the first transistor) changes from OFF to ON. The transistor M15 changes from ON to OFF in response to a change in the light emission control signal Em_N. When the transistor M15 changes to OFF, the supply of the reset potential Vrst to the gate of the drive transistor M11 is stopped.

At time T2, the transistors M12, M13, M14, and M16 are ON. Transistors M15 and M17 are OFF. Since the transistors M15 and M17 are OFF and the transistors M12 and M14 are ON, the threshold compensation voltage is written in the holding capacity C10. At time T2, writing of the threshold compensation voltage to the holding capacity C10 starts.

From time T2 to time T3, the potential levels of the signals S_N, S_N + 1, S_N + 3, and Em_N are maintained. At time T3, the selection signal S_N changes from Low to High. Further, the selection signal S_N + 3 changes from High to Low.

In response to the change in the selection signal S_N, the transistors M12, M14, and M16 change from ON to OFF. Therefore, at time T3, the writing of the threshold compensation voltage to the holding capacity C10 is completed. The period from the time T2 to T3 is the writing period of the threshold compensation voltage to the holding capacity C10, and the length thereof is 2H in the example of FIG.

In response to the change in the selection signal S_N + 3 at time T3, the transistor M17 (example of the second transistor) changes from OFF to ON. The transistors M13 and M17 are ON, and the data signal Vdata is written to the holding capacitance C10 via the transistors M13 and M17. At time T3, writing of the data signal Vdata to the holding capacity C10 starts. From time T3 to time T4, the potential levels of the signals S_N, S_N + 1, S_N + 3, and Em_N are maintained.

At time T4, the selection signal S_N + 1 changes from Low to High. As a result, the transistor M13 is turned from ON to OFF, and data writing to the Nth pixel circuit line is completed. Times T3 to T4 are data writing periods in the Nth pixel circuit line, and the length thereof is 1H. After the time T4, the selection signal S_N + 1 is maintained at High.

At time T4, the light emission control signal Em_N changes from High to Low. As a result, the transistor M15 changes from OFF to ON. As a result, a drive current is applied to the OLED element E1, and the OLED element starts emitting light. After 2H from the time T4, the selection signal S_N + 3 changes from Low to High. The transistor M17 changes from ON to OFF depending on the end edge of the selection signal S_N + 3. The two transistors M13 and M17 are OFF, and the leakage from the holding capacitance to the data line can be reduced more effectively during the light emission period.

FIG. 14 schematically shows the layout of the control signal line for transmitting the control signal to the pixel circuit 250. Differences from the configuration example shown in FIG. 5 will be mainly described. The control signal line 232B is omitted and the control signal line 231C is added to the configuration example shown in FIG. The control signal line 231C transmits the selection signal S_K output by the shift register unit 312 in the Kth stage to the pixel circuit line in the (K-3) stage.

FIG. 15 shows another configuration example of the pixel circuit and the control signal. The element configuration of the pixel circuit 260 shown in FIG. 15 is the same as that of the pixel circuit 200 shown in FIG. The control signal of some transistors of the pixel circuit 260 is different from the control signal of the same transistor of the pixel circuit 200. Specifically, the selection signal S_N + 1 is input to the gate of the transistor M13 (example of the first transistor). Further, the selection signal S_N + 2 is input to the gate of the transistor M17. Other points of the pixel circuit 260 are the same as those of the pixel circuit 200.

FIG. 16 shows an example of a signal timing chart that controls the pixel circuit 260 shown in FIG. FIG. 16 shows the time change of the selection signal S_N, the selection signal S_N + 1, the selection signal S_N + 2, and the light emission control signal Em_N in one frame. FIG. 16 shows the change in signal potential level.

In the timing chart of FIG. 16, the 1H period is a period in which the data signal Vdata is written in the pixel circuit, and is a period in which the transistors M13 and M17 are ON. The threshold compensation period is 1H or more, which is 1H in the example of FIG.

At time T11, the selection signal S_N + 1 is High and the transistor M13 is OFF. The selection signal S_N + 2 is High, and the transistor M17 is OFF. The light emission control signal Em_N is Low, and the transistor M15 is ON.

At time T11, the selection signal S_N changes from High to Low. Transistors M12, M14 and M16 change from OFF to ON in response to changes in the selection signal S_N.

The transistor M16 is changed to ON, and the supply of the reset potential Vrst to the anode of the OLED element E1 is started. The transistors M12, M15 and M16 are ON, and the supply of the reset potential Vrst to the gate of the drive transistor M11 is started. This state continues from time T11 to time T12. Times T11 to T12 are reset periods of the anode potential of the OLED element E1 and the gate potential of the drive transistor M11. The period length from time T11 to time T12 is 1H.

At time T12, the selection signal S_N + 1 changes from High to Low. Further, at time T12, the light emission control signal Em_N changes from Low to High. In response to the change in the selection signal S_N + 1, the transistor M13 changes from OFF to ON. The transistor M15 changes from ON to OFF in response to a change in the light emission control signal Em_N. When the transistor M15 changes to OFF, the supply of the reset potential Vrst to the gate of the drive transistor M11 is stopped.

At time T12, the transistors M12, M13, M14, and M16 are ON. Transistors M15 and M17 are OFF. Since the transistors M15 and M17 are OFF and the transistors M12 and M14 are ON, the threshold compensation voltage is written in the holding capacity C10. At time T12, writing of the threshold compensation voltage to the holding capacity C10 starts.

From time T12 to time T13, the potential levels of the signals S_N, S_N + 1, S_N + 2, and Em_N are maintained. At time T13, the selection signal S_N changes from Low to High. Further, the selection signal S_N + 2 changes from High to Low.

In response to the change in the selection signal S_N, the transistors M12, M14, and M16 change from ON to OFF. Therefore, at time T13, the writing of the threshold compensation voltage to the holding capacity C10 is completed. The period from the time T12 to T13 is the writing period of the threshold compensation voltage to the holding capacity C10, and the length thereof is 1H in the example of FIG.

The transistor M17 changes from OFF to ON in response to a change in the selection signal S_N + 2 at time T13. The transistors M13 and M17 are ON, and the data signal Vdata is written to the holding capacitance C10 via the transistors M13 and M17. At time T13, writing of the data signal Vdata to the holding capacity C10 starts. From time T13 to time T14, the potential levels of the signals S_N, S_N + 1, S_N + 2, and Em_N are maintained.

At time T14, the selection signal S_N + 1 changes from Low to High. As a result, the transistor M13 is turned from ON to OFF, and data writing to the Nth pixel circuit line is completed. Times T13 to T14 are data writing periods in the Nth pixel circuit line, and the length thereof is 1H. After the time T14, the selection signal S_N + 1 is maintained at High.

At time T14, the light emission control signal Em_N changes from High to Low. As a result, the transistor M15 changes from OFF to ON. As a result, a drive current is applied to the OLED element E1, and the OLED element starts emitting light. After 1H from the time T14, the selection signal S_N + 2 changes from Low to High, and the transistor M17 changes from ON to OFF. The two transistors M13 and M17 are OFF, and the leakage from the holding capacitance to the data line can be reduced more effectively during the light emission period.

FIG. 17 shows another configuration example of the pixel circuit and the control signal. The main block 275_N-1 is the main block of the pixel circuit included in the pixel circuit row of the (N-1) th row. The pixel circuit 270_N is a pixel circuit included in the pixel circuit row of the Nth row, and the main block 275_N is a main block of the pixel circuit 270_N.

For the sake of explanation, the OLED element controlled by the pixel circuit including the main block 275_N-1 is designated by the reference numeral E1_N-1, and the OLED element controlled by the pixel circuit 270_N is designated by the reference numeral E1_N. The OLED element E1_N-1 is included in the pixel row of the (N-1) th row, and the OLED element E1_N is included in the pixel row of the Nth row. The main block 275_N-1 and the transistor M13 (not shown in FIG. 17) form a pixel circuit on the (N-1) th row. The positional relationship between the main block 275_N-1 and the corresponding transistor M13 and the circuit relationship are the same as the relationship between the main block 275_N and the transistor M13_N.

Hereinafter, the pixel circuit 270_N will be described. Compared with the pixel circuit 200 shown in FIG. 2, the connection positions of the transistor M17 (example of the first transistor) and the transistor M13 (example of the second transistor) are different. In the configuration example of FIG. 2, the transistor M17 is connected between the data line and the transistor M13. In the configuration example of FIG. 17, the transistor M13 is connected between the data line and the transistor M17. Similar operation is possible even if the transistors M17 and M13 are exchanged in this way.

In the pixel circuit 270_N that controls the light emission of the light emitting element E1_N, the transistor M17 is controlled by the selection signal S_N + 1. The transistor M13_N of the pixel circuit 270_N is arranged at a position away from other components of the pixel circuit 270_N. The pixel circuit 270_N is composed of a main block 275_N composed of a transistor M13_N and other transistors and capacitive elements.

The main blocks of the pixel circuit rows controlled by the same control line are arranged linearly along the X-axis, for example, as shown in FIG. 5 or 14. A region including the main block of the pixel circuit row and not including the components of the main block of the other pixel circuit row is referred to as a pixel circuit row region (pixel circuit row region). There is a boundary that separates adjacent pixel circuit row areas.

FIG. 18 schematically shows a plurality of continuous pixel circuit row regions. In FIG. 18, the broken line rectangle indicates a region including the main block of the pixel circuit, and as an example, the region including one main block is indicated by reference numeral 401. The region 401 may include components of a pixel circuit different from the main block, but does not include components of other main blocks. In FIG. 18, as an example, the pixel circuit row area of the (N-1) th row is designated by the reference numeral 411_N-1, and the pixel circuit row region of the Nth row is designated by the reference numeral 411_N. The boundary 412 between the pixel circuit line area 411_N-1 and the pixel circuit line area 411_N separates the two areas. In the example shown in FIG. 18, the size (width) of each pixel circuit row region along the Y axis is common.

Returning to FIG. 17, the transistor M13_N is arranged in the pixel circuit row region 411_N-1 in the (N-1) th row. The other transistors M11 to M16 for controlling the light emission of the light emitting element E1_N are arranged in the pixel circuit line region 411_N of the Nth line. The transistor M13_N is controlled by the light emission control signal Em_N-1. The block region 401 of the pixel circuit row region 411_N-1 in the (N-1) th row includes, for example, the transistor M13_N in addition to the main block 275_N-1. Further, the block region 401 of the pixel circuit row region 411_N on the Nth row includes, for example, the transistor M13_N + 1 in addition to the main block 275_N.

The transistor M13_N and the transistor M17 are connected in series between the data line 237 and the holding capacitance including the capacitances C11 and C12. The transistor M13_N and the transistor M17 are switch transistors for selecting a pixel circuit for supplying a data signal and writing the data signal Vdata to the holding capacitance. The changes in the selection signal and the light emission control signal are the same as in the example described with reference to FIG.

As described above, the transistor M13_N is arranged in the pixel circuit row region 411_N-1 on the (N-1) th row. Further, the transistor M13_N is controlled by a light emission control signal Em_N-1 in a row different from the N row, in the pixel circuit row in the (N-1) th row in the example of FIG. Therefore, the number of control lines for controlling the pixel circuit 270_N is reduced, and an efficient element layout is possible.

FIG. 19 shows another configuration example of the pixel circuit and the control signal. Differences from the configuration example shown in FIG. 17 will be mainly described. The transistor M13_N-1 is a transistor for controlling light emission of the OLED element E1_N-1.

The transistor M13_N (example of the second transistor) is arranged in the pixel circuit row region 411_N of the Nth row. In the configuration example of FIG. 19, the main block can be considered to include all the components of the pixel circuit. A transmission line (control signal line) 238 branched from the control signal line 232B for transmitting the light emission control signal Em_N-1 on the (N-1) line is connected to the gate of the transistor M13_N. The control signal line 232B passes through the pixel circuit line region 411_N-1 on the (N-1) th row.

The light emission control signal Em_N-1 is given to the gate of the transistor M13_N via the transmission line 238. As described above, the signal for controlling the transistor M13_N of the pixel circuit of the Nth row is given by the transmission line branched from the control signal line at a position different from the pixel circuit row area 411_N of the Nth row. Therefore, the number of control lines for controlling the pixel circuit 270_N is reduced, and an efficient element layout is possible.

In the examples of FIGS. 17 and 18, the transistor M13_N is arranged in the region 411_N-1 of the pixel circuit line in the (N-1) line, but as a different example, the transistor M17_N in the pixel circuit 270_N is placed in the (N + 1) line. It is also conceivable to place it in the area of the pixel circuit line of. In that configuration, the transistor M17 may be connected between the transistor M13 and the data line, and the transistor M13_N may be arranged in the pixel circuit row region 411_N on the Nth row.

FIG. 20 shows an example of a pixel circuit and a control signal having this configuration. Differences from the configuration example shown in FIG. 17 will be mainly described. FIG. 20 shows the pixel circuit 270_N in the pixel circuit row of the Nth row and the main block 275_N + 1 of the pixel circuit in the pixel circuit row of the (N + 1) row. The transistor M17_N-1 is a transistor included in the pixel circuit line in the (N-1) th row.

The Nth pixel circuit line is controlled by the control signals S_N, Em_N-1, Em_N, and S_N + 1. The pixel circuit line in the (N + 1) th stage is controlled by the control signals S_N + 1, Em_N, Em_N + 1, and the control signal S_N + 2 (not shown in FIG. 20).

In the pixel circuit 270_N, the connection positions of the transistor M13_N (example of the second transistor) and the transistor M17_N (example of the first transistor) are interchanged from the example of FIG. The transistor M17_N of the pixel circuit 270_N is arranged at a position away from other components of the pixel circuit 270_N.

The main block 275_N + 1 is composed of transistors M11 to M16 and capacitances C11 and 12, and the transistor M17 (not shown in FIG. 20) is excluded. That is, the main block of the pixel circuit 270_N is composed of components excluding the transistor M17_N from the pixel circuit 270_N.

FIG. 21 schematically shows a plurality of continuous pixel circuit row regions. Differences from FIG. 18 will be described. In the configuration example of FIG. 21, the control line from the shift register unit 312 of the Nth stage and the control line from the shift register unit 322 of the (N-1) th stage and the Nth stage in the area 411_N of the pixel circuit line. It is passing.

The transistor M17_N is arranged in the pixel circuit row region 411_N + 1 in the (N + 1) th row. The other transistors M11 to M16 of the pixel circuit 270_N are arranged in the pixel circuit row region 411_N of the Nth row. The block region 401 of the pixel circuit row region 411_N + 1 in the (N + 1) th row includes, for example, the transistor M17_N in addition to the main block 275_N + 1. Further, the block region 401 of the pixel circuit row region 411_N on the Nth row includes, for example, the transistor M17_N-1 in addition to the main block of the pixel circuit 270_N.

FIG. 22 shows a configuration example in which the control signal line of the transistor M17 is routed from the region of the adjacent pixel circuit line with respect to the configuration example shown in FIG. Differences from the configuration example of FIG. 20 will be mainly described. The transistor M17_N is arranged in the pixel circuit row region 411_N on the Nth row. In the configuration example of FIG. 22, the main block can be considered to include all the components of the pixel circuit. A transmission line (control signal line) 239 branched from the control signal line 231A that transmits the selection signal S_N + 1 on the (N + 1) th line is connected to the gate of the transistor 17_N. The control signal line 231A passes through the pixel circuit row region 411_N + 1 in the (N + 1) th row.

The selection signal S_N + 1 is given to the gate of the transistor 17_N via the transmission line 239. As described above, the signal for controlling the transistor M17_N of the pixel circuit of the Nth row is given by the transmission line branched from the control signal line at a position different from the pixel circuit row region 411_N of the Nth row. Therefore, the number of control lines for controlling the pixel circuit 270_N is reduced, and an efficient element layout is possible.

Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments. A person skilled in the art can easily change, add, or convert each element of the above embodiment within the scope of the present disclosure. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

1 OLED display device 10 TFT board 25 Display area 31 Scan driver 32 Emission driver 231A-231A, 232A-232C Control signal line 200, 210, 220, 230, 240, 250, 260 pixel circuit 310, 320 Shift register 312, 322 shift Register unit C10, C20 Holding capacity E1 OLED element M11-M17, M22-M24, M27 Transistor

Claims (13)

It ’s a display device,
A display area containing a multi-pixel circuit line and
Including the drive circuit,
Each of the multipixel circuit rows comprises a multipixel circuit.
Each of the multi-pixel circuits
A drive transistor that controls the amount of current to the light emitting element,
The holding capacity that holds the control voltage of the drive transistor,
The first transistor and the second transistor connected in series, which transmit a data signal to the holding capacitance,
A threshold compensation transistor for writing the threshold compensation voltage of the drive transistor to the holding capacitance,
Including
The drive circuit shifts the control signal pulse from the front stage to the rear stage in the multi-pixel circuit line at regular intervals.
The pulse width of the control signal pulse is more than twice the fixed period.
The drive circuit
During the threshold compensation period, the threshold compensation transistor is kept ON, the threshold compensation voltage is written to the holding capacitance, and the threshold compensation voltage is written.
In the data writing period after the threshold compensation period, the threshold compensation transistor is turned off, the first transistor and the second transistor are kept ON, and the data signal is written to the holding capacitance.
The pulse width of the control signal pulse is at least twice the data writing period, and is more than twice.
The drive circuit
The first transistor is controlled by the first control signal pulse, and the first transistor is controlled by the first control signal pulse.
The second transistor is controlled by a second control signal pulse different from the first control signal pulse.
The first transistor is turned on by the start edge of the first control signal pulse before the start of the data write period.
After the end of the threshold compensation period, the first transistor is kept ON and the second transistor is turned ON by the start edge of the second control signal pulse to start the data writing period.
The first transistor is turned off by the end edge of the first control signal pulse to end the data writing period.
Display device. The display device according to claim 1.
The pulse width of the control signal pulse is three times or more the data writing period.
The threshold compensation period is at least twice the data writing period.
Display device. The display device according to claim 1.
Further including a light emission control switch transistor for turning on / off the supply of the drive current from the drive transistor to the light emitting element.
The drive circuit keeps the light emission control switch transistor OFF during the threshold compensation period and the data writing period.
After the end of the data writing period, the light emission control switch transistor is turned on.
Display device. The display device according to claim 1.
The drive circuit
In the reset period before the threshold compensation period, a reset potential is supplied to the gate of the drive transistor to supply the reset potential.
Keeping the first transistor and the second transistor OFF during the reset period.
Display device. The display device according to claim 4.
The drive circuit turns on the first transistor by the start edge of the first control signal pulse at the start of the threshold compensation period.
Display device. The display device according to claim 1.
The drive circuit includes a first driver and a second driver.
The first driver shifts the control signal pulse of the first polarity from the front stage to the rear stage in the plurality of pixel circuit lines at regular intervals.
The second driver shifts the control signal pulse of the opposite polarity of the first polarity from the front stage to the rear stage in the plurality of pixel circuit lines at regular intervals.
The control signal pulse from the first driver and the control signal pulse from the second driver are synchronized.
Display device. The display device according to claim 6.
The drive circuit controls each pixel circuit of the plurality of pixel circuits by two control signal pulses from the first driver and two control signal pulses from the second driver.
Display device. The display device according to claim 1.
The drive circuit turns off the second transistor by the end edge of the second control signal pulse while the light emitting element is emitting light.
Display device. The display device according to claim 1.
The first transistor, the second transistor, and the threshold compensation transistor are N-type thin film transistors.
The drive transistor is a P-type thin film transistor.
Display device. The display device according to claim 9.
The threshold value compensating transistor is a first threshold value compensating transistor.
The display device is an N-type thin film transistor and further includes a second threshold value compensating transistor controlled by the same control signal as the first threshold value compensating transistor.
While the first threshold value compensating transistor is ON, the drive transistor is connected to a diode.
The second threshold compensation transistor gives a reference potential to the holding capacitance while it is ON.
Display device. The display device according to claim 1.
The first transistor or the second transistor of the pixel circuit of the pixel circuit row of the Nth row is arranged in a pixel circuit row region different from the pixel circuit row region of the Nth row.
Display device. The display device according to claim 1.
The first control signal pulse or the second control signal pulse that controls the pixel circuit row of the Nth row is the first control signal pulse obtained by a transmission line branched from a control signal line located at a position different from the pixel circuit row region of the Nth row. Controlling the transistor or the second transistor,
Display device. The display device according to claim 12, wherein the transmission line is branched from a control signal line passing through a pixel circuit line area adjacent to the pixel circuit line area of the Nth line.
Display device.

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