JP2022103663A - Image processing equipment, image processing methods and programs for image processing equipment - Google Patents

Abstract

Kind Code: A1 A plurality of seed values can be generated in a short time based on one seed value so that pseudorandom number sequences for image processing of a plurality of blocks obtained by dividing an image do not collide. do. Kind Code: A1 An image processing apparatus includes seed value generation means for generating a plurality of seed values for a plurality of blocks into which an image is divided based on one seed value, and a plurality of seed values for the plurality of blocks. A pseudorandom number generating means 102 for generating a pseudorandom number sequence for each of the plurality of blocks based on the seed value of the plurality of blocks, and a plurality of pseudorandom number sequences obtained by dividing the image using the pseudorandom number sequence for each of the plurality of blocks. and image processing means 101 for performing image processing on each block, wherein the seed value generation means skips a predetermined number of pseudorandom number sequences generated by the pseudorandom number generation means based on the one seed value. A plurality of pseudo-random numbers are generated as the plurality of seed values. [Selection drawing] Fig. 1

Description

The present invention relates to an image processing apparatus, an image processing method and a program of the image processing apparatus.

Random numbers may be required when performing image processing on a computer or logic circuit. Random numbers are roughly divided into two types, true random numbers generated by observing physical phenomena and pseudo-random numbers that output values that appear to be random using a predetermined algorithm.

Pseudo-random numbers are not true random numbers, but because the algorithm is fixed, it is easier to check the quality of random numbers than true random numbers. For example, the quality of random numbers can be confirmed by a statistical random number test method, for example, SP800-22 of NIST. Therefore, if it can be confirmed that the quality matches the application, it can be said that there is no problem even if a pseudo-random number is used instead of a true random number.

Pseudo-random numbers also have the advantage of being reproducible. Reproducibility is the property that the same pseudo-random number sequence can be generated again. Therefore, when the same random number sequence is used multiple times, it is necessary to save all the random number sequences in the case of true random numbers, whereas in the case of pseudo-random numbers, it is only necessary to regenerate them.

There are roughly two types of pseudo-random numbers, pseudo-random numbers that can be used for encryption and other general pseudo-random numbers. Pseudo-random numbers that can be used for cryptography have high random number quality, but usually slower random number generation. Since image processing does not require very high quality random numbers, pseudo-random numbers for cryptographic purposes are not usually used in image processing, and general and simple pseudo-random numbers are used in image processing.

One of the simple pseudo-random number algorithms is the linear feedback shift register. The linear feedback shift register does not have the quality that can be used for encryption as it is, but it can be used alone if it uses general random numbers such as image processing. Another example of a pseudo-random number algorithm is Xorshift (see, for example, Non-Patent Document 1).

In Patent Document 1, for example, in order to enlarge an image, pixels are added to the input image, and the added points are separated by using pseudo-random numbers, so that the change points of the image pattern due to the addition of pixels are conspicuous. It describes how to avoid it.

Patent Document 2 describes a method of avoiding generation of the same random number in a plurality of pseudo-random number generation circuits by setting different seed values (initial values) in a plurality of pseudo-random number generation circuits. ..

In Patent Document 3, the same initial value is set in a plurality of pseudo-random number generation circuits, but a method of generating different pseudo-random numbers by changing the position for extracting the pseudo-random numbers from the pseudo-random number sequences in each pseudo-random number generation circuit is used. Have been described.

Patent Document 4 and Patent Document 5 describe a method of calculating the value of the shift register when the phase of the linear feedback shift register is arbitrarily advanced.

Japanese Patent No. 6066955 Japanese Unexamined Patent Publication No. 5-206793 Japanese Unexamined Patent Publication No. 2009-151429 Japanese Patent Application Laid-Open No. 2003-345246 Japanese Unexamined Patent Publication No. 11-4144

Marsaglia, "Xorshift RNGs" (2003)

However, in the method of Patent Document 3, when the image is divided into a plurality of blocks and a pseudo-random number is generated for each block, it is necessary to generate a large number of pseudo-random numbers in the pseudo-random number sequence. Further, although Patent Document 4 and Patent Document 5 describe how to advance the phase, a circuit configuration necessary for image processing in which an image is divided into a plurality of blocks, for example, how to hold a plurality of seed values and how to generate a seed value. The timing of is not disclosed.

An object of the present invention is to generate a plurality of seed values in a short time based on one seed value so that pseudo-random numbers for image processing of a plurality of blocks obtained by dividing an image do not collide with each other. To be able to do it.

The image processing apparatus of the present invention has a seed value generation means for generating a plurality of seed values for a plurality of blocks obtained by dividing an image based on one seed value, and a plurality of seeds for the plurality of blocks. A plurality of blocks obtained by dividing the image by using a pseudo-random number generation means for generating a pseudo-random number sequence for each of the plurality of blocks based on the value and a pseudo-random number sequence for each of the plurality of blocks are used. The seed value generation means has an image processing means for image processing, and the seed value generation means skips a predetermined number of pseudo-random numbers in the pseudo-random number sequence generated based on the one seed value. Is generated as the plurality of seed values.

According to the present invention, it is possible to generate a plurality of seed values in a short time based on one seed value so that pseudo-random numbers for image processing of a plurality of blocks obtained by dividing an image do not collide with each other. can.

It is a figure which shows the configuration example of an image processing apparatus. It is a figure which shows the structural example of the pseudo-random number generation part. It is a figure which shows the transition of the value of a shift register. It is a figure which shows the processing content of the seed value generation part. It is a figure for demonstrating the processing content of the pseudo-random number string skip part. It is a figure which shows the configuration example of the pseudo-random number sequence skip part. It is a figure which shows the structural example of the pseudo-random number generation part. It is a figure for demonstrating the processing content of the pseudo-random number string skip part. It is a flowchart which shows the pseudo-random number generation method of Xorshift. It is a figure which shows the structural example of the pseudo-random number generation part. It is a figure which shows the structural example of a linear feedback shift register. It is a figure which shows the example which divides an input image into a plurality of blocks. It is a figure which shows the insertion position of a pixel. It is a figure which shows the insertion position of a pixel.

FIG. 11 is a circuit diagram showing a configuration example of a linear feedback shift register that generates a pseudo-random number. In the shift register 1101, each register holds 1 bit and can hold 5 bits in total, and when 1 bit is input from the left, the holding bit is shifted by one. The exclusive OR operation unit 1102 inputs some bits of the shift register 1101 and outputs one bit of the result of the exclusive OR of the input bits. Each time the shift register 1101 shifts once, one bit of pseudo-random number is output.

The period of the pseudo-random number generated by the linear feedback shift register is configured to be maximum. The period of the pseudo-random number depends on the number of bits that can be held by the shift register 1101 and the bits that are input to the exclusive-OR arithmetic unit 1102. Assuming that the number of bits of the shift register 1101 is N, the number of bit states that can be represented by the shift register 1101 is 2 ^N. However, when all the bits of the shift register 1101 are 0, the bits of the shift register 1101 are always 0. Therefore, excluding that one pattern, the number of bit states that the shift register 1101 can represent is 2 ^N −. It becomes one. Therefore, 2 ^N -1 is the maximum period of the pseudo-random number. The input to the exclusive OR arithmetic unit 1102 is configured so that the period of the bit state represented by the shift register 1101 is 2 ^N -1. As a result, the period of the pseudo-random number also becomes 2 ^N -1.

Pseudo-random numbers can be used for image processing. Pseudo-random numbers can be used in image processing in order to make moire and changes in image patterns that occur due to enlargement / reduction processing and halftone processing performed on image data less noticeable. For example, pixels are added to the input image in order to enlarge the image. Normally, when a pixel is added, the image pattern changes at the position where the pixel is added. Therefore, if the addition point of the pixel is fixed uniformly, the change point of the image pattern that occurs at the position where the pixel is added becomes conspicuous in one place. Therefore, by using pseudo-random numbers to separate the additional points, it is possible to make the change points of the image pattern due to the addition of pixels inconspicuous.

FIG. 12 is a diagram showing an example of dividing an input image into a plurality of blocks. By performing image processing for each block, it is possible to process a plurality of blocks in parallel and change the enlargement ratio for each block. However, in order to perform image processing for each block, it is necessary to generate a pseudo-random number for each block.

FIG. 13 is a diagram showing an example of a pixel insertion position when the same pseudo-random number is used for each block of FIG. 12 and a pixel is inserted. If the same seed value (initial value) is used for each block and the same pseudo-random number sequence is generated for each block, pixels will be inserted at the same position in all blocks. Since the pixels are inserted at the same position in all the blocks, the image pattern may change periodically and be recognized as a pattern.

Therefore, it is better that the pseudo-random number strings used for each block are separate. By setting different seed values (initial values) in a plurality of pseudo-random number generation circuits, it is possible to avoid generating the same random number in a plurality of pseudo-random number generation circuits. However, even if a different seed value is set for each block, since the period of the pseudo-random number sequence is finite, there is a possibility that the pseudo-random number sequences of a plurality of blocks partially collide.

FIG. 14 is a diagram showing an example of a pixel insertion position when pseudo-random numbers of a plurality of blocks partially collide. Since the pseudo-random numbers of a plurality of blocks partially collide, the insertion positions of the pixels of the plurality of blocks partially overlap. Therefore, the same pattern has occurred at the overlapping points of the plurality of blocks. As a result, the image pattern may change periodically and be recognized as a pattern.

In order to reliably avoid partial collision of the pseudo-random number sequence as described above, for example, the same initial value is set in a plurality of pseudo-random number generation circuits, but the position where the pseudo-random number is taken out from the pseudo-random number sequence is set for each pseudo-random number. By changing it with the generation circuit, it is possible to avoid collision of pseudo-random numbers.

However, when the number of blocks is large, there is a problem that the amount of calculation required for generating pseudo-random numbers increases. For example, when there are 1000 blocks, it is necessary to generate 1000 pseudo-random numbers in the pseudo-random number sequence in order to extract one pseudo-random number from the pseudo-random number sequence. In image processing, pseudo-random numbers may be required for each pixel, so it is necessary to generate pseudo-random numbers with a small amount of calculation while preventing collisions of pseudo-random numbers between blocks.

As another collision avoidance method, it is conceivable to hold a plurality of non-collision seed values in advance and generate a pseudo-random number sequence using the seed values held before the start of image processing. However, if seed values that do not collide are generated in advance and all are held externally, the number of circuits for holding seed values externally will increase, and the seed values held externally will be used in the image processing circuit. It takes time to write. For example, if there are 1000 seeds, 1000 external holding circuits are required, and if it takes 100 cycles to write the seed values to the image processing circuit, all the seed values are written. It takes 100,000 cycles.

In order to solve the above problem, there is no need to set seed values for each of a plurality of blocks from the outside, and an embodiment capable of generating pseudo-random numbers during image processing of each block in a short time is provided. This will be described below.

(First Embodiment)
FIG. 1 is a diagram showing a configuration example of the image processing apparatus 100 according to the first embodiment. The image processing device 100 includes an image processing circuit 101, a pseudo-random number generation unit 102, a plurality of seed value holding units 103, a seed value setting unit 104, a seed value generation unit 105, and a pseudo-random number sequence skip unit 106. Have. Hereinafter, the image processing method of the image processing apparatus 100 will be described.

The image processing circuit 101 performs image processing that requires pseudo-random numbers, such as image enlargement / reduction processing. The image processing circuit 101 inputs an input image, divides the input image into a plurality of blocks, performs image processing on each block, and outputs an output image.

The pseudo-random number generator 102 has a linear feedback shift register and generates a pseudo-random number sequence. Each of the plurality of seed value holding units 103 holds the seed values of the pseudo-random number sequence required for image processing of the plurality of blocks of the input image. For example, when the image processing circuit 101 divides a maximum of 1024 blocks, the seed value holding unit 103 is composed of 1024 blocks.

The seed value setting unit 104 sets a seed value in any one of the plurality of seed value holding units 103. This seed value is a seed value required for one block out of a plurality of blocks. When the seed value generation unit 105 confirms that the seed value setting unit 104 has written the seed value to any one of the plurality of seed value holding units 103, the seed value generation unit 105 is required for other blocks based on the seed value. Seed value is generated and written to another seed value holding unit 103. The pseudo-random number sequence skip unit 106 is used by the seed value generation unit 105 to generate a seed value.

FIG. 2 is a diagram showing a configuration example of the pseudo-random number generation unit 102 of FIG. The pseudo-random number generator 102 is composed of, for example, a Fibonacci linear feedback shift register. The pseudo-random number generator 102 has a shift register 201 and an exclusive OR arithmetic unit 202.

The shift register 201 is composed of 31-bit registers, and when one bit is input from the left, the bits of all the registers are shifted to the right by one bit, and the one bit overflowing from the rightmost is output as a pseudo random number. The exclusive logical sum calculator 202 inputs the output bits of the shift register 201 and the bits of some of the 31-bit registers of the shift register 201. Then, the exclusive OR arithmetic unit 202 outputs one bit to the register of the first stage of the shift register 201 as a result of the exclusive OR of the input bits. As a result, the pseudo-random number generation unit 102 can generate a 31-bit pseudo-random number.

FIG. 3 is a diagram showing the transition of the bit value of the shift register 201 when the Fibonacci linear feedback shift register implemented by the pseudo-random number generation unit 102 is operated. The seed value 301 represents the initial value of the shift register 201. The transition value 302 represents how the bit value of the shift register 201 transitions when the random number generation is repeated once, twice, three times, ..., ^231-2 times. .. The seed value 301 and the transition value 302 all have different values. The transition value 303 is the transition value of the ^231-1st time, but the same value as the seed value 301 is obtained only at the ^231-1st time. The transition value 304 represents the transition value after the ^231st time, but is the same value as the transition value 302. That is, the shift register 201 has periodicity in the generated value, and repeatedly generates a sequence in which the seed value 301 and the transition value 302 represent ^231-1 in one cycle.

Since the shift register 201 is a 31-bit register, the maximum number of numbers that can be represented by the shift register 201 is 2 ³¹ . However, when all the bits are 0, the bit value does not change, so that it cannot be used for random number generation, and the actual upper limit is ^231-1 . Further, the length of one cycle of the bit value transition of the shift register 201 is also ^231-1 . That is, FIG. 3 shows the first after going through all the ^231-1 values that the ^shift register 201 can take as values from the seed value 301 to the arrival of the second transition value 303. It means that it has returned to the value of.

From the above, we can see the following. No matter what seed value 301 is selected, the shift register 201 will be either the seed value 301 or the transition value 302, so the generated random number sequences will be generated only in the order shown in FIG. ..

That is, regarding the seed value 301, the following can be understood. First, if the two seed values are the same, the transition will be the same, so the same pseudo-random number sequence will be generated. Further, even if the two seed values are different, if two close values are used as the seed values in the sequence represented by the seed value 301 and the transition value 302, the generated pseudo-random number sequences partially match. .. Note that using two close values as seed values means that the distance between the seed values is shorter than the number of pseudo-random numbers required for image processing of each block.

In image processing, when such a collision of pseudo-random numbers occurs, the image processing results of each block may partially match and be recognized as a pattern.

In this embodiment, in order to avoid this, the interval between the seed values of each block is set to a value ten separated on the sequence indicated by the seed value 301 and the transition value 302, so that the collision of the pseudo-random number sequence of each block The purpose is to prevent. It should be noted that setting the interval between the seed values of each block to a value ten-separated means that the value is set at a wider interval than the maximum number of pseudo-random numbers required for image processing of each block. For example, if a maximum of 1 million pseudo-random numbers are required for each block, collisions can be prevented by setting the seed value interval of each block to 2 million.

FIG. 4 is a flowchart showing a processing method of the seed value generation unit 105 of FIG. In step S401, the seed value setting unit 104 writes a 31-bit seed value to any one of the plurality of seed value holding units 103. The seed value generation unit 105 waits for the 31-bit seed value writing by the seed value setting unit 104 to be completed, and proceeds to step S402 when the writing is completed.

In step S402, the seed value generation unit 105 reads the 31-bit seed value of the seed value holding unit 103 written in step S401. Next, in step S403, the seed value generation unit 105 instructs the execution of the processing of the pseudo-random number sequence skip unit 106, and obtains the seed value of the next block. Next, in step S404, the seed value generation unit 105 writes the seed value obtained in step S403 to any one of the plurality of seed value holding units 103.

Next, in step S405, the seed value generation unit 105 determines whether or not all the necessary seed values have been written to all the seed value holding units 103. If all the seed values have not been written, the seed value generation unit 105 returns to step S403, repeats the processing of the seed values of the other blocks, and if all the seed values have been written, the figure. The processing of the flowchart of 4 is terminated. As a result, the seed value generation unit 105 can cause the plurality of seed value holding units 103 to hold a plurality of seed values corresponding to the plurality of blocks of the input image.

FIG. 5 is a diagram for explaining a processing method of the pseudo-random number sequence skip unit 106 of FIG. FIG. 5 shows the processing content calculated by the pseudo-random number sequence skip unit 106. The pseudo-random number sequence skip unit 106 is a circuit that outputs a value when the bit value of the linear feedback shift register of the pseudo-random number generation unit 102 shown in FIG. 2 is shifted by a predetermined number of times. For example, the pseudo-random number sequence skip unit 106 is implemented so as to output the value after shifting only 2 million times. The input value 501 is an initial 31-bit value of the linear feedback shift register of the pseudo-random number sequence skip unit 106. The exclusive-OR arithmetic unit 502 performs the same processing as the exclusive-OR arithmetic unit 202 of FIG. The transition value 503 represents the same value as the result of shifting the bit of the shift register 201 of the pseudo-random number generation unit 102 shown in FIG. The output value 504 is a bit value after shifting the bit value of the linear feedback shift register of the pseudo-random number sequence skip unit 106 and generating the transition value 503 2 million times.

Looking at FIG. 5, it can be seen that the operation between the input value 501 and the output value 504 is only the exclusive OR arithmetic unit 502. That is, the expression representing each bit value of the output value 504 can be expressed only by each bit of the input value 501 and the operation of the exclusive OR arithmetic unit 502.

An expression containing only the operation of the exclusive OR arithmetic unit 502 can be converted into a simple expression by modifying the expression. Since the commutative law and the associative law hold in the operation of the exclusive OR arithmetic unit 502, the order of calculation can be arbitrarily changed. Further, when an even number of the same values are collected and the exclusive OR is calculated, it becomes 0. And since the exclusive OR of a certain value and 0 does not change the value, 0 can be ignored. That is, all bit values that appear even in the expression can be ignored. Similarly, any odd number of bit values appearing in an expression may be ignored, leaving one. That is, the formula for calculating each bit value of the output value 504 represents that the formula can be a formula that only takes an exclusive OR after selecting some bit values of the input value 501 without duplication.

FIG. 6 is a diagram showing a configuration example of the pseudo-random number sequence skip section 106 of FIG. The pseudo-random number sequence skip unit 106 has 31 1-bit calculation units 601. Each of the 31 1-bit calculators 601 has an exclusive OR calculator 604.

The 1-bit calculation unit 601 inputs a 31-bit input value 602 and outputs a 1-bit output value 605. Each of the 31 1-bit calculation units 601 calculates 31 1-bit output values 605.

The input value 602 is a 31-bit input value. The mask 603 selects only a part of the 31-bit input value 602, outputs the selected bit to the exclusive-OR calculator 604, sets the other bits to 0, and sets the other bit to the exclusive-OR calculator. Output to 604. The exclusive-OR arithmetic unit 604 calculates the exclusive-OR of the bit values output by the mask 603, and outputs the calculation result as a 1-bit output value 605.

If the bits selected by the mask 603 are fixed, the mask 603 may be used as a mere connection, and the exclusive OR calculator 604 may calculate the exclusive OR of only the bits connected by the mask 603. .. Further, as another configuration example of the mask 603, the bits selected by the mask 603 may be changed from the outside so that the interval between the seed values can be changed.

Further, as yet another configuration example of the mask 603, the mask 603 and the exclusive OR arithmetic unit 604 are processed bit by bit, and the output value 605 of one bit is calculated over 31 cycles. You can also. In this case, the number of cycles required for the calculation of the pseudo-random number sequence skip unit 106 increases, but the circuit scale can be further reduced.

In FIG. 6, the pseudo-random number sequence skip unit 106 is composed of 31 1-bit calculation units 601. However, as another configuration example, only one 1-bit calculation unit 601 may be configured. In the case of this configuration, the 31-bit output value 605 with the same result as in FIG. 6 can be calculated by repeatedly executing the process of the 1-bit calculation unit 601 31 times.

As described above, the seed value setting unit 104 writes the 31-bit seed value of the first block to the first seed value holding unit 103 of the plurality of seed value holding units 103. After that, the seed value generation unit 105 reads out the 31-bit seed value of the first block from the first seed value holding unit 103. Then, the seed value generation unit 105 outputs the 31-bit seed value of the first block to the pseudo-random number sequence skip unit 106, and instructs the operation of the 31-bit seed value of the second block. .. As shown in FIG. 5, the pseudo-random number sequence skip unit 106 inputs the 31-bit seed value of the first block as the input value 501, and after 2 million bit shifts, the seed value of the second block is used. It is output to the seed value generation unit 105 as an output value 504. The seed value generation unit 105 writes the seed value of the second block to the second seed value holding unit 103. The interval between the seed value of the first block and the seed value of the second block is 2 million times.

Next, the seed value generation unit 105 outputs the 31-bit seed value of the second block to the pseudo-random number sequence skip unit 106, and instructs the operation of the 31-bit seed value of the third block. do. As shown in FIG. 5, the pseudo-random number sequence skip unit 106 inputs the 31-bit seed value of the second block as the input value 501, and after 2 million bit shifts, the seed value of the third block is used. It is output to the seed value generation unit 105 as an output value 504. The seed value generation unit 105 writes the seed value of the third block to the third seed value holding unit 103. The interval between the seed value of the second block and the seed value of the third block is 2 million times.

Hereinafter, in the same manner, the seed value generation unit 105 uses the pseudo-random number sequence skip unit 106 to write the 31-bit seed values of all the blocks to all the seed value holding units 103. The interval between seed values of adjacent blocks is 2 million times.

The image processing circuit 101 reads the seed value of the first block from the first seed value holding unit 103 for the first block of the input image, and one for the pseudo random number generation unit 102. Outputs the seed value of the eye block and instructs to generate a pseudo random number. Then, as shown in FIG. 3, the pseudo-random number generator 102 sets the seed value of the first block as the seed value 301 in the shift register 201, and generates, for example, 1 million pseudo-random numbers, for example, 1 million. The pseudo-random numbers are output to the image processing circuit 101. The image processing circuit 101 uses, for example, one million pseudo-random numbers to perform image processing such as image enlargement / reduction processing on the first block of the input image, and the output image of the first block. And save.

Next, the image processing circuit 101 reads the seed value of the second block from the second seed value holding unit 103 for the second block of the input image, and reads the seed value of the second block to the pseudo random number generation unit 102. Second, the seed value of the second block is output, and a pseudo random number generation is instructed. Then, as shown in FIG. 3, the pseudo-random number generator 102 sets the seed value of the second block as the seed value 301 in the shift register 201, and generates, for example, 1 million pseudo-random numbers, for example, 1 million. The pseudo-random numbers are output to the image processing circuit 101. The image processing circuit 101 uses, for example, one million pseudo-random numbers to perform image processing such as image enlargement / reduction processing on the second block of the input image, and the output image of the second block. And save.

Hereinafter, in the same manner, the image processing circuit 101 performs image processing on the blocks from the third to the end of the input image using pseudo random numbers, respectively, and outputs an image of the blocks from the third to the end. And save. Then, the image processing circuit 101 integrates the output images of all the blocks and outputs the integrated output image.

Since the pseudo-random number generation unit 102 has an interval of seed values of adjacent blocks of 2 million times, it is possible to prevent collision of pseudo-random number sequences of each block of the input image. The image processing circuit 101 can, for example, prevent duplication of the insertion positions of pixels of each block of the input image, and prevent the generation of patterns due to periodic changes in the image pattern.

As described above, the seed value setting unit 104 sets one seed value for one seed value holding unit 103. The seed value generation unit 105 uses the pseudo-random number sequence skip unit 106 to divide the input image into a plurality of seed values based on one seed value set by the seed value setting unit 104. To generate. The pseudo-random number generation unit 102 is a pseudo-random number generation unit, and generates a pseudo-random number sequence for each of the plurality of blocks based on the plurality of seed values for the plurality of blocks. The image processing circuit 101 is an image processing unit, and uses a pseudo-random number sequence for each of the above-mentioned plurality of blocks to perform image processing on each of the plurality of blocks obtained by dividing the input image.

The seed value generation unit 105 generates a plurality of pseudo-random numbers skipped by a predetermined number from the pseudo-random number sequence generated based on the above-mentioned one seed value as a plurality of seed values. The predetermined number is a number larger than the maximum number of pseudo-random numbers used by the image processing circuit 101 for image processing of each block.

The above-mentioned plurality of seed values include the above-mentioned one seed value. The seed value setting unit 104 writes the above-mentioned one seed value to one seed value holding unit 103. The seed value generation unit 105 writes a seed value other than the above-mentioned one seed value among the above-mentioned plurality of seed values to the other seed value holding unit 103.

As shown in FIG. 2, the pseudo-random number generation unit 102 generates a pseudo-random number by performing an exclusive OR operation based on the seed value. The seed value generation unit 105 uses the pseudo-random number sequence skip unit 106 to perform an exclusive OR operation on some bits of one seed value among the above-mentioned plurality of seed values, as shown in FIG. By doing so, other seed values among the above-mentioned plurality of seed values are generated.

The pseudo-random number sequence skip unit 106 has a plurality of 1-bit calculation units 601. Each of the plurality of 1-bit calculation units 601 is a bit calculation unit, and by performing an exclusive OR operation on some bits of one seed value among the above-mentioned plurality of seed values, the above-mentioned Generates one bit of the other seed value among the multiple seed values of.

The pseudo-random number sequence skip unit 106 performs an exclusive OR operation on some bits of one seed value among the above-mentioned plurality of seed values, thereby performing an exclusive OR operation among the above-mentioned plurality of seed values. The process of generating one bit of another seed value may be repeated a plurality of times. Further, the pseudo-random number sequence skip unit 106 can change the predetermined number by changing some bits of one seed value among the plurality of seed values to other bits.

As described above, in the present embodiment, the seed value generation unit 105 can adjust the interval between the seed values held in the seed value holding unit 103. The maximum number of pseudo-random numbers that need to be generated for each seed value can be estimated from the size of each block, so if the seed value interval is wider than the maximum number, the pseudo-random number sequence used in each block will be used. Can be prevented from colliding.

When the seed value setting unit 104 sets the first seed value, the seed value generation unit 105 can automatically generate a plurality of seed values in which the pseudo-random number strings do not collide with each other by using the pseudo-random number sequence skip unit 106. As a result, it is not necessary to set the seed value of each of the plurality of blocks obtained by dividing the input image from the outside, and it is possible to generate a pseudo-random number for image processing of each block in a short time.

(Second embodiment)
The image processing apparatus 100 according to the second embodiment has the same configuration as that of FIG. 1 of the first embodiment, but the pseudo-random number generation unit 102 is composed of a Galois linear feedback shift register. Even in the case of the Galois linear feedback shift register, the pseudo-random number sequence skip unit 106 can be realized by the configuration shown in FIG. 6 of the first embodiment.

FIG. 7 is a diagram showing a configuration example of the pseudo-random number generation unit 102 according to the second embodiment. The pseudo-random number generator 102 has a plurality of exclusive OR arithmetic units 701 and a shift register 702. The exclusive OR calculator 701 inputs 2 bits and outputs a 1-bit result of the input 2-bit exclusive OR. The shift register 702 has 31 registers, each register holds 1 bit, and the entire register holds a 31-bit value. However, some exclusive OR arithmetic units 701 are inserted between the 31-bit registers of the shift register 702. The exclusive OR arithmetic unit 701 takes an exclusive OR of 1 bit input from the register in the previous stage and 1 bit output from the output end (right end) of the shift register 702, and sets 1 bit as the next stage. Output to the register. As a result, the pseudo-random number generation unit 102 can generate a 31-bit pseudo-random number.

FIG. 8 corresponds to FIG. 5 of the first embodiment and is a diagram for explaining a processing method of the pseudo-random number sequence skip unit 106. However, in FIG. 8, only one stage of FIG. 5 is shown. The input value 801 is an initial 31-bit value of the Galois linear feedback shift register of the pseudo-random number sequence skip unit 106. The exclusive-OR arithmetic unit 802 performs the same processing as the exclusive-OR arithmetic unit 701 of FIG. 7. The transition value 803 represents the same value as the result of shifting the bits of the shift register 702 in FIG. 7.

Looking at FIG. 8, it can be seen that the operation of the pseudo-random number sequence skip unit 106 of the present embodiment is performed only by the exclusive OR arithmetic unit 802. That is, the pseudo-random number sequence skip section 106 of the present embodiment can also be implemented with the configuration of FIG. 6, as in the result examined in FIG. 5 of the first embodiment.

(Third embodiment)
The image processing device 100 according to the third embodiment has the same configuration as that of FIG. 1 of the first embodiment, but the pseudo-random number generation unit 102 is configured by Xorshift. Also in the case of Xorshift, the pseudo-random number sequence skip unit 106 can be realized by the configuration shown in FIG. 6 of the first embodiment.

FIG. 9 is a flowchart showing an example of the pseudo-random number generation process of Xorshift of the pseudo-random number generation unit 102. However, the variable y is a 32-bit signless integer. The variable y represents one value in the pseudo-random number sequence. By the process of FIG. 9, the value of the variable y is updated to the value of the next pseudo-random number.

In step S901, the pseudo-random number generator 102 takes an exclusive OR of the value of the variable y and the value obtained by shifting the value of the variable y to the left by 13 bits, and assigns the value to the variable y. In step S902, the pseudo-random number generator 102 takes an exclusive OR of the value of the variable y and the value obtained by shifting the value of the variable y to the right by 17 bits, and assigns the value to the variable y. In step S903, the pseudo-random number generator 102 takes an exclusive OR of the value of the variable y and the value obtained by shifting the value of the variable y to the left by 5 bits, and assigns the value to the variable y. As a result, the variable y is generated as a pseudo-random number. In the process of FIG. 9, as a result of left shift or right shift, the bits outside the 32-bit range are ignored.

FIG. 10 is a diagram showing the pseudo-random number generation process of Xorshift shown in FIG. 9 by the exclusive OR arithmetic unit 1002. Further, FIG. 10 is a diagram showing a configuration example of the pseudo-random number generation unit 102 according to the present embodiment.

The pseudo-random number value 1001 represents the current 32-bit pseudo-random number value. The pseudo-random number generator 102 uses the circuit of FIG. 10 to obtain the next pseudo-random number value 1005 based on the current pseudo-random number value 1001. The exclusive-OR arithmetic unit 1002 performs an exclusive-OR operation. The variable 1003 represents the variable y of the calculation result of step S901. The variable 1004 represents the variable y of the calculation result of step S902. The pseudo-random number value 1005 represents the variable y of the calculation result of step S903.

The processing content of the pseudo-random number sequence skip unit 106 according to the present embodiment can be realized by repeating the processing of FIG. 10 as shown in FIG. Looking at FIG. 10, it can be seen that the operation of the pseudo-random number sequence skip unit 106 of the present embodiment is performed only by the exclusive OR arithmetic unit 1002. That is, similarly to the first embodiment, the pseudo-random number sequence skip unit 106 of the present embodiment can also be implemented with the configuration of FIG.

(Other embodiments)
The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by the processing to be performed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

It should be noted that the above embodiments are merely specific examples for carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner by these. That is, the present invention can be implemented in various forms without departing from the technical idea or its main features.

100 Image processing device, 101 Image processing circuit, 102 Pseudo-random number generator, 103 Seed value holding unit, 104 Seed value setting unit, 105 Seed value generation unit, 106 Pseudo-random number sequence skipping unit

Claims (13)

A seed value generation means that generates a plurality of seed values for a plurality of blocks obtained by dividing an image based on one seed value.
A pseudo-random number generation means that generates a pseudo-random number sequence for each of the plurality of blocks based on a plurality of seed values for the plurality of blocks.
It has an image processing means for performing image processing on each of the plurality of blocks obtained by dividing the image by using a pseudo-random number sequence for each of the plurality of blocks.
The seed value generation means generates, as the plurality of seed values, a plurality of pseudo-random numbers skipped by a predetermined number from the pseudo-random number sequence generated by the pseudo-random number generation means based on the one seed value. Characteristic image processing device. The image processing apparatus according to claim 1, wherein the predetermined number is a number larger than the maximum number of pseudo-random numbers used by the image processing means for image processing of each block. The image processing apparatus according to claim 1 or 2, further comprising a seed value setting means for setting one seed value. The plurality of seed values include the one seed value.
The seed value setting means writes the one seed value,
The image processing apparatus according to claim 3, wherein the seed value generating means writes a seed value other than the one seed value among the plurality of seed values. The pseudo-random number generation means generates a pseudo-random number by performing an exclusive OR operation based on the seed value.
The seed value generation means performs an exclusive OR operation on some bits of one seed value among the plurality of seed values, thereby performing an exclusive OR operation on the other seed values among the plurality of seed values. The image processing apparatus according to any one of claims 1 to 4, wherein the image processing apparatus is generated. The seed value generating means has a plurality of bit arithmetic means, and has a plurality of bit arithmetic means.
Each of the plurality of bit operation means performs an exclusive OR operation on some bits of one seed value among the plurality of seed values, thereby performing an exclusive OR operation on the other of the plurality of seed values. The image processing apparatus according to claim 5, wherein 1 bit of the seed value of is generated. The seed value generation means performs an exclusive OR operation on some bits of one seed value among the plurality of seed values, thereby performing an exclusive OR operation on the other seed values among the plurality of seed values. The image processing apparatus according to claim 5, wherein the process of generating one bit of the above is repeated a plurality of times. 5. The seed value generating means is characterized in that the predetermined number is changed by changing some bits of one seed value among the plurality of seed values to other bits. 7. The image processing apparatus according to any one of 7. The image processing apparatus according to any one of claims 1 to 8, wherein the pseudo-random number generation means generates a pseudo-random number by using a Fibonacci linear feedback shift register. The image processing apparatus according to any one of claims 1 to 8, wherein the pseudo-random number generation means generates a pseudo-random number by using a Galois linear feedback shift register. The image processing apparatus according to any one of claims 1 to 8, wherein the pseudo-random number generation means generates a pseudo-random number of Xorshift. A seed value generation step that generates multiple seed values for multiple blocks that divide an image based on one seed value.
A pseudo-random number generation step that generates a pseudo-random number sequence for each of the plurality of blocks based on the plurality of seed values for the plurality of blocks.
It has an image processing step of performing image processing on each of the plurality of blocks obtained by dividing the image by using a pseudo-random number sequence for each of the plurality of blocks.
In the seed value generation step, a plurality of pseudo-random numbers skipped by a predetermined number from the pseudo-random number sequence generated based on the one seed value in the pseudo-random number generation step are generated as the plurality of seed values. An image processing method of a featured image processing device. A program for making a computer function as each means of the image processing apparatus according to any one of claims 1 to 11.

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