JP2022091189A - Power conversion device and method for controlling the same - Google Patents

Abstract

To reduce distortion of an output voltage by suppressing a gain of control for performing feedback of a capacitor current in the vicinity of zero-cross of a voltage command value given to a three-level converter in a power conversion device.SOLUTION: A voltage control unit 4 outputs a voltage command value before damping compensation based on deviation between a capacitor voltage command value Vref and a capacitor voltage detection value Vc. A damping compensation unit 5 calculates a damping compensation term based on a capacitor current detection value Ic, and multiplies the damping compensation term by a gain Gain to output it as a damping compensation value. The gain Gain is set to 0 at a zero-crossing point of phase voltage command values Vu, Vv, and Vw. An inverter output voltage command value Vinv* is calculated by adding the voltage command value before damping compensation and the damping compensation value. A gate signal GATE of a three-level converter is generated by PWM comparison of the phase voltage command values Vu, Vv, and Vw obtained by two-phase-three-phase conversion of the inverter output voltage command value Vinv* with a triangular wave carrier signal.SELECTED DRAWING: Figure 1

Description

The present invention relates to a control method for a power conversion device.

In a power converter that generates a pulse voltage by PWM control of a DC / three-phase AC converter, an ACL (AC reactor) or an LC consisting of a three-phase transformer and a filter capacitor is used to smooth the pulse voltage. A filter is used. Further, in the system interconnection device, an LC filter composed of an LC filter and an ACL or a three-phase transformer is used.

A power converter in which an LC filter or LCL filter is installed between the output pulse voltage source of the DC / three-phase AC converter and the AC voltage source or load of the system is the output current of the DC / three-phase AC converter. Includes the harmonic current generated by PWM. The current of this harmonic component flows into the filter capacitor, and the output current flowing to the system or load has the harmonic component reduced.

Patent Document 1 and Patent Document 2 (see FIG. 12) describe a control system for controlling the voltage of the converter output in a configuration in which an LC filter is installed in the output pulse voltage source of the DC / three-phase AC converter. The control that feeds back the capacitor current is disclosed in. By using the control that feeds back the capacitor current, it is possible to reduce the output voltage distortion caused by the resonance of the resonance frequency of the LC filter and the harmonic component included in the pulse voltage.

As the DC / three-phase AC converter, a two-level converter, a three-level converter, or the like is generally used. Typical circuit configurations of the three-level converter are shown in FIGS. 13 and 14 (Patent Documents 3 and 4).

The three-level converter is a device that includes a voltage source of voltage E divided by two and outputs three levels of AC voltage of + E, 0, and −E. Further, the 3-level converter theoretically reduces the frequency (carrier frequency) of the triangular wave carrier signal (reference numeral 34 in FIG. 12) for performing PWM modulation while reducing the output voltage distortion as compared with the 2-level converter. Can be reduced.

However, in the vicinity of the zero cross of the voltage command value given to the three-level converter, the width of the pulse voltage modulated by PWM becomes narrow, and the pulse voltage may not be output due to the dead time.

Japanese Unexamined Patent Publication No. 2012-39827 Patent No. 3298441 Japanese Unexamined Patent Publication No. 2019-146380 Japanese Unexamined Patent Publication No. 2018-148709

Patent Document 1 and Patent Document 2 disclose that the output voltage distortion caused by the resonance of the resonance frequency of the LC filter and the harmonic component included in the pulse voltage can be reduced by using the control of feeding back the capacitor current. .. However, what is shown in Patent Document 2 is a two-level converter (see FIGS. 1 and 7 of Patent Document 2). No mention is made of its application to 3-level transducers.

When this is applied to a 3-level converter operating at a low carrier frequency, the width of the pulse voltage modulated by PWM becomes narrow near the zero cross of the voltage command value given to the 3-level converter, and the pulse voltage is output due to the dead time. It may not be done.

As a result, in the 3-level converter, there may be a region where the output voltage distortion due to the resonance between the LC filter and the harmonic component of the pulse voltage cannot be reduced in the vicinity of the zero cross of the voltage command value. This was found by the simulation shown in FIG. 2 described later.

Therefore, in this region, it is necessary to take measures to suppress the control of feeding back the capacitor current (do not perform, lower the gain, make it variable, etc.).

From the above, it is possible to reduce the distortion of the output voltage by taking measures to suppress the control gain that feeds back the capacitor current in the vicinity of the zero cross of the voltage command value given to the three-level converter in the power converter. It becomes an issue.

The present invention has been devised in view of the above-mentioned conventional problems, and one aspect thereof is a three-level converter, an LC filter or an LCL filter connected between the three-level converter and a load, and the like. The power conversion device is equipped with a voltage control unit that outputs the voltage command value before damping compensation based on the deviation between the capacitor voltage command value and the capacitor voltage detection value, and the damping compensation term is calculated based on the capacitor current detection value. Then, the damping compensation term is multiplied by the gain and output as the damping compensation value, and the damping compensation unit sets the gain to 0 at the zero crossing point of the phase voltage command value, the voltage command value before the damping compensation, and the damping compensation value. An adder that outputs the inverter output voltage command value by adding, a two-phase three-phase converter that converts the inverter output voltage command value into two-phase and three-phase and outputs the phase voltage command value, and the phase voltage command. It is characterized by including a PWM control unit that generates a gate signal of the three-level converter based on a PWM comparison between a value and a triangular wave carrier signal.

Further, as one aspect thereof, the damping compensator sets the gain to 1 when the minimum value of the absolute values of the phase voltage command values is equal to or higher than the first set threshold value, and the minimum value is the first set threshold value. If it is less than, the gain is set to 0.

As another embodiment, the damping compensator sets the gain to 1 when the minimum value of the absolute values of the phase voltage command values is equal to or greater than the first set threshold value, and the minimum value is the first set threshold value. If it is less than, the gain is the value obtained by dividing the minimum value by the first set threshold value.

As another aspect, the damping compensator sets the gain to 1 when the minimum value of the absolute values of the phase voltage command values is equal to or greater than the first set threshold value, and the minimum value is the first set threshold value. If it is less than or equal to or greater than the second set threshold value, the value obtained by subtracting the second set threshold value from the minimum value and dividing by the value obtained by subtracting the second set threshold value from the first set threshold value is defined as the gain. When the minimum value is less than the second set threshold value, the gain is set to 0.

According to the present invention, in the power converter, it is possible to reduce the distortion of the output voltage by taking measures to suppress the gain of the control that feeds back the capacitor current in the vicinity of the zero cross of the voltage command value given to the three-level converter. Become.

A block diagram showing a main circuit configuration and a control unit of a power converter. The figure which shows the simulation waveform which performed damping compensation. The figure which shows the simulation waveform which did not perform damping compensation. The figure which shows the magnitude of the minimum value of the phase voltage command value of three phases. The block diagram which shows the damping compensation part in Embodiment 1. FIG. The figure which shows the waveform of the gain in Embodiment 1. FIG. The block diagram which shows the damping compensation part in Embodiment 2. The figure which shows the waveform of the gain in Embodiment 2. The block diagram which shows the damping compensation part in Embodiment 3. The figure which shows the waveform of the gain in Embodiment 3. FIG. The figure which shows the case where the constant gain = 1 and the simulation result of Embodiment 3. The figure which shows the main circuit structure of Patent Document 2. The figure which shows the main circuit structure of Patent Document 4. The figure which shows the main circuit structure of Patent Document 4.

Hereinafter, the power conversion device according to the present invention will be described in detail with reference to FIGS. 1 to 11.

FIG. 1 (a) shows the main circuit configuration of a power conversion device in which an LC filter is installed at the output of a DC / three-phase AC converter, and FIG. 1 (b) shows a block of a control unit of a voltage control system with damping compensation added. Is shown. First, the main circuit configuration of FIG. 1A will be described.

The inverter INV converts DC power into AC power and outputs it. The inverter output is output to the load via an LC filter having a reactor L and a capacitor C.

The inverter INV is a 3-level converter. The representative circuit configurations of the three-level converter are shown in FIGS. 13 and 14, but other circuit configurations may be used. Further, although the LC filter is shown in FIG. 1A, it may be an LC filter.

Here, Ic is a capacitor current detection value, Vc is a capacitor voltage detection value, IL is a load current, and DC is a DC power supply.

Next, the control unit of FIG. 1B will be described. The three-phase two-phase converter 1 converts the three-phase (UVW phase) capacitor voltage detection value Vc into three-phase two-phase conversion and converts it into the d-axis and q-axis capacitor voltage detection values. The three-phase two-phase converter 2 converts the three-phase (UVW phase) capacitor current detection value Ic into three-phase two-phase conversion and converts it into the d-axis and q-axis capacitor current detection values.

Vref in FIG. 1A is a capacitor voltage command value at point A in FIG. 1A. Here, the capacitor voltage command value Vref is a value on the dq coordinate. The subtractor 3 subtracts the d-axis and q-axis capacitor voltage detection values Vc from the capacitor voltage command value Vref, and outputs the deviation between the capacitor voltage command value Vref and the capacitor voltage detection value Vc.

The AVR (voltage control unit) 4 performs PI control or the like based on the deviation between the capacitor voltage command value Vref and the capacitor voltage detection value Vc, and outputs the voltage command value before damping compensation.

The damping compensation unit 5 outputs a damping compensation value based on the d-axis and q-axis capacitor current detection values Ic. The adder 6 adds the damping compensation value to the damping compensation pre-voltage command value to generate the inverter output voltage command value Viv * (voltage command at point B in FIG. 1B).

The two-phase three-phase converter 7 converts the inverter output voltage command value Vinv * into two-phase three-phase, and outputs the three-phase phase voltage command values Vu, Vv, and Vw. The PWM control unit 8 generates a gate signal (on / off command signal) of each switching element in the three-level converter based on the comparison between the three-phase phase voltage command values Vu, Vv, Vw and the triangular wave carrier signal.

Patent Document 2 (FIG. 2) shown in FIG. 12 discloses a control system that feeds back the LC filter capacitor current. The feedback control is stabilized by adding the feedback system of the capacitor current.

FIG. 2 shows a simulation waveform in which damping compensation is performed by feeding back only the harmonic component of the filter capacitor current, and FIG. 3 shows a simulation waveform in which damping compensation is not performed. 2 and 3 (a) are the line voltage waveforms at point A in FIG. 1, FIG. 2 and 3 (b) are the line voltage waveforms at point B in FIG. 1, and FIGS. 2 and 3 (c). ) Is the waveform of the load current IL in FIG.

The waveform of the substantially sine wave shown in FIGS. 2 and 3 (d) is an input signal (three-phase phase voltage command values Vu, Vv, Vw) to the PWM control unit 8 of FIG. The triangular wave of FIG. 2 and FIG. 3 (d) is a triangular wave carrier signal used for generating a gate signal in the PWM control unit 8 of FIG. (E) of FIGS. 2 and 3 is a PWM voltage command waveform, and a gate signal GATE is output from the PWM control unit 8 based on the PWM voltage command waveform. Moreover, these simulations are performed using a three-level converter as a model.

As shown in the dotted line of FIG. 2, the pulsation of the carrier frequency component occurs in the voltage waveform around the voltage command value zero cross. This is caused by the fact that the thin pulse voltage near the zero cross described above disappears due to the dead time and the control performance deteriorates.

On the other hand, in the voltage waveform around the zero cross without damping compensation in FIG. 3, the pulsation as shown in FIG. 2 is reduced. The voltage waveforms in FIGS. 2 and 3 show the line voltage. Therefore, the dotted line portion deviated by 30 degrees from the zero cross of the line voltage corresponds to the vicinity of the zero cross of the phase voltage.

The width of the pulse voltage becomes narrow near the zero cross of the voltage command value. When damping compensation is performed for this narrow pulse voltage, a difference between the theoretical value to be compensated and the value that can be actually compensated is likely to occur, and the compensation operation is rather counterproductive due to this difference. It is also possible. As a proof of this, the pulsation of the voltage waveform around the zero cross is reduced in FIG. 3 without damping compensation than in FIG. 2 with damping compensation.

By the way, the minimum value of the three-phase phase voltage command values Vu, Vv, Vw shown in FIG. 4 (the phase voltage command value of the phase having the lowest absolute value among the three-phase phase voltage command values Vu, Vv, Vw). Since the size (solid line) corresponds to the region around the zero cross, the minimum absolute value of the three-phase phase voltage command values Vu, Vv, Vw is used as the zero cross detector, and the variable gain to the damping compensation term is set. The control method of generating and multiplying will be described in the following embodiments 1 to 3. In the first to third embodiments, the gain Gain to be multiplied by the damping compensation term at the zero cross point of the phase voltage command values Vu, Vv, and Vw is set to 0.

[Embodiment 1]
FIG. 5 is a block diagram of the damping compensation unit 5 of the first embodiment. The ABS (absolute value conversion unit) 9 sets the three-phase voltage command value (phase voltage command values Vu, Vv, Vw input to the “PWM control unit 8” in FIG. 1 (b)) of the previous control cycle as an absolute value. Convert. When three-phase modulation is performed on the phase voltage command value, either the phase voltage command value before the three-phase modulation or after the three-phase modulation may be used. The minimum value selection unit 10 selects and outputs the lowest value among the three absolute values.

As shown in FIG. 6, the comparator 11 compares the first set threshold value LV_H with the output of the minimum value selection unit 10. As shown in FIG. 6, the switch 12 outputs 1 as a gain Gain when the output of the minimum value selection unit 10 is equal to or higher than the first set threshold value LV_H, and 0 as a gain Gain when the output is less than the first set threshold value LV_H. Output.

The HPF (high-pass filter) 13 extracts harmonics of the capacitor current detection value Ic (output of the three-phase two-phase converter 2). The multiplier 14 multiplies the output of HPF 13 by the coefficient K. The output of the multiplier 14 is the damping compensation term. The multiplier 15 multiplies the output (dumping compensation term) of the multiplier 14 by the gain Gain. The output of the multiplier 15 becomes the output (dumping compensation value) of the damping compensation unit 5.

[Embodiment 2]
FIG. 7 is a block diagram of the damping compensation unit 5 of the second embodiment. Here, the same parts as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted, and only the differences from the first embodiment will be described.

The divider 16 divides the output of the minimum value selection unit 10 by the first set threshold value LV_H. The switch 17 inputs 1 and the output of the divider 16, and as shown in FIG. 8, if the output of the minimum value selection unit 10 is equal to or higher than the first setting threshold value LV_H, 1 is output as a gain Gain and the minimum value is selected. If the output of unit 10 is less than the first setting threshold LV_H, the output of the divider 16 (the value obtained by dividing the output of the minimum value selection unit 10 by the first setting threshold LV_H) is output as a gain Gain. When the output of the minimum value selection unit 10 is less than the first setting threshold value LV_H, the gain Gain hangs down from 1 to 0.

[Embodiment 3]
FIG. 9 is a block diagram of the damping compensation unit 5 of the third embodiment. Here, the same parts as those of the first and second embodiments are designated by the same reference numerals, and the description thereof will be omitted, and only the differences from the first and second embodiments will be described.

The comparator 11 compares the output of the minimum value selection unit 10 with the first set threshold value LV_H, and outputs a switching signal to the switch 22. The comparator 18 compares the output of the minimum value selection unit 10 with the second set threshold value LV_L, and outputs a switching signal to the switch 23.

The subtractor 19 subtracts the second set threshold value LV_L from the output of the minimum value selection unit 10. The subtractor 20 subtracts the second set threshold value LV_L from the first set threshold value LV_H. The divider 21 divides the output of the subtractor 19 by the output of the subtractor 20. That is, as shown in FIG. 10, by subtracting the second setting threshold value LV_L from the output of the minimum value selection unit 10 and dividing by the difference between the upper and lower limits of the setting threshold value, the output of the minimum value selection unit 10 is the second setting threshold value LV_L. When the value is less than the first set threshold value LV_H, the gain Gain hangs from 1 to 0.

The switch 22 outputs 1 when the output of the minimum value selection unit 10 is equal to or higher than the first setting threshold value LV_H, and outputs the output of the divider 21 when the output of the minimum value selection unit 10 is less than the first setting threshold value LV_H. do.

The switch 23 outputs the output of the switch 22 when the output of the minimum value selection unit 10 is equal to or greater than the second setting threshold value LV_L, and outputs 0 when the output of the minimum value selection unit 10 is less than the second setting threshold value LV_L. ..

That is, the first and second setting threshold values LV_H and LV_L are compared with the output of the minimum value selection unit 10, and if the output of the minimum value selection unit 10 is equal to or higher than the first setting threshold value LV_H, gain Gain = 1 is selected. When the output of the unit 10 is less than the second setting threshold value LV_L, the gain Gain = 0, and when the output of the minimum value selection unit 10 is equal to or more than the second setting threshold value LV_L and less than the first setting threshold value LV_H, the calculated hanging gain Gain is used. Get on the damping compensation term.

In the damping compensation, FIG. 11 shows the simulation results of the output voltage distortion factor and the waveform (line voltage) in the case of (a) always setting the gain = 1 and (b) performing the gain correction shown in the third embodiment. show. (Simulation conditions: output voltage = 270V, output power = 6kW, resistance load, LV_H = 69V, LV_L = 47V). In FIG. 11B using the third embodiment, it can be seen that the output voltage distortion is reduced.

As shown above, according to the first to third embodiments, in the power conversion device that controls the voltage of the three-level converter output, when the control of feeding back the capacitor current to the control system is used, the voltage is given to the three-level converter. It is unnecessary by detecting the zero cross of the phase voltage command value by a simple calculation and lowering the control gain that feeds back the capacitor current only when the control performance deteriorates due to the loss of the pulse voltage at the time of zero cross (around zero cross). It is possible to reduce voltage pulsation and suppress voltage distortion.

Although the above description has been made in detail only for the specific examples described in the present invention, it is obvious to those skilled in the art that various modifications and modifications are possible within the scope of the technical idea of the present invention. It goes without saying that such modifications and modifications fall within the scope of the claims.

1,2 ... Three-phase two-phase converter 3,19,20 ... Subtractor 4 ... AVR (voltage control unit)
5 ... Damping compensation unit 6 ... Adder 7 ... Two-phase three-phase converter 8 ... PWM control unit 9 ... ABS (absolute value conversion unit)
10 ... Minimum value selection unit 11, 18 ... Comparator 12, 17, 22, 23 ... Switch 13 ... HPF (high-pass filter)
14,15 ... Multiplier 16,21 ... Divider INV ... Inverter L ... Reactor C ... Capacitor

Claims (5)

A power converter including a three-level converter, an LC filter or an LCL filter connected between the three-level converter and a load, and the like.
A voltage control unit that outputs the voltage command value before damping compensation based on the deviation between the capacitor voltage command value and the capacitor voltage detection value,
A damping compensation unit that calculates a damping compensation term based on the capacitor current detection value, multiplies the damping compensation term by a gain, outputs it as a damping compensation value, and sets the gain to 0 at the zero crossing point of the phase voltage command value.
An adder that outputs the inverter output voltage command value by adding the damping compensation value and the damping compensation value.
A two-phase three-phase converter that converts the inverter output voltage command value into two-phase and three-phase and outputs the phase voltage command value.
A PWM control unit that generates a gate signal of the three-level converter based on a PWM comparison between the phase voltage command value and the triangular wave carrier signal.
A power conversion device characterized by being equipped with. The damping compensation unit is
When the minimum value of the absolute values of the phase voltage command values is equal to or greater than the first set threshold value, the gain is set to 1.
The power conversion device according to claim 1, wherein the gain is set to 0 when the minimum value is less than the first set threshold value. The damping compensation unit is
When the minimum value of the absolute values of the phase voltage command values is equal to or greater than the first set threshold value, the gain is set to 1.
The power conversion device according to claim 1, wherein when the minimum value is less than the first set threshold value, the value obtained by dividing the minimum value by the first set threshold value is used as the gain. The damping compensation unit is
When the minimum value of the absolute values of the phase voltage command values is equal to or greater than the first set threshold value, the gain is set to 1.
When the minimum value is less than the first set threshold value and greater than or equal to the second set threshold value, the value obtained by subtracting the second set threshold value from the minimum value and the value obtained by subtracting the second set threshold value from the first set threshold value. The value divided by is used as the gain.
The power conversion device according to claim 1, wherein the gain is set to 0 when the minimum value is less than the second set threshold value. It is a control method of a three-level converter, an LC filter or an LCL filter connected between the three-level converter and a load, and a power converter provided.
The voltage control unit outputs the voltage command value before damping compensation based on the deviation between the capacitor voltage command value and the capacitor voltage detection value.
The damping compensation unit calculates the damping compensation term based on the capacitor current detection value, multiplies the damping compensation term by the gain and outputs it as the damping compensation value, and sets the gain to 0 at the zero cross point of the phase voltage command value.
The adder adds the damping compensation value and the damping compensation value to output the inverter output voltage command value.
The two-phase three-phase converter converts the inverter output voltage command value into two-phase three-phase and outputs the phase voltage command value.
A control method for a power conversion device, wherein the PWM control unit generates a gate signal of the three-level converter based on a PWM comparison between the phase voltage command value and a triangular wave carrier signal.

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