JP2022090951A - Solid-state imaging device, adjustment method, and electronic device - Google Patents

Abstract

To provide a solid-state imaging device capable of avoiding a decrease in the amount of saturation signal and a decrease in yield.SOLUTION: A solid-state imaging device includes a photoelectric conversion unit that converts light into electric charges, which is provided on a semiconductor substrate, a charge storage unit to which the electric charge is transferred from the photoelectric conversion unit, an overflow path that discharges the excess charge, and an adjustment circuit that adjusts the potential barrier of the overflow path.SELECTED DRAWING: Figure 4

Description

The present disclosure relates to solid-state image sensors, adjustment methods and electronic devices.

A CMOS (Complementary MOS) type solid-state image sensor that can be manufactured by a process similar to that of a MOS (Metal-Oxide-Semiconductor Ductor) integrated circuit can be applied as a pixel to an image pickup device that captures a subject. The solid-state image sensor has a feature that an active structure having an amplification function for each pixel can be easily created by a miniaturization technique associated with a CMOS process. Further, in the solid-state image sensor, peripheral circuits such as a drive circuit for driving a pixel array unit, which is an aggregate of pixels, and a signal processing circuit for processing signals output from each pixel of the pixel array unit are referred to as a pixel array unit. It has the feature that it can be integrated on the same semiconductor substrate (chip). Due to these characteristics, CMOS type solid-state image sensors are being actively developed.

Japanese Unexamined Patent Publication No. 2004-223634

Conventionally, it has been studied how to handle the excess charge overflowing from the photodiode of the solid-state image sensor when the above-mentioned solid-state image sensor is irradiated with a large amount of light. Various structures have been proposed for discharging charges. For example, various structures have been proposed that allow excess charge to overflow from a photodiode, but an overflow potential barrier that determines the saturation signal amount when overflowing when the saturation signal amount (threshold value) is exceeded. It is difficult to control the potential of the diode accurately. Therefore, in any of the structures, it is difficult to avoid the variation in the potential of the overflow potential barrier, which leads to a decrease in the saturation signal amount and a decrease in the yield.

Therefore, the present disclosure proposes a solid-state image sensor, an adjustment method, and an electronic device that can avoid a decrease in the saturation signal amount and a decrease in the yield.

According to the present disclosure, a photoelectric conversion unit that converts light into electric charge, a charge storage unit that transfers the electric charge from the photoelectric conversion unit, and an overflow path that discharges the excess electric charge are provided on the semiconductor substrate. , A solid-state imaging device comprising an adjusting circuit for adjusting the potential barrier of the overflow path.

Further, according to the present disclosure, a photoelectric conversion unit that converts light into electric charge, a charge storage unit that transfers the electric charge from the photoelectric conversion unit, and an overflow unit that discharges the excess electric charge are provided on the semiconductor substrate. A method for adjusting the potential barrier of a solid-state imaging device having a path and an adjusting circuit for adjusting the potential barrier of the overflow path, wherein the adjusting circuit is based on a measurement result of a saturation signal amount of a photoelectric conversion unit. Adjustment methods are provided, including adjusting the potential barrier.

Further, according to the present disclosure, a photoelectric conversion unit that converts light into electric charge, a charge storage unit that transfers the electric charge from the photoelectric conversion unit, and an overflow unit that discharges excess electric charge are provided on the semiconductor substrate. An electronic device is provided that comprises a solid-state imaging device comprising a path and an adjustment circuit that adjusts the potential barrier of the overflow path.

It is explanatory drawing which shows the plane structure example of the image pickup apparatus 1 which concerns on embodiment of this disclosure. It is an equivalent circuit diagram of the pixel 100 which concerns on 1st Embodiment of this disclosure. It is a plane schematic diagram which shows an example of the detailed structure of the pixel 100 which concerns on 1st Embodiment of this disclosure. It is sectional drawing which shows an example of the detailed structure of the pixel 100 which concerns on 1st Embodiment of this disclosure. It is sectional drawing which shows an example of the detailed structure of the pixel 100 which concerns on 2nd Embodiment of this disclosure. It is sectional drawing which shows an example of the detailed structure of the pixel 100 which concerns on 3rd Embodiment of this disclosure. It is sectional drawing which shows an example of the detailed structure of the pixel 100 which concerns on 4th Embodiment of this disclosure. It is a plane schematic diagram which shows an example of the detailed structure of the pixel 100 which concerns on 5th Embodiment of this disclosure. It is sectional drawing which shows an example of the detailed structure of the pixel 100 which concerns on 5th Embodiment of this disclosure. It is sectional drawing which shows an example of the detailed structure of the pixel 100 which concerns on 6th Embodiment of this disclosure. It is a plane schematic diagram which shows an example of the detailed structure of the pixel 100 which concerns on 7th Embodiment of this disclosure. It is sectional drawing which shows an example of the detailed structure of the pixel 100 which concerns on 7th Embodiment of this disclosure. FIG. 1 is a schematic plan view (No. 1) showing an example of the detailed configuration of the pixel array unit 30 according to the seventh embodiment of the present disclosure. FIG. 2 is a schematic plan view (No. 2) showing an example of the detailed configuration of the pixel array unit 30 according to the seventh embodiment of the present disclosure. It is an equivalent circuit diagram of the pixel 100 which concerns on 8th Embodiment of this disclosure. It is a plane schematic diagram which shows an example of the detailed structure of the pixel 100 which concerns on 8th Embodiment of this disclosure. It is a plane schematic diagram which shows an example of the detailed structure of the pixel 100 which concerns on 9th Embodiment of this disclosure. It is sectional drawing which shows an example of the detailed structure of the pixel 100 which concerns on 9th Embodiment of this disclosure. It is a schematic diagram for demonstrating the manufacturing method of the pixel 100 which concerns on 10th Embodiment of this disclosure. It is a schematic diagram for demonstrating the shipping process of the image pickup apparatus 1 which concerns on 11th Embodiment of this disclosure. It is a block diagram (No. 1) which shows an example of the circuit block which concerns on 11th Embodiment of this disclosure. It is an equivalent circuit diagram which shows an example of the fuse cut circuit 52 which concerns on 11th Embodiment of this disclosure. It is a block diagram (No. 2) which shows an example of the circuit block which concerns on 11th Embodiment of this disclosure. It is explanatory drawing which shows an example of the schematic functional structure of the camera 700 to which the technique (the present technique) which concerns on this disclosure can be applied. It is a block diagram which shows an example of the schematic functional structure of the smartphone 900 to which the technique (the present technique) which concerns on this disclosure can be applied.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the following embodiments, the same parts are designated by the same reference numerals, so that overlapping description will be omitted.

Further, in the present specification and the drawings, a plurality of components having substantially the same or similar functional configurations may be distinguished by adding different numbers after the same reference numerals. However, if it is not necessary to particularly distinguish each of the plurality of components having substantially the same or similar functional configurations, only the same reference numerals are given. Further, similar components of different embodiments may be distinguished by adding different alphabets after the same reference numerals. However, if it is not necessary to distinguish each of the similar components, only the same reference numerals are given.

In addition, the drawings referred to in the following description are drawings for explaining and understanding one embodiment of the present disclosure, and for the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings are actually shown. May differ from. Further, the image pickup apparatus shown in the figure can be appropriately redesigned in consideration of the following description and known techniques. Further, in the description using the cross-sectional view of the image pickup device, the vertical direction of the laminated structure of the image pickup device corresponds to the relative direction when the light receiving surface on which the light incident on the image pickup device enters is facing down. It may differ from the vertical direction according to the actual gravitational acceleration.

Further, in the following description, a case where the embodiment of the present disclosure is applied to a back-illuminated image pickup apparatus will be described as an example. Therefore, in the image pickup apparatus, light is incident from the back surface side of the substrate. .. Therefore, in the following description, the front surface of the substrate is the surface facing the back surface when the side on which light is incident is the back surface.

Further, in the following circuit (electrical connection) description, unless otherwise specified, "electrically connected" means connecting a plurality of elements so that electricity (signal) is conducted. Means that. In addition, the term "electrically connected" in the following description includes not only the case of directly and electrically connecting a plurality of elements, but also indirectly and electrically through other elements. It shall also include the case of connecting to.

Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. The explanation will be given in the following order.
1. 1. Schematic configuration of the image pickup device 2. Background to the creation of the embodiment according to the present disclosure by the present inventor. First Embodiment
3.1 Equivalent circuit
3.2 Planar structure
3.3 Cross-sectional structure 4. Second embodiment 5. Third embodiment 6. Fourth embodiment 7. Fifth Embodiment
7.1 Planar structure
7.2 Cross-sectional structure 8. Sixth Embodiment 9. Seventh Embodiment
9.1 Planar structure
9.2 Cross-sectional structure
9.3 Planar structure of pixel array unit 30 10. Eighth embodiment
10.1 Equivalent circuit
10.2 Planar structure 11. Ninth embodiment
11.1 Planar structure
11.2 Cross-sectional structure 12. 10. The tenth embodiment 13. Eleventh Embodiment 14. Summary 15. Application example to camera 16. Application example to smartphone 17. supplement

<< 1. Outline configuration of image pickup device >>
First, with reference to FIG. 1, a schematic configuration of the image pickup apparatus 1 according to the embodiment of the present disclosure will be described. FIG. 1 is an explanatory diagram showing a plan configuration example of the image pickup apparatus 1 according to the embodiment of the present disclosure. As shown in FIG. 1, the image pickup apparatus 1 according to the embodiment of the present disclosure includes, for example, a pixel array unit 30 in which a plurality of pixels 100 are arranged in a matric manner on a semiconductor substrate 10 made of silicon, and the pixels. It has a peripheral circuit unit provided so as to surround the array unit 30. Further, the image pickup apparatus 1 includes a vertical drive circuit unit 32, a column signal processing circuit unit 34, a horizontal drive circuit unit 36, an output circuit unit 38, a control circuit unit 40, and the like as the peripheral circuit unit. The details of each block of the image pickup apparatus 1 will be described below.

(Pixel array unit 30)
The pixel array unit 30 has a plurality of pixels 100 arranged two-dimensionally in a matrix along the row direction and the column direction on the semiconductor substrate 10. Each pixel 100 has a photodiode (photoelectric conversion unit) (not shown) that performs photoelectric conversion on incident light to generate an electric charge, and a plurality of pixel transistors (for example, a MOS (Metal-Oxide-Semiconductor) transistor). (Not shown). The pixel transistor includes, for example, four MOS transistors such as a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor. Further, in the pixel array unit 30, a plurality of pixels 100 are arranged two-dimensionally according to, for example, a Bayer arrangement. Here, in the Bayer arrangement, pixels 100 that absorb light having a green wavelength (for example, a wavelength of 495 nm to 570 nm) and generate a charge are arranged in a checkered pattern, and the remaining portion has a red wavelength (for example, a wavelength of 620 nm or more). A pixel 100 that absorbs light having a wavelength of 750 nm and generates a charge and a pixel 100 that absorbs light having a blue wavelength (for example, a wavelength of 450 nm to 495 nm) and generates a charge are arranged alternately in a row. , An array pattern. The detailed structure of the pixel 100 will be described later.

(Vertical drive circuit unit 32)
The vertical drive circuit unit 32 is formed by, for example, a shift register, selects a pixel drive wiring 42, supplies a pulse for driving the pixel 100 to the selected pixel drive wiring 42, and drives the pixel 100 in row units. .. That is, the vertical drive circuit unit 32 selectively scans each pixel 100 of the pixel array unit 30 in the vertical direction (vertical direction in FIG. 1) in a row-by-row manner, and receives light from the photoelectric conversion unit (not shown) of each pixel 100. A pixel signal based on the signal charge generated according to the amount is supplied to the column signal processing circuit unit 34 described later through the vertical signal line 44.

(Column signal processing circuit unit 34)
The column signal processing circuit unit 34 is arranged for each column of the pixel 100, and performs signal processing such as noise removal for each pixel signal for the pixel signal output from the pixel 100 for one row. For example, the column signal processing circuit unit 34 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Degital) conversion in order to remove fixed pattern noise peculiar to pixels.

(Horizontal drive circuit unit 36)
The horizontal drive circuit unit 36 is formed by, for example, a shift register, and by sequentially outputting horizontal scan pulses, each of the above-mentioned column signal processing circuit units 34 is sequentially selected, and pixels from each of the column signal processing circuit units 34. The signal is output to the horizontal signal line 46.

(Output circuit unit 38)
The output circuit unit 38 performs signal processing on the pixel signals sequentially supplied from each of the column signal processing circuit units 34 described above through the horizontal signal line 46 and outputs the signals. The output circuit unit 38 may function as a functional unit for buffering, for example, or may perform processing such as black level adjustment, column variation correction, and various digital signal processing. Note that buffering refers to temporarily storing pixel signals in order to compensate for differences in processing speed and transfer speed when exchanging pixel signals. Further, the input / output terminal 48 is a terminal for exchanging signals with an external device.

(Control circuit unit 40)
The control circuit unit 40 receives an input clock and data instructing an operation mode or the like, and outputs data such as internal information of the image pickup apparatus 1. That is, the control circuit unit 40 is based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, and is a clock signal that serves as a reference for the operation of the vertical drive circuit unit 32, the column signal processing circuit unit 34, the horizontal drive circuit unit 36, and the like. Generate a control signal. Then, the control circuit unit 40 outputs the generated clock signal and control signal to the vertical drive circuit unit 32, the column signal processing circuit unit 34, the horizontal drive circuit unit 36, and the like.

<< 2. Background to the Inventor's Creation of the Embodiment According to the Disclosure >>
Next, before explaining the details of the embodiment according to the present disclosure, the background that led to the creation of the embodiment according to the present disclosure by the present inventor will be described.

As described above, a CMOS type solid-state image sensor that can be manufactured by the same process as the MOS integrated circuit can be applied to the image pickup device 1 as the pixel 100. The solid-state image sensor has a feature that an active structure having an amplification function can be easily created for each pixel 100 by the miniaturization technique associated with the CMOS process. Further, the solid-state image sensor has the same peripheral circuit units as the pixel array unit 30, such as a drive circuit for driving the pixel array unit 30 and a signal processing circuit for processing signals output from each pixel 100 of the pixel array unit 30. It has a feature that it can be integrated on a semiconductor substrate (chip) 10. Due to these characteristics, CMOS type solid-state image sensors are being actively developed.

Among such solid-state image sensors, there is a back-illuminated image sensor that is irradiated with light on the back surface of the semiconductor substrate 10. Conventionally, studies have been made on how to handle the excess charge overflowing from the photodiode when a large amount of light is applied to the pixel 100 as a solid-state image sensor, and the excess charge is discharged. Various structures have been proposed for this. When the excess charge flows out to the adjacent pixels 100, the adjacent pixels 100 generate an unintended pixel signal, so that the image as it should be cannot be captured. Such a phenomenon is called blooming.

For example, as a structure conventionally studied, there is a structure in which excess charge can be overflowed from under the gate of the transfer transistor that transfers the charge from the photodiode to the floating diffusion region to the floating diffusion region.

When such a structure is selected, in the manufacture of a solid-state image sensor, charges are transferred at high speed while accurately setting the potential of the potential barrier of the overflow path formed in the region under the gate of the transfer transistor to a desired state. Therefore, it is required to accurately control the impurity profile in the region under the gate of the transfer transistor. That is, according to the above structure, since the potential control of the potential barrier of the overflow path and the transfer design must be satisfied at the same time, the difficulty of manufacturing (mass production) becomes high. Since it is difficult to accurately control and manufacture the impurity profile in the region under the gate of the transfer transistor, the potential of the potential barrier of the overflow path varies, and the saturation signal amount decreases or the saturation signal amount decreases depending on the pixel. It becomes difficult for excess charge to be discharged, which leads to a decrease in yield. In addition, according to the above structure, by giving priority to the potential control of the potential barrier of the overflow path, other characteristics of the pixel 100 may be deteriorated.

As another structure, for example, by forming an overflow path under the floating diffusion region to generate an excess charge in the film thickness direction of the semiconductor substrate 10, the overflow path is independent of the transfer design. A structure capable of controlling the potential of the potential barrier of the above can be mentioned. In this structure, in order to provide an overflow path, for example, an n-type semiconductor region-p-type semiconductor region-n-type semiconductor region is formed along the film thickness direction of the semiconductor substrate 10. However, even in this structure, it is difficult to accurately control the impurity profile in the region where the overflow path is provided, and it is difficult to avoid variations in the potential of the potential barrier of the overflow path. Therefore, even in the structure, the saturation signal amount is lowered and the yield is lowered.

Therefore, in view of the above situation, the present inventor provides an overflow path on the photodiode independently of the gate of the transfer transistor, and further, individually by biasing to apply the potential of the potential barrier of the overflow path. We have created a structure of pixels 100 that can be adjusted to. Further, in the embodiment of the present disclosure created by the present inventor, the saturation signal amount is measured in advance for each image pickup device 1, wafer, or lot, and the bias value to be applied is determined based on the measurement result. By doing so, the bias applied to the overflow path can be determined in consideration of the variation in the potential of the potential barrier of the overflow path. In the embodiment of the present disclosure created by the present inventor as described above, the saturation signal amount decreases or the excess charge becomes difficult to be discharged due to the variation in the potential of the potential barrier of the overflow path, and the yield decreases. Can be avoided. In addition, according to the above structure, since the overflow path is provided on the photodiode independently of the gate of the transfer transistor, it is possible to improve other characteristics of the pixel 100. Hereinafter, the details of the embodiments of the present disclosure created by the present inventor will be sequentially described.

<< 3. First Embodiment >>
<3.1 Equivalent circuit>
First, with reference to FIG. 2, the equivalent circuit of the pixel 100 according to the first embodiment of the present disclosure created by the present inventor will be described. FIG. 2 is an equivalent circuit diagram of the pixel 100 according to the present embodiment.

As shown in FIG. 2, the pixel 100 has a photodiode PD as a photoelectric conversion element (photoelectric conversion unit) that converts light into electric charges, and a charge discharge transistor OF. Further, the pixel 100 has a transfer transistor TG, a stray diffusion region FD, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL.

Specifically, as shown in FIG. 2, in the pixel 100, one of the source / drain of the charge discharge transistor OF is electrically connected to the photodiode PD that generates charge by receiving light. Further, the other of the source / drain of the charge discharge transistor OF is electrically connected to the power supply circuit (power supply potential VDD). Then, the charge discharge transistor OF can discharge excess charge from the photodiode PD to the power supply circuit (power supply potential VDD) according to the voltage applied to its own gate.

Further, as shown in FIG. 2, in the pixel 100, one of the source / drain of the transfer transistor TG is electrically connected to the photodiode PD, and the other of the source / drain of the transfer transistor TG is the floating diffusion region FD. Is electrically connected to. Then, the transfer transistor TG becomes conductive according to the voltage applied to its own gate, and the electric charge generated by the photodiode PD can be transferred to the stray diffusion region FD.

Further, the floating diffusion region FD is electrically connected to the gate of the amplification transistor AMP that converts the electric charge into a voltage and outputs it as a signal. Further, one of the source / drain of the amplification transistor AMP is electrically connected to one of the source / drain of the selection transistor that outputs the signal obtained by conversion to the signal line according to the selection signal. Further, the other of the source / drain of the amplification transistor AMP is electrically connected to the power supply circuit (power supply potential VDD).

Further, the other of the source / drain of the selection transistor SEL is electrically connected to the signal line that transmits the converted voltage as a signal, and is further electrically connected to the column signal processing circuit unit 34 described above. Further, the gate of the selection transistor SEL is electrically connected to a selection line (not shown) for selecting a line for outputting a signal, and further electrically connected to the above-mentioned vertical drive circuit unit 32. That is, the electric charge accumulated in the floating diffusion region FD is converted into a voltage by the amplification transistor AMP2 under the control of the selection transistor SEL, and is output to the signal line.

Further, as shown in FIG. 2, the stray diffusion region FD is electrically connected to one of the drain / source of the reset transistor RST for resetting the accumulated charge. The gate of the reset transistor RST is electrically connected to a reset signal line (not shown), and further electrically connected to the above-mentioned vertical drive circuit unit 32. Further, the other of the drain / source of the reset transistor RST is electrically connected to the power supply circuit (power supply potential VDD). Then, the reset transistor RST becomes conductive according to the voltage applied to its own gate, and the electric charge accumulated in the stray diffusion region FD can be reset (discharged to the power supply circuit (power supply potential VDD)).

The equivalent circuit of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 2, and may include, for example, other elements and the like, and is not particularly limited.

<3.2 Planar structure>
First, an example of the planar structure of the pixel 100 according to the first embodiment of the present disclosure will be described with reference to FIG. FIG. 3 is a schematic plan view showing an example of the detailed configuration of the pixel 100 according to the present embodiment, and is a view when the pixel 100 is viewed from above the surface of the semiconductor substrate 102.

As shown in FIG. 3, in the pixel 100, a pixel separation portion 104 made of an insulating film embedded in a groove provided in the semiconductor substrate 102 is provided so as to surround the outer periphery of the pixel 100. Further, the p-type (second conductive type) semiconductor substrate 102 surrounded by the pixel separation portion 104 is provided with an n-type (first conductive type) semiconductor region 106. Further, on the semiconductor substrate 102, a charge discharge transistor OF, a transfer transistor TG, a reset transistor RST, an amplification transistor AMP, and gate electrodes 108o, 108t, 108r of the selection transistor SEL are placed on the semiconductor substrate 102 via an oxide insulating film (not shown). 108a and 108s are provided.

Specifically, as shown in FIG. 3, the gate electrodes 108t and 108r of the transfer transistor TG and the reset transistor RST are arranged along the vertical direction in the figure, and the gate electrode 108t and the gate electrode 108r are arranged in a plan view. The n-type semiconductor region located between them functions as a floating diffusion region FD for accumulating charges. Further, the gate electrodes 108o, 108a, 108s of the charge discharge transistor OF, the amplification transistor AMP, and the selection transistor SEL are arranged along the vertical direction in the figure, and are sandwiched between the gate electrodes 108o, 108a, 108s in a plan view. The n-type semiconductor region is used as a source or drain of these transistors. Further, the p-type semiconductor substrate 102 surrounded by the pixel separation portion 104 is provided with a contact 140 for setting the p-well region (not shown) of the p-type semiconductor substrate to a predetermined potential.

The planar structure of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 3, and may include, for example, other elements and the like, and is not particularly limited.

<3.3 Cross-sectional structure>
Next, with reference to FIG. 4, an example of the cross-sectional structure of the pixel 100 according to the first embodiment of the present disclosure will be described. FIG. 4 is a schematic cross-sectional view showing an example of the detailed configuration of the pixel 100 according to the present embodiment. In detail, FIG. 4 is a cross-sectional view when the pixel 100 is cut along the line AA'of FIG. 3, and in detail, the lower side in FIG. 4 is the back surface side of the semiconductor substrate 102. The upper side of 4 is the surface side of the semiconductor substrate 102.

First, as shown in FIG. 4, the pixel 100 has a semiconductor substrate 102 made of a silicon substrate or the like. Specifically, a p-type semiconductor region (not shown) and an n-type semiconductor region (not shown) are laminated in the semiconductor substrate 102, whereby a photodiode (PD) (photoelectric conversion unit) is formed in the semiconductor substrate 102. 110 is formed. The photodiode 110 performs photoelectric conversion by light incident from the back surface of the semiconductor substrate 102 to generate electric charges. Further, a p-type separation layer 150 is provided above the photodiode 110. The p-type separation layer 150 has a function of separating the n-type semiconductor region (not shown) of the photodiode 110 and the n-type diffusion region (not shown) of the pixel transistor.

Next, the lower side in FIG. 4, that is, the back side of the semiconductor substrate 102 will be described. Above the back surface of the semiconductor substrate 102, an on-chip lens 120 made of a styrene resin, an acrylic resin, a styrene-acrylic copolymer resin, a siloxane resin, or the like, which is incident with light, is provided.

Below the on-chip lens 120, for example, hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TIO ₂ ), silicon oxide, etc., or an antireflection film 122 made of a laminate thereof is formed. It will be provided. Further, another film may be laminated on the antireflection film 122.

Further, although not shown in FIG. 4, a pixel separation unit 104 is provided so as to surround the pixel 100 so as to penetrate the semiconductor substrate 102 and prevent incident light from entering the adjacent pixel 100. ing. The pixel separation portion 104 is composed of, for example, a trench penetrating from the back surface to the front surface or from the front surface to the back surface of the semiconductor substrate 200, and an insulating film such as silicon oxide embedded in the trench.

Next, the upper side in FIG. 4, that is, the front side of the semiconductor substrate 102 will be described. Adjacent to the photodiode 110, a gate electrode (transfer gate) 108t of the transfer transistor TG is provided on the surface of the semiconductor substrate 102. The gate electrode 108t is, for example, made of a polysilicon film and has an embedded portion 118 embedded in an n-type semiconductor region 106 of a semiconductor substrate 102 via an insulating film 114 and a p-type semiconductor region (not shown). It has a type gate electrode structure. Further, a floating diffusion region (FD) (charge storage portion) (see FIG. 3) is formed in the n-type semiconductor region 106 near the surface of the semiconductor substrate 102 close to the gate electrode 108t of the transfer transistor TG, and the transfer transistor is formed. The electric charge generated by the photodiode 110 can be transferred to the stray diffusion region (FD) according to the voltage applied to the gate electrode 108t of the TG.

Further, adjacent to the photodiode 110, a gate electrode (overflow gate) 108o of the charge discharge transistor OF is provided on the surface of the semiconductor substrate 102. The gate electrode 108o is a vertical type having, for example, a polysilicon film and having an embedded portion 118 embedded in an n-type semiconductor region 106 of a semiconductor substrate 102 via an insulating film 114 and a p-type semiconductor region (not shown). It has a gate electrode structure. Further, the n-type semiconductor region 106 near the surface of the semiconductor substrate 102 close to the gate electrode 108 of the charge discharge transistor TG is electrically connected to a power supply circuit (not shown) (see FIG. 3). Therefore, an overflow path for discharging the excess charge generated by the photodiode 110 is formed around the gate electrode 108o of the charge discharge transistor OF, and the surplus charge is discharged to the power supply circuit through the overflow path. Will be done.

In the present embodiment, the potential of the potential barrier of the overflow path can be adjusted by a negative bias (for example, about −1.2V) applied to the gate electrode 108o. Therefore, the gate electrode 108o is electrically connected to a dedicated power source (a power source capable of generating a negative bias) (adjustment circuit) (not shown) (not shown), which is not shown, and a negative bias is applied. In the present embodiment, by having such a structure, it is possible to adjust the bias applied to the gate electrode 108o even when the potential of the potential barrier of the overflow path varies depending on the quality of the pixel 100. Therefore, the potential of the potential barrier of the overflow path can be controlled to the optimum state.

Further, in the present embodiment, by forming the gate electrode 108t of the transfer transistor TG into a vertical gate electrode structure, charge transfer can be made faster. Further, in the present embodiment, by forming the gate electrode 108o of the charge discharge transistor OF into a vertical gate electrode structure, the potential of the potential barrier can be accurately measured even if the overflow path is located deep in the semiconductor substrate 102. It becomes possible to adjust.

The cross-sectional structure of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 4, and may include, for example, other elements and the like, and is not particularly limited.

<< 4. Second embodiment >>
Next, with reference to FIG. 5, an example of the cross-sectional structure of the pixel 100 according to the second embodiment of the present disclosure will be described. FIG. 5 is a schematic cross-sectional view showing an example of the detailed configuration of the pixel 100 according to the present embodiment. In detail, FIG. 5 is a cross-sectional view when the pixel 100 is cut along the line AA'of FIG. 3, and in detail, the lower side in FIG. 5 is the back surface side of the semiconductor substrate 102. The upper side of 5 is the surface side of the semiconductor substrate 102.

In the present embodiment, unlike the first embodiment described above, the gate electrode (overflow gate) 108o of the charge discharge transistor OF is provided on the surface of the semiconductor substrate 102. The gate electrode 108o is made of, for example, a polysilicon film and has a flat plate type gate electrode structure laminated on a p-type semiconductor region 116 in a semiconductor substrate 102 via an insulating film 114. In the present embodiment, since the gate electrode 108o of the charge discharge transistor OF has a flat plate type gate electrode structure, the interface in contact with the insulating film 114 or the like has a simple structure, so that the charge is captured at the interface. The phenomenon is less likely to occur, and the generation of dark current can be suppressed.

The cross-sectional structure of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 5, and may include, for example, other elements and the like, and is not particularly limited.

<< 5. Third Embodiment >>
Next, with reference to FIG. 6, an example of the cross-sectional structure of the pixel 100 according to the third embodiment of the present disclosure will be described. FIG. 6 is a schematic cross-sectional view showing an example of the detailed configuration of the pixel 100 according to the present embodiment. In detail, FIG. 6 is a cross-sectional view when the pixel 100 is cut along the line AA'of FIG. 3, and in detail, the lower side in FIG. 6 is the back surface side of the semiconductor substrate 102. The upper side of 6 is the surface side of the semiconductor substrate 102.

In the present embodiment, unlike the first embodiment described above, the gate electrode (transfer gate) 108t of the transfer transistor TG is provided on the surface of the semiconductor substrate 102. The gate electrode 108t is made of, for example, a polysilicon film and has a flat plate type gate electrode structure laminated on a p-type semiconductor region 116 in a semiconductor substrate 102 via an insulating film 114. In the present embodiment, since the gate electrode 108t of the transfer transistor OF has a flat plate type gate electrode structure, the interface in contact with the insulating film 114 or the like has a simple structure, so that charges are captured at the interface and the like. Is less likely to occur, and the generation of dark current can be suppressed.

The cross-sectional structure of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 6, and may include, for example, other elements and the like, and is not particularly limited.

<< 6. Fourth Embodiment >>
Next, with reference to FIG. 7, an example of the cross-sectional structure of the pixel 100 according to the fourth embodiment of the present disclosure will be described. FIG. 7 is a schematic cross-sectional view showing an example of the detailed configuration of the pixel 100 according to the present embodiment. In detail, FIG. 7 is a cross-sectional view when the pixel 100 is cut along the line AA'of FIG. 3, and in detail, the lower side in FIG. 7 is the back surface side of the semiconductor substrate 102. The upper side of 7 is the front side of the semiconductor substrate 102.

In the present embodiment, unlike the first embodiment described above, the gate electrode (overflow gate) 108o of the charge discharge transistor OF and the gate electrode (transfer gate) 108t of the transfer transistor TG are provided on the surface of the semiconductor substrate 102. Has been done. Specifically, the gate electrodes 108o and 108t are made of, for example, a polysilicon film, and have a flat plate type gate electrode structure laminated on the p-type semiconductor region 116 in the semiconductor substrate 102 via the insulating film 114. In the present embodiment, unlike the first embodiment, since the vertical gate electrode structure is not formed, the number of steps is small and the increase in manufacturing cost can be suppressed.

The cross-sectional structure of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 7, and may include, for example, other elements and the like, and is not particularly limited.

<< 7. Fifth Embodiment >>
<7.1 Planar structure>
First, with reference to FIG. 8, an example of the planar structure of the pixel 100 according to the fifth embodiment of the present disclosure will be described. FIG. 8 is a schematic plan view showing an example of the detailed configuration of the pixel 100 according to the present embodiment, and is a view when the pixel 100 is viewed from above the surface of the semiconductor substrate 102.

In the present embodiment, unlike the first embodiment, even if a positive bias is directly applied to the n-type semiconductor region 106 in which the overflow path is formed to adjust the potential of the potential barrier of the overflow path. good. Therefore, in the present embodiment, unlike the first embodiment, the gate electrode 108o of the charge discharge transistor OF is not provided, and the contact 130 that is directly electrically connected to the semiconductor region is provided. The contact 130 can be formed of, for example, polysilicon.

The planar structure of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 8, and may include, for example, other elements and the like, and is not particularly limited.

<7.2 Cross-sectional structure>
Next, with reference to FIG. 9, an example of the cross-sectional structure of the pixel 100 according to the fifth embodiment of the present disclosure will be described. FIG. 9 is a schematic cross-sectional view showing an example of the detailed configuration of the pixel 100 according to the present embodiment. In detail, FIG. 9 is a cross-sectional view when the pixel 100 is cut along the line BB'of FIG. 8, and in detail, the lower side in FIG. 9 is the back surface side of the semiconductor substrate 102. The upper side of 9 is the front side of the semiconductor substrate 102.

In the present embodiment, the n-type semiconductor region 106 is provided in the vicinity of the surface of the semiconductor substrate 102 adjacent to the photodiode 110, and the contact 130 electrically connected to the n-type semiconductor region 106 is provided. .. An overflow path for discharging the excess charge generated by the photodiode 110 is formed in the n-type semiconductor region 106 electrically connected to the contact 130, and the excess charge is supplied as a power source through the overflow path. It will be discharged to the circuit.

In this embodiment, the potential of the overflow path potential barrier can be adjusted by applying a positive bias through the contact 130. Therefore, the contact 130 is electrically connected to a dedicated power source (a power source capable of generating a positive bias) (adjustment circuit) (not shown) (not shown), which is not shown, and a positive bias is applied. In the present embodiment, by having such a structure, the bias to be applied can be adjusted even when the potential of the potential barrier of the overflow path varies depending on the workmanship of the pixel 100. Therefore, the overflow path can be adjusted. The potential of the potential barrier can be controlled to the optimum state. Further, in the present embodiment, since a positive bias is applied to the contact 130, the power supply connected to the contact 130 has a simpler configuration than a negative bias power supply that requires a complicated configuration. Can be a power source. As a result, according to the present embodiment, the image pickup device 1 can be miniaturized and the increase in manufacturing cost can be suppressed.

The cross-sectional structure of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 9, and may include, for example, other elements and the like, and is not particularly limited.

<< 8. Sixth Embodiment >>
Next, with reference to FIG. 10, an example of the cross-sectional structure of the pixel 100 according to the sixth embodiment of the present disclosure will be described. FIG. 10 is a schematic cross-sectional view showing an example of the detailed configuration of the pixel 100 according to the present embodiment. In detail, FIG. 10 is a cross-sectional view when the pixel 100 is cut along the line BB'of FIG. 8, and in detail, the lower side in FIG. 10 is the back surface side of the semiconductor substrate 102. The upper side of 10 is the surface side of the semiconductor substrate 102.

In the present embodiment, unlike the fifth embodiment described above, the gate electrode (transfer gate) 108t of the transfer transistor TG is provided on the surface of the semiconductor substrate 102. The gate electrode 108t is made of, for example, a polysilicon film and has a flat plate type gate electrode structure laminated on a p-type semiconductor region 116 in a semiconductor substrate 102 via an insulating film 114. In the present embodiment, since the gate electrode 108t of the transfer transistor OF has a flat plate type gate electrode structure, the interface in contact with the insulating film 114 or the like has a simple structure, so that charges are captured at the interface and the like. Is less likely to occur, and the generation of dark current can be suppressed. Further, in the present embodiment, unlike the fifth embodiment, since the vertical gate electrode structure is not formed, the number of steps is small and the increase in manufacturing cost can be suppressed.

The cross-sectional structure of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 10, and may include, for example, other elements and the like, and is not particularly limited.

<< 9. Seventh Embodiment >>
<9.1 Planar structure>
First, with reference to FIG. 11, an example of the planar structure of the pixel 100 according to the seventh embodiment of the present disclosure will be described. FIG. 11 is a schematic plan view showing an example of the detailed configuration of the pixel 100 according to the present embodiment, and is a view when the pixel 100 is viewed from above the surface of the semiconductor substrate 102.

As shown in FIG. 11, in the pixel 100, a pixel separation portion 104 made of an insulating film embedded in a groove provided in the semiconductor substrate 102 is provided so as to surround the outer periphery of the pixel 100. Further, a photodiode 110 is provided on the semiconductor substrate 102 surrounded by the pixel separation unit 104. Further, in the lower left corner of the semiconductor substrate 102 surrounded by the pixel separation portion 104, a gate electrode 108t of the transfer transistor TG and a floating diffusion region FD adjacent to the gate electrode 108t to store electric charges are provided. ing. Further, a contact 130 is provided in the upper right corner of the figure of the photodiode 110. Further, on the outer periphery of the pixel 100, a reset transistor RST, an amplification transistor AMP, and gate electrodes 108r, 108a, 108s of the selection transistor SEL are provided on the semiconductor substrate 102 via an oxide insulating film (not shown). There is.

The planar structure of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 11, and may include, for example, other elements and the like, and is not particularly limited.

<9.2 Cross-sectional structure>
Next, with reference to FIG. 12, an example of the cross-sectional structure of the pixel 100 according to the seventh embodiment of the present disclosure will be described. FIG. 12 is a schematic cross-sectional view showing an example of the detailed configuration of the pixel 100 according to the present embodiment. In detail, FIG. 12 is a cross-sectional view when the pixel 100 is cut along the line C—C ′ of FIG. 11, and in detail, the lower side in FIG. 12 is the back surface side of the semiconductor substrate 102. The upper side of 12 is the front side of the semiconductor substrate 102.

In the present embodiment, the n-type semiconductor region 106 is provided in the vicinity of the surface of the semiconductor substrate 102 adjacent to the photodiode 110, and the contact 130 electrically connected to the n-type semiconductor region 106 is provided. .. An overflow path for discharging the excess charge generated by the photodiode 110 is formed in the n-type semiconductor region 106 electrically connected to the contact 130, and the excess charge is supplied as a power source through the overflow path. It will be discharged to the circuit.

In this embodiment, the potential of the overflow path potential barrier can be adjusted by applying a positive bias through the contact 130. Therefore, the contact 130 is electrically connected to a dedicated power source (a power source capable of generating a positive bias) (adjustment circuit) (not shown) (not shown), which is not shown, and a positive bias is applied. In the present embodiment, by having such a structure, the bias to be applied can be adjusted even when the potential of the potential barrier of the overflow path varies depending on the workmanship of the pixel 100. Therefore, the overflow path can be adjusted. The potential of the potential barrier can be controlled to the optimum state. Further, in the present embodiment, since a positive bias is applied to the contact 130, the power supply connected to the contact 130 has a simpler configuration than a negative bias power supply that requires a complicated configuration. Can be a power source. As a result, according to the present embodiment, the image pickup device 1 can be miniaturized and the increase in manufacturing cost can be suppressed.

The cross-sectional structure of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 12, and may include, for example, other elements and the like, and is not particularly limited.

<9.3 Planar structure of pixel array unit 30>
Next, an example of the planar structure of the pixel array unit 30 according to the seventh embodiment of the present disclosure will be described with reference to FIGS. 13 and 14. 13 and 14 are schematic plan views showing an example of the detailed configuration of the pixel array unit 30 according to the present embodiment, and are views when the pixels 100 are viewed from above the surface of the semiconductor substrate 102.

For example, as shown in FIG. 13, in the pixel array unit 30 according to the present embodiment, the pixels 100 having the planar structure shown in FIG. 11 may be arranged in a matrix in a 2 × 2 arrangement. At this time, it is preferable to arrange the pixels 100 so that the floating diffusion region FD is located at the center of the pixel array unit 30. By doing so, each pixel 100 can share one floating diffusion region FD. Further, in the example shown in FIG. 13, the reset transistor RST, the amplification transistor AMP, and the gate electrodes 108r, 108a, 108s of the selection transistor SEL are provided on the outer periphery of the pixel array unit 30, and each pixel 100 is provided with one each. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL may be shared.

Further, as shown in FIG. 14, in the pixel array unit 30 according to the present embodiment, two configurations shown in FIG. 13 can be arranged, that is, even if the pixels 100 are arranged in a matrix in a 2 × 4 arrangement. good. Also in the example of FIG. 14, it is preferable to arrange the floating diffusion region FD so as to be located at the center of the four pixels 100, and by doing so, the four pixels 100 share one floating diffusion region FD. can do. Further, in the example shown in FIG. 14, the reset transistor RST, the amplification transistor AMP, and the gate electrodes 108r, 108a, 108s of the selection transistor SEL are provided on the outer periphery of the pixel array unit 30. By doing so, the eight pixels 100 may share one reset transistor RST, an amplification transistor AMP, and a selection transistor SEL.

The planar structure of the pixel array unit 30 according to the present embodiment is not limited to the examples shown in FIGS. 13 and 14, and for example, other numbers of pixels 100 may be arranged, and the plan structure is particularly limited. It's not a thing.

<< 10. Eighth Embodiment >>
<10.1 Equivalent circuit>
First, the equivalent circuit of the pixel 100 according to the eighth embodiment of the present disclosure will be described with reference to FIG. FIG. 15 is an equivalent circuit diagram of the pixel 100 according to the present embodiment.

As shown in FIG. 15, in the pixel 100 according to the present embodiment, the charge discharge transistor OF may be electrically connected to the capacitor FC instead of the power supply circuit. That is, the excess charge may be discharged to the capacitor FC electrically connected to the overflow path. Further, the capacitor FC may discharge the accumulated charge to the power supply circuit by being controlled by the electrically connected capacitor control transistor FCG. Further, in the present embodiment, the pixel 100 also has a capacitor connection transistor FDG that connects the floating diffusion region FD and the capacitor FC.

The equivalent circuit of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 15, and may include, for example, other elements and the like, and is not particularly limited.

<10.2 Planar structure>
Next, with reference to FIG. 16, an example of the planar structure of the pixel 100 according to the eighth embodiment of the present disclosure will be described. FIG. 16 is a schematic plan view showing an example of the detailed configuration of the pixel 100 according to the present embodiment, and is a view when the pixel 100 is viewed from above the surface of the semiconductor substrate 102.

As shown in FIG. 16, in the pixel 100 according to the present embodiment, the pixel separation unit 104 is provided so as to surround the outer periphery of the pixel 100. Further, on the semiconductor substrate 102 surrounded by the pixel separation unit 104, a charge discharge transistor OF, a transfer transistor TG, a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and a capacitor control are performed via an insulating film (not shown). The gate electrodes 108o, 108t, 108r, 108a, 108s, 108c, 108d of the transistor FCG and the capacitor connection transistor FDG are provided.

The planar structure of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 16, and may include, for example, other elements and the like, and is not particularly limited.

Further, since the cross-sectional view when the pixel 100 is cut along the DD'line of FIG. 16 is the same as that of FIG. 5, the description of the cross-sectional structure is omitted here. Although not shown in the present embodiment, it is preferable that the interface of the region where the overflow path is formed is pinned by the p-type semiconductor region.

<< 11. Ninth embodiment >>
<11.1 Planar structure>
First, with reference to FIG. 17, an example of the planar structure of the pixel 100 according to the ninth embodiment of the present disclosure will be described. FIG. 17 is a schematic plan view showing an example of the detailed configuration of the pixel 100 according to the present embodiment, and is a view when the pixel 100 is viewed from above the surface of the semiconductor substrate 102.

In this embodiment, the overflow path may be electrically connected to a power supply circuit connected to the reset transistor RST. Specifically, as shown in FIG. 17, the gate electrodes 108t, 108r, and 108o of the transfer transistor TG, the reset transistor RST, and the charge discharge transistor OF are arranged along the vertical direction in the figure, and the gate electrodes are arranged in a plan view. The n-type semiconductor region 106 located between the 108r and the gate electrode 108o is connected to the power supply circuit, and excess charge is discharged through the region.

The planar structure of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 17, and may include, for example, other elements and the like, and is not particularly limited.

<11.2 Cross-sectional structure>
Next, with reference to FIG. 18, an example of the cross-sectional structure of the pixel 100 according to the ninth embodiment of the present disclosure will be described. FIG. 18 is a schematic cross-sectional view showing an example of the detailed configuration of the pixel 100 according to the present embodiment. In detail, FIG. 18 is a cross-sectional view when the pixel 100 is cut along the line EE of FIG. 17, and in detail, the lower side in FIG. 18 is the back surface side of the semiconductor substrate 102. The upper side of 18 is the surface side of the semiconductor substrate 102.

In the present embodiment, as shown in FIG. 18, the gate electrode (overflow gate) 108o of the charge discharge transistor OF has a flat plate type gate electrode structure. In the present embodiment, since the gate electrode 108o of the charge discharge transistor OF has a flat plate type gate electrode structure, the interface in contact with the insulating film 114 or the like has a simple structure, so that the charge is captured at the interface. The phenomenon is less likely to occur, and the generation of dark current can be suppressed. Further, in the present embodiment, since the vertical gate electrode structure is not formed, the number of steps is small and the increase in manufacturing cost can be suppressed.

The cross-sectional structure of the pixel 100 according to the present embodiment is not limited to the example shown in FIG. 18, and may include, for example, other elements and the like, and is not particularly limited.

<< 12. Tenth Embodiment >>
Next, with reference to FIG. 19, a method of manufacturing the pixel 100 according to the embodiment of the present disclosure will be described. FIG. 19 is a schematic diagram for explaining a method of manufacturing the pixel 100 according to the present embodiment. It corresponds to the cross section of the pixel 100 at each stage in the manufacturing method.

First, as shown in the upper left of FIG. 19, a part of the semiconductor substrate 102 is covered with a resist mask, and ions are implanted into a predetermined region in the semiconductor substrate 102 to form the photodiode 110.

Next, as shown in the upper right of FIG. 19, a p-type impurity is ion-implanted into a predetermined region of the semiconductor substrate 102 using a resist mask to form the p-type separation layer 150.

Next, as shown in the lower left of FIG. 19, an n-type impurity is ion-implanted using a resist mask to form an n-type semiconductor region 106.

Further, as shown in the lower right of FIG. 19, after forming a groove on the surface of the semiconductor substrate 102 and forming a p-type semiconductor region (not shown) or an insulating film 114 (not shown in FIG. 19) in the groove. By forming a polysilicon film, a gate electrode 108 having a vertical gate structure is formed.

As described above, the pixel 100 according to the embodiment of the present disclosure can be easily manufactured by using the manufacturing process of the existing semiconductor device.

<< 13. Eleventh Embodiment >>
By the way, the image pickup apparatus according to the embodiment of the present disclosure is shipped as a product through a plurality of steps shown in FIG. 20, which is a schematic diagram for explaining the shipping process of the image pickup apparatus 1 according to the present embodiment. Specifically, first, after forming the semiconductor element described with reference to FIG. 19, the electrical characteristics are tested in the form of the wafer (electrical characteristic test step). Wafers judged to be non-defective in the electrical property test process will be sent to the next process. Next, after a dicing step of cutting the wafer for each chip and a packaging step of enclosing the chips in a package, the electrical characteristics are tested again in the form of a package (electrical property test step). Then, the image pickup device 1 determined to be a non-defective product will be shipped.

In the present embodiment, as described above, in order to realize that the potential adjustment of the electronic barrier of the overflow path is optimized according to the performance of each image pickup apparatus 1, the pixels 100 are saturated in advance before shipment. The signal amount is measured, and the bias applied to the overflow path is adjusted based on the measurement result. Specifically, in the present embodiment, in the electrical property test step in the form of the wafer as it is, or in the electrical property test step in the form of the package, the image pickup device 1 enclosed in each wafer, each chip, or in the package. The saturation signal amount is measured by irradiating the image pickup device 1 light for each lot or each lot. Then, the value of the bias to be applied is determined based on the measured saturation signal amount with reference to the calibration curve showing the relationship between the saturation signal amount and the bias obtained in advance. Then, in the present embodiment, the determined bias value is stored in the image pickup apparatus 1, and the bias applied to the overflow path by the adjustment circuit is adjusted according to the stored value.

The details of the adjustment circuit will be described with reference to FIGS. 21 to 23. 21 and 23 are block diagrams showing an example of a circuit block according to the present embodiment. Further, FIG. 22 is an equivalent circuit diagram showing an example of the fuse cut circuit 52 according to the present embodiment.

For example, in the present embodiment, the image pickup apparatus 1 has a circuit block as shown in FIG. 21 to hold a bias determined based on the measured saturation signal amount, and the held bias applies a bias to the overflow path. To adjust. As shown in FIG. 21, the image pickup apparatus 1 can have a bias setting information holding unit 50 and a fuse cut circuit 52. The bias setting information holding unit 50 has an OTP (One Time Programmable) circuit, and can store the determined bias value. Further, as shown in FIG. 22, the fuse cut circuit 52 is a circuit composed of a resistor and a switch, and by selecting a combination of resistors to be used according to the determined bias value, each pixel 100 ( The bias applied to the overflow path of the pixel array unit 30) can be adjusted.

Further, in the present embodiment, the image pickup apparatus 1 has a circuit block as shown in FIG. 23 to hold a bias determined based on the measured saturation signal amount, and the held bias applies a bias to the overflow path. May be adjusted. As shown in FIG. 23, the image pickup apparatus 1 may have a logic gate circuit 54 instead of the fuse cut circuit 52. The logic gate circuit 54 has a built-in logic circuit, and a bias applied to the overflow path of each pixel 100 (pixel array unit 30) by outputting a predetermined signal from the logic circuit according to the determined bias value. Can be adjusted.

<< 14. Summary >>
As described above, in each embodiment of the present disclosure, an overflow path is provided on the photodiode PD independently of the gate electrode 108t of the transfer transistor TR, and a bias applied to the overflow path is further applied by the adjustment circuit. By applying, the potential of the potential barrier of the overflow path PD can be individually adjusted. Further, in each embodiment of the present disclosure, the saturation signal amount is measured in advance for each image pickup device 1, wafer, or lot, and the bias value to be applied is determined based on the measurement result, thereby overflowing. The bias applied to the overflow path can be determined in consideration of the variation in the potential of the potential barrier of the path. According to each of the embodiments of the present disclosure, the variation in the potential of the potential barrier of the overflow path reduces the amount of saturation signal or makes it difficult for excess charge to be discharged, resulting in a decrease in yield. Can be avoided. In addition, according to each embodiment of the present disclosure, it is possible to improve other characteristics of the pixel 100 by providing an overflow path on the photodiode, independent of the gate of the transfer transistor.

In the above-described embodiment of the present disclosure, the case where it is applied to the back-illuminated CMOS image sensor structure has been described, but the embodiment of the present disclosure is not limited to this, and is applied to other structures. May be good.

In the above-described embodiment of the present disclosure, the pixel 100 in which the first conductive type is n-type, the second conductive type is p-type, and electrons are used as signal charges has been described. The morphology is not limited to such examples. For example, this embodiment can be applied to a pixel 100 in which the first conductive type is p-type, the second conductive type is n-type, and holes are used as signal charges.

Further, in the above-described embodiment of the present disclosure, the semiconductor substrate 102 does not necessarily have to be a silicon substrate, and may be another substrate (for example, an SOI (Silicon On Insulator) substrate, a SiGe substrate, or the like). Further, the semiconductor substrate 102 may have a semiconductor structure or the like formed on such various substrates.

Further, the image pickup device 1 according to the embodiment of the present disclosure is not limited to the image pickup device that detects the distribution of the incident light amount of visible light and captures the image as an image. For example, in this embodiment, an image pickup device that captures the distribution of incident amounts of infrared rays, X-rays, particles, etc. as an image, and a fingerprint that detects the distribution of other physical quantities such as pressure and capacitance and captures images as an image. It can be applied to an image pickup device (physical quantity distribution detection device) such as a detection sensor.

Further, the image pickup apparatus 1 according to the embodiment of the present disclosure can be manufactured by using the methods, devices, and conditions used for manufacturing a general semiconductor device. That is, the image pickup apparatus 1 according to the present embodiment can be manufactured by using the manufacturing process of the existing semiconductor device.

Examples of the above-mentioned manufacturing method include a PVD (Physical Vapor Deposition) method, a CVD (Chemical Vapor Deposition) method, and an ALD (Atomic Layer Deposition) method. The PVD method includes a vacuum vapor deposition method, an EB (electron beam) vapor deposition method, various sputtering methods (magnetron sputtering method, RF (Radio Frequency) -DC (Direct Current) combined bias sputtering method, and ECR (Electron Cyclotron Precision) sputtering method. , Opposed target sputtering method, high frequency sputtering method, etc.), ion plating method, laser ablation method, molecular beam epitaxy method (MBE (Molecular Beam Epitaxy) method), laser transfer method. Examples of the CVD method include a plasma CVD method, a thermal CVD method, an organic metal (MO) CVD method, and an optical CVD method. Further, as other methods, electrolytic plating method, electroless plating method, spin coating method; immersion method; casting method; microcontact printing method; drop casting method; screen printing method, inkjet printing method, offset printing method, gravure printing. Various printing methods such as method and flexographic printing method; stamp method; spray method; air doctor coater method, blade coater method, rod coater method, knife coater method, squeeze coater method, reverse roll coater method, transfer roll coater method, gravure coater method. , Kiss coater method, cast coater method, spray coater method, slit orifice coater method, calendar coater method and various other coating methods can be mentioned. Further, examples of the patterning method include shadow mask, laser transfer, chemical etching such as photolithography, and physical etching by ultraviolet rays or laser. In addition, examples of the flattening technique include a CMP (Chemical Mechanical Polishing) method, a laser flattening method, a reflow method, and the like.

In addition, each step in the manufacturing method according to the embodiment of the present disclosure described above does not necessarily have to be processed in the order described. For example, each step may be processed in an appropriately reordered manner. Further, the method used in each step does not necessarily have to be performed according to the described method, and may be performed by another method.

<< 15. Application example to camera >>
The technique according to the present disclosure (the present technique) can be further applied to various products. For example, the technique according to the present disclosure may be applied to a camera or the like. Therefore, with reference to FIG. 24, a configuration example of the camera 700 as an electronic device to which the present technology is applied will be described. FIG. 24 is an explanatory diagram showing an example of a schematic functional configuration of the camera 700 to which the technique according to the present disclosure (the present technique) can be applied.

As shown in FIG. 24, the camera 700 includes an image pickup device 702, an optical lens 710, a shutter mechanism 712, a drive circuit unit 714, and a signal processing circuit unit 716. The optical lens 710 forms an image of image light (incident light) from the subject on the image pickup surface of the image pickup apparatus 702. As a result, the signal charge is accumulated in the pixel 100 of the image pickup apparatus 702 for a certain period of time. The shutter mechanism 712 controls the light irradiation period and the light shielding period to the image pickup apparatus 702 by opening and closing. The drive circuit unit 714 supplies drive signals for controlling the signal transfer operation of the image pickup apparatus 702, the shutter operation of the shutter mechanism 712, and the like. That is, the image pickup apparatus 702 performs signal transfer based on the drive signal (timing signal) supplied from the drive circuit unit 714. The signal processing circuit unit 716 performs various signal processing. For example, the signal processing circuit unit 716 outputs the signal-processed video signal to a storage medium (not shown) such as a memory, or outputs it to a display unit (not shown).

<< 16. Application example to smartphone >>
The technique according to the present disclosure (the present technique) can be further applied to various products. For example, the technique according to the present disclosure may be applied to smartphones and the like. Therefore, with reference to FIG. 25, a configuration example of the smartphone 900 as an electronic device to which the present technology is applied will be described. FIG. 25 is a block diagram showing an example of a schematic functional configuration of a smartphone 900 to which the technique according to the present disclosure (the present technique) can be applied.

As shown in FIG. 18, the smartphone 900 includes a CPU (Central Processing Unit) 901, a ROM (Read Only Memory) 902, and a RAM (Random Access Memory) 903. The smartphone 900 also includes a storage device 904, a communication module 905, and a sensor module 907. Further, the smartphone 900 includes an image pickup device 909, a display device 910, a speaker 911, a microphone 912, an input device 913, and a bus 914. Further, the smartphone 900 may have a processing circuit such as a DSP (Digital Signal Processor) in place of or in combination with the CPU 901.

The CPU 901 functions as an arithmetic processing device and a control device, and controls all or a part of the operation in the smartphone 900 according to various programs recorded in the ROM 902, the RAM 903, the storage device 904, and the like. The ROM 902 stores programs, calculation parameters, and the like used by the CPU 901. The RAM 903 primary stores a program used in the execution of the CPU 901, parameters that appropriately change in the execution, and the like. The CPU 901, ROM 902, and RAM 903 are connected to each other by a bus 914. Further, the storage device 904 is a data storage device configured as an example of the storage unit of the smartphone 900. The storage device 904 is composed of, for example, a magnetic storage device such as an HDD (Hard Disk Drive), a semiconductor storage device, an optical storage device, and the like. The storage device 904 stores programs executed by the CPU 901, various data, various data acquired from the outside, and the like.

The communication module 905 is a communication interface composed of, for example, a communication device for connecting to the communication network 906. The communication module 905 may be, for example, a communication card for a wired or wireless LAN (Local Area Network), Bluetooth (registered trademark), WUSB (Wireless USB), or the like. Further, the communication module 905 may be a router for optical communication, a router for ADSL (Asymmetric Digital Subscriber Line), a modem for various communications, or the like. The communication module 905 transmits / receives signals and the like to and from the Internet and other communication devices by using a predetermined protocol such as TCP (Transmission Control Protocol) / IP (Internet Protocol). The communication network 906 connected to the communication module 905 is a network connected by wire or wirelessly, and is, for example, the Internet, a home LAN, infrared communication, satellite communication, or the like.

The sensor module 907 may be, for example, a motion sensor (eg, acceleration sensor, gyro sensor, geomagnetic sensor, etc.), a biometric information sensor (eg, pulse sensor, blood pressure sensor, fingerprint sensor, etc.), or a position sensor (eg, GNSS (Global Navigation)). Includes various sensors such as Satellite System) receivers, etc.).

The image pickup device 909 is provided on the surface of the smartphone 900 and can take an image of an object or the like located on the back side or the front side of the smartphone 900. Specifically, the image pickup device 909 is for an image pickup element (not shown) such as a CMOS (Complementary MOS) image sensor to which the technique (the present technique) according to the present disclosure can be applied, and a signal photoelectrically converted by the image pickup element. It can be configured to include a signal processing circuit (not shown) that performs image pickup signal processing. Further, the image pickup apparatus 909 further includes an optical system mechanism (not shown) composed of an image pickup lens, a zoom lens, a focus lens, and the like, and a drive system mechanism (not shown) that controls the operation of the optical system mechanism. Can be done. Then, the image pickup element collects the incident light from the object as an optical image, and the signal processing circuit photoelectrically converts the imaged optical image on a pixel-by-pixel basis and reads out the signal of each pixel as an image pickup signal. , The captured image can be acquired by image processing.

The display device 910 is provided on the surface of the smartphone 900, and can be, for example, a display device such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display. The display device 910 can display an operation screen, an image captured by the image pickup device 909 described above, and the like.

The speaker 911 can output, for example, a call voice, a voice accompanying the video content displayed by the display device 910 described above, or the like to the user.

The microphone 912 can collect, for example, a user's call voice, a voice including a command for activating a function of the smartphone 900, and a voice of the surrounding environment of the smartphone 900.

The input device 913 is a device operated by the user, such as a button, a keyboard, a touch panel, and a mouse. The input device 913 includes an input control circuit that generates an input signal based on the information input by the user and outputs the input signal to the CPU 901. By operating the input device 913, the user can input various data to the smartphone 900 and instruct the processing operation.

The configuration example of the smartphone 900 has been shown above. Each of the above components may be configured by using general-purpose members, or may be configured by hardware specialized for the function of each component. Such a configuration may be changed as appropriate depending on the technical level at the time of implementation.

<< 17. Supplement >>
Although the preferred embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that anyone with ordinary knowledge in the technical field of the present disclosure may come up with various modifications or amendments within the scope of the technical ideas described in the claims. Is, of course, understood to belong to the technical scope of the present disclosure.

In addition, the effects described herein are merely explanatory or exemplary and are not limited. That is, the techniques according to the present disclosure may have other effects apparent to those skilled in the art from the description herein, in addition to or in place of the above effects.

The present technology can also have the following configurations.
(1)
Provided on the semiconductor substrate,
A photoelectric conversion unit that converts light into electric charges,
A charge storage unit to which the charge is transferred from the photoelectric conversion unit and a charge storage unit
An overflow path that discharges the excess charge and
An adjustment circuit that adjusts the potential barrier of the overflow path, and
A solid-state image sensor.
(2)
The solid-state image pickup device according to (1) above, wherein the potential barrier is adjusted by a negative bias applied to an overflow gate provided on the overflow path.
(3)
The solid-state image pickup device according to (2) above, wherein the overflow gate has a vertical gate electrode structure having an embedded portion embedded in the semiconductor substrate.
(4)
The solid-state image sensor according to (2) above, wherein the overflow gate has a flat plate type gate electrode structure provided on the semiconductor substrate.
(5)
The solid-state image sensor according to (1) above, wherein the potential barrier is adjusted by a positive bias applied to the overflow path.
(6)
The solid-state image sensor according to any one of (1) to (5) above, further comprising a transfer gate for transferring the charge from the photoelectric conversion unit to the charge storage unit.
(7)
The solid-state image pickup device according to (6) above, wherein the transfer gate has a vertical gate electrode structure having an embedded portion embedded in the semiconductor substrate.
(8)
The solid-state image pickup device according to (6) above, wherein the transfer gate has a flat plate type gate electrode structure provided on the semiconductor substrate.
(9)
The solid-state image pickup device according to any one of (1) to (8) above, wherein the overflow path is electrically connected to a power supply circuit.
(10)
The solid-state image sensor according to any one of (1) to (8) above, wherein the overflow path is electrically connected to a capacitor.
(11)
The solid-state image pickup device according to any one of (1) to (10) above, wherein the adjustment circuit adjusts the potential barrier based on the measurement result of the saturation signal amount of the photoelectric conversion unit.
(12)
The solid-state image pickup device according to (11) above, wherein the adjustment circuit includes a fuse cut circuit.
(13)
The solid-state image pickup device according to (11) above, wherein the adjustment circuit includes a logic gate circuit.
(14)
Provided on the semiconductor substrate,
A photoelectric conversion unit that converts light into electric charges,
A charge storage unit to which the charge is transferred from the photoelectric conversion unit and a charge storage unit
An overflow path that discharges the excess charge and
An adjustment circuit that adjusts the potential barrier of the overflow path, and
It is a method of adjusting the potential barrier of the solid-state image sensor having the above.
The adjustment circuit adjusts the potential barrier based on the measurement result of the saturation signal amount of the photoelectric conversion unit.
Adjustment method including that.
(15)
Provided on the semiconductor substrate,
A photoelectric conversion unit that converts light into electric charges,
A charge storage unit to which the charge is transferred from the photoelectric conversion unit and a charge storage unit
An overflow path that discharges the excess charge and
An adjustment circuit that adjusts the potential barrier of the overflow path, and
An electronic device equipped with a solid-state image sensor.

1,702,909 Imaging device 10,102 Semiconductor board 30 Pixel array part 32 Vertical drive circuit part 34 Column signal processing circuit part 36 Horizontal drive circuit part 38 Output circuit part 40 Control circuit part 42 Pixel drive wiring 44 Vertical signal line 46 Horizontal Signal line 48 Input / output terminal 50 Bias setting information holding part 52 Fuse cut circuit 54 Logic gate circuit 100 pixels 104 Pixel separation part 106 n-type semiconductor area 108 Gate electrode 110 photodiode 114 Insulation film 116 p-type semiconductor area 118 Embedded part 120 on Chip lens 122 Antireflection film 130, 140 Contact 150 p-type separation layer 700 Camera 710 Optical lens 712 Shutter mechanism 714 Drive circuit unit 716 Signal processing circuit unit 900 Smartphone 901 CPU
902 ROM
903 RAM
904 Storage device 905 Communication module 906 Communication network 907 Sensor module 910 Display device 911 Speaker 912 Microphone 913 Input device 914 Bus

Claims (15)

Provided on the semiconductor substrate,
A photoelectric conversion unit that converts light into electric charges,
A charge storage unit to which the charge is transferred from the photoelectric conversion unit and a charge storage unit
An overflow path that discharges the excess charge and
An adjustment circuit that adjusts the potential barrier of the overflow path, and
A solid-state image sensor. The solid-state image sensor according to claim 1, wherein the potential barrier is adjusted by a negative bias applied to an overflow gate provided on the overflow path. The solid-state image sensor according to claim 2, wherein the overflow gate has a vertical gate electrode structure having an embedded portion embedded in the semiconductor substrate. The solid-state image sensor according to claim 2, wherein the overflow gate has a flat plate type gate electrode structure provided on the semiconductor substrate. The solid-state image sensor according to claim 1, wherein the potential barrier is adjusted by a positive bias applied to the overflow path. The solid-state image pickup device according to claim 1, further comprising a transfer gate for transferring the charge from the photoelectric conversion unit to the charge storage unit. The solid-state image sensor according to claim 6, wherein the transfer gate has a vertical gate electrode structure having an embedded portion embedded in the semiconductor substrate. The solid-state image sensor according to claim 6, wherein the transfer gate has a flat plate type gate electrode structure provided on the semiconductor substrate. The solid-state image sensor according to claim 1, wherein the overflow path is electrically connected to a power supply circuit. The solid-state image sensor according to claim 1, wherein the overflow path is electrically connected to a capacitor. The solid-state imaging device according to claim 1, wherein the adjustment circuit adjusts the potential barrier based on the measurement result of the saturation signal amount of the photoelectric conversion unit. The solid-state image pickup device according to claim 11, wherein the adjustment circuit includes a fuse cut circuit. The solid-state image pickup device according to claim 11, wherein the adjustment circuit includes a logic gate circuit. Provided on the semiconductor substrate,
A photoelectric conversion unit that converts light into electric charges,
A charge storage unit to which the charge is transferred from the photoelectric conversion unit and a charge storage unit
An overflow path that discharges the excess charge and
An adjustment circuit that adjusts the potential barrier of the overflow path, and
It is a method of adjusting the potential barrier of the solid-state image sensor having the above.
The adjustment circuit adjusts the potential barrier based on the measurement result of the saturation signal amount of the photoelectric conversion unit.
Adjustment method including that. Provided on the semiconductor substrate,
A photoelectric conversion unit that converts light into electric charges,
A charge storage unit to which the charge is transferred from the photoelectric conversion unit and a charge storage unit
An overflow path that discharges the excess charge and
An adjustment circuit that adjusts the potential barrier of the overflow path, and
An electronic device equipped with a solid-state image sensor.

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