JP2022087761A - Semiconductor device and connection member - Google Patents

Semiconductor device and connection member Download PDF

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Publication number
JP2022087761A
JP2022087761A JP2020199925A JP2020199925A JP2022087761A JP 2022087761 A JP2022087761 A JP 2022087761A JP 2020199925 A JP2020199925 A JP 2020199925A JP 2020199925 A JP2020199925 A JP 2020199925A JP 2022087761 A JP2022087761 A JP 2022087761A
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electrode
semiconductor device
flat portion
gate pad
connecting member
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博可 漆畑
Hiroyoshi Urushibata
瑛基 伊藤
Eiki Ito
渉 木村
Wataru Kimura
剛史 山路
Takeshi Yamaji
弘隆 遠藤
Hirotaka Endo
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KATO DENKI SEISAKUSHO KK
Shindengen Electric Manufacturing Co Ltd
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KATO DENKI SEISAKUSHO KK
Shindengen Electric Manufacturing Co Ltd
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Priority to JP2020199925A priority Critical patent/JP2022087761A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

To provide a semiconductor device in which reliability is hardly deteriorated even in the case of using a miniaturized semiconductor chip.SOLUTION: A semiconductor device 100 comprises: a semiconductor chip 20 having an electrode 23; and a connection member 40 that is structured by a conductive plate-like member, is projected toward the electrode 23, and includes an electrode assembly part 41 bonded via the electrode 23 to a conductive joint material 60. The electrode assembly part 41 includes: a flat part 44 formed in a region containing at least a center of a surface on the side opposite to the electrode 23 in the electrode assembly part 41; and a fillet formation part 45 that is formed in an outer peripheral region of the surface on the side opposite to the electrode 23 in the electrode assembly part 41, and is structured so that an interval between the front surface and the electrode 23 is longer than the interval between the front surface of the flat part 44 and the electrode 23. The conductive joint material 60 is arranged both in a space between the electrode 23 and the flat part 44 and a space between the electrode 23 and the fillet formation part 45.SELECTED DRAWING: Figure 1

Description

本発明は、半導体装置及び接続部材に関する。 The present invention relates to semiconductor devices and connecting members.

従来、半導体チップの電極とはんだを介して接合された接続部材を備える半導体装置が知られている（例えば、特許文献１参照。従来の半導体装置９００。）。 Conventionally, a semiconductor device including a connecting member joined to an electrode of a semiconductor chip via solder is known (see, for example, Patent Document 1; conventional semiconductor device 900).

従来の半導体装置９００は、図９に示すように、リードフレーム９１０と、リードフレーム９１０上に配置され、半導体チップ本体９２１と、リードフレーム９１０側とは反対側の表面に形成された電極９２２と、電極９２２の周囲に形成されたパッシベーション膜９２４を有する半導体チップ９２０と、導電性の板状部材からなり、電極９２２上に導電性接合材９６２を介して配置される導電性の接続部材９４０とを備える。接続部材９４０は、導電性の板状部材で構成され、電極９２２に向かって突出し、かつ、電極９２２と導電性接合材９６２を介して接合される電極接合部９４１を有する。 As shown in FIG. 9, the conventional semiconductor device 900 includes a lead frame 910, a semiconductor chip main body 921 arranged on the lead frame 910, and an electrode 922 formed on a surface opposite to the lead frame 910 side. , A semiconductor chip 920 having a passion film 924 formed around the electrode 922, and a conductive connecting member 940 which is composed of a conductive plate-shaped member and is arranged on the electrode 922 via a conductive bonding material 962. To prepare for. The connecting member 940 is composed of a conductive plate-shaped member, and has an electrode joining portion 941 that protrudes toward the electrode 922 and is joined to the electrode 922 via the conductive joining material 962.

米国特許２０１８／０１７４９５１号明細書公報U.S. Pat. No. 2018/0174951 Specification

ところで近年、電子機器や半導体装置の小型化に伴い、半導体装置内に組み込まれる半導体チップ（例えばＭＯＳＦＥＴ）のより一層の小型化が求められている。しかしながら、小型化された半導体チップにおいては電極、特にゲート電極（ゲートパッド、図１０の符号９２３参照）が狭くなるため、半導体装置の製造過程において、接続部材９４０の電極接合部９４１がゲートパッド９２３上から位置ずれしたときにゲートパッド９２３の周囲のパッシベーション膜９２４に乗り上げてしまうおそれがある（図１０参照）。接続部材９４０は一般的に比較的硬い金属板で構成されているため、パッシベーション膜９２４に乗り上げた接続部材９４０の電極接合部９４１は熱応力等で半導体チップ９２０のパッシベーション膜９２４や半導体チップ９２０内部にダメージを与えるおそれがあり、信頼性が低下するおそれがある、という問題がある。 By the way, in recent years, with the miniaturization of electronic devices and semiconductor devices, there is a demand for further miniaturization of semiconductor chips (for example, MOSFETs) incorporated in semiconductor devices. However, in a miniaturized semiconductor chip, the electrodes, especially the gate electrode (gate pad, see reference numeral 923 in FIG. 10) are narrowed, so that the electrode joining portion 941 of the connecting member 940 is the gate pad 923 in the manufacturing process of the semiconductor device. When the position is displaced from the top, the passivation film 924 around the gate pad 923 may run on the gate pad 923 (see FIG. 10). Since the connecting member 940 is generally made of a relatively hard metal plate, the electrode joint portion 941 of the connecting member 940 that rides on the passivation film 924 is subjected to thermal stress or the like to cause the passivation film 924 of the semiconductor chip 920 or the inside of the semiconductor chip 920. There is a problem that there is a risk of damaging the device and reducing reliability.

また、接続部材９４０の電極接合部９４１が位置ずれしてゲートパッド９２３が形成されている領域からはみ出した場合には、電極接合部９４１におけるゲートパッド９２３が形成されている領域からはみ出した部分の表面と電極（ゲートパッド９２３）との間には導電性接合材９６２が配置されていないため、接合強度が低下するおそれがあり、この観点においても、信頼性が低下するおそれがある。 Further, when the electrode joint portion 941 of the connecting member 940 is misaligned and protrudes from the region where the gate pad 923 is formed, the portion of the electrode joint portion 941 that protrudes from the region where the gate pad 923 is formed. Since the conductive bonding material 962 is not arranged between the surface and the electrode (gate pad 923), the bonding strength may decrease, and the reliability may also decrease from this viewpoint.

さらにまた、半導体チップ９２０及び接続部材９４０を封止樹脂９５０で封止したときに、電極接合部９４１におけるゲートパッド９２３が形成されている領域からはみ出した部分の表面と半導体チップ９２０表面との間の狭い空間に封止樹脂が入り込むため、熱膨張率の違いから封止樹脂９５０にクラックが入るおそれがあり、この観点においても信頼性が低下するおそれがある、という問題がある（図１０（ｂ）の一点鎖線Ｆで囲まれた領域参照）。これらの問題は、ゲートパッドだけでなく、面積が狭い電極全般に生じる問題である。 Furthermore, when the semiconductor chip 920 and the connecting member 940 are sealed with the sealing resin 950, between the surface of the portion of the electrode joining portion 941 protruding from the region where the gate pad 923 is formed and the surface of the semiconductor chip 920. Since the sealing resin enters the narrow space, the sealing resin 950 may be cracked due to the difference in the coefficient of thermal expansion, and there is a problem that the reliability may be lowered from this viewpoint as well (FIG. 10 (FIG. 10). b) See the area surrounded by the alternate long and short dash line F). These problems occur not only in the gate pad but also in the electrodes having a small area in general.

そこで本発明は、上記した問題を解決するためになされたものであり、小型化された半導体チップを用いた場合であっても、信頼性が低下し難い半導体装置を提供することを目的とする。また、このような半導体装置に用いられる接合部材を提供することを目的とする。 Therefore, the present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device whose reliability does not easily decrease even when a miniaturized semiconductor chip is used. .. Another object of the present invention is to provide a joining member used in such a semiconductor device.

本発明の半導体装置は、電極を有する半導体チップと、導電性の板状部材で構成され、前記電極に向かって突出し、かつ、前記電極と導電性接合材を介して接合される電極接合部を有する接続部材とを備え、前記電極接合部は、前記電極接合部における前記電極と対向する側の面の少なくとも中央を含む領域に形成された平坦部と、前記電極接合部における前記電極と対向する側の面の外周領域に形成され、表面と前記電極との間の間隔が前記平坦部の表面と前記電極との間の間隔よりも長くなるように構成されたフィレット形成部とを有し、前記導電性接合材は、前記電極と前記平坦部の間、及び、前記電極と前記フィレット形成部の間の両方に配置されていることを特徴とする。 The semiconductor device of the present invention is composed of a semiconductor chip having an electrode and a conductive plate-shaped member, and has an electrode bonding portion that protrudes toward the electrode and is bonded to the electrode via a conductive bonding material. The electrode joint includes a flat portion formed in a region including at least the center of the surface of the electrode joint facing the electrode, and the electrode joint faces the electrode in the electrode joint. It has a fillet-forming portion formed in the outer peripheral region of the side surface and configured such that the distance between the surface and the electrode is longer than the distance between the surface of the flat portion and the electrode. The conductive bonding material is characterized in that it is arranged both between the electrode and the flat portion and between the electrode and the fillet forming portion.

なお、本明細書中、「板状部材」とは、板状の部材そのものだけでなく、板状の部材を折り曲げ加工、打ち抜き加工、切削加工等の加工を施したものを含むものとする。また、「フィレット形成部」は、フィレット形成部の表面と電極との間の間隔が平坦部の表面と電極との間の間隔よりも長く、フィレット形成部と電極との間に平坦部の表面と電極の間よりも広い空間が形成される構成部分であり、当該広い空間には導電性接合材が入り込み、当該空間を満たすとともに、導電性接合材が平坦部よりも高い高さ位置からなだらかに丸みを帯びて広がることによりフィレット形状を形成するように構成された部分である。 In the present specification, the "plate-shaped member" includes not only the plate-shaped member itself but also a plate-shaped member that has been subjected to processing such as bending, punching, and cutting. Further, in the "fillet forming portion", the distance between the surface of the fillet forming portion and the electrode is longer than the distance between the surface of the flat portion and the electrode, and the surface of the flat portion between the fillet forming portion and the electrode is formed. It is a component that forms a wider space than between the electrode and the electrode, and the conductive bonding material enters the wide space to fill the space, and the conductive bonding material is gentle from a height position higher than the flat portion. It is a part configured to form a fillet shape by spreading rounded.

本発明の接続部材は、導電性の板状部材で構成され、一方向に向かって突出し、かつ、半導体チップの電極と導電性接合材を介して接合される電極接合部を有し、前記電極接合部は、前記半導体チップの前記電極と前記導電性接合材を介して接合したときに、前記電極接合部における前記電極と対向する側の面の少なくとも中央を含む領域に形成された平坦部と、前記電極接合部における前記電極と対向する側の面の外周領域に形成され、表面と前記電極との間の間隔が前記平坦部の表面と前記電極との間の間隔よりも長くなるように構成されたフィレット形成部とを有することを特徴とする。 The connecting member of the present invention is made of a conductive plate-shaped member, has an electrode joining portion that protrudes in one direction and is joined to an electrode of a semiconductor chip via a conductive joining material, and has the electrode. The joint portion is a flat portion formed in a region including at least the center of the surface of the electrode joint portion on the side facing the electrode when the electrode of the semiconductor chip is bonded to the electrode via the conductive bonding material. , The distance between the surface and the electrode is longer than the distance between the surface of the flat portion and the electrode so as to be formed in the outer peripheral region of the surface of the electrode joint portion facing the electrode. It is characterized by having a configured fillet forming portion.

本発明の半導体装置及び接続部材によれば、電極接合部は、電極接合部における電極と対向する側の面の外周領域に形成され、表面と電極との間の間隔が平坦部の表面と電極との間の間隔よりも長くなるように構成されたフィレット形成部を有するため、半導体装置の製造過程において、接続部材の電極接合部が電極上から位置ずれしたときに電極の周囲のパッシベーション膜に接続部材の電極接合部が乗り上げてしまうことを防ぐことができる。従って、接続部材が熱応力等によって半導体チップのパッシベーション膜や半導体チップ内部にダメージを与えることを防ぐことができ、信頼性を高くすることができる。 According to the semiconductor device and the connecting member of the present invention, the electrode joint portion is formed in the outer peripheral region of the surface of the electrode joint portion on the side facing the electrode, and the distance between the surface and the electrode is the surface of the flat portion and the electrode. Since it has a fillet forming portion configured to be longer than the distance between the electrodes, when the electrode joint portion of the connecting member is displaced from the electrode in the manufacturing process of the semiconductor device, the passivation film around the electrode is formed. It is possible to prevent the electrode joint portion of the connecting member from riding on. Therefore, it is possible to prevent the connecting member from damaging the passivation film of the semiconductor chip and the inside of the semiconductor chip due to thermal stress or the like, and it is possible to improve the reliability.

また、本発明の半導体装置及び接続部材によれば、電極接合部は、電極接合部における電極と対向する側の面の外周領域に形成され、表面と電極との間の間隔が平坦部の表面と電極との間の間隔よりも長くなるように構成されたフィレット形成部を有し、導電性接合材は、電極と平坦部の間、及び、電極とフィレット形成部の間の両方に配置されているため、電極接合部が位置ずれした場合であっても、電極接合部における電極が形成されている領域からはみ出した部分の表面と電極との間に導電性接合材が配置されていることとなる。従って、半導体チップと接続部材との間の接合強度が低下し難くなり、この観点においても信頼性が低下することを防ぐことができる。 Further, according to the semiconductor device and the connecting member of the present invention, the electrode joint portion is formed in the outer peripheral region of the surface of the electrode joint portion on the side facing the electrode, and the distance between the surface and the electrode is the surface of the flat portion. It has a fillet forming part configured to be longer than the distance between the electrode and the electrode, and the conductive bonding material is arranged both between the electrode and the flat part and between the electrode and the fillet forming part. Therefore, even if the electrode joint is misaligned, the conductive joint material is arranged between the surface of the portion of the electrode joint that protrudes from the region where the electrode is formed and the electrode. It becomes. Therefore, it becomes difficult for the bonding strength between the semiconductor chip and the connecting member to decrease, and it is possible to prevent the reliability from decreasing from this viewpoint as well.

さらにまた、本発明の半導体装置及び接続部材によれば、電極接合部は、電極接合部における電極と対向する側の面の外周領域に形成され、表面と電極との間の間隔が平坦部の表面と電極との間の間隔よりも長くなるように構成されたフィレット形成部を有し、導電性接合材は、電極と平坦部の間、及び、電極とフィレット形成部の間の両方に配置されているため、仮に電極接合部が位置ずれした状態で半導体チップ及び接続部材を封止樹脂で封止したときでも、電極が形成されている領域からはみ出した部分の電極接合部の表面と半導体チップ表面との間には、導電性接合材が配置されていることとなり、当該空間に封止樹脂が入り込むことを防ぐことができる。その結果、封止樹脂にクラックが入ることを防ぐことができ、この観点においても信頼性が低下することを防ぐことができる。 Furthermore, according to the semiconductor device and the connecting member of the present invention, the electrode joint is formed in the outer peripheral region of the surface of the electrode joint on the side facing the electrode, and the distance between the surface and the electrode is flat. It has a fillet forming part configured to be longer than the distance between the surface and the electrode, and the conductive bonding material is placed both between the electrode and the flat part and between the electrode and the fillet forming part. Therefore, even if the semiconductor chip and the connecting member are sealed with a sealing resin in a state where the electrode joints are misaligned, the surface of the electrode joints and the semiconductor are located outside the region where the electrodes are formed. A conductive bonding material is arranged between the chip surface and the chip surface, and it is possible to prevent the sealing resin from entering the space. As a result, it is possible to prevent the sealing resin from being cracked, and it is possible to prevent the reliability from being lowered from this viewpoint as well.

実施形態１に係る半導体装置１００を説明するために示す図である。図１（ａ）は半導体装置１００の平面図を示し、図１（ｂ）は図１（ａ）のＡ－Ａ断面図を示し、図１（ｃ）は図１（ａ）のＢ－Ｂ断面図を示す。It is a figure which shows for demonstrating the semiconductor device 100 which concerns on Embodiment 1. FIG. 1 (a) shows a plan view of the semiconductor device 100, FIG. 1 (b) shows a sectional view taken along the line AA of FIG. 1 (a), and FIG. 1 (c) shows BB of FIG. 1 (a). A cross-sectional view is shown. 第２接続部材４０が位置ずれしたときの様子を示す図である。なお、図２は、図１（ｃ）に対応する断面図である（以下、図３，４及び６において同じ）。It is a figure which shows the state when the 2nd connection member 40 is displaced. Note that FIG. 2 is a cross-sectional view corresponding to FIG. 1 (c) (hereinafter, the same applies to FIGS. 3, 4 and 6). 実施形態２に係る半導体装置１０１を説明するために示す断面図である。It is sectional drawing which shows for demonstrating the semiconductor device 101 which concerns on Embodiment 2. FIG. 実施形態３に係る半導体装置１０２を説明するために示す断面図である。It is sectional drawing which shows for demonstrating the semiconductor device 102 which concerns on Embodiment 3. FIG. 実施形態４に係る半導体装置１０３を説明するために示す図である。図５（ａ）は半導体装置１０３の平面図を示し、図５（ｂ）は図５（ａ）のＣ―Ｃ断面図を示す。It is a figure which shows for demonstrating the semiconductor device 103 which concerns on Embodiment 4. 5 (a) shows a plan view of the semiconductor device 103, and FIG. 5 (b) shows a sectional view taken along the line CC of FIG. 5 (a). 変形例１に係る半導体装置１０４を説明するために示す図である。It is a figure which shows for demonstrating the semiconductor device 104 which concerns on modification 1. FIG. 変形例２に係る半導体装置１０５を説明するために示す図である。図７（ａ）は半導体装置１０５における第２接続部材４０ｄを示す平面図であり、図７（ｂ）は図７（ａ）のＤ－Ｄ断面図であり、図７（ｃ）は図７（ａ）のＥ－Ｅ断面図である。It is a figure which shows for demonstrating the semiconductor device 105 which concerns on modification 2. 7 (a) is a plan view showing a second connecting member 40d in the semiconductor device 105, FIG. 7 (b) is a sectional view taken along the line DD of FIG. 7 (a), and FIG. 7 (c) is a sectional view taken along the line DD. It is sectional drawing of EE of (a). 変形例３に係る半導体装置１０６を説明するために示す平面図である。It is a top view shown for demonstrating the semiconductor device 106 which concerns on modification 3. FIG. 従来の半導体装置９００を示す断面図である。符号９５０は封止樹脂を示し、符号９６４は導電性接合材を示す。It is sectional drawing which shows the conventional semiconductor device 900. Reference numeral 950 indicates a sealing resin, and reference numeral 964 indicates a conductive bonding material. 小型化された半導体チップにおけるゲートパッド９２３と電極接合部９４１との関係を示す図である。図１０（ａ）は電極接合部９４１が正しい位置に配置された様子を示す図であり、図１０（ｂ）は電極接合部９４１が位置ずれしたときの様子を示す図である。符号９６２は導電性接合材を示し、符号９２１は半導体チップ本体を示す。It is a figure which shows the relationship between the gate pad 923 and the electrode junction 941 in a miniaturized semiconductor chip. FIG. 10A is a diagram showing a state in which the electrode joint portion 941 is arranged at a correct position, and FIG. 10B is a diagram showing a state in which the electrode joint portion 941 is displaced. Reference numeral 962 indicates a conductive joining material, and reference numeral 921 indicates a semiconductor chip body.

以下、本発明の半導体装置及び接続部材について、図に示す実施形態に基づいて説明する。なお、各図面は模式図であり、必ずしも実際の寸法を厳密に反映したものではない。 Hereinafter, the semiconductor device and the connecting member of the present invention will be described with reference to the embodiments shown in the drawings. It should be noted that each drawing is a schematic view and does not necessarily accurately reflect the actual dimensions.

［実施形態１］
１．実施形態１における半導体装置１００の構成
実施形態１に係る半導体装置１００は、図１（ａ）に示すように、基板１０と、半導体チップ２０と、半導体チップ２０の表面のソースパッド２２と接続された第１接続部材３０と、半導体チップ２０の表面のゲートパッド２３と接続されている第２接続部材４０と、封止樹脂５０とを備える。基板１０、半導体チップ２０、第１接続部材３０、第２接続部材４０は、封止樹脂５０で樹脂封止されているが、基板１０の裏面、第１接続部材３０の第１外部端子３３、及び、第２接続部材４０の第２外部端子４３が封止樹脂５０から露出している。 [Embodiment 1]
1. 1. Configuration of semiconductor device 100 according to the first embodiment
As shown in FIG. 1A, the semiconductor device 100 according to the first embodiment includes a substrate 10, a semiconductor chip 20, a first connecting member 30 connected to a source pad 22 on the surface of the semiconductor chip 20, and a semiconductor. A second connecting member 40 connected to the gate pad 23 on the surface of the chip 20 and a sealing resin 50 are provided. The substrate 10, the semiconductor chip 20, the first connecting member 30, and the second connecting member 40 are resin-sealed with the sealing resin 50, but the back surface of the substrate 10, the first external terminal 33 of the first connecting member 30, Further, the second external terminal 43 of the second connecting member 40 is exposed from the sealing resin 50.

基板１０（ダイパッドフレーム）は、リードフレームからなり、半導体チップ２０を配置するためのダイパッド（図示せず）を有する。基板１０の裏面は、封止樹脂５０から露出している。 The substrate 10 (die pad frame) is composed of a lead frame and has a die pad (not shown) for arranging the semiconductor chip 20. The back surface of the substrate 10 is exposed from the sealing resin 50.

半導体チップ２０は、ダイパッド上に導電性接合材（はんだ）を介して接合されている。半導体チップ２０は、半導体基体２１の表面（基板１０と対向する側の面とは反対側の面）に、ソースパッド２２（ソース電極）、ゲートパッド２３（ゲート電極）及びパッシベーション膜２４を有し、裏面（基板１０と対向する側の面）にドレイン電極（図示せず）を有する。なお、本実施形態においては、半導体チップ２０として、３端子ＭＯＳＦＥＴを用いるが、ダイオード、ＩＧＢＴ、サイリスタその他適宜の素子を用いることができる。 The semiconductor chip 20 is bonded to the die pad via a conductive bonding material (solder). The semiconductor chip 20 has a source pad 22 (source electrode), a gate pad 23 (gate electrode), and a passivation film 24 on the surface of the semiconductor substrate 21 (the surface opposite to the surface facing the substrate 10). , A drain electrode (not shown) is provided on the back surface (the surface facing the substrate 10). In this embodiment, a 3-terminal MOSFET is used as the semiconductor chip 20, but a diode, an IGBT, a thyristor, or any other appropriate element can be used.

ソースパッド２２は、半導体基体２１の表面の中央を含む領域を占めている。ソースパッド２２の表面は、導体膜（例えば、ＮｉＡｕ膜又はＮｉＡｇ膜）からなる。ゲートパッド２３は、半導体基体２１の表面の隅に近い領域にソースパッド２２と離隔して形成されている。ゲートパッド２３が占める面積は、ソースパッド２２が占める面積よりも大幅に小さい。 The source pad 22 occupies a region including the center of the surface of the semiconductor substrate 21. The surface of the source pad 22 is made of a conductor film (for example, a NiAu film or a NiAg film). The gate pad 23 is formed in a region near the corner of the surface of the semiconductor substrate 21 so as to be separated from the source pad 22. The area occupied by the gate pad 23 is significantly smaller than the area occupied by the source pad 22.

第１接続部材３０は、導電性の板状部材（例えば、銅板）からなり、ソースパッド２２上に導電性接合材（図示せず）を介して配置されている。第１接続部材３０は、第１電極接合部３１と、第１連結部３２と、第１外部端子３３とを有する。第１電極接合部３１は、平面的に見て略矩形形状を有し、ソースパッド２２と導電性接合材を介して接合されている。第１連結部３２は、第１電極接合部３１の角部と連結されており、そこから水平方向に沿って封止樹脂５０の外側まで直線状に延びている。第１外部端子３３は、第１連結部３２の先端に形成されており、外部の配線や電極と接続することができる。 The first connecting member 30 is made of a conductive plate-shaped member (for example, a copper plate), and is arranged on the source pad 22 via a conductive joining material (not shown). The first connecting member 30 has a first electrode joining portion 31, a first connecting portion 32, and a first external terminal 33. The first electrode bonding portion 31 has a substantially rectangular shape when viewed in a plane, and is bonded to the source pad 22 via a conductive bonding material. The first connecting portion 32 is connected to the corner portion of the first electrode joining portion 31, and extends linearly from there to the outside of the sealing resin 50 along the horizontal direction. The first external terminal 33 is formed at the tip of the first connecting portion 32 and can be connected to external wiring or electrodes.

第２接続部材４０は、導電性の板状部材（例えば、銅板）で構成されている。第２接続部材４０は、図１（ｂ）に示すように、第２電極接合部４１と、第２連結部４２と、第２外部端子４３と係止部４６とを有する。図１（ａ）に示すように、第２接続部材４０は、平面的に見て直線状に形成されており、第２電極接合部４１の一方側には第２連結部４２が連結されており、他方側には水平方向に沿って第２連結部４２とは反対側に向かってわずかに張り出している係止部４６が設けられている。なお、係止部４６により、第２接続部材４０近傍の封止樹脂５０がモールドロックされる。 The second connecting member 40 is made of a conductive plate-shaped member (for example, a copper plate). As shown in FIG. 1B, the second connecting member 40 has a second electrode joining portion 41, a second connecting portion 42, a second external terminal 43, and a locking portion 46. As shown in FIG. 1A, the second connecting member 40 is formed in a linear shape when viewed in a horizontal plane, and the second connecting portion 42 is connected to one side of the second electrode joining portion 41. A locking portion 46 is provided on the other side so as to slightly project along the horizontal direction toward the side opposite to the second connecting portion 42. The locking portion 46 mold-locks the sealing resin 50 in the vicinity of the second connecting member 40.

第２電極接合部４１は、ゲートパッド２３(一方向）に向かって突出し、かつ、ゲートパッド２３と導電性接合材６０を介して接合される。第２電極接合部４１は、平坦部４４側（半導体チップ側）が狭いテーパ形状をしている。本実施形態においては、打ち出し加工によって第２電極接合部４１を形成する。このため、半導体チップ２０側とは反対側の表面に凹部４７が形成されている。第２電極接合部４１は、第２電極接合部４１におけるゲートパッド２３と対向する側の面の少なくとも中央を含む領域に形成された平坦部４４と、第２電極接合部４１におけるゲートパッド２３と対向する側の面の外周領域に形成され、表面とゲートパッド２３との間の間隔Ｈ２が平坦部４４の表面とゲートパッド２３との間の間隔Ｈ１よりも長くなるように構成されたフィレット形成部４５とを有する。第２電極接合部４１におけるゲートパッド２３と対向する側の面（平坦部４４及びフィレット形成部４５の表面）には、メッキが施されておらず、銅材と導電性接合材６０（はんだ）とが直接接している。 The second electrode bonding portion 41 projects toward the gate pad 23 (one direction) and is bonded to the gate pad 23 via the conductive bonding material 60. The second electrode joint portion 41 has a tapered shape with a narrow flat portion 44 side (semiconductor chip side). In the present embodiment, the second electrode joint portion 41 is formed by embossing. Therefore, the recess 47 is formed on the surface opposite to the semiconductor chip 20 side. The second electrode joint 41 includes a flat portion 44 formed in a region including at least the center of the surface facing the gate pad 23 in the second electrode joint 41, and the gate pad 23 in the second electrode joint 41. A fillet formed in the outer peripheral region of the surface on the opposite side so that the distance H2 between the surface and the gate pad 23 is longer than the distance H1 between the surface of the flat portion 44 and the gate pad 23. It has a portion 45. The surface of the second electrode joint 41 on the side facing the gate pad 23 (the surface of the flat portion 44 and the fillet forming portion 45) is not plated, and the copper material and the conductive joint material 60 (solder) are not plated. Is in direct contact with.

断面でみたときに平坦部４４の幅Ｌ１は、ゲートパッド２３の幅Ｌ２の０．４倍～０．６倍の範囲内にある。また、断面で見たときにフィレット形成部４５の幅Ｌ３（平面的に見て平坦部４４との境界地点から第２電極接合部４１の外縁までの長さ）は、平坦部４４の幅Ｌ１（ゲートパッド２３と対向する面が平坦な領域の長さ）の０．２倍～０．４倍の範囲内にある。なお、「断面で見たとき」とは、矩形のゲートパッド２３の対向する２辺を通る断面で見たときのことをいい、矩形のゲートパッド２３の長辺に沿った断面や矩形のゲートパッド２３の短辺に沿った断面を含む。 When viewed in cross section, the width L1 of the flat portion 44 is within the range of 0.4 times to 0.6 times the width L2 of the gate pad 23. Further, when viewed in cross section, the width L3 of the fillet forming portion 45 (the length from the boundary point with the flat portion 44 to the outer edge of the second electrode joint portion 41 when viewed in a plane) is the width L1 of the flat portion 44. It is in the range of 0.2 times to 0.4 times (the length of the region where the surface facing the gate pad 23 is flat). The term "when viewed in cross section" refers to a cross section that passes through two opposite sides of the rectangular gate pad 23, and is a cross section along the long side of the rectangular gate pad 23 or a rectangular gate. Includes a cross section along the short side of the pad 23.

フィレット形成部４５におけるゲートパッド２３と対向する側の面は、平坦部４４から斜めに延びる傾斜面Ｓ１であり、第２電極接合部４１の側面Ｓ０と繋がっている。言い換えると、フィレット形成部４５は、第２電極接合部４１におけるゲートパッド２３と対向する平坦部３４と同一の平面と、第２電極接合部４１の側面Ｓ０と同一平面とで形成される角部を面取りして傾斜面Ｓ１（Ｃ面）とした構造を有する。平坦部４４に対するフィレット形成部４５の傾斜面の角度は、半導体チップ２０上に配置したときにパッシベーション膜２４から遠くなるような角度であり、好ましくは３０°～６０°の範囲内にあり、例えば４５度である。平坦部４４を基準としたときの第２電極接合部４１の外縁の位置におけるフィレット形成部４５の表面の高さをＨとし、平坦部４４が形成されている領域における第２電極接合部４１の厚さをＴとすると、０．２５×Ｔ≦Ｈを満たす。実施形態１においては、平面的に見て矩形形状の平坦部４４の周囲を囲うように矩形形状の４辺全てにフィレット形成部４５が形成されている。 The surface of the fillet forming portion 45 on the side facing the gate pad 23 is an inclined surface S1 extending diagonally from the flat portion 44, and is connected to the side surface S0 of the second electrode joint portion 41. In other words, the fillet forming portion 45 is a corner portion formed by the same plane as the flat portion 34 facing the gate pad 23 in the second electrode joint portion 41 and the same plane as the side surface S0 of the second electrode joint portion 41. Has a structure in which an inclined surface S1 (C surface) is formed by chamfering. The angle of the inclined surface of the fillet forming portion 45 with respect to the flat portion 44 is an angle that is far from the passivation film 24 when placed on the semiconductor chip 20, and is preferably in the range of 30 ° to 60 °, for example. It is 45 degrees. The height of the surface of the fillet forming portion 45 at the position of the outer edge of the second electrode joining portion 41 with respect to the flat portion 44 is set to H, and the height of the surface of the second electrode joining portion 41 in the region where the flat portion 44 is formed is defined as H. Assuming that the thickness is T, 0.25 × T ≦ H is satisfied. In the first embodiment, the fillet forming portions 45 are formed on all four sides of the rectangular shape so as to surround the periphery of the rectangular flat portion 44 when viewed in a plane.

フィレット形成部４５におけるゲートパッド２３と対向する側の面全体が導電性接合材６０で覆われており、導電性接合材６０は、第２電極接合部４１の側面Ｓ０と傾斜面Ｓ１とが繋がっている地点からゲートパッド２３の端部までなだらかなカーブを描くフィレット形状が形成されている。 The entire surface of the fillet forming portion 45 on the side facing the gate pad 23 is covered with the conductive joining material 60, and the side surface S0 of the second electrode joining portion 41 and the inclined surface S1 are connected to each other in the conductive joining material 60. A fillet shape that draws a gentle curve from the point where the gate pad 23 is formed to the end of the gate pad 23 is formed.

第２連結部４２は、第２電極接合部４１と繋がり水平方向に沿って封止樹脂５０の外側まで直線状に延びており、封止樹脂５０の外側で段差が形成されている。第２外部端子４３は、第２連結部４２の先端に形成され、外部の電極や配線と接続される。第２外部端子４３は、第２連結部４２から直線状に延びている。 The second connecting portion 42 is connected to the second electrode joining portion 41 and extends linearly to the outside of the sealing resin 50 along the horizontal direction, and a step is formed on the outside of the sealing resin 50. The second external terminal 43 is formed at the tip of the second connecting portion 42 and is connected to an external electrode or wiring. The second external terminal 43 extends linearly from the second connecting portion 42.

封止樹脂５０は、適宜の樹脂を用いることができる。 As the sealing resin 50, an appropriate resin can be used.

導電性接合材６０は、平坦部４４とゲートパッド２３の間、及び、フィレット形成部４５とゲートパッド２３の間の両方に配置されている。 The conductive joining material 60 is arranged both between the flat portion 44 and the gate pad 23, and between the fillet forming portion 45 and the gate pad 23.

ここで、実施形態１に係る半導体装置１００の製造過程において、仮に第２電極接合部４１がゲートパッド２３から位置ずれし、第２電極接合部４１の側面Ｓ０がゲートパッド２３をはみ出した場合について説明する。この場合でも、実施形態１に係る半導体装置１００は、図２に示すように、フィレット形成部４５が形成されていることから第２電極接合部４１がパッシベーション膜１４に乗り上げることがない。また、導電性接合材６０は、量は少なくなるもののゲートパッド２３とフィレット形成部４５の間に配置された状態を維持することができる。このため、接合強度が低下したり、封止樹脂５０が入り込みクラックが発生することを防ぐことができる（図２の破線Ｄで囲まれた領域参照）。 Here, in the case where the second electrode joint portion 41 is displaced from the gate pad 23 and the side surface S0 of the second electrode joint portion 41 protrudes from the gate pad 23 in the manufacturing process of the semiconductor device 100 according to the first embodiment. explain. Even in this case, as shown in FIG. 2, in the semiconductor device 100 according to the first embodiment, since the fillet forming portion 45 is formed, the second electrode joint portion 41 does not ride on the passivation film 14. Further, the conductive joining material 60 can maintain the state of being arranged between the gate pad 23 and the fillet forming portion 45, although the amount is small. Therefore, it is possible to prevent the bonding strength from being lowered and the sealing resin 50 from entering and cracking (see the region surrounded by the broken line D in FIG. 2).

２．実施形態１に係る半導体装置１００及び第２接続部材４０の効果
実施形態１に係る半導体装置１００及び第２接続部材４０によれば、第２電極接合部４１は、第２電極接合部４１におけるゲートパッド２３と対向する側の面の外周領域に形成され、表面とゲートパッド２３との間の間隔が平坦部４４の表面とゲートパッド２３との間の間隔よりも長くなるように構成されたフィレット形成部４５を有するため、半導体装置の製造過程において、第２接続部材４０の第２電極接合部４１がゲートパッド２３上から位置ずれしたときにゲートパッド２３の周囲のパッシベーション膜２４に第２接続部材４０の第２電極接合部４１が乗り上げてしまうことを防ぐことができる。従って、第２接続部材４０が熱応力等によって半導体チップ２０のパッシベーション膜２４や半導体チップ２０内部にダメージを与えることを防ぐことができ、信頼性を高くすることができる。 2. 2. Effect of Semiconductor Device 100 and Second Connection Member 40 According to Embodiment 1. According to the semiconductor device 100 and second connection member 40 according to the first embodiment, the second electrode joint portion 41 is a gate in the second electrode joint portion 41. A fillet formed in the outer peripheral region of the surface facing the pad 23 so that the distance between the surface and the gate pad 23 is longer than the distance between the surface of the flat portion 44 and the gate pad 23. Since the semiconductor device has the forming portion 45, when the second electrode joint portion 41 of the second connecting member 40 is displaced from the gate pad 23 in the manufacturing process of the semiconductor device, the second connection is made to the passion film 24 around the gate pad 23. It is possible to prevent the second electrode joint portion 41 of the member 40 from riding on. Therefore, it is possible to prevent the second connecting member 40 from damaging the passivation film 24 of the semiconductor chip 20 and the inside of the semiconductor chip 20 due to thermal stress or the like, and it is possible to improve the reliability.

また、実施形態１に係る半導体装置１００及び第２接続部材４０によれば、第２電極接合部４１は、第２電極接合部４１におけるゲートパッド２３と対向する側の面の外周領域に形成され、表面とゲートパッド２３との間の間隔が平坦部４４の表面とゲートパッド２３との間の間隔よりも長くなるように構成されたフィレット形成部４５を有し、導電性接合材６０は、ゲートパッド２３と平坦部４４の間、及び、ゲートパッド２３とフィレット形成部４５の間の両方に配置されているため、第２電極接合部４１が位置ずれした場合であっても、第２電極接合部４１におけるゲートパッド２３が形成されている領域からはみ出した部分の表面とゲートパッド２３との間に導電性接合材６０が配置されていることとなる。従って、半導体チップ２０と第２接続部材４０との間の接合強度が低下し難くなり、この観点においても信頼性が低下することを防ぐことができる。 Further, according to the semiconductor device 100 and the second connection member 40 according to the first embodiment, the second electrode joint portion 41 is formed in the outer peripheral region of the surface of the second electrode joint portion 41 on the side facing the gate pad 23. The conductive bonding material 60 has a fillet forming portion 45 configured such that the distance between the surface and the gate pad 23 is longer than the distance between the surface of the flat portion 44 and the gate pad 23. Since it is arranged both between the gate pad 23 and the flat portion 44 and between the gate pad 23 and the fillet forming portion 45, even if the second electrode joint portion 41 is misaligned, the second electrode The conductive bonding material 60 is arranged between the surface of the portion of the bonding portion 41 protruding from the region where the gate pad 23 is formed and the gate pad 23. Therefore, it becomes difficult for the bonding strength between the semiconductor chip 20 and the second connecting member 40 to decrease, and it is possible to prevent the reliability from decreasing from this viewpoint as well.

また、実施形態１に係る半導体装置１００及び第２接続部材４０によれば、第２電極接合部４１は、第２電極接合部４１におけるゲートパッド２３と対向する側の面の外周領域に形成され、表面とゲートパッド２３との間の間隔が平坦部４４の表面とゲートパッド２３との間の間隔よりも長くなるように構成されたフィレット形成部４５を有し、導電性接合材６０は、ゲートパッド２３と平坦部４４の間、及び、ゲートパッド２３とフィレット形成部４５の間の両方に配置されているため、仮に第２電極接合部４１が位置ずれした状態で半導体チップ２０及び第２接続部材４０を封止樹脂５０で封止したときでも、ゲートパッド２３が形成されている領域からはみ出した部分の第２電極接合部４１の表面とゲートパッド２３との間には、導電性接合材６０が配置されていることとなり、当該空間に封止樹脂５０が入り込むことを防ぐことができる。その結果、封止樹脂５０にクラックが入ることを防ぐことができ、この観点においても信頼性が低下することを防ぐことができる。 Further, according to the semiconductor device 100 and the second connection member 40 according to the first embodiment, the second electrode joint portion 41 is formed in the outer peripheral region of the surface of the second electrode joint portion 41 facing the gate pad 23. The conductive bonding material 60 has a fillet forming portion 45 configured such that the distance between the surface and the gate pad 23 is longer than the distance between the surface of the flat portion 44 and the gate pad 23. Since it is arranged both between the gate pad 23 and the flat portion 44 and between the gate pad 23 and the fillet forming portion 45, the semiconductor chip 20 and the second are assumed to be in a state where the second electrode joint portion 41 is misaligned. Even when the connecting member 40 is sealed with the sealing resin 50, a conductive bond is formed between the surface of the second electrode joint portion 41 and the gate pad 23 in a portion protruding from the region where the gate pad 23 is formed. Since the material 60 is arranged, it is possible to prevent the sealing resin 50 from entering the space. As a result, it is possible to prevent the sealing resin 50 from being cracked, and it is possible to prevent the reliability from being lowered from this viewpoint as well.

また、実施形態１に係る半導体装置１００及び第２接続部材４０によれば、第２電極接合部４１は、平坦部４４側が狭いテーパ形状をしているため、パッシベーション膜２４から第２接続部材４０までの距離が長くなり、仮に第２接続部材４０が位置ずれした場合でもパッシベーション膜２４上に第２接続部材４０が乗り上げ難くなる。 Further, according to the semiconductor device 100 and the second connecting member 40 according to the first embodiment, since the second electrode joint portion 41 has a narrow tapered shape on the flat portion 44 side, the passivation film 24 to the second connecting member 40 Even if the position of the second connecting member 40 is displaced, it becomes difficult for the second connecting member 40 to ride on the passivation film 24.

また、実施形態１に係る半導体装置１００及び第２接続部材４０によれば、フィレット形成部４５におけるゲートパッド２３と対向する側の面は、平坦部４４から斜めに延びる傾斜面Ｓ１であるため、比較的簡便な方法でフィレット形成部４５を形成することができる。 Further, according to the semiconductor device 100 and the second connecting member 40 according to the first embodiment, the surface of the fillet forming portion 45 on the side facing the gate pad 23 is an inclined surface S1 extending diagonally from the flat portion 44. The fillet forming portion 45 can be formed by a relatively simple method.

ところで、一般に、接続部材が導電性接合材を介して電極と接合する場合、導電性接合材に発生する熱応力を緩和するために、はんだ厚を確保することが有効であることが知られている。そして、単純にクリップに対して電極パッドを大きくできて位置ずれマージンが確保できる場合は問題ないが、電極パットを大きくできないゲート電極は位置ずれマージンが取れないため、第２電極接合部の周辺部のはんだ厚を確保することが難しい。これに対して、実施形態１に係る半導体装置１００及び第２接続部材４０においては、電極は、ゲートパッドであり、第２電極接合部４１は、第２電極接合部４１におけるゲートパッド２３と対向する側の面の外周領域に形成され、表面とゲートパッド２３との間の間隔が平坦部４４の表面とゲートパッド２３との間の間隔よりも長くなるように構成されたフィレット形成部４５を有し、導電性接合材６０は、ゲートパッド２３と平坦部４４の間、及び、ゲートパッド２３とフィレット形成部４５の間の両方に配置されているため、設置面積が小さいゲートパッドであっても、第２電極接合部４１の周辺部のはんだ厚を確保することができる。 By the way, it is generally known that when a connecting member is joined to an electrode via a conductive joining material, it is effective to secure a solder thickness in order to alleviate the thermal stress generated in the conductive joining material. There is. Then, there is no problem if the electrode pad can be simply enlarged with respect to the clip and the misalignment margin can be secured. It is difficult to secure the solder thickness. On the other hand, in the semiconductor device 100 and the second connection member 40 according to the first embodiment, the electrode is a gate pad, and the second electrode joint portion 41 faces the gate pad 23 in the second electrode joint portion 41. A fillet forming portion 45 formed in the outer peripheral region of the surface on the side of the soldering surface and configured such that the distance between the surface and the gate pad 23 is longer than the distance between the surface of the flat portion 44 and the gate pad 23. Since the conductive bonding material 60 is arranged both between the gate pad 23 and the flat portion 44 and between the gate pad 23 and the fillet forming portion 45, the gate pad has a small installation area. Also, it is possible to secure the solder thickness of the peripheral portion of the second electrode joint portion 41.

また、実施形態１に係る半導体装置１００及び第２接続部材４０によれば、第２電極接合部４１におけるゲートパッド２３と対向する側の面（平坦部４４及びフィレット形成部４５の表面）には、メッキが施されていないため、メッキ工程が必要なく、高い生産性で半導体装置を製造することができる。 Further, according to the semiconductor device 100 and the second connecting member 40 according to the first embodiment, the surface of the second electrode joining portion 41 on the side facing the gate pad 23 (the surface of the flat portion 44 and the fillet forming portion 45) is Since it is not plated, a semiconductor device can be manufactured with high productivity without the need for a plating process.

また、実施形態１に係る半導体装置１００及び第２接続部材４０によれば、断面でみたとき平坦部４４の幅Ｌ１は、ゲートパッド２３の幅Ｌ２の０．４倍～０．６倍の範囲内にあるため、製造過程において、第２接続部材４０が位置ずれした場合のマージンを十分とることができる。また、ゲートパッド２３と平坦部４４との間隔を一定に保ち易く、電流の偏りが少なくなる。 Further, according to the semiconductor device 100 and the second connecting member 40 according to the first embodiment, the width L1 of the flat portion 44 when viewed in cross section is in the range of 0.4 times to 0.6 times the width L2 of the gate pad 23. Since it is inside, a sufficient margin can be taken when the second connecting member 40 is displaced in the manufacturing process. Further, it is easy to keep the distance between the gate pad 23 and the flat portion 44 constant, and the bias of the current is reduced.

なお、平坦部４４の幅Ｌ１をゲートパッド２３の幅Ｌ２の０．４倍以上としたのは、ゲートパッド２３の幅Ｌ２を０．４未満とした場合には、ゲートパッド２３と第２電極接合部４１との間隔にばらつきが大きくなり、ゲートの制御に用いる比較的微弱な電流のバラツキが生じ易くなることから、半導体チップ２０のオンオフが高い精度でできなくなるおそれがあるからであり、平坦部４４の幅Ｌ１をゲートパッド２３の幅Ｌ２の０．６倍以下としたのは、ゲートパッド２３の幅Ｌ２の０．６倍を超えることとすると、フィレット形成部４５の領域面積が小さくなり、フィレット形成部４５を設けた効果が小さくなってしまい、信頼性を高くすることが難しいからである。 The reason why the width L1 of the flat portion 44 is 0.4 times or more the width L2 of the gate pad 23 is that when the width L2 of the gate pad 23 is less than 0.4, the gate pad 23 and the second electrode are used. This is because the distance from the joint portion 41 becomes large and the relatively weak current used for controlling the gate tends to vary, so that the semiconductor chip 20 may not be turned on and off with high accuracy, and is flat. The reason why the width L1 of the portion 44 is 0.6 times or less of the width L2 of the gate pad 23 is that if it exceeds 0.6 times the width L2 of the gate pad 23, the area area of the fillet forming portion 45 becomes small. This is because the effect of providing the fillet forming portion 45 becomes small, and it is difficult to improve the reliability.

また、実施形態１に係る半導体装置１００及び第２接続部材４０によれば、断面で見たときにフィレット形成部４５の幅Ｌ３は、平坦部４４の幅Ｌ１の０．２倍～０．４倍の範囲内にあるため、半導体装置の製造過程において、第２電極接合部４１がゲートパッド２３の位置から位置ずれしたときに、第２接続部材４０がパッシベーション膜２４上に乗り上げることを防ぐことができるとともに、電流の流れが不安定になりにくくなる。 Further, according to the semiconductor device 100 and the second connecting member 40 according to the first embodiment, the width L3 of the fillet forming portion 45 is 0.2 times to 0.4 times the width L1 of the flat portion 44 when viewed in cross section. Since it is within the double range, it is possible to prevent the second connecting member 40 from riding on the passivation film 24 when the second electrode joint portion 41 is displaced from the position of the gate pad 23 in the manufacturing process of the semiconductor device. At the same time, the current flow is less likely to become unstable.

なお、フィレット形成部４５の幅Ｌ３を平坦部４４の幅Ｌ１の０．２倍以上としたのは、フィレット形成部４５の幅Ｌ３が平坦部４４の幅Ｌ１の０．２倍未満の場合には、フィレット形成部４５が形成されている面積が小さすぎて、第２電極接合部４１が電極（ゲートパッド２３）の位置から位置ずれした場合に第２接続部材４０がパッシベーション膜２４上に乗り上げるおそれがあるからであり、フィレット形成部４５の幅Ｌ３を平坦部４４の幅Ｌ１の０．４倍以下としたのは、フィレット形成部４５の幅Ｌ３が平坦部４４の幅Ｌ１の０．４倍を超える場合には、平坦部４４の面積が狭くなりすぎるため、電流の流れが不安定になるおそれがあるからである。 The width L3 of the fillet forming portion 45 is set to 0.2 times or more the width L1 of the flat portion 44 when the width L3 of the fillet forming portion 45 is less than 0.2 times the width L1 of the flat portion 44. The second connecting member 40 rides on the passion film 24 when the area where the fillet forming portion 45 is formed is too small and the second electrode joining portion 41 is displaced from the position of the electrode (gate pad 23). The reason why the width L3 of the fillet forming portion 45 is 0.4 times or less the width L1 of the flat portion 44 is that the width L3 of the fillet forming portion 45 is 0.4 of the width L1 of the flat portion 44. If it exceeds twice, the area of the flat portion 44 becomes too small, and the current flow may become unstable.

また、実施形態１に係る半導体装置１００及び第２接続部材４０によれば、平坦部４４の高さ位置を基準としたときの第２電極接合部４１の位置における面取りされた空間の高さをＨとし、平坦部４４が形成されている領域における第２電極接合部４１の厚さをＴとすると、０．２５×Ｔ≦Ｈを満たすため、第２接続部材４０をパッシベーション膜２４の端部から十分な距離を離すことができるとともに、フィレット形成部４５とゲートパッド２３との間に十分な空間を形成することができる。そして、その空間に十分な厚みを有する導電性接合材（はんだ）を配置することができる。 Further, according to the semiconductor device 100 and the second connecting member 40 according to the first embodiment, the height of the chamfered space at the position of the second electrode joint portion 41 with respect to the height position of the flat portion 44 is determined. Assuming that H is H and the thickness of the second electrode joint 41 in the region where the flat portion 44 is formed is T, the second connecting member 40 is attached to the end portion of the passivation film 24 in order to satisfy 0.25 × T ≦ H. It is possible to keep a sufficient distance from the fillet forming portion 45 and to form a sufficient space between the fillet forming portion 45 and the gate pad 23. Then, a conductive bonding material (solder) having a sufficient thickness can be arranged in the space.

なお、０．２５×Ｔ≦Ｈを満たすこととしたのは、高さＨが０．２５×Ｔ未満の場合には、第２接続部材４０をパッシベーション膜２４の端部から十分な距離を離すことが難しく、さらには第２接続部材４０が位置ずれしたときに十分なはんだ厚を確保することが難しいからである。なお、高さＨの上限は、第２電極接合部４１の厚みと同じ厚さのとき、すなわち、第２電極接合部４１における上端まで形成されている場合であるから、Ｈ＝Ｔの場合である。 It should be noted that the reason why 0.25 × T ≦ H is satisfied is that when the height H is less than 0.25 × T, the second connecting member 40 is sufficiently separated from the end portion of the passivation film 24. This is because it is difficult to secure a sufficient solder thickness when the second connecting member 40 is displaced. The upper limit of the height H is the same as the thickness of the second electrode joint 41, that is, when it is formed up to the upper end of the second electrode joint 41, so that H = T. be.

［実施形態２］
実施形態２に係る半導体装置１０１は、基本的には実施形態１に係る半導体装置１００と同様の構成を有するが、フィレット形成部の構成が実施形態１に係る半導体装置１００の場合とは異なる。すなわち、実施形態２に係る半導体装置１０１において、フィレット形成部４５におけるゲートパッド２３と対向する側の面は、平坦部４４と繋がる曲面である（図３参照）。言い換えると、フィレット形成部４５ａは、断面で見て平坦部４４ａを延ばした平面と、第２電極接合部４１ａの側面Ｓ０を延ばした平面との交点を中心軸として円状（円柱状）に角部を切り欠いて形成されたＲ形状を有する。当該曲面は、平坦部４４ａとフィレット形成部４５ａの表面との接続点、及び、フィレット形成部４５ａと第２電極接合部４１ａの側面との接続点を結んだ直線よりも第２電極接合部４１ａの中心に向かって凹んだ曲面である。 [Embodiment 2]
The semiconductor device 101 according to the second embodiment basically has the same configuration as the semiconductor device 100 according to the first embodiment, but the configuration of the fillet forming portion is different from the case of the semiconductor device 100 according to the first embodiment. That is, in the semiconductor device 101 according to the second embodiment, the surface of the fillet forming portion 45 on the side facing the gate pad 23 is a curved surface connected to the flat portion 44 (see FIG. 3). In other words, the fillet forming portion 45a has a circular (cylindrical) angle with the intersection of the flat surface extending the flat portion 44a and the flat surface extending the side surface S0 of the second electrode joint portion 41a as the central axis as the central axis. It has an R shape formed by cutting out a portion. The curved surface has a second electrode joint portion 41a rather than a straight line connecting the connection point between the flat portion 44a and the surface of the fillet forming portion 45a and the connection point between the fillet forming portion 45a and the side surface of the second electrode joint portion 41a. It is a curved surface that is recessed toward the center of.

このように、実施形態２に係る半導体装置１０１は、フィレット形成部の構成が実施形態１に係る半導体装置１００の場合とは異なるが、実施形態１に係る半導体装置１００の場合と同様に、第２電極接合部４１ａは、第２電極接合部４１ａにおけるゲートパッド２３と対向する側の面の外周領域に形成され、表面とゲートパッド２３との間の間隔が平坦部４４ａの表面とゲートパッド２３との間の間隔よりも長くなるように構成されたフィレット形成部４５ａを有するため、半導体装置の製造過程において、第２接続部材４０ａの第２電極接合部４１ａがゲートパッド２３上から位置ずれしたときにゲートパッド２３の周囲のパッシベーション膜２４に第２接続部材４０ａの第２電極接合部４１ａが乗り上げてしまうことを防ぐことができる。従って、第２接続部材４０ａが熱応力等によって半導体チップ２０のパッシベーション膜２４や半導体チップ２０内部にダメージを与えることを防ぐことができ、信頼性を高くすることができる。 As described above, the semiconductor device 101 according to the second embodiment has a different configuration of the fillet forming portion from the semiconductor device 100 according to the first embodiment, but is similar to the semiconductor device 100 according to the first embodiment. The two-electrode joint portion 41a is formed in the outer peripheral region of the surface of the second electrode joint portion 41a on the side facing the gate pad 23, and the distance between the surface and the gate pad 23 is the surface of the flat portion 44a and the gate pad 23. Since the fillet forming portion 45a is configured to be longer than the distance between the two, the second electrode joint portion 41a of the second connecting member 40a is displaced from the gate pad 23 in the manufacturing process of the semiconductor device. Occasionally, it is possible to prevent the second electrode joint portion 41a of the second connecting member 40a from riding on the passivation film 24 around the gate pad 23. Therefore, it is possible to prevent the second connecting member 40a from damaging the passivation film 24 of the semiconductor chip 20 and the inside of the semiconductor chip 20 due to thermal stress or the like, and it is possible to improve the reliability.

また、実施形態２に係る半導体装置１０１によれば、フィレット形成部４５ａにおけるゲートパッド２３と対向する側の面は、平坦部４４と繋がる曲面であるため、フィレット形成部４５ａの表面が傾斜面の場合よりも、フィレット形成部４５ａと導電性接合材６０との接触面積が大きくなるため、第２接続部材４０ａと導電性接合材６０との間の接合強度が高くなる。また、第２電極接合部４１ａの中心に向かって凹んだ曲面である場合には、傾斜面の場合よりも多い量の導電性接合材６０をフィレット形成部４５ａとゲートパッド２３との間に配置することができ、はんだ厚を維持することができ、導電性接合材にかかる熱応力を緩和することができる。 Further, according to the semiconductor device 101 according to the second embodiment, since the surface of the fillet forming portion 45a on the side facing the gate pad 23 is a curved surface connected to the flat portion 44, the surface of the fillet forming portion 45a is an inclined surface. Since the contact area between the fillet forming portion 45a and the conductive bonding material 60 is larger than in the case, the bonding strength between the second connecting member 40a and the conductive bonding material 60 is increased. Further, in the case of a curved surface recessed toward the center of the second electrode bonding portion 41a, a larger amount of the conductive bonding material 60 is arranged between the fillet forming portion 45a and the gate pad 23 than in the case of an inclined surface. It is possible to maintain the solder thickness and alleviate the thermal stress applied to the conductive joining material.

なお、実施形態２に係る半導体装置１０１は、フィレット形成部の構成以外の点においては実施形態１に係る半導体装置１００と同様の構成を有するため、実施形態１に係る半導体装置１００が有する効果のうち該当する効果を有する。 Since the semiconductor device 101 according to the second embodiment has the same configuration as the semiconductor device 100 according to the first embodiment except for the configuration of the fillet forming portion, the effect of the semiconductor device 100 according to the first embodiment is obtained. Of these, it has the corresponding effect.

［実施形態３］
実施形態３に係る半導体装置１０２は、基本的には実施形態１に係る半導体装置１００と同様の構成を有するが、フィレット形成部の構成が実施形態１に係る半導体装置１００の場合とは異なる。すなわち、実施形態３に係る半導体装置１０２においては、断面でみたときに平坦部４４ｂとフィレット形成部４５ｂとで階段形状を構成している（図４参照）。 [Embodiment 3]
The semiconductor device 102 according to the third embodiment basically has the same configuration as the semiconductor device 100 according to the first embodiment, but the configuration of the fillet forming portion is different from that of the semiconductor device 100 according to the first embodiment. That is, in the semiconductor device 102 according to the third embodiment, the flat portion 44b and the fillet forming portion 45b form a staircase shape when viewed in cross section (see FIG. 4).

フィレット形成部４５ｂは、平坦部４４ｂと段差を形成され、中途の位置でさらにもう一つ段差が形成され、第２電極接合部４１の側面と繋がっている。これにより、平坦部４４ｂとフィレット形成部４５ｂとで２段の階段形状を構成している。 The fillet forming portion 45b has a step formed with the flat portion 44b, and another step is formed at a position in the middle, and is connected to the side surface of the second electrode joint portion 41. As a result, the flat portion 44b and the fillet forming portion 45b form a two-step staircase shape.

このように、実施形態３に係る半導体装置１０２は、フィレット形成部の構成が実施形態１に係る半導体装置１００の場合とは異なるが、実施形態１に係る半導体装置１００の場合と同様に、第２電極接合部４１ｂは、第２電極接合部４１ｂにおけるゲートパッド２３と対向する側の面の外周領域に形成され、表面とゲートパッド２３との間の間隔が平坦部４４ｂの表面とゲートパッド２３との間の間隔よりも長くなるように構成されたフィレット形成部４５ｂを有するため、半導体装置の製造過程において、第２接続部材４０ｂの第２電極接合部４１ｂがゲートパッド２３上から位置ずれしたときにゲートパッド２３の周囲のパッシベーション膜２４に第２接続部材４０ｂの第２電極接合部４１ｂが乗り上げてしまうことを防ぐことができる。従って、第２接続部材４０ｂが熱応力等によって半導体チップ２０のパッシベーション膜２４や半導体チップ２０内部にダメージを与えることを防ぐことができ、信頼性を高くすることができる。 As described above, the semiconductor device 102 according to the third embodiment is different from the case of the semiconductor device 100 according to the first embodiment in the configuration of the fillet forming portion, but is the same as the case of the semiconductor device 100 according to the first embodiment. The two-electrode joint portion 41b is formed in the outer peripheral region of the surface of the second electrode joint portion 41b on the side facing the gate pad 23, and the distance between the surface and the gate pad 23 is the surface of the flat portion 44b and the gate pad 23. Since the fillet forming portion 45b configured to be longer than the distance between the two is provided, the second electrode joint portion 41b of the second connecting member 40b is displaced from the gate pad 23 in the manufacturing process of the semiconductor device. Occasionally, it is possible to prevent the second electrode joint portion 41b of the second connecting member 40b from riding on the passivation film 24 around the gate pad 23. Therefore, it is possible to prevent the second connecting member 40b from damaging the passivation film 24 of the semiconductor chip 20 and the inside of the semiconductor chip 20 due to thermal stress or the like, and it is possible to improve the reliability.

また、実施形態３に係る半導体装置１０２によれば、断面でみたときに平坦部４４ｂとフィレット形成部４５ｂとで階段形状を構成しているため、隣接する段差の間の空間に導電性接合材６０が入り込みやすくなり、フィレット形成部４５ｂのはんだ厚を確保し易くなる。また、フィレット形成部４５ｂと導電性接合材６０との接触面積が大きくなり、接合強度が高くなる。 Further, according to the semiconductor device 102 according to the third embodiment, since the flat portion 44b and the fillet forming portion 45b form a stepped shape when viewed in cross section, the conductive joining material is formed in the space between the adjacent steps. It becomes easy for 60 to enter, and it becomes easy to secure the solder thickness of the fillet forming portion 45b. Further, the contact area between the fillet forming portion 45b and the conductive bonding material 60 becomes large, and the bonding strength increases.

なお、実施形態３に係る半導体装置１０２は、フィレット形成部の構成以外の点においては実施形態１に係る半導体装置１００と同様の構成を有するため、実施形態１に係る半導体装置１００が有する効果のうち該当する効果を有する。 Since the semiconductor device 102 according to the third embodiment has the same configuration as the semiconductor device 100 according to the first embodiment except for the configuration of the fillet forming portion, the effect of the semiconductor device 100 according to the first embodiment can be obtained. Of these, it has the corresponding effect.

［実施形態４］
実施形態４に係る半導体装置１０３は、基本的には実施形態１に係る半導体装置１００と同様の構成を有するが、第１接続部材の構成が実施形態１に係る半導体装置１００の場合とは異なる。すなわち、実施形態４に係る半導体装置１０３においては、半導体チップ２０ａにおいて、ソースパッド２２ａは、実施形態１よりもかなり小さく、ソースパッド２２ａと接続される第１接続部材３０ａに本発明の接続部材が適用されている（図５参照）。 [Embodiment 4]
The semiconductor device 103 according to the fourth embodiment basically has the same configuration as the semiconductor device 100 according to the first embodiment, but the configuration of the first connecting member is different from the case of the semiconductor device 100 according to the first embodiment. .. That is, in the semiconductor device 103 according to the fourth embodiment, in the semiconductor chip 20a, the source pad 22a is considerably smaller than that of the first embodiment, and the connecting member of the present invention is attached to the first connecting member 30a connected to the source pad 22a. It has been applied (see Figure 5).

実施形態４において、第１電極接合部３１ａは、電極（ソースパッド２２ａ）に向かって突出し、かつ、電極（ソースパッド２２ａ）と導電性接合材６２を介して接合されている。第１電極接合部３１ａは、第１電極接合部３１ａにおける電極（ソースパッド２２ａ）と対向する側の面の少なくとも中央を含む領域に形成された平坦部３４ａと、第１電極接合部３１ａにおける電極（ソースパッド２２ａ）と対向する側の面の外周領域に形成され、表面と電極（ソースパッド２２ａ）との間の間隔が平坦部３４ａの表面と電極（ソースパッド２２ａ）との間の間隔よりも長くなるように構成されたフィレット形成部３５ａとを有し、導電性接合材６２は、電極（ソースパッド２２ａ）と平坦部３４ａの間、及び、電極（ソースパッド２２ａ）とフィレット形成部３５ａの間の両方に配置されている。 In the fourth embodiment, the first electrode bonding portion 31a protrudes toward the electrode (source pad 22a) and is bonded to the electrode (source pad 22a) via the conductive bonding material 62. The first electrode joint portion 31a has a flat portion 34a formed in a region including at least the center of the surface facing the electrode (source pad 22a) in the first electrode joint portion 31a, and an electrode in the first electrode joint portion 31a. It is formed in the outer peripheral region of the surface facing (source pad 22a), and the distance between the surface and the electrode (source pad 22a) is larger than the distance between the surface of the flat portion 34a and the electrode (source pad 22a). Also has a fillet forming portion 35a configured to be long, the conductive bonding material 62 is between the electrode (source pad 22a) and the flat portion 34a, and the electrode (source pad 22a) and the fillet forming portion 35a. It is located between both.

第１連結部３２ａは、第１電極接合部３１の一辺と連結されており、そこから水平方向に沿って封止樹脂５０の外側まで直線状に延びているとともに、中途で枝分かれして、櫛歯状に３本並行して封止樹脂５０の外側まで延びている。櫛歯状に延びる第１連結部３２ａのそれぞれの先端には、第１外部端子３３ａ、３３ｂ、３３ｃがそれぞれ形成されている。 The first connecting portion 32a is connected to one side of the first electrode joining portion 31, and extends linearly from there to the outside of the sealing resin 50 along the horizontal direction, and is branched in the middle to form a comb. Three teeth extend in parallel to the outside of the sealing resin 50. First external terminals 33a, 33b, 33c are formed at the tips of the first connecting portions 32a extending in a comb-teeth shape, respectively.

このように、実施形態４に係る半導体装置１０３は、第１接続部材の構成が実施形態１に係る半導体装置１００の場合とは異なるが、実施形態１に係る半導体装置１００の場合と同様に、第１電極接合部３１ａは、第１電極接合部３１ａにおけるソースパッド２２ａと対向する側の面の外周領域に形成され、表面とソースパッド２２ａとの間の間隔が平坦部３４ａの表面とソースパッド２２ａとの間の間隔よりも長くなるように構成されたフィレット形成部３５ａを有するため、半導体装置の製造過程において、第１接続部材３０ａの第１電極接合部３１ａがソースパッド２２ａ上から位置ずれしたときにソースパッド２２ａの周囲のパッシベーション膜２４に第１接続部材３０ａの第１電極接合部３１ａが乗り上げてしまうことを防ぐことができる。従って、第１接続部材３０ａが熱応力等によって半導体チップ２０のパッシベーション膜２４や半導体チップ２０内部にダメージを与えることを防ぐことができ、信頼性を高くすることができる。 As described above, the semiconductor device 103 according to the fourth embodiment has a different configuration of the first connecting member from the semiconductor device 100 according to the first embodiment, but is similar to the semiconductor device 100 according to the first embodiment. The first electrode joint portion 31a is formed in the outer peripheral region of the surface of the first electrode joint portion 31a on the side facing the source pad 22a, and the distance between the surface and the source pad 22a is between the surface of the flat portion 34a and the source pad. Since the fillet forming portion 35a configured to be longer than the distance from the 22a is provided, the first electrode joint portion 31a of the first connecting member 30a is displaced from the source pad 22a in the manufacturing process of the semiconductor device. At this time, it is possible to prevent the first electrode joint portion 31a of the first connecting member 30a from riding on the passivation film 24 around the source pad 22a. Therefore, it is possible to prevent the first connecting member 30a from damaging the passivation film 24 of the semiconductor chip 20 and the inside of the semiconductor chip 20 due to thermal stress or the like, and it is possible to improve the reliability.

なお、実施形態４に係る半導体装置１０３は、第１接続部材の構成以外の点においては実施形態１に係る半導体装置１００と同様の構成を有するため、実施形態１に係る半導体装置１００が有する効果のうち該当する効果を有する。 Since the semiconductor device 103 according to the fourth embodiment has the same configuration as the semiconductor device 100 according to the first embodiment except for the configuration of the first connecting member, the effect of the semiconductor device 100 according to the first embodiment is obtained. Has the corresponding effect.

以上、本発明を上記の実施形態に基づいて説明したが、本発明は上記の実施形態に限定されるものではない。その趣旨を逸脱しない範囲において種々の態様において実施することが可能であり、例えば、次のような変形も可能である。 Although the present invention has been described above based on the above embodiment, the present invention is not limited to the above embodiment. It can be carried out in various embodiments within a range that does not deviate from the purpose, and for example, the following modifications are also possible.

（１）上記実施形態において記載した構成要素の数、材質、形状、位置、大きさ等は例示であり、本発明の効果を損なわない範囲において変更することが可能である。 (1) The number, material, shape, position, size, etc. of the constituent elements described in the above embodiment are examples, and can be changed as long as the effects of the present invention are not impaired.

（２）上記実施形態１においては、フィレット形成部において、第２電極接合部の側面の途中から傾斜面を形成したが、本発明はこれに限定されるものではない。フィレット形成部において、第２電極接合部の側面全てを傾斜面としてもよい（変形例１に係る半導体装置１０４。図６のフィレット形成部４５ｃ参照）。 (2) In the first embodiment, the fillet forming portion forms an inclined surface from the middle of the side surface of the second electrode joint portion, but the present invention is not limited to this. In the fillet forming portion, all the side surfaces of the second electrode joint portion may be inclined surfaces (semiconductor device 104 according to the first modification; see the fillet forming portion 45c in FIG. 6).

（３）上記各実施形態においては、平面的に見て矩形形状の平坦部４４の周囲を囲うように４辺全てにフィレット形成部４５を形成したが、本発明はこれに限定されるものではない。平面的に見て矩形形状の平坦部４４の周囲を囲う４辺のうち１辺、２辺又は３辺にフィレット形成部を形成してもよい（３辺の場合、変形例２に係る半導体装置１０５。図７のフィレット形成部４５ｄ参照）。 (3) In each of the above embodiments, the fillet forming portions 45 are formed on all four sides so as to surround the periphery of the rectangular flat portion 44 when viewed in a plane, but the present invention is not limited thereto. do not have. A fillet-forming portion may be formed on one side, two sides, or three sides of the four sides surrounding the rectangular flat portion 44 when viewed in a plane (in the case of three sides, the semiconductor device according to the modified example 2). 105. See fillet forming portion 45d in FIG. 7).

（４）上記各実施形態においては、フィレット形成部を、平面的に見て矩形形状の電極接合部の外周領域の各辺に沿って形成したが、本発明はこれに限定されるものではない。平面的に見て矩形形状の電極接合部の外周領域の各角部にフィレット形成部を形成してもよい（変形例３に係る半導体装置１０６。図８の電極接合部４１ｅ参照）。電極接合部の角部が電極の外縁に近い形状（例えば、電極が円形状の場合）の場合には、上記した構成とすることにより平坦部４４ｅとパッシベーション膜との間の距離を長くすることができ、接続部材が電極上から位置ずれした場合であってもパッシベーション膜に乗り上げ難くなる。 (4) In each of the above embodiments, the fillet forming portion is formed along each side of the outer peripheral region of the rectangular electrode joint portion when viewed in a plane, but the present invention is not limited thereto. .. Fillet-forming portions may be formed at each corner of the outer peripheral region of the rectangular electrode junction when viewed in a plane (semiconductor device 106 according to Modification 3; see the electrode junction 41e in FIG. 8). When the corner of the electrode joint has a shape close to the outer edge of the electrode (for example, when the electrode has a circular shape), the distance between the flat portion 44e and the passivation film should be increased by adopting the above configuration. Even if the connecting member is displaced from the electrode, it becomes difficult to ride on the passivation film.

（５）上記各実施形態においては、基板として、リードフレームからなる基板を用いたが、本発明はこれに限定されるものではない。一般的なプリント基板等適宜の基板を用いてもよい。 (5) In each of the above embodiments, a substrate made of a lead frame is used as the substrate, but the present invention is not limited thereto. An appropriate substrate such as a general printed circuit board may be used.

２０…半導体チップ、２２…ソースパッド、２３…ゲートパッド、３０，３０ａ…第１接続部材、３１，３１ａ…第１電極接合部、３４ａ，４４，４４ａ，４４ｂ，４４ｃ、４４ｄ…平坦部、３５ａ，４５，４５ａ，４５ｂ，４５ｃ、４５ｄ…フィレット形成部、４０，４０ａ，４０ｂ，４０ｃ，４０ｄ，４０ｅ…第２接続部材、４１，４１ａ，４１ｂ，４１ｃ，４１ｄ，４１ｅ…第２電極接合部、６０，６２…導電性接合材、１００，１０１，１０２，１０３，１０４，１０５，１０６，９００…半導体装置 20 ... Semiconductor chip, 22 ... Source pad, 23 ... Gate pad, 30, 30a ... First connection member, 31, 31a ... First electrode joint, 34a, 44, 44a, 44b, 44c, 44d ... Flat portion, 35a , 45, 45a, 45b, 45c, 45d ... Fillet forming portion, 40, 40a, 40b, 40c, 40d, 40e ... Second connecting member, 41, 41a, 41b, 41c, 41d, 41e ... Second electrode joint, 60, 62 ... Conductive bonding material, 100, 101, 102, 103, 104, 105, 106, 900 ... Semiconductor device

Claims (11)

電極を有する半導体チップと、
導電性の板状部材で構成され、前記電極に向かって突出し、かつ、前記電極と導電性接合材を介して接合される電極接合部を有する接続部材とを備え、
前記電極接合部は、前記電極接合部における前記電極と対向する側の面の少なくとも中央を含む領域に形成された平坦部と、前記電極接合部における前記電極と対向する側の面の外周領域に形成され、表面と前記電極との間の間隔が前記平坦部の表面と前記電極との間の間隔よりも長くなるように構成されたフィレット形成部とを有し、
前記導電性接合材は、前記電極と前記平坦部の間、及び、前記電極と前記フィレット形成部の間の両方に配置されていることを特徴とする半導体装置。 A semiconductor chip with electrodes and
It is composed of a conductive plate-shaped member, and includes a connecting member that protrudes toward the electrode and has an electrode joining portion that is joined to the electrode via a conductive joining material.
The electrode joint portion is formed in a flat portion formed in a region including at least the center of the surface of the electrode joint portion on the side facing the electrode, and an outer peripheral region of the surface of the electrode joint portion on the side facing the electrode. It has a fillet-forming portion that is formed and configured such that the distance between the surface and the electrode is greater than the distance between the surface of the flat portion and the electrode.
A semiconductor device characterized in that the conductive bonding material is arranged both between the electrode and the flat portion and between the electrode and the fillet forming portion. 前記電極接合部は、前記平坦部側が狭いテーパ形状をしていることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the electrode joint portion has a narrow tapered shape on the flat portion side. 前記フィレット形成部における前記電極と対向する側の面は、前記平坦部から斜めに延びる傾斜面であることを特徴とする請求項２に記載の半導体装置。 The semiconductor device according to claim 2, wherein the surface of the fillet-forming portion on the side facing the electrode is an inclined surface extending obliquely from the flat portion. 前記フィレット形成部における前記電極と対向する側の面は、前記平坦部と繋がる曲面であることを特徴とする請求項２に記載の半導体装置。 The semiconductor device according to claim 2, wherein the surface of the fillet forming portion on the side facing the electrode is a curved surface connected to the flat portion. 断面でみたときに前記平坦部と前記フィレット形成部とで階段形状を構成していることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the flat portion and the fillet forming portion form a staircase shape when viewed in cross section. 前記電極は、ゲートパッドであることを特徴とする請求項１～５のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 5, wherein the electrode is a gate pad. 前記電極接合部における前記電極と対向する側の面には、メッキが施されていないことを特徴とする請求項１～６のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 6, wherein the surface of the electrode joint portion on the side facing the electrode is not plated. 断面でみたときに前記平坦部の幅は、前記電極の幅の０．４倍～０．６倍の範囲内にあることを特徴とする請求項１～７のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 7, wherein the width of the flat portion is in the range of 0.4 times to 0.6 times the width of the electrode when viewed in cross section. 断面で見たときに前記フィレット形成部の幅は、前記平坦部の幅の０．２倍～０．４倍の範囲内にあることを特徴とする請求項１～８のいずれかに記載の半導体装置。 The aspect according to any one of claims 1 to 8, wherein the width of the fillet-forming portion is in the range of 0.2 times to 0.4 times the width of the flat portion when viewed in cross section. Semiconductor device. 前記平坦部の高さ位置を基準としたときの、前記電極接合部の外縁の位置における前記フィレット形成部の表面の高さをＨとし、前記平坦部が形成されている領域における前記電極接合部の厚さをＴとすると、０．２５×Ｔ≦Ｈを満たすことを特徴とする請求項１～９のいずれかに記載の半導体装置。 Let H be the height of the surface of the fillet forming portion at the position of the outer edge of the electrode joining portion with respect to the height position of the flat portion, and the electrode joining portion in the region where the flat portion is formed. The semiconductor device according to any one of claims 1 to 9, wherein the thickness is T, and 0.25 × T ≦ H is satisfied. 導電性の板状部材で構成され、
一方向に向かって突出し、かつ、半導体チップの電極と導電性接合材を介して接合される電極接合部を有し、
前記電極接合部は、前記半導体チップの前記電極と前記導電性接合材を介して接合したときに前記電極接合部における前記電極と対向する側の面の少なくとも中央を含む領域に形成された平坦部と、前記電極接合部における前記電極と対向する側の面の外周領域に形成され、表面と前記電極との間の間隔が前記平坦部の表面と前記電極との間の間隔よりも長くなるように構成されたフィレット形成部とを有することを特徴とする接続部材。 Consists of conductive plate-shaped members,
It has an electrode junction that projects in one direction and is bonded to the electrodes of the semiconductor chip via a conductive bonding material.
The electrode bonding portion is a flat portion formed in a region including at least the center of the surface of the electrode bonding portion on the side facing the electrode when the electrode is bonded to the electrode of the semiconductor chip via the conductive bonding material. And so that the distance between the surface and the electrode is longer than the distance between the surface of the flat portion and the electrode. A connecting member having a fillet forming portion configured in the above.
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