JP2022081380A - Gate drive circuit and control method for gate drive circuit - Google Patents

Abstract

To provide a gate drive circuit, capable of being applied with a negative bias while keeping isolation between a high voltage circuit and a low voltage circuit, and capable of miniaturization in low cost.SOLUTION: A gate drive circuit includes a transmission circuit 10 for transferring a gate signal and power, a first transformer Tr1 whose primary winding is connected to the transmission circuit 10, and a first stage drive circuit 11 to nth stage drive circuit 1n for controlling each of semiconductor devices 1 to n connected in series with n pieces. When a gate command is high, the first stage drive circuit 11 to the nth stage drive circuit 1n respectively connects a first power supply capacitor C11 to a target semiconductor device to be driven in parallel by controlling first to fifth switch devices FET1 to FET5. When the gate command for the target semiconductor device to be driven is low, a second power supply capacitor C21 is connected to the target semiconductor device to be driven in reverse parallel by controlling the first to fifth switch devices FET1 to FET5.SELECTED DRAWING: Figure 1

Description

The present invention relates to a gate drive circuit for driving semiconductor devices connected in series.

In the pulse power supply as described in Patent Document 1, a plurality of semiconductor devices are connected in series in order to increase the withstand voltage. FIG. 16 shows a circuit configuration diagram of Patent Document 1 (left: gate amplifier circuit, right: overall configuration diagram). As shown in FIG. 16, in Patent Document 1, an optical fiber is used to insulate a semiconductor element on the high voltage side and a control circuit on the low voltage side, and a semiconductor device is driven by driving a gate amplifier.

Japanese Unexamined Patent Publication No. 03-237811

In this case, since a negative voltage cannot be applied when the gate is off, if the threshold voltage of the gate voltage is low as in SiC- MOSFET, there is a risk of erroneous arc, short circuit occurs, and voltage sharing becomes uneven, and the device becomes There is a risk of damage.

Further, since the gate amplifier needs to be connected in parallel with the semiconductor device to be driven, elements such as a transistor (reference numeral 33 in Patent Document 1) constituting the gate amplifier have a withstand voltage equivalent to that of the semiconductor element to be driven. It is necessary to have it, and there is a problem that it is expensive and large in size.

From the above, it is an issue that the gate drive circuit can apply a negative bias while maintaining the insulation between the high-voltage circuit and the low-voltage circuit, and can be reduced in size at low cost.

The present invention has been devised in view of the above-mentioned conventional problems, and one aspect thereof is a gate drive circuit of n semiconductor devices connected in series, a transmission unit for transmitting a gate signal and power, and a transmission unit. A transformer unit having a first transformer to which a primary winding is connected to the transmission unit and a drive circuit unit having a first-stage drive circuit to an n-stage drive circuit for controlling n semiconductor devices are provided. The first-stage drive circuit to the n-th stage drive circuit have a plurality of switch devices and first and second stages between the secondary winding and the tertiary winding of the first transformer and the semiconductor device to be driven, respectively. It has a power supply capacitor, and when the gate command of the semiconductor device to be driven is high, the plurality of switch devices are controlled to connect the first power supply capacitor in parallel to the semiconductor device to be driven, and the drive target is When the gate command of the semiconductor device is low, the plurality of switch devices are controlled to connect the second power supply capacitor in antiparallel to the semiconductor device to be driven.

Further, as one aspect thereof, the transmission unit is connected between the input diode, the first full bridge circuit connected to the input diode, the first full bridge circuit, and the primary winding of the first transformer. Each of the first-stage drive circuit to the n-th stage drive circuit is provided with a transmission circuit having a first DC cut diode, and an anode is connected to one end of a secondary winding of the first transformer. A first diode, a second diode having an anode connected to the other end of the secondary winding of the first transformer, and a third diode having an anode connected to the cathode of the first diode and the cathode of the second diode. A first and second power supply capacitors connected in series between the cathode of the third diode and the midpoint of the tertiary winding of the first transformer, and an anode at one end of the tertiary winding of the first transformer. A connected fourth diode, a fifth diode having an anode connected to the other end of the tertiary winding of the first transformer, an anode connected to the cathode of the fourth diode and the cathode of the fifth diode, and a cathode. Is connected to the connection point of the first and second power supply diodes and the connection point of the fourth, fifth, and sixth diodes, and one end is connected to the third winding of the first transformer. The first resistor having the other end connected to the point and the first terminal are connected to the connection points of the first, second, and third diodes, and the second terminal is the connection between the third diode and the first power supply capacitor. A first switch device connected to a point and having a third terminal connected to the first terminal of the semiconductor device to be driven, and a first terminal connected to a connection point of the first, second, and third diodes. The second terminal is connected to the first terminal of the semiconductor device to be driven, the third terminal is connected to the midpoint of the tertiary winding of the first transformer, and the second terminal is the first terminal. , The third switch device connected to the connection point of the second and third diodes and the third terminal connected to the middle point of the tertiary winding of the first transformer, and the first terminal is the fourth, fifth and fifth. A fourth switch device connected to a connection point of the sixth diode, a second terminal connected to the cathode of the sixth diode, and a third terminal connected to the first terminal of the third switch device, and a first terminal. Is connected to the connection point of the 4th, 5th, 5th and 6th diodes, the 2nd terminal is connected to the 1st terminal of the 3rd switch device, and the 3rd terminal is the middle point of the tertiary winding of the 1st transformer. Equipped with a 5th switch device connected to the diode The third terminal of the semiconductor device to be operated is characterized in that it is connected to the connection point of the first and second power supply capacitors and the midpoint of the secondary winding of the first transformer.

As another aspect, the transformer unit includes the first transformer and the second transformer, and the transmission unit includes an input diode, a first full bridge circuit connected to the input diode, and the first. An ON-side transmission circuit having a first DC cut diode connected between the full bridge circuit and the primary winding of the first transformer, a second full bridge circuit connected to the input diode, and the above. The OFF side transmission circuit including a second DC cut diode connected between the second full bridge circuit and the primary winding of the second transformer is provided, and the drive circuit unit is the first stage. The drive circuit to the nth stage drive circuit and the first stage OFF side drive circuit to the nth stage OFF side drive circuit are provided, and the first stage drive circuit to the nth stage drive circuit are each of the first transformer. A first diode having an anode connected to one end of the secondary winding, a second diode having an anode connected to the other end of the secondary winding of the first transformer, a cathode of the first diode, and the second diode. A third diode having an anode connected to the cathode of the diode, first and second power supply capacitors connected in series between the cathode of the third diode and the midpoint of the tertiary winding of the first transformer, and the above. A fourth diode having an anode connected to one end of the tertiary winding of the first transformer, a fifth diode having an anode connected to the other end of the tertiary winding of the first transformer, a cathode of the fourth diode, and the above. An anode is connected to the cathode of the 5th diode, and one end is connected to the connection point of the 6th diode whose cathode is connected to the connection point of the 1st and 2nd power supply capacitors and the connection point of the 4th, 5th and 6th diodes. A first resistor having the other end connected to the middle point of the tertiary winding of the first transformer, and a second resistor having one end connected to the connection point of the first, second, and third diodes. One terminal is connected to the other end of the second resistor, the second terminal is connected to the connection point between the third diode and the first power supply capacitor, and the third terminal is connected to the first terminal of the semiconductor device to be driven. The connected first switch device and the first terminal are connected to the other end of the second resistor, the second terminal is connected to the first terminal of the semiconductor device to be driven, and the third terminal is the first transformer. The second switch device connected to the midpoint of the tertiary winding of the above, the second terminal is connected to the other end of the second resistor, and the third terminal is connected to the midpoint of the tertiary winding of the first transformer. The third switch device and the anode are the third switch. A seventh diode connected to the first terminal of the device and having a cathode connected to the cathode of the sixth diode, and a first terminal connected to a connection point of the fourth, fifth, and sixth diodes, and a third terminal. The third terminal of the semiconductor device to be driven includes a fifth switch device connected to the middle point of the tertiary winding of the first transformer, and the third terminal of the semiconductor device to be driven is a connection point of the first and second power supply capacitors and the first. The diode is connected to one end of the secondary winding of the second transformer in each of the first stage OFF side drive circuit to the nth stage OFF side drive circuit, which is connected to the middle point of the secondary winding of the first transformer. An eighth diode having a cathode connected to the connection point between the third diode and the first power supply capacitor, and an anode connected to the other end of the secondary winding of the second transformer, the third diode and the first diode. A ninth diode having a cathode connected to the connection point of the power supply capacitor, and a tenth diode having an anode connected to one end of the tertiary winding of the second transformer and a cathode connected to the first terminal of the third switch device. An eleventh diode having an anode connected to the other end of the tertiary winding of the second transformer and a cathode connected to the first terminal of the third switch device, and a secondary winding of the second transformer. That the midpoint of the wire was connected to the midpoint of the secondary winding of the first transformer, and the midpoint of the tertiary winding of the second transformer was connected to the midpoint of the tertiary winding of the first transformer. It is a feature.

Further, as one aspect thereof, a third resistance is connected between the second terminal of the fifth switch device and the first terminal of the third switch device.

Further, as one aspect thereof, a first voltage adjusting mechanism is provided between the first switch device and the first power supply capacitor, and a second voltage adjusting mechanism is provided between the second switch device and the second power supply capacitor. It is characterized by the provision of.

Further, as one aspect thereof, in the first and second voltage adjusting mechanisms, the second terminal is connected to the first power supply capacitor or the second power supply capacitor, and the third terminal is the first switch device or the second power supply capacitor. A semiconductor element connected to a switch device, a reference voltage having one end connected to a connection point of the first and second power supply capacitors, a sixth resistor connected to one end of the reference voltage, and the sixth resistance. Output using the 7th resistor connected between the other end and the 1st switch device or the 2nd switch device, and the connection point between the other end of the reference voltage and the 6th and 7th resistors as input terminals. The terminal is provided with an amplifier circuit in which the terminal is connected to the first terminal of the semiconductor element.

Further, as one aspect thereof, the first and second full bridge circuits are connected in series between the first and second semiconductor switches connected in series between both ends of the input capacitor and the third in series between both ends of the input capacitor. , The fourth semiconductor switch, and the connection point of the third and fourth semiconductor switches is one end of the primary winding of the first transformer or the connection point of the first DC cut capacitor via the first DC cut capacitor or the second DC cut capacitor. It is connected to one end of the primary winding of the second transformer, and the connection point of the first and second semiconductor switches is connected to the other end of the primary winding of the first transformer or the other end of the primary winding of the second transformer. When the voltage of the first and second DC cut capacitors is positive, the control circuit turns on the first and fourth semiconductor switches, turns off the second and third semiconductor switches, and turns off the first. When the voltage of the second DC cut capacitor is negative, the first and fourth semiconductor switches are turned off, and the second and third semiconductor switches are turned on.

Further, as one aspect thereof, the voltage of the first and second DC cut capacitors is characterized by being a value subjected to a low-pass filter process or a moving average process.

Further, as one aspect thereof, the timing of sampling the voltage of the first and second DC cut capacitors is the timing of the apex of the carrier, and the switching timing of the first to fourth semiconductor switches is the 0 cross of the carrier. It is characterized by timing.

As another aspect, the first and second full bridge circuits are connected in series between the first and second semiconductor switches connected in series between both ends of the input capacitor and the third in series between both ends of the input capacitor. , The fourth semiconductor switch, and the connection point of the third and fourth semiconductor switches is one end of the primary winding of the first transformer or the connection point of the first DC cut capacitor via the first DC cut capacitor or the second DC cut capacitor. It is connected to one end of the primary winding of the second transformer, and the connection point of the first and second semiconductor switches is connected to the other end of the primary winding of the first transformer or the other end of the primary winding of the second transformer. The control circuit samples and holds the phase information of the output of the voltage control type transmitter that controls the transmission frequency by the input voltage and the voltage control type transmitter when the gate command is off, and uses it as sample phase information. The output sample hold circuit and the phase that outputs 2π as the phase command value when the sample phase information is π or more and less than 2π, and outputs 0 as the phase command value when the sample phase information is 0 or more and less than π. The voltage control type includes a determination unit, a PI controller that performs PI control based on the phase command value and the sample phase information, and outputs a voltage as a result of the PI control to the voltage control type transmitter. When the output of the transmitter is positive, the first and fourth semiconductor switches are turned on, the second and third semiconductor switches are turned off, and when the output of the voltage control type transmitter is negative, the first and first semiconductor switches are turned on. The fourth semiconductor switch is turned off, and the second and third semiconductor switches are turned on.

Further, as one aspect thereof, the control circuit includes a capacitor voltage feedback unit that performs PI control based on the difference between the voltage command value and the voltage detection value of the first DC cut capacitor or the second DC cut capacitor. The PI controller is characterized in that PI control is performed based on a value obtained by subtracting the sample phase information from a value obtained by adding the phase command value and the output of the capacitor voltage feedback unit.

As another aspect, the control circuit includes a capacitor current feedback unit that performs PI control based on the difference between the current command value and the current detection value of the first DC cut capacitor or the second DC cut capacitor. The PI controller is characterized in that PI control is performed based on a value obtained by subtracting the sample phase information from a value obtained by adding the phase command value and the output of the capacitor current feedback unit.

Further, as one aspect thereof, the voltage control type transmitter has an eighth resistor having one end connected to an input terminal, a ninth resistor having one end connected to an input terminal, and one to the other end of the eighth resistor. The first comparator to which the input terminal of the first comparator is connected and the other input terminal is connected to the other end of the ninth resistor, and the capacitor connected between one input terminal and the output terminal of the first comparator. A tenth resistor having one end connected to one input terminal of the first comparator, a semiconductor switch having a second terminal connected to the other end of the tenth resistor and the third terminal grounded, and the first comparator. The eleventh resistor connected between the other input terminal of the semiconductor switch and the third terminal of the semiconductor switch, the second comparator to which one input terminal is connected to the output of the first comparator, and the second comparator. A twelfth resistor having one end connected to the other input terminal and the other end grounded, a thirteenth resistor connected between the output terminal of the second comparator and the other input terminal, and a third resistor of the semiconductor device. It is characterized by including a 14th resistor connected between the 1 terminal and the output terminal of the 2nd comparator, and a duty ratio correction unit that corrects the duty ratio according to the output of the 2nd comparator. ..

According to the present invention, in the gate drive circuit, it is possible to apply a negative bias while maintaining the insulation between the high voltage circuit and the low voltage circuit, and it is possible to realize miniaturization at low cost.

The circuit block diagram which shows the gate drive circuit in Embodiment 1. FIG. The figure which shows the operation example of Embodiment 1. FIG. The circuit block diagram which shows the gate drive circuit in Embodiment 2. The figure which shows the operation example of Embodiment 2. The circuit block diagram which shows the gate drive circuit in Embodiment 3. The figure which shows the configuration example of a regulator. The figure which shows the influence on the operation of the capacitor voltage Vc for DC cut. The block diagram of the control circuit in Embodiment 4. The block diagram of the control circuit in Embodiment 5. The block diagram of the control circuit in Embodiment 6. The block diagram of the control circuit in Embodiment 7. The figure which shows the structural example of VCO. The figure which shows the characteristic example of a VCO. The block diagram of the control circuit in Embodiment 8. The block diagram of the control circuit in Embodiment 9. The circuit block diagram of Patent Document 1.

Hereinafter, embodiments 1 to 9 of the gate drive circuit according to the present invention will be described in detail with reference to FIGS. 1 to 15.

[Embodiment 1]
FIG. 1 shows a circuit configuration example of the gate drive circuit according to the first embodiment. FIG. 1 shows a configuration in which n semiconductor devices 1 to n to be driven are connected in series, and n is an arbitrary natural number (1, 2, 3 ... n). The gate drive circuit includes a transmission unit that transmits a gate signal and power, a transformer unit that has a first transformer Tr1, and a first-stage drive circuit 11 to n-th stage drive circuit 1n that controls n semiconductor devices, respectively. It is equipped with a drive circuit unit. The configurations of the first-stage drive circuit 11 to the n-th stage drive circuit 1n are the same.

The transmission unit of the first embodiment includes a transmission circuit 10. In the transmission circuit 10, the first and second semiconductor switches S1 and S2 are connected in series between both ends of the input capacitor Vin. Further, the third and fourth semiconductor switches S3 and S4 are connected in series between both ends of the input capacitor Vin. The first to fourth semiconductor switches S1 to S4 are used as the first full bridge circuit. One end of the first DC cut capacitor C1 is connected to the connection points of the third and fourth semiconductor switches S3 and S4, and one end of the primary winding of the first transformer Tr1 is connected to the other end of the first DC cut capacitor C1. Is connected. The connection points of the first and second semiconductor switches S1 and S2 are connected to the other end of the primary winding of the first transformer Tr1. The switching patterns of the first to fourth semiconductor switches S1 to S4 are generated based on the gate command of the semiconductor devices 1 to n to be driven.

In the first stage drive circuit 11, the anode of the first diode D1 is connected to one end of the secondary winding of the first transformer Tr1. The anode of the second diode D2 is connected to the other end of the secondary winding of the first transformer Tr1. The anode of the third diode D3 is connected to the cathode of the first diode D1 and the cathode of the second diode D2. The first and second power supply capacitors C11 and C21 are connected in series between the cathode of the third diode D3 and the midpoint of the tertiary winding of the first transformer Tr1.

The anode of the fourth diode D4 is connected to one end of the tertiary winding of the first transformer Tr1. The anode of the fifth diode D5 is connected to the other end of the tertiary winding of the first transformer Tr1. The anode of the sixth diode D6 is connected to the cathode of the fourth diode D4 and the cathode of the fifth diode D5. The cathode of the sixth diode D6 is connected to the connection points of the first and second power supply capacitors C11 and C21. One end of the first resistor R1 is connected to the connection points of the fourth, fifth, and sixth diodes D4, D5, and D6, and the other end is connected to the midpoint of the tertiary winding of the first transformer Tr.

In the first switch device FET1, the first terminal (gate terminal) is connected to the connection point of the first, second and third diodes D1, D2, D3, and the second terminal (drain terminal) is connected to the third diode D3. 1 It is connected to the connection point of the power supply capacitor C11, and the third terminal (source terminal) is connected to the first terminal (gate terminal) of the semiconductor device 1 to be driven.

In the second switch device FET 2, the first terminal (gate terminal) is connected to the connection point of the first, second and third diodes D1, D2, D3, and the second terminal (drain terminal) is the semiconductor device 1 to be driven. It is connected to the first terminal (gate terminal) of the above, and the third terminal (source terminal) is connected to the midpoint of the tertiary winding of the first transformer Tr.

In the third switch device FET3, the second terminal (drain terminal) is connected to the connection point of the first, second and third diodes D1, D2, D3, and the third terminal (source terminal) is the tertiary of the first transformer Tr. Connected to the midpoint of the winding.

In the fourth switch device FET4, the first terminal (gate terminal) is connected to the connection points of the fourth, fifth, and sixth diodes D4, D5, and D6, and the second terminal (drain terminal) is the cathode of the sixth diode D6. The third terminal (source terminal) is connected to the first terminal (gate terminal) of the third switch device FET3.

In the fifth switch device FET 5, the first terminal (gate terminal) is connected to the connection points of the fourth, fifth, and sixth diodes D4, D5, and D6, and the second terminal (drain terminal) is the third switch device FET 3. It is connected to the first terminal (gate terminal), and the third terminal (source terminal) is connected to the midpoint of the tertiary winding of the first transformer Tr. The third terminal (source terminal) of the semiconductor device to be driven is connected to the midpoint of the secondary windings of the first and second power supply capacitors C11 and C21 and the first transformer Tr1.

The second-stage drive circuit 12 to n-th stage drive circuit 1n is the same as the first-stage drive circuit 11.

In the transmission circuit 10, the gate command and power are transmitted from the first stage drive circuit 11 to the nth stage drive circuit 1n, and the power supply capacitors C11 of the first stage drive circuit 11 and the power supply capacitors C1n of the nth stage drive circuit 1n are transmitted. At the same time as charging C2n, the conduction state of the semiconductor devices 1 to n to be driven is controlled.

The charging voltage of the first power supply capacitors C11 to C1n and the second power supply capacitors C21 to C2n should be set to arbitrary values by changing the turns ratio of the primary winding, the secondary winding and the tertiary winding of the first transformer Tr. Is possible. Further, by using the first transformer Tr, it is possible to electrically insulate the high voltage side and the low voltage side.

Further, in general, the voltage applied to the gate is a voltage that is several tenths of the withstand voltage between the drain and the source. Since the voltage applied to the first power supply capacitors C11 to C1n and the second power supply capacitors C21 to C2n is set by the voltage applied to the gate, the withstand voltage of the constituent first to fifth switch devices FET1 to FET5 is also lowered accordingly. Since it can be set, cost reduction and miniaturization can be realized as compared with Patent Document 1.

The first-stage to nth-stage drive circuits 11 to 1n operate so as to conduct the semiconductor devices 1 to n to be driven while the transmission circuit 10 is operating, and are driven when the operation of the transmission circuit 10 is stopped. It operates so as to turn off the target semiconductor devices 1 to n. The operation chart is shown in FIG. Hereinafter, the ON / OFF operation of the semiconductor device 1 to be driven will be focused on and described.

When the gate command of the semiconductor device 1 to be driven becomes high, the transmission circuit 10 starts operation and transmits electric power to the first stage drive circuit 11. Then, the first switch device FET 1 and the fifth switch device FET 5 are conductive, the first power supply capacitor C11 is connected in parallel to the semiconductor device 1 to be driven, and the semiconductor device 1 to be driven is conductive.

When the gate command of the semiconductor device 1 to be driven becomes low, the transmission circuit 10 stops operating, and power transmission to the first-stage drive circuit 11 is stopped. Then, the second, third, and fourth switch devices FET2, FET3, and FET4 are conductive, and the second power supply capacitor C21 is connected in antiparallel to the semiconductor device 1 to be driven, and the charging voltage of the second power supply capacitor C21 is combined. Since the same voltage is applied as a negative voltage, the semiconductor element device 1 to be driven is turned off. Since the second-stage to n-th stage drive circuits 12 to 1n also operate in the same manner, it is possible to control ON / OFF of the semiconductor devices 2 to n to be driven.

Therefore, it is possible to realize a bipolar output, a negative bias can be applied, and an inexpensive and compact gate drive circuit can be realized while maintaining the insulation between the high voltage circuit and the low voltage circuit.

[Embodiment 2]
FIG. 3 shows a circuit configuration example of the gate drive circuit according to the second embodiment. FIG. 3 shows a configuration in which n semiconductor devices 1 to n to be driven are connected in series, and n is an arbitrary natural number (1, 2, 3, ..., N).

In FIG. 3, A1, B1, C1, D1, ..., An, Bn, Cn, and Dn represent wiring connection destinations, A1 is connected to A1, B1 is connected to B1, and so on.

The transformer unit of the second embodiment includes a first transformer Tr1 and a second transformer Tr2. The transmission circuit unit includes an ON side transmission circuit 10a and an OFF side transmission circuit 10b. The drive circuit unit includes the 1st stage ON side drive circuit (1st stage drive circuit) 11a to the nth stage ON side drive circuit (nth stage drive circuit) 1na and the 1st stage OFF side drive circuit 11b to nth stage. The OFF side drive circuit 1nb is provided.

The configurations of the 1st stage ON side drive circuit 11a and the 2nd stage to nth stage ON side drive circuits 12a to 1na are the same, and the 1st stage OFF side drive circuit 11b and the 2nd stage to nth stage OFF side are the same. The configurations of the drive circuits 12b to 1nb are the same. The second embodiment is characterized in that the on command and the off command of the semiconductor devices 1 to n to be driven are transmitted separately. As a result, it is possible to control the on and off of the semiconductor devices 1 to n to be driven without depending on the characteristics of the constituent elements, so that the operation can be performed at a higher speed than that of the first embodiment.

As shown in FIG. 3, the ON side transmission circuit 10a is the same as the transmission circuit 10 of the first embodiment. The switching patterns of the first to fourth semiconductor switches S1 to S4 are generated based on the gate ON command of the semiconductor devices 1 to n to be driven.

In the OFF side transmission circuit 10b, the first and second semiconductor switches S1c and S2c are connected in series between both ends of the input capacitor Vin. Further, the third and fourth semiconductor switches S3c and S4c are connected in series between both ends of the input capacitor Vin. One end of the second DC cut capacitor C2 is connected to the connection points of the third and fourth semiconductor switches S3c and S4c. One end of the primary winding of the second transformer Tr2 is connected to the other end of the second DC cut capacitor C2. The connection points of the first and second semiconductor switches S1c and S2c are connected to the other end of the primary winding of the second transformer Tr2.

The switching patterns of the first to fourth semiconductor switches S1c to S4c are generated based on the gate OFF command of the semiconductor devices 1 to n to be driven.

Next, only the difference between the first-stage ON side drive circuit 11a and the first-stage drive circuit 11 of the first stage will be described. A second resistor R2 is connected between the connection points of the first, second and third diodes D1, D2 and D3 and the first terminal (gate terminal) of the first and second switch devices FET1 and FET2. .. Further, a seventh diode D7 is provided instead of the fourth switch device FET4. The anode of the 7th diode D7 is connected to the 1st terminal (gate terminal) of the 3rd switch device FET3, and the cathode of the 7th diode D7 is connected to the cathode of the 6th diode D6. Further, a third resistor R3 is connected between the first terminal (gate terminal) of the third switch device FET 3 and the second terminal (drain terminal) of the fifth switch device FET 5. The third resistor R3 may be omitted. When the third resistance R3 is omitted, it operates as a short circuit.

In the first-stage OFF drive circuit 11b, the anode of the eighth diode D8 is connected to one end of the secondary winding of the second transformer Tr2. The anode of the ninth diode D9 is connected to the other end of the secondary winding of the second transformer Tr2. The cathode of the 8th diode D8 and the cathode of the 9th diode D9 are connected, and the connection point is D1. D1 is connected to the connection point between the third diode D3 and the first power supply capacitor C11. Further, the midpoint of the secondary winding of the second transformer Tr2 is C1. C1 is connected to the midpoint of the secondary winding of the first transformer Tr1.

The anode of the 10th diode D10 is connected to one end of the tertiary winding of the second transformer Tr2. The anode of the 11th diode D11 is connected to the other end of the tertiary winding of the second transformer Tr2. The cathode of the 10th diode D10 and the cathode of the 11th diode D11 are connected, and the connection point is A1. A1 is connected to the first terminal (gate terminal) of the third switch device FET3. Further, the midpoint of the tertiary winding of the second transformer Tr2 is B1. B1 is connected to the midpoint of the tertiary winding of the first transformer Tr1.

In the ON side transmission circuit 10a, the gate ON command and power are transmitted from the first stage ON side drive circuit 11a to the nth stage ON side drive circuit 1na, and the first power supply capacitor C11, No. 1 of the first stage ON side drive circuit 11a. 2 From the power supply capacitor C21, the first power supply capacitor C1n and the second power supply capacitor C2n of the nth stage ON side drive circuit 1na are charged, and at the same time, the semiconductor devices 1 to n to be driven are controlled to be in a conductive state.

In the OFF side transmission circuit 10b, the gate OFF command and power are transmitted from the first stage OFF side drive circuit 11b to the nth stage OFF side drive circuit 1nb, and the first power supply capacitors C11 and 2 of the first stage ON side drive circuit 11a are transmitted. The first power supply capacitor C1n and the second power supply capacitor C2n of the nth stage ON side drive circuit 1na from the power supply capacitor C21 are charged, and at the same time, the semiconductor devices 1 to n to be driven are controlled to be in a non-conducting state.

The charging voltage of the first power supply capacitor C11 to the first power supply capacitor C1n and the second power supply capacitor C21 to the second power supply capacitor C2n is the primary winding, the secondary winding and the tertiary winding of the first and second transformers Tr1 and Tr2. It is possible to set any value by changing the turns ratio. Further, by using the first and second transformers Tr1 and Tr2, it is possible to electrically insulate the high voltage side and the low voltage side.

Further, in general, the voltage applied to the gate is a voltage that is several tenths of the withstand voltage between the drain and the source. Since the voltage applied to the first power supply capacitors C11 to C1n and the second power supply capacitors C21 to C2n is set by the voltage applied to the gate, the first to third and fifth switch devices FET1 to FET3 and FET5 to be configured are set. Since the withstand voltage can be set low accordingly, cost reduction and miniaturization can be realized as compared with Patent Document 1.

The 1st to nth stages ON side drive circuits 11a to 1na operate so as to conduct the semiconductor devices 1 to n to be driven while the ON side transmission circuit 10a operates and the OFF side transmission circuit 10b is stopped. do.

On the other hand, in the 1st to nth stages OFF side drive circuits 11b to 1nb, the operation of the ON side transmission circuit 10a is stopped, and while the OFF side transmission circuit 10b is operating, the semiconductor devices 1 to n to be driven are driven. It works to turn it off.

The operation chart is shown in FIG. Hereinafter, the ON / OFF operation of the semiconductor device 1 to be driven will be focused on and described. When the gate command of the semiconductor device 1 to be driven becomes high, the ON side transmission circuit 10a starts operation and transmits electric power to the first stage ON side drive circuit 11a. Then, the first switch device FET 1 and the fifth switch device FET 5 are conductive, the first power supply capacitor C11 is connected in parallel to the semiconductor device 1 to be driven, and the semiconductor device 1 to be driven is conductive.

When the gate command of the semiconductor device 1 to be driven becomes low, the ON side transmission circuit 10a stops the operation, and the OFF side transmission circuit 10b starts the operation. Then, the second and third switch devices FET2 and FET3 are conducted, and the second power supply capacitor C21 is connected in antiparallel to the semiconductor device 1 to be driven, and the voltage equal to the charging voltage of the second power supply capacitor C21 is regarded as a negative voltage. Since it is applied, the semiconductor device 1 to be driven is turned off. Since the second to nth stages operate in the same manner, it is possible to control ON / OFF of the semiconductor devices 2 to n to be driven.

Therefore, it is possible to realize a bipolar output, a negative bias can be applied, and an inexpensive and compact gate drive circuit can be realized while maintaining the insulation between the high voltage circuit and the low voltage circuit.

[Embodiment 3]
FIG. 5 shows a circuit configuration example of the gate drive circuit according to the third embodiment. The third embodiment is characterized in that voltage adjusting mechanisms (hereinafter referred to as regulators) 31 and 32 are provided between the first and second power supply capacitors C11 and C21 and the first and second switch devices FET1 and FET2. There is.

As shown in FIG. 5, the third power supply capacitor C31 is connected in parallel with the first power supply capacitor C11. A first regulator 31 is connected between the first power supply capacitor C11 and the second terminal (drain terminal) of the first switch device FET1. The fourth power supply capacitor C41 is connected in parallel with the second power supply capacitor C21. A second regulator 32 is connected between the second power supply capacitor C21 and the third terminal (source terminal) of the second switch device FET2.

In the third embodiment, the third resistor R3 of the second embodiment is deleted. Between the connection points of the 10th, 11th, and 7th diodes D10, D11, and D7 and the 1st terminal (gate terminal) of the 3rd switch device FET3 and the 2nd terminal (drain terminal) of the 5th switch device FET5. The fourth resistor R4 is connected. The fifth resistance R5 is connected between the connection point of the fourth, fifth, fifth and sixth diodes D4, D5, D6 and the first resistance R1 and the first terminal (gate terminal) of the fifth switch device FET5. ..

The terminal 1 of the first regulator 31 is connected to the first power supply capacitor C11. The terminal 2 of the first regulator 31 is connected to the connection points of the first and second power supply capacitors C11 and C21. The terminal 3 of the first regulator 31 is connected to the second terminal (drain terminal) of the first switch device FET1. The terminal 1 of the second regulator 32 is connected to the second power supply capacitor C21. The terminal 2 of the second regulator 32 is connected to the connection points of the first and second power supply capacitors C11 and C21. The terminal 3 of the second regulator 32 is connected to the third terminal (source terminal) of the second switch device FET2.

FIG. 6 shows a configuration example of the first and second regulators 31 and 32. The first and second regulators 31 and 32 include a semiconductor element 41, a reference voltage 42, an amplifier circuit 43, a sixth resistance R6, and a seventh resistance R7.

In the semiconductor element 41, the second terminal (drain terminal) is connected to the first power supply capacitor C11 or the second power supply capacitor C21, and the third terminal (source terminal) is connected to the first switch device FET1 or the second switch device FET2. To.

One end of the reference voltage 42 is connected to the connection points of the first and second power supply capacitors C11 and C21. The sixth resistance R6 is connected to one end of the reference voltage 42. The seventh resistor R7 is connected between the other end of the sixth resistor R6 and the first switch device FET 1 or the second switch device FET 2.

The amplifier circuit 43 uses the other end of the reference voltage 42 and the connection point of the sixth and seventh resistances R6 and R7 as input terminals, and connects the output terminal to the first terminal (gate terminal) of the semiconductor element 41.

The example of FIG. 6 is a three-terminal linear regulator, and a switching regulator or the like may be used instead. The voltage on the positive bias side is controlled by the first regulator 31, and the voltage on the negative bias side is controlled by the second regulator 32. As a result, a stable voltage can be supplied to the semiconductor devices 1 to n to be driven without depending on the characteristics of the element or the voltage drop due to the wiring impedance.

By stabilizing the voltage applied between the gate and the source, it is possible to prevent an increase in loss due to a decrease in the voltage between the gate and the source. Other operations are the same as those in the second embodiment, and can be expanded to n stages.

[Embodiment 4]
In the transmission circuit 10 of the first embodiment, the power to be transmitted to the gates of the semiconductor devices 1 to n to be driven and the gate signal of the semiconductor device are transmitted by driving the first full bridge circuit. The first DC cut capacitor C1 is connected between the output of the first full bridge circuit and the first transformer Tr1 for the purpose of preventing the DC demagnetization of the first transformer Tr1, but the dead time of the first full bridge circuit and the semiconductor The DC voltage is charged to the first DC cut capacitor C1 due to the variation in the voltage drop of the switch.

As shown in FIG. 7, the voltage applied to the first transformer Tr1 is the voltage output by the first full bridge circuit minus the voltage Vc of the first DC cut capacitor C1. If the voltage Vc charged in the first DC cut capacitor C1 is large, a sufficient voltage is not applied to the first transformer Tr1, and the voltage is not sufficiently output to the secondary side of the first transformer Tr1. The turn-on of the 5 switch devices FET1 and FET5 is delayed and causes a decrease in the rising speed of the gate voltage.

In the fourth embodiment, a gate drive circuit capable of high-speed operation regardless of the operating state is provided by controlling the voltage charged in the first DC cut capacitor C1 by devising the switching pattern of the first full bridge circuit. explain.

FIG. 8 shows a configuration example of the control circuit according to the fourth embodiment. The DC cut capacitor voltage Vc is detected. The comparator 33a determines whether or not the DC cut capacitor voltage Vc is larger than 0 (whether or not the DC cut capacitor voltage Vc is positive). If the DC cut capacitor voltage Vc is positive, the command generation unit 34a generates a command to turn on the first and fourth semiconductor switches S1 and S4 and turn off the second and third semiconductor switches S2 and S3. ..

The comparator 33b determines whether or not the DC cut capacitor voltage Vc is smaller than 0 (whether or not the DC cut capacitor voltage Vc is negative). If the DC cut capacitor voltage Vc is negative, the command generation unit 34b generates a command to turn on the second and third semiconductor switches S2 and S3 and turn off the first and fourth semiconductor switches S1 and S4. ..

The gate circuit 35 outputs the gate signal to the semiconductor switches S1 to S4 according to the commands generated by the command generation units 34a and 34b.

The fourth embodiment is characterized in that the DC cut capacitor voltage Vc is detected and the gate signal of the full bridge circuit is selected based on the polarity of the voltage.

When the value of the DC cut capacitor voltage Vc is positive, the first and fourth semiconductor switches S1 and S4 are turned on, and the second and third semiconductor switches S2 and S3 are turned off. When the value of the DC cut capacitor voltage Vc is negative, the first and fourth semiconductor switches S1 and S4 are turned off, and the second and third semiconductor switches S2 and S3 are turned on. This makes it possible to always keep the DC cut capacitor voltage Vc at 0.

Although the configuration in which the present embodiment 4 is applied to the first embodiment has been described, it is also possible to apply the present embodiment 4 to the ON side transmission circuit 10a and the OFF side transmission circuit 10b of the second and third embodiments.

Therefore, the voltage required for the transformer can be applied without being affected by the dead time or the variation of the semiconductor switch, so that the turn-on speed of the semiconductor device to be driven can be improved. Therefore, a gate drive circuit capable of high-speed operation can be realized.

[Embodiment 5]
FIG. 9 shows a configuration example of the control circuit according to the fifth embodiment. In the fifth embodiment, as shown in FIG. 9, the average processing unit 36 is added to the fourth embodiment.

In the fifth embodiment, the DC cut capacitor voltage Vc is detected, and the DC cut capacitor voltage Vc is filtered by the average processing unit 36 with a low-pass filter or the moving average process is performed to calculate the average value. It is characterized in that the gate signal of the full bridge circuit is selected based on the polarity of the processed voltage.

By adding the processing of the average processing unit 36 to the fourth embodiment, it is possible to prevent an error in determination due to noise or the like. Other operations are the same as in the fourth embodiment, and when the value of the DC cut capacitor voltage Vc is positive, the first and fourth semiconductor switches S1 and S4 are turned on, and the second and third semiconductor switches S2 and S3 are turned off. Let me. When the value of the DC cut capacitor voltage Vc is negative, the first and fourth semiconductor switches S1 and S4 are turned off, and the second and third semiconductor switches S2 and S3 are turned on. This makes it possible to always keep the DC cut capacitor voltage Vc at 0.

Therefore, the voltage required for the pulse transformer can be applied without being affected by the dead time or the variation of the element, so that the turn-on speed of the semiconductor device to be driven can be improved.

[Embodiment 6]
FIG. 10 shows a configuration example of the control circuit according to the sixth embodiment. In the sixth embodiment, the vertex detection circuit 37, the first hold circuit 38, the comparator 39, and the second hold circuit 40 are added to the fourth embodiment.

The vertex detection circuit 37 in FIG. 10 has a role of detecting the vertex of the carrier, and outputs a signal when the vertex of the carrier is detected. The first hold circuit 38 updates the output value according to the output of the vertex detection circuit 37.

A carrier and its center point (0) are input to the comparator 39, and high is output when the carrier is lower than 0, and low is output when the carrier is higher than 0. The second hold circuit 40 updates the output value at the falling edge or the rising edge of the output of the comparator 39.

Therefore, the value of the DC cut capacitor voltage Vc is sampled at the apex of the carrier, and the switching timing of the first to fourth semiconductor switches S1 to S4 is 0 cross of the carrier.

By providing the above circuit, the sampling timing of the DC cut capacitor voltage Vc and the switching timing of the first to fourth semiconductor switches S1 to S4 are surely deviated, so that the judgment error due to noise due to switching can be prevented. Can be done.

Other operations are the same as in the fourth embodiment, and when the value of the DC cut capacitor voltage Vc is positive, the first and fourth semiconductor switches S1 and S4 are turned on, and the second and third semiconductor switches S2 and S3 are turned off. Let me. When the value of the DC cut capacitor voltage Vc is negative, the first and fourth semiconductor switches S1 and S4 are turned off, and the second and third semiconductor switches S2 and S3 are turned on.

This makes it possible to always keep the DC cut capacitor voltage Vc at 0. Therefore, the voltage required for the transformer can be applied without being affected by the dead time or the variation of the semiconductor element, so that the turn-on speed of the semiconductor device to be driven can be improved.

Further, although the configuration in which the sixth embodiment is applied to the fourth embodiment has been described, the sixth embodiment may be applied to the fifth embodiment.

[Embodiment 7]
In FIG. 1, the power and the gate signal to be transmitted to the gate of the semiconductor device to be driven are transmitted by driving the first full bridge circuit. A first DC cut capacitor C1 is connected between the first full bridge circuit and the first transformer Tr1 for the purpose of preventing DC demagnetization of the first transformer Tr1. In the fourth to sixth embodiments, the voltage is fed back so that the time average of the DC cut capacitor voltage Vc becomes 0 regardless of the operating state, and the voltage is applied to the first transformer Tr1 by controlling the switching pattern of the first full bridge circuit. The voltage is secured and the stable operation of the gate drive circuit is realized.

However, in the case of the above method, the rate of change of the DC cut capacitor voltage Vc depends on the magnitude of the exciting inductance of the first transformer Tr1. Therefore, when the exciting inductance of the first transformer Tr1 is large, the flowing current becomes small and the change speed of the DC cut capacitor voltage Vc becomes slow.

Since the switching pattern is switched when the polarity of the DC cut capacitor voltage Vc is switched, the switching frequency becomes low as a result. When the switching frequency becomes low, the exciting current becomes large and the residual magnetic flux of the first transformer Tr1 becomes high, so that the time for which the output voltage is held becomes long. This leads to the problem that the gate drive circuit cannot reproduce a short pulse width (that is, the gate drive circuit cannot operate at high speed).

In the seventh embodiment, high-speed operation of the gate drive circuit is realized by increasing the switching frequency and controlling the residual magnetic flux of the transformer to be low without being affected by the circuit parameters.

FIG. 11 shows a block diagram of the control circuit according to the seventh embodiment. The voltage controlled oscillator (hereinafter referred to as VCO) 44 controls the oscillation frequency by the input voltage. The edge detection unit 45 detects the off-timing edge of the gate command. The sample hold circuit 46 samples the phase information θ of the output of the VCO 44 at the timing when the gate command is off, and outputs the sample phase information θ as the sample phase information θ.

The phase determination unit 47 outputs 2π if the sample phase information θ output from the sample hold circuit 46 is π ≦ θ <2π, and outputs 0 if 0 ≦ θ <π. The output of the phase determination unit 47 is used as the phase command value. The subtractor 48 calculates the difference between the phase command value and the sample phase information θ. The PI control unit 49 performs PI control based on the phase command value and the sample phase information. Specifically, PI control is performed based on the difference calculated by the subtractor 48, and the resulting voltage is output to the VCO 44. The output of the VCO 44 is output to the comparators 33a and 33b and the sample hold circuit 46. The comparators 33a, 33b and later are the same as those in the fourth embodiment.

In the seventh embodiment, the output frequency of the VCO 44 is set so that the phase information θ becomes 2π or 0 by sampling and feeding back the phase information θ of the frequency output by the VCO 44 at the off timing of the gate command of the semiconductor device to be driven. Control. As a result, the output frequency of the VCO44 is determined by the voltage input to the VCO44, so the switching frequency can be determined without being affected by circuit parameters such as the excitation inductance, and the residual magnetic flux of the first transformer Tr1 is reduced to realize high-speed operation. do.

A typical configuration example of the VCO 44 is shown in FIG. As shown in FIG. 12, one end of the eighth resistor R8 is connected to the input terminal Input. Further, one end of the ninth resistor R9 is connected to the input terminal Input. The other end of the eighth resistor R8 is connected to one input terminal of the first comparator 50. The other end of the ninth resistor R9 is connected to the other input terminal of the first comparator 50. A capacitor 51 is connected between one input terminal and an output terminal of the first comparator 50.

Further, one end of the tenth resistor R10 is connected to one input terminal of the first comparator 50. A second terminal (drain terminal) of the semiconductor switch 52 is connected to the other end of the tenth resistor R10. The third terminal (source terminal) of the semiconductor switch 52 is grounded. Further, the 11th resistance R11 is connected between the other input terminal of the first comparator 50 and the third terminal (source terminal) of the semiconductor switch 52.

The output terminal of the first comparator 50 is connected to one input terminal of the second comparator 53. One end of the 12th resistor R12 is connected to the other input terminal of the second comparator 53. The other end of the 12th resistance R12 is grounded. A thirteenth resistor R13 is connected between the other input terminal of the second comparator 53 and the output terminal of the second comparator 53. Further, a 14th resistor R14 is connected between the first terminal (gate terminal) of the semiconductor switch 52 and the output terminal of the second comparator 53. The output of the second comparator 53 is input to the duty ratio correction unit 54. The duty ratio correction unit 54 corrects the duty ratio according to the output of the second comparator 53. The output of the duty ratio correction unit 54 becomes the output of the VCO 44.

FIG. 12 is just a representative example of VCO44, and any one having the same function can be substituted. Further, FIG. 13 shows an example of the characteristics of the VCO 44 assumed in the seventh embodiment. As shown in FIG. 13, the frequency f increases as the input voltage of the VCO 44 increases. It is assumed that the output of VCO44 is a square wave with a duty of 50%.

The phase determination unit 47 generates a phase command value based on the magnitude of the sample phase information θ. When the sample phase information θ is less than π, 0 is output as the phase command value, and when the sample phase information θ is π or more, 2π is output as the phase command value. The difference between the phase command value (output of the phase determination unit 47) and the sample phase information θ (phase detection value) is input to the PI controller 49, and the output is input to the VCO 44. By outputting the frequency based on the input, the VCO 44 can be controlled so that the phase information θ becomes 0 or 2π at the timing when the gate command is turned off.

As a result, the switching frequency can be adjusted according to the gate pulse width of the semiconductor device to be driven, and the DC cut capacitor voltage Vc = 0 can be controlled at the timing when the gate command is turned off. Therefore, the residual of the first transformer Tr1. The magnetic flux can be suppressed to almost zero, and high-speed operation of the gate drive circuit can be realized.

As shown above, according to the seventh embodiment, by controlling the drive frequency of the gate drive circuit according to the gate command, high withstand voltage and high speed operation are possible without being affected by the constants of the circuit. A gate drive circuit can be realized.

Although the present embodiment 7 has been described with an example applied to the gate drive circuit of the first embodiment, it can also be applied to the gate drive circuits of the second and third embodiments.

[Embodiment 8]
FIG. 14 shows a block diagram of the control circuit according to the eighth embodiment. Similar to the seventh embodiment, the phase information θ of the frequency output by the VCO 44 is sampled and fed back at the off timing of the gate command of the semiconductor device to be driven, so that the output frequency of the VCO 44 is set to 2π or 0. Control. As a result, the residual magnetic flux of the first transformer Tr1 (second transformer Tr2) is reduced to realize high-speed operation.

The eighth embodiment is characterized in that the capacitor voltage feedback unit 55 is added to the configuration of the seventh embodiment. The capacitor voltage feedback unit 55 calculates in the subtraction unit 56 the difference between the voltage command value and the voltage detection value of the first DC cut capacitor (in the case of the OFF side transmission circuit 10b, the second DC cut capacitor C2). The PI controller 57 performs PI control based on the difference. The subtractor 48 subtracts the sample phase information θ from the sum of the phase command value and the output of the PI controller 57. Other configurations are the same as those in the seventh embodiment.

The capacitor voltage feedback unit 55 corrects the input voltage of the VCO 44 so that the DC cut capacitor voltage vc becomes 0 by inputting 0 to the voltage command value. As a result, the DC component becomes 0 by correcting the dead time for preventing the semiconductor switch of the first and second full bridge circuits from being short-circuited and the DC component generated by the variation of the semiconductor switches of the first and second full bridge circuits. The frequency can be controlled as such. Regarding the calculation between different physical quantities such as voltage value and phase, unit conversion is performed at the time of calculation and matching is obtained.

As a result, the switching frequency can be adjusted according to the gate pulse width of the semiconductor device to be driven without being affected by the dead time or the variation of the semiconductor switch, so that high-speed operation of the gate drive circuit can be realized.

Although the example of the present embodiment 8 applied to the gate drive circuit of the first embodiment has been described, the present embodiment 8 can also be applied to the gate drive circuits of the second and third embodiments.

[Embodiment 9]
FIG. 15 shows a block diagram of the control circuit according to the ninth embodiment. Similar to the seventh embodiment, the phase information θ of the frequency output by the VCO 44 is sampled and fed back at the off timing of the gate command of the semiconductor device to be driven, so that the output frequency of the VCO 44 is set to 2π or 0. Control. As a result, the residual magnetic flux of the first transformer Tr1 (second transformer Tr2) is reduced to realize high-speed operation.

The ninth embodiment is characterized in that the capacitor current feedback unit 58 is added to the configuration of the seventh embodiment. The capacitor current feedback unit 58 calculates the difference between the current command value and the current detection value ic of the first DC cut capacitor C1 (in the case of the OFF side transmission circuit 10b, the second DC cut capacitor C2) in the subtraction unit 59. do. The PI controller 57 performs PI control based on the difference. The subtractor 48 subtracts the sample phase information θ from the sum of the phase command value and the output of the PI controller 57. Other configurations are the same as those in the seventh embodiment.

The capacitor current feedback unit 58 corrects the input voltage of the VCO 44 so that the current of the first DC cut capacitor C1 becomes 0 by inputting 0 to the current command value. As a result, the DC component becomes 0 by correcting the dead time for preventing the semiconductor switch of the first and second full bridge circuits from being short-circuited and the DC component generated by the variation of the semiconductor switches of the first and second full bridge circuits. The frequency can be controlled as such.

Further, in the case of the eighth embodiment, there is a possibility that the surge voltage at the time of switching may be detected, but the influence can be mitigated by detecting the current. Regarding the calculation between different physical quantities such as current value and phase, unit conversion is performed at the time of calculation and matching is obtained.

As a result, the switching frequency can be adjusted according to the gate pulse width of the semiconductor device to be driven without being affected by the dead time or the variation of the semiconductor switch, so that high-speed operation of the gate drive circuit can be realized.

Although the example 9 applied to the gate drive circuit of the first embodiment has been described, the present embodiment 9 can also be applied to the gate drive circuits of the second and third embodiments.

Although the above description has been made in detail only for the specific examples described in the present invention, it is obvious to those skilled in the art that various modifications and modifications are possible within the scope of the technical idea of the present invention. It goes without saying that such modifications and modifications fall within the scope of the claims.

1 ... Semiconductor device to be driven 10, 10a, 10b ... Transmission circuit, ON side transmission circuit, OFF side transmission circuit 11 to 1n ... 1st stage drive circuit to nth stage drive circuit 11a to 1na ... 1st stage to n stages Eye ON side drive circuit (1st to nth stage drive circuit)
11b to 1nb ... 1st to nth stage OFF side drive circuit Tr1, Tr2 ... 1st transformer, 2nd transformer D1 to D7 ... 1st to 7th diodes FET1 to FET5 ... 1st to 5th switch devices C11, C21 ... 1st power supply capacitor, 2nd power supply capacitor S1 to S4 ... 1st to 4th semiconductor switches C1, C2 ... 1st and 2nd DC cut capacitors Vin ... Input capacitors 31, 32 ... Regulator (voltage adjustment mechanism)
33a, 33b, 39 ... Comparator 34a, 34b ... Command generator 35 ... Gate circuit 36 ... Average processing unit 37 ... Peak detection circuit 38, 40 ... First and second hold circuits 44 ... Voltage control type transmitter 45 ... Edge Detection unit 46 ... Sample hold circuit 47 ... Phase determination unit 48 ... Subtractor 49 ... PI control unit 50 ... First comparator 51 ... Condenser 52 ... Semiconductor switch 53 ... Second comparator 54 ... Duty ratio correction unit 55 ... Condenser voltage feedback unit 56 ... Subtraction unit 57 ... PI controller 58 ... Condenser current feedback unit 59 ... Subtraction unit

Claims (14)

A gate drive circuit for n semiconductor devices connected in series.
A transmission unit that transmits gate signals and power,
A transformer unit having a first transformer to which a primary winding is connected to the transmission unit, and a transformer unit.
A drive circuit unit having a first-stage drive circuit to an n-th stage drive circuit that controls each of the n semiconductor devices is provided.
The first-stage drive circuit to the n-th stage drive circuit have a plurality of switch devices and first and second power supplies between the secondary winding and the tertiary winding of the first transformer and the semiconductor device to be driven, respectively. When the gate command of the semiconductor device to be driven has a capacitor and the gate command is high, the plurality of switch devices are controlled to connect the first power supply capacitor in parallel to the semiconductor device to be driven, and the drive target is described. A gate drive circuit characterized in that when the gate command of a semiconductor device is low, the plurality of switch devices are controlled and the second power supply capacitor is connected in antiparallel to the semiconductor device to be driven. The transmission unit is for a first DC cut connected between an input capacitor, a first full bridge circuit connected to the input capacitor, and between the first full bridge circuit and the primary winding of the first transformer. With a capacitor and a transmission circuit with
The first-stage drive circuit to the n-th stage drive circuit are each
A first diode having an anode connected to one end of the secondary winding of the first transformer,
A second diode with an anode connected to the other end of the secondary winding of the first transformer,
A third diode having an anode connected to the cathode of the first diode and the cathode of the second diode,
The first and second power supply capacitors connected in series between the cathode of the third diode and the midpoint of the tertiary winding of the first transformer,
A fourth diode with an anode connected to one end of the tertiary winding of the first transformer,
A fifth diode having an anode connected to the other end of the tertiary winding of the first transformer,
A sixth diode in which the anode is connected to the cathode of the fourth diode and the cathode of the fifth diode, and the cathode is connected to the connection point of the first and second power supply capacitors.
A first resistor having one end connected to the connection point of the fourth, fifth, and sixth diodes and the other end connected to the midpoint of the tertiary winding of the first transformer.
The first terminal is connected to the connection point of the first, second, and third diodes, the second terminal is connected to the connection point between the third diode and the first power supply capacitor, and the third terminal is the drive target. The first switch device connected to the first terminal of the semiconductor device,
The first terminal is connected to the connection point of the first, second and third diodes, the second terminal is connected to the first terminal of the semiconductor device to be driven, and the third terminal is the tertiary winding of the first transformer. The second switch device connected to the midpoint of the line,
A third switch device in which the second terminal is connected to the connection point of the first, second, and third diodes, and the third terminal is connected to the midpoint of the tertiary winding of the first transformer.
The first terminal is connected to the connection point of the fourth, fifth, and sixth diodes, the second terminal is connected to the cathode of the sixth diode, and the third terminal is connected to the first terminal of the third switch device. 4th switch device and
The first terminal is connected to the connection point of the fourth, fifth, and sixth diodes, the second terminal is connected to the first terminal of the third switch device, and the third terminal is the tertiary winding of the first transformer. With the 5th switch device connected to the midpoint,
1. The third terminal of the semiconductor device to be driven is connected to the connection point of the first and second power supply capacitors and the midpoint of the secondary winding of the first transformer. The gate drive circuit described. The transformer unit includes the first transformer and the second transformer.
The transmission unit
It has an input capacitor, a first full bridge circuit connected to the input capacitor, and a first DC cut capacitor connected between the first full bridge circuit and the primary winding of the first transformer. ON side transmission circuit and
An OFF side transmission circuit having a second full bridge circuit connected to the input capacitor and a second DC cut capacitor connected between the second full bridge circuit and the primary winding of the second transformer. And, with
The drive circuit unit includes the first stage drive circuit to the nth stage drive circuit and the first stage OFF side drive circuit to the nth stage OFF side drive circuit.
The first-stage drive circuit to the n-th stage drive circuit are each
A first diode having an anode connected to one end of the secondary winding of the first transformer,
A second diode with an anode connected to the other end of the secondary winding of the first transformer,
A third diode having an anode connected to the cathode of the first diode and the cathode of the second diode,
The first and second power supply capacitors connected in series between the cathode of the third diode and the midpoint of the tertiary winding of the first transformer,
A fourth diode with an anode connected to one end of the tertiary winding of the first transformer,
A fifth diode having an anode connected to the other end of the tertiary winding of the first transformer,
A sixth diode in which the anode is connected to the cathode of the fourth diode and the cathode of the fifth diode, and the cathode is connected to the connection point of the first and second power supply capacitors.
A first resistor having one end connected to the connection point of the fourth, fifth, and sixth diodes and the other end connected to the midpoint of the tertiary winding of the first transformer.
The second resistor, one end of which is connected to the connection point of the first, second, and third diodes,
The first terminal is connected to the other end of the second resistor, the second terminal is connected to the connection point between the third diode and the first power supply capacitor, and the third terminal is the first terminal of the semiconductor device to be driven. With the first switch device connected to
The first terminal is connected to the other end of the second resistor, the second terminal is connected to the first terminal of the semiconductor device to be driven, and the third terminal is connected to the midpoint of the tertiary winding of the first transformer. With the second switch device
A third switch device in which the second terminal is connected to the other end of the second resistor and the third terminal is connected to the midpoint of the tertiary winding of the first transformer.
A seventh diode whose anode is connected to the first terminal of the third switch device and whose cathode is connected to the cathode of the sixth diode,
A fifth switch device in which the first terminal is connected to the connection point of the fourth, fifth, and sixth diodes, and the third terminal is connected to the midpoint of the tertiary winding of the first transformer.
The third terminal of the semiconductor device to be driven is connected to the connection point of the first and second power supply capacitors and the midpoint of the secondary winding of the first transformer.
The first-stage OFF-side drive circuit to the n-th-stage OFF-side drive circuit are respectively.
An eighth diode having an anode connected to one end of the secondary winding of the second transformer and a cathode connected to the connection point between the third diode and the first power supply capacitor.
A ninth diode having an anode connected to the other end of the secondary winding of the second transformer and a cathode connected to the connection point between the third diode and the first power supply capacitor.
A tenth diode having an anode connected to one end of the tertiary winding of the second transformer and a cathode connected to the first terminal of the third switch device.
An eleventh diode having an anode connected to the other end of the tertiary winding of the second transformer and a cathode connected to the first terminal of the third switch device is provided.
The midpoint of the secondary winding of the second transformer is connected to the midpoint of the secondary winding of the first transformer, and the midpoint of the tertiary winding of the second transformer is the tertiary winding of the first transformer. The gate drive circuit according to claim 1, wherein the gate drive circuit is connected to a midpoint. The gate drive circuit according to claim 3, wherein a third resistor is connected between the second terminal of the fifth switch device and the first terminal of the third switch device. A first voltage adjusting mechanism is provided between the first switch device and the first power supply capacitor.
The gate drive circuit according to any one of claims 2 to 4, wherein a second voltage adjusting mechanism is provided between the second switch device and the second power supply capacitor. The first and second voltage adjusting mechanisms are
A semiconductor device having a second terminal connected to the first power supply capacitor or the second power supply capacitor and a third terminal connected to the first switch device or the second switch device.
The reference voltage with one end connected to the connection point of the first and second power supply capacitors,
The sixth resistance connected to one end of the reference voltage and
A seventh resistance connected between the other end of the sixth resistance and the first switch device or the second switch device.
An amplifier circuit having an input terminal at the connection point between the other end of the reference voltage and the sixth and seventh resistances and an output terminal connected to the first terminal of the semiconductor element.
5. The gate drive circuit according to claim 5. The first and second full bridge circuits include a first and second semiconductor switch connected in series between both ends of the input capacitor, and a third and fourth semiconductor switch connected in series between both ends of the input capacitor. The connection point of the third and fourth semiconductor switches is one end of the primary winding of the first transformer or the primary winding of the second transformer via the first DC cut capacitor or the second DC cut capacitor. The connection point of the first and second semiconductor switches is connected to the other end of the primary winding of the first transformer or the other end of the primary winding of the second transformer.
The control circuit is
When the voltage of the first and second DC cut capacitors is positive, the first and fourth semiconductor switches are turned on, and the second and third semiconductor switches are turned off.
Claims 2 to 2, wherein when the voltage of the first and second DC cut capacitors is negative, the first and fourth semiconductor switches are turned off and the second and third semiconductor switches are turned on. The gate drive circuit according to any one of 6. The gate drive circuit according to claim 7, wherein the voltage of the first and second DC cut capacitors is a value subjected to a low-pass filter process or a moving average process. The timing of sampling the voltage of the first and second DC cut capacitors is the timing of the apex of the carrier.
The gate drive circuit according to claim 7, wherein the switching timing of the first to fourth semiconductor switches is the timing of zero crossing of the carrier. The first and second full bridge circuits include a first and second semiconductor switch connected in series between both ends of the input capacitor, and a third and fourth semiconductor switch connected in series between both ends of the input capacitor. The connection point of the third and fourth semiconductor switches is one end of the primary winding of the first transformer or the primary winding of the second transformer via the first DC cut capacitor or the second DC cut capacitor. The connection point of the first and second semiconductor switches is connected to the other end of the primary winding of the first transformer or the other end of the primary winding of the second transformer.
The control circuit is
A voltage-controlled transmitter that controls the transmission frequency according to the input voltage,
A sample hold circuit that sample-holds the phase information of the output of the voltage control type transmitter when the gate command is off and outputs it as sample phase information.
When the sample phase information is π or more and less than 2π, 2π is output as a phase command value, and when the sample phase information is 0 or more and less than π, 0 is output as the phase command value.
A PI controller that performs PI control based on the phase command value and the sample phase information and outputs the voltage resulting from the PI control to the voltage control type transmitter.
Equipped with
When the output of the voltage control type transmitter is positive, the first and fourth semiconductor switches are turned on, and the second and third semiconductor switches are turned off.
Any of claims 2 to 6, wherein when the output of the voltage control type transmitter is negative, the first and fourth semiconductor switches are turned off and the second and third semiconductor switches are turned on. The gate drive circuit described in Crab. The control circuit is
A capacitor voltage feedback unit that performs PI control based on the difference between the voltage command value and the voltage detection value of the first DC cut capacitor or the second DC cut capacitor is provided.
The gate drive according to claim 10, wherein the PI controller performs PI control based on a value obtained by subtracting the sample phase information from a value obtained by adding the phase command value and the output of the capacitor voltage feedback unit. circuit. The control circuit is
A capacitor current feedback unit that performs PI control based on the difference between the current command value and the current detection value of the first DC cut capacitor or the second DC cut capacitor is provided.
The gate drive according to claim 10, wherein the PI controller performs PI control based on a value obtained by subtracting the sample phase information from a value obtained by adding the phase command value and the output of the capacitor current feedback unit. circuit. The voltage control type transmitter is
The 8th resistance with one end connected to the input terminal,
The 9th resistance with one end connected to the input terminal,
A first comparator having one input terminal connected to the other end of the eighth resistance and the other input terminal connected to the other end of the ninth resistance.
A capacitor connected between one input terminal and the output terminal of the first comparator,
A tenth resistor having one end connected to one input terminal of the first comparator,
A semiconductor switch in which the second terminal is connected to the other end of the tenth resistor and the third terminal is grounded.
An eleventh resistor connected between the other input terminal of the first comparator and the third terminal of the semiconductor switch,
A second comparator in which one input terminal is connected to the output of the first comparator, and
A twelfth resistor having one end connected to the other input terminal of the second comparator and the other end grounded.
A thirteenth resistor connected between the output terminal of the second comparator and the other input terminal,
A 14th resistor connected between the first terminal of the semiconductor device and the output terminal of the second comparator,
The gate drive circuit according to any one of claims 11 to 12, further comprising a duty ratio correction unit that corrects the duty ratio according to the output of the second comparator. A transmission unit that transmits gate signals and power, a transformer unit that has a first transformer with a primary winding connected to the transmission unit, and a first-stage drive circuit to n-stage drive that controls n semiconductor devices, respectively. A drive circuit unit having a circuit is provided, and the first-stage drive circuit to the n-th stage drive circuit are located between the secondary winding and the tertiary winding of the first transformer and the semiconductor device to be driven, respectively. It is a control method of a gate drive circuit including a plurality of switch devices and first and second power supply capacitors.
Each of the first-stage drive circuit to the n-th stage drive circuit controls the plurality of switch devices when the gate command of the semiconductor device to be driven is high, and the first power supply capacitor is used for the semiconductor device to be driven. When the gate command of the semiconductor device to be driven is low, the plurality of switch devices are controlled to connect the second power supply capacitor to the semiconductor device to be driven in antiparallel connection. How to control the gate drive circuit.

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