JP2022067308A5

JP2022067308A5 -

Info

Publication number: JP2022067308A5
Application number: JP2020175945A
Authority: JP
Filing date: 2020-10-20
Publication date: 2023-07-21
Anticipated expiration: 2040-10-20

Description

本発明は、以下の解決手段によって上述の課題を解決する（かっこ書きで、対応する実施形態の構成を示す。）。
本発明（第１３実施形態）は、
所定のカウンタ（８ビットカウンタ５０１）と、
所定のレジスタ（割込み待ちモニタレジスタ３０１）と、を備え、
メイン処理（図９７）と、タイマ割込み処理（図２３２）を実行可能とし、
メイン処理は、割込みを禁止する命令（ＤＩ命令、又はＣＡＬＬＥＸ命令）から割込みを許可する命令（ＥＩ命令、又はＲＥＴＥＸ命令）まで割込みを禁止する割込み禁止状態を有し、
割込み禁止期間の設計上の最大時間を「Ｓ」とし、所定のカウンタの値がタイムアウトする周期の時間を「Ｔ」としたとき、「Ｔ＞Ｓ」となるように構成され、
所定のカウンタの値を更新しタイムアウトすると（図２３３中、「Ｔ１」）、所定のレジスタに割込み要求があったことを示す情報を記憶可能に構成され（割込み待ちモニタレジスタ３０１をオンにし）、
所定のレジスタに割込み要求があったことを示す情報を記憶している状況が割込み許可状態である場合は、タイマ割込み処理を実行可能に構成され、
所定のレジスタに割込み要求があったことを示す情報を記憶している状況が割込み禁止状態である場合は、所定のレジスタに記憶されている割込み要求があったことを示す情報をクリアせず、割込み許可状態となった後にタイマ割込み処理を実行可能に構成され、
割込み禁止状態である場合でも所定のカウンタの値を更新可能に構成され、
割込み禁止状態でタイムアウトをＮ回（Ｎは、２以上の数値）した場合であっても、割込み許可状態となった後に割込み禁止状態でタイムアウトをＮ回したことに基づいてタイマ割込み処理がＮ回連続して実行されないように構成され（図２３５）、
タイマ割込み処理を実行する際に、所定のレジスタに記憶されている割込み要求があったことを示す情報をクリア可能に構成され、
タイマ割込み処理を実行する際に割込み禁止状態となり、タイマ割込み処理を終了する際には、タイマ割込み処理を終了するための復帰命令の直前に割込み許可命令を実行するように構成され、
タイマ割込み処理を終了するための復帰命令の直前の割込み許可命令を実行した直後であってタイマ割込み処理を終了するための復帰命令の直前にはタイマ割込み処理が実行されないように構成される
ことを特徴とする。 The present invention solves the above-described problems by the following solutions (the structure of the corresponding embodiment is shown in parentheses).
The present invention (thirteenth embodiment) is
a predetermined counter (8-bit counter 501);
a predetermined register (interrupt wait monitor register 301),
Main processing (Fig. 97) and timer interrupt processing (Fig. 232) can be executed,
The main process has an interrupt disabled state in which interrupts are disabled from an interrupt disabled instruction (DI instruction or CALLEX instruction) to an interrupt enabled instruction (EI instruction or RETEX instruction),
When the design maximum time of the interrupt disabled period is "S" and the period of time when the value of the predetermined counter times out is "T", it is configured so that "T>S",
When the value of a predetermined counter is updated and times out (“T1” in FIG. 233), information indicating that there is an interrupt request can be stored in a predetermined register (interrupt wait monitor register 301 is turned on),
when the state in which information indicating that an interrupt request has been received in a predetermined register is an interrupt enabled state, timer interrupt processing can be executed;
When the information indicating that an interrupt request has been stored in a predetermined register is in an interrupt disabled state, the information indicating that an interrupt request has been stored in the predetermined register is not cleared, and timer interrupt processing can be executed after an interrupt enabled state,
configured so that the value of a predetermined counter can be updated even when interrupts are disabled;
Even if timeout occurs N times in the interrupt disabled state (N is a numerical value of 2 or more), the timer interrupt processing is configured so that the timer interrupt processing is not executed continuously N times based on the fact that the timeout has occurred N times in the interrupt disabled state after the interrupt enabled state (Fig. 235),
configured to be able to clear information indicating that there is an interrupt request stored in a predetermined register when executing timer interrupt processing,
interrupt disabled state when executing timer interrupt processing, and when ending timer interrupt processing, an interrupt enable instruction is executed immediately before a return instruction for ending timer interrupt processing,
It is configured so that timer interrupt processing is not executed immediately before the return instruction for ending timer interrupt processing immediately after execution of the interrupt enable instruction immediately before the return instruction for ending timer interrupt processing.
It is characterized by

Claims

a predetermined counter;
a predetermined register;
Main processing and timer interrupt processing can be executed,
The main processing has an interrupt disabled state in which interrupts are disabled from an interrupt disabled instruction to an interrupt enabled instruction,
When the design maximum time of the interrupt disabled period is "S" and the period of time when the value of the predetermined counter times out is "T", it is configured so that "T>S",
When the value of a predetermined counter is updated and timeout occurs, information indicating that an interrupt request has been received can be stored in a predetermined register,
when the state in which information indicating that an interrupt request has been received in a predetermined register is an interrupt enabled state, timer interrupt processing can be executed;
When the information indicating that an interrupt request has been stored in a predetermined register is in an interrupt disabled state, the information indicating that an interrupt request has been stored in the predetermined register is not cleared, and timer interrupt processing can be executed after an interrupt enabled state,
configured so that the value of a predetermined counter can be updated even when interrupts are disabled;
The timer interrupt processing is configured not to be executed N times consecutively on the basis of N timeouts in the interrupt disabled state after entering the interrupt enabled state, even when timeout is performed N times (N is a numerical value of 2 or more) in the interrupt disabled state,
configured to be able to clear information indicating that there is an interrupt request stored in a predetermined register when executing timer interrupt processing,
interrupt disabled state when executing timer interrupt processing, and when ending timer interrupt processing, an interrupt enable instruction is executed immediately before a return instruction for ending timer interrupt processing,
The game machine is characterized in that timer interrupt processing is not executed immediately after execution of an interrupt permission instruction immediately before a return instruction for ending timer interrupt processing and immediately before a return instruction for ending timer interrupt processing.