JP2022066988A - Manufacturing method of semiconductor device - Google Patents

Abstract

To provide a manufacturing method of a semiconductor device suitable for efficiently manufacturing a semiconductor device provided with a sealing material that seals the circuit surface side of a semiconductor chip while suppressing chip breakage and chip shift.SOLUTION: A manufacturing method of a semiconductor device includes a half-cut step, a sealing step, a back grind step, and an individualization step. In the half-cut step, a dividing groove G having a depth from the circuit surface Wa to the middle of the thickness and partitioning a plurality of chip forming portions 10 is formed on a wafer W. In the sealing step, a sealing material portion 21 for sealing the circuit surface Wa side of the wafer W is formed. In the back grind step, the back surface Wb side of the wafer W is ground until the dividing groove G is exposed on the back surface Wb side. In the individualization step, the sealing material portion 21 is cut in the thickness direction along the dividing groove G around each of the chip forming portions 10 to obtain a chip C with a plurality of sealing materials.SELECTED DRAWING: Figure 2

Description

The present invention relates to a method for manufacturing a semiconductor device.

The flip-chip mounting type semiconductor device includes, for example, a semiconductor chip, a plurality of bump electrodes provided on the circuit surface of the semiconductor chip, and a sealing resin that covers a predetermined surface of the semiconductor chip. In such a semiconductor device, the bump electrode side is bonded to the mounting substrate. From the viewpoint of mounting reliability, it is important that the chip circuit surface of the semiconductor device on the mounting board and the periphery of the bump electrode are sealed with a sealing resin. A method for manufacturing a flip-chip mounting type semiconductor device provided with a sealing resin for sealing a chip circuit surface is described in, for example, Patent Document 1 below.

Japanese Unexamined Patent Publication No. 2019-91845

Flip-chip mounting type semiconductor devices are manufactured, for example, as follows. First, the semiconductor wafer is thinned by backgrinding (backgrinding process). The semiconductor wafer has a circuit surface and a back surface opposite to the circuit surface. In this step, the wafer is thinned by grinding from the back surface side of the semiconductor wafer with the back grind tape bonded to the circuit surface side of the semiconductor wafer. Next, the thinned wafer is cut by a rotary blade to cut the wafer in the thickness direction and individualize it into semiconductor chips (chip conversion step). Next, a plurality of semiconductor chips are arranged on the adhesive surface of the temporary fixing tape at intervals from each other (chip arrangement step). Next, a predetermined portion of each semiconductor chip is sealed with a sealing resin (sealing step). In this step, the sealing resin is collectively supplied to a plurality of semiconductor chips on the temporary fixing tape, and each semiconductor chip is resin-sealed (the gap between the chips is filled with the sealing resin). Then, after the sealing resin is cured, the sealing resin portion is cut in the thickness direction along the gap between the semiconductor chips (dicing step). As a result, a semiconductor device as a semiconductor chip with a sealing resin can be obtained.

In the above-mentioned backgrinding step, the smaller the thickness required for the thinned wafer, the more easily the wafer is cracked. Cracks occur, for example, due to variations in grinding pressure at various points on the back surface of the wafer. Cracks remain as an aspect of chip breakage in manufactured semiconductor devices. In the chipping process, the thinner the wafer, the more easily chipping occurs in the obtained semiconductor chip. In the chip placement process, chip shift (deviation of the chip position from a desired position) is likely to occur when the semiconductor chip is placed on the temporary fixing tape. The chip shift causes a variation in the distance between chips in a plurality of semiconductor chips on the temporary fixing tape, and causes a variation in the thickness of the encapsulating resin covering the side surface of the semiconductor chip in a plurality of manufactured semiconductor devices. Variations in the thickness of the sealing resin in the semiconductor device are not preferable from the viewpoint of sealing reliability.

The present invention provides a method for manufacturing a semiconductor device, which is suitable for efficiently manufacturing a semiconductor device including a sealing material for sealing the circuit surface side of the semiconductor chip while suppressing chip breakage and chip shift. ..

The present invention [1] has a circuit surface and a back surface opposite to the circuit surface, and has a thickness between the circuit surface and the back surface. A half-cut step of forming a dividing groove for partitioning a plurality of chip forming portions having a depth up to, and a sealing step of forming a sealing material portion for sealing the circuit surface side of the wafer. A back grind step of grinding the back surface side of the wafer so that the dividing groove is exposed on the back surface side, and cutting the sealing material portion in the thickness direction along the dividing groove around each chip forming portion. Includes a method of manufacturing a semiconductor device, comprising a step of disassembling to obtain a plurality of chips with encapsulants.

In the present invention [2], the wafer is provided with a plurality of bumps on the circuit surface, and after the sealing step, each of the plurality of bumps is sealed on the side opposite to the circuit surface. The method for manufacturing a semiconductor device according to the above [1], which has an exposed portion exposed from the material portion.

The present invention [3] is described in the above [1] or [2], wherein in the sealing step, the circuit surface side of the wafer is sealed with a sealing resin sheet to form the sealing material portion. Includes methods for manufacturing semiconductor devices.

The present invention [4] further includes a back surface sealing step of forming a back surface encapsulating material portion for sealing the back surface side of the wafer between the back grind step and the individualization step. In the unification step, any one of the above [1] to [3], in which the encapsulant portion and the back surface encapsulant portion are cut in the thickness direction along the dividing groove around each chip forming portion. The method for manufacturing a semiconductor device according to the above.

In the method for manufacturing a semiconductor device of the present invention, a plurality of chip forming portions are formed on a wafer in a half-cutting step, and a plurality of chip forming portions are separated in a subsequent back grind step to form a plurality of chips. can get. That is, according to this manufacturing method, the wafer can be individually separated into chips without dicing (full-cut dicing) in the entire thickness direction of the wafer. Such a manufacturing method is suitable for suppressing the above-mentioned chipping.

Further, in the back grind step of the present manufacturing method, as described above, the back surface side of the wafer is ground so that the dividing groove is exposed on the back surface side. In such a back grind process, since the dividing groove is exposed on the back surface side, a plurality of chip forming portions are in a state of being separated from each other, and variations in grinding pressure with respect to various parts on the back surface of the wafer are absorbed by the individual chip forming portions. To. Such a configuration is suitable for suppressing the above-mentioned cracks caused by variations in grinding pressure.

In addition, in the present manufacturing method, the circuit surface side of the wafer is set after the half-cut process (formation of a plurality of chip forming portions) as described above and before the back grind process (individualization into chips). A sealing material portion to be sealed is formed (sealing step). In the sealing step, the circuit surface side of a plurality of chip forming portions (parts of the wafer and the mutual distance is fixed) in the wafer can be collectively sealed. In this manufacturing method, the step of arranging the chips separated from each other is not carried out before the sealing step. Therefore, according to this manufacturing method, it is possible to efficiently manufacture a semiconductor device in which the chip circuit surface is sealed without causing the above-mentioned chip shift.

Represents a part of the steps in the first embodiment of the method for manufacturing a semiconductor device of the present invention. 1A shows a process of preparing a wafer, FIG. 1B shows a process of forming a bump on a wafer, FIG. 1C shows a process of attaching a dicing tape to a wafer, and FIG. 1D shows a half-cut wafer. Represents the process to be performed. The process following the process shown in FIG. 1 is represented. FIG. 2A shows a step of forming a sealing material portion on a wafer, FIG. 2B shows a step of attaching a backgrinding tape to the wafer, FIG. 2C shows a step of backgrinding the wafer, and FIG. 2D shows a step of backgrinding the wafer. , Represents a process of forming a back surface encapsulant portion on a wafer. The process following the process shown in FIG. 2 is represented. FIG. 3A shows a process of attaching a dicing tape to a wafer with a sealing material, FIG. 3B shows a process of dicing a wafer with a sealing material, and FIG. 3C shows a semiconductor chip with a sealing material bonded to a mounting substrate. Represents the process to be performed. A part of the steps in the modified example of the manufacturing method of the semiconductor device shown in FIGS. 1 to 3 is shown. FIG. 4A shows a process of attaching a dicing tape to a wafer with a sealing material, FIG. 4B shows a process of dicing a wafer with a sealing material, and FIG. 4C shows a semiconductor chip with a sealing material bonded to a mounting substrate. Represents the process to be performed. Represents a part of the steps in the second embodiment of the method for manufacturing a semiconductor device of the present invention. 5A shows a process of preparing a wafer, FIG. 5B shows a process of forming pillars on a wafer, FIG. 5C shows a process of attaching a dicing tape to a wafer, and FIG. 5D shows a half-cut wafer. Represents the process to be performed. The process following the process shown in FIG. 5 is represented. FIG. 6A shows a step of forming a sealing material portion on a wafer, FIG. 6B shows a step of thinning the sealing material portion, and FIG. 6C shows a step of forming a bump on a wafer with a sealing material. .. The process following the process shown in FIG. 6 is represented. FIG. 7A shows the process of attaching the backgrinding tape to the wafer with the encapsulant, FIG. 7B shows the process of backgrinding the wafer with the encapsulant, and FIG. 7C shows the backside sealing of the wafer with the encapsulant. It represents a process of forming a stop material portion. The process following the process shown in FIG. 7 is represented. FIG. 8A shows a process of attaching a dicing tape to a semiconductor wafer with a sealing material, FIG. 8B shows a process of dicing a semiconductor wafer with a sealing material, and FIG. 8C shows a mounting substrate of a semiconductor chip with a sealing material. Represents the process of joining to. A part of the steps in the modified example of the manufacturing method of the semiconductor device shown in FIGS. 5 to 8 is shown. FIG. 9A shows a process of attaching a dicing tape to a semiconductor wafer with a sealing material, FIG. 9B shows a process of dicing a semiconductor wafer with a sealing material, and FIG. 9C shows a process of picking up a semiconductor chip with a sealing material. A process is shown, and FIG. 9D shows a process of joining a semiconductor chip with a sealing material to a mounting substrate. It represents a part of the steps in the manufacturing method of the semiconductor device of Comparative Example 1. The process following the process shown in FIG. 10 is represented. It represents a part of the steps in the manufacturing method of the semiconductor device of Comparative Example 2. The process following the process shown in FIG. 12 is represented. It represents a part of the steps in the manufacturing method of the semiconductor device of Comparative Example 3. The process following the process shown in FIG. 14 is represented. The process following the process shown in FIG. 15 is represented.

1 to 3 show a first embodiment of the method for manufacturing a semiconductor device of the present invention. The method for manufacturing a semiconductor device of the present embodiment is a method for manufacturing a semiconductor device X1 (including a chip C with a sealing material) as shown in FIG. 3C.

In this manufacturing method, first, as shown in FIG. 1A, a wafer W is prepared. The wafer W has a circuit surface Wa and a back surface Wb on the opposite side of the circuit surface Wa, and has a thickness between the circuit surface Wa and the back surface Wb. In the present embodiment, the wafer W includes a disk-shaped semiconductor wafer and a wiring structure portion (not shown) arranged on one side of the semiconductor wafer in the thickness direction to form a circuit surface Wa. The thickness of the semiconductor wafer is, for example, 200 to 1000 μm. A plurality of semiconductor elements are built on the Wa side of the circuit surface of the semiconductor wafer. The wiring structure includes a rewiring layer electrically connected to a semiconductor element in a semiconductor wafer.

Next, as shown in FIG. 1B, a plurality of bumps B are formed on the circuit surface Wa of the wafer W. Specifically, for each semiconductor element in the wafer W, a predetermined number of bumps B electrically connected to the element are formed. Examples of the material of the bump B include gold, silver, copper, lead, tin, and alloys thereof. The height of the bump B is, for example, 10 to 300 μm.

Next, as shown in FIG. 1C, the dicing tape T1 is attached to the wafer W. The dicing tape T1 is, for example, an adhesive sheet including a base material (not shown) and an adhesive layer (not shown) on one surface in the thickness direction thereof, and has a disk shape having a size corresponding to the wafer W. The exposed surface of the pressure-sensitive adhesive layer forms the pressure-sensitive surface T1a of the dicing tape T1. In this step, specifically, the adhesive surface T1a of the dicing tape T1 is bonded to the back surface Wb of the wafer W. As a result, the wafer W is held on the dicing tape T1.

Next, as shown in FIG. 1D, a dividing groove G having a depth from the circuit surface Wa to the middle of the thickness is formed on the wafer W (half-cut step). Specifically, a dividing groove G that opens to the circuit surface Wa side is formed on the wafer W held by the dicing tape T1 by cutting from the circuit surface Wa side to the middle of the thickness. Examples of the cutting method include blade dicing (the same applies to the cutting method in the half-cutting step described later). The dividing groove G is a gap that divides a plurality of chip forming portions 10 in the wafer W, and is formed in a grid pattern, for example, in a plan view on the Wa side of the circuit surface. The chip forming portion 10 has a circuit surface 11 (chip circuit surface) and a side surface 12. A semiconductor element is built in each chip forming portion 10. The groove width of the dividing groove G is, for example, 10 to 100 μm. The depth of the dividing groove G is, for example, greater than or equal to the thickness of the semiconductor chip of the object to be formed, and is, for example, 10 to 500 μm.

Next, after the dicing tape T1 is peeled off, as shown in FIG. 2A, a sealing material portion 21 for sealing the circuit surface Wa side of the wafer W is formed (sealing step). In the present embodiment, the encapsulant portion 21 is formed so as to enter the dividing groove G and a part of each bump B is exposed from the encapsulant portion 21. Preferably, the dividing groove G is filled with the sealing material portion 21.

In this step, the encapsulant portion 21 may be formed of a liquid thermosetting composition, or the encapsulant portion 21 may be formed of a sheet-shaped thermosetting composition (sealing resin sheet). good. The thermosetting composition contains, for example, an epoxy resin, a curing agent for epoxy resin (phenol resin or the like), an inorganic filler, a curing accelerator, and a black colorant.

When a liquid thermosetting composition is used, for example, after applying the liquid thermosetting composition on the circuit surface Wa, the resin is cured by heating to form the sealing material portion 21.

When using a sealing resin sheet, first, the sealing resin sheet is attached to the Wa side of the circuit surface. At this time, the bumps B are bonded so that a part of each bump B is exposed from the sealing resin sheet (the sealing resin sheet has a thickness capable of such bonding). Next, the sealing resin sheet is cured by heating to form the sealing material portion 21. Examples of the bonding method include a vacuum press. When the sealing resin sheet is bonded by a vacuum press, the sealing resin sheet is preferably handled in a form in which a protective film is bonded to one side thereof. A configuration using a sealing resin sheet (easily prepared as a sheet having a high thickness and uniformly molded) in the sealing step is suitable for forming the sealing material portion 21 with high thickness accuracy.

After such a sealing step, each of the plurality of bumps B has an exposed portion Ba exposed from the sealing material portion 21 on the side opposite to the circuit surface Wa. In the present embodiment, the exposed portion Ba protrudes outside the sealing material portion 21.

Next, as shown in FIG. 2B, the backgrinding tape T2 is attached to the wafer W with the sealing material portion 21. The backgrinding tape T2 is an adhesive sheet including a base material 31 and an adhesive layer 32 on one surface in the thickness direction thereof, and has, for example, a disk shape having a size corresponding to the wafer W.

The base material 31 is, for example, a plastic base material. Examples of the constituent material of the plastic base material include polyester, polyolefin, polyvinyl chloride, polycarbonate, polyetheretherketone, polyimide, polyetherimide, and polyamide. Examples of the polyester include polyethylene terephthalate (PET), polyethylene naphthalate, and polybutylene terephthalate (PBT). These may be used alone or in combination of two or more. The thickness of the base material 31 is, for example, 40 to 200 μm.

Examples of the material of the pressure-sensitive adhesive layer 32 include an acrylic pressure-sensitive adhesive, a rubber-based pressure-sensitive adhesive, a silicone-based pressure-sensitive adhesive, and a urethane-based pressure-sensitive adhesive. These may be used alone or in combination of two or more. Further, the pressure-sensitive adhesive layer 32 has a thickness such that the entire exposed portion Ba of the bump B can enter the pressure-sensitive adhesive layer 32. The thickness of the pressure-sensitive adhesive layer 32 is, for example, 100 to 300 μm.

Specifically, in this step, the adhesive layer 32 side of the backgrinding tape T2 is placed on the circuit surface Wa side (sealing material) of the wafer W so that the entire exposed portion Ba of the bump B enters the adhesive layer 32. Attach it to the part 21 side). As a result, the wafer W is held on the backgrinding tape T2.

Next, as shown in FIG. 2C, the wafer W is thinned by backgrinding (backgrinding step). Specifically, the wafer W held on the backgrinding tape T2 is thinned to a predetermined thickness by grinding from the back surface Wb side. The thickness of the thinned wafer W is, for example, 10 to 400 μm. For the grinding process, for example, a back grind device equipped with a grinding wheel is used.

In this step, the back surface Wb side of the wafer W is ground so that the dividing groove G is exposed on the back surface Wb side. As a result, the plurality of chip forming portions 10 are separated from each other while being held by the backgrinding tape T2, and the back surface 13 is formed for each chip forming portion 10.

Next, as shown in FIG. 2D, a sealing material portion 22 (back surface sealing material portion) for sealing the back surface Wb of the wafer W is formed (back surface sealing step). In this step, for example, a liquid sealing curable resin is applied on the back surface Wb, and then the resin is cured to form the sealing material portion 22. Alternatively, a sheet-shaped curable resin for encapsulation (encapsulating resin sheet) may be attached to the back surface Wb, and then the encapsulating resin sheet may be cured to form the encapsulant portion 22. A configuration using a sealing resin sheet (easily prepared as a sheet having a high thickness and uniformly molded) in the back surface sealing step is suitable for forming the sealing material portion 22 with high thickness accuracy. The sealing curable resin is, for example, a resin composition containing an epoxy resin, a curing agent for epoxy resin (phenol resin or the like), an inorganic filler, a curing accelerator, and a black colorant.

Next, as shown in FIG. 3A, the dicing tape T3 is attached to the back surface Wb side (encapsulating material portion 22 side) of the wafer W with the encapsulant portions 21 and 22, and the encapsulant portions 21 and 22 are attached. The back grind tape T2 is peeled off from the wafer W. The dicing tape T3 is, for example, an adhesive sheet including a base material (not shown) and an adhesive layer (not shown) on one surface in the thickness direction thereof, and has a disk shape having a size corresponding to the wafer W. The exposed surface of the pressure-sensitive adhesive layer forms the pressure-sensitive surface T3a of the dicing tape T3. In this step, specifically, the adhesive surface T3a of the dicing tape T3 is attached to the back surface Wb of the wafer W.

Next, as shown in FIG. 3B, the wafer W with the sealing material portions 21 and 22 on the dicing tape T3 is individualized (individualization step). Specifically, a plurality of wafers W with encapsulant portions 21 and 22 held in the dicing tape T3 are cut in the thickness direction along a planned cutting line in the dividing groove G around each chip forming portion 10. (In this embodiment, the tip C with the sealing material portions 21 and 22) is obtained. Examples of the cutting method include blade dicing and laser dicing (the same applies to the cutting method in the individualization step described later).

Next, the chip C with a sealing material is picked up from the dicing tape T3 by, for example, an adsorption jig (not shown), and then the chip C with the sealing material is placed on a predetermined base material 50 as shown in FIG. 3C. On the other hand, implement it. The bump B of the chip C with a sealing material faces the base material 50, and the chip C with a sealing material is surface-mounted on the base material 50. Examples of the base material 50 include a lead frame, a TAB (Tape Automated Bonding) film, and a wiring board (the same applies to the base material 50 described later).

As described above, the semiconductor device X1 including the chip C with a sealing material can be manufactured. In the semiconductor device X1, the circuit surface 11 and the side surface 12 of the chip C are sealed by the encapsulant portion 21, the bump B penetrates the encapsulant portion 21 and is partially exposed, and the back surface 13 of the chip C is exposed. Is sealed by the sealing material portion 22.

In the method for manufacturing a semiconductor device of the present embodiment, a plurality of chip forming portions 10 are formed on the wafer W in the half-cut step (shown in FIG. 1D), and in the subsequent back grind step (shown in FIG. 2C). Therefore, the plurality of chip forming portions 10 are separated into chips. That is, according to this manufacturing method, the wafer W can be individually separated into chips C without dicing (full-cut dicing) in the entire thickness direction of the wafer W. Such a method for manufacturing a semiconductor device is suitable for suppressing chipping of the chip C.

In the back grind step (shown in FIG. 2C) of the present manufacturing method, as described above, the back surface Wb side of the wafer W is ground so that the dividing groove G is exposed to the back surface Wb side. In such a back grind step, since the split groove G is exposed on the back surface Wb side, the plurality of chip forming portions 10 are in a state of being separated from each other, and the variation of the grinding pressure with respect to each part of the back surface Wb varies among the individual chip forming portions 10. Is absorbed by. Such a configuration is suitable for suppressing cracks in the wafer W due to variations in grinding pressure during back grind.

In this manufacturing method, the circuit surface Wa side of the wafer W is sealed after the half-cut step (formation of a plurality of chip forming portions 10) and before the back grind step (individualization into chips C). The sealing material portion 21 is formed (sealing step shown in FIG. 2A). In the sealing step, the circuit surface Wa side of the plurality of chip forming portions 10 (parts of the wafer W and the mutual distance is fixed) in the wafer W can be collectively sealed. In this manufacturing method, the step of arranging the semiconductor chips separated from each other is not carried out before the sealing step. Therefore, this manufacturing method is suitable for efficiently manufacturing the semiconductor device X1 in which the circuit surface 11 and the side surface 12 of the chip C are sealed without causing a chip shift.

In the back surface sealing step (shown in FIG. 3A) of the present manufacturing method, the back surface Wb side of the plurality of chip forming portions 10 in the wafer W can be collectively sealed. In this manufacturing method, the step of arranging the semiconductor chips separated from each other is not carried out before the backside sealing step. Therefore, this manufacturing method is suitable for efficiently manufacturing the semiconductor device X1 in which the back surface 13 of the chip C is sealed without causing a chip shift.

As described above, this manufacturing method is suitable for efficiently manufacturing the semiconductor device X1 including the chip C sealed by the sealing material portions 21, 22 while suppressing chip breakage and chip shift. Further, since it is not necessary to form the pillar P described later in this manufacturing method, it is suitable for efficiently manufacturing a semiconductor device by suppressing the number of steps.

In the method for manufacturing a semiconductor device described above, after the step shown in FIG. 2C, the subsequent steps may be carried out without carrying out the backside sealing step shown in FIG. 2D. FIG. 4 shows a part of the steps in such a modification.

In this modification, after the back grind step shown in FIG. 2C, the adhesive surface T3a of the dicing tape T3 is attached to the back surface Wb side of the wafer W with the encapsulant portion 21 as shown in FIG. 4A.

Next, as shown in FIG. 4B, the wafer W with the sealing material portion 21 on the dicing tape T3 is individualized (individualization step). Specifically, the wafer W with the sealing material portion 21 held on the dicing tape T3 is cut in the thickness direction along the planned cutting line in the dividing groove G around each chip forming portion 10, and a plurality of sealed pieces are sealed. A tip C with a stop material (in this modification, a tip C with a sealing material portion 21) is obtained.

Next, the chip C with a sealing material is picked up from the dicing tape T3 by, for example, an adsorption jig (not shown), and then the chip C with the sealing material is placed on a predetermined base material 50 as shown in FIG. 4C. On the other hand, implement it. The bump B of the chip C with a sealing material faces the base material 50, and the chip C with a sealing material is surface-mounted on the base material 50.

As described above, the semiconductor device X1'with the chip C with a sealing material can be manufactured. In the semiconductor device X1', the circuit surface 11 and the side surface 12 of the chip C are sealed by the encapsulant portion 21, and the bump B penetrates the encapsulant portion 21 and is partially exposed. From the viewpoint of protecting the chip C, the above-mentioned semiconductor device X1 further including a sealing material portion 22 for sealing the back surface 13 of the chip C is preferable to such a semiconductor device X1'.

5 to 8 show a second embodiment of the method for manufacturing a semiconductor device of the present invention. The method for manufacturing a semiconductor device of the present embodiment is a method for manufacturing a semiconductor device X2 (including a chip C with a sealing material having a pillar P) as shown in FIG. 8C.

In this manufacturing method, first, as shown in FIG. 5A, a wafer W is prepared. The configuration of this wafer W is the same as described above with respect to the above-mentioned wafer W used in the first embodiment.

Next, as shown in FIG. 5B, a plurality of pillars P are formed on the circuit surface Wa of the wafer W. Specifically, for each semiconductor element in the wafer W, a predetermined number of pillars P electrically connected to the element are formed. Materials for pillar P include, for example, gold, silver, copper, and alloys thereof. The height of the pillar P is, for example, 10 to 100 μm.

Next, as shown in FIG. 5C, the dicing tape T1 is attached to the wafer W. The configuration of the dicing tape T1 is the same as described above with respect to the above-mentioned dicing tape T1 used in the first embodiment. In this step, specifically, the adhesive surface T1a of the dicing tape T1 is bonded to the back surface Wb of the wafer W. As a result, the wafer W is held on the dicing tape T1.

Next, as shown in FIG. 5D, a dividing groove G having a depth from the circuit surface Wa to the middle of the thickness is formed on the wafer W (half-cut step). Specifically, a dividing groove G that opens to the circuit surface Wa side is formed on the wafer W held by the dicing tape T1 by cutting from the circuit surface Wa side to the middle of the thickness. The dividing groove G is a gap that divides a plurality of chip forming portions 10 in the wafer W, and is formed in a grid pattern, for example, in a plan view on the Wa side of the circuit surface. The chip forming portion 10 has a circuit surface 11 (chip circuit surface) and a side surface 12. A semiconductor element is built in each chip forming portion 10. The groove width and depth of the dividing groove G are the same as the groove width and depth of the dividing groove G in the first embodiment.

Next, as shown in FIG. 6A, a sealing material portion 21 for sealing the circuit surface Wa side of the wafer W is formed (sealing step). In the present embodiment, the sealing material portion 21 is formed so as to enter the dividing groove G and cover the plurality of pillars P. Preferably, the dividing groove G is filled with the sealing material portion 21. The material, form (liquid, sheet-like), and forming method of the encapsulant portion 21 are the same as those described above for the encapsulant portion 21 in the first embodiment.

Next, as shown in FIG. 6B, the encapsulant portion 21 is ground to expose the tip Pa of the pillar P to the outside of the encapsulant portion 21. For grinding, for example, a back grind device equipped with a grinding wheel is used.

Next, as shown in FIG. 6C, a plurality of bumps B are formed on the circuit surface Wa side of the wafer W. Specifically, the bump B is formed on the tip Pa of each pillar P on the circuit surface Wa.

Next, as shown in FIG. 7A, the backgrinding tape T2 is attached to the wafer W with the sealing material portion 21. The configuration of the backgrinding tape T2 is the same as described above with respect to the above-mentioned backgrinding tape T2 used in the first embodiment.

Specifically, in this step, the adhesive layer 32 side of the backgrinding tape T2 is on the circuit surface Wa side (encapsulating material portion 21 side) of the wafer W so that the entire bump B enters the adhesive layer 32. Paste to. As a result, the wafer W is held on the backgrinding tape T2.

Next, as shown in FIG. 7B, the wafer W is thinned by backgrinding (backgrinding step). Specifically, the same as described above with reference to FIG. 2C, the back surface Wb side of the wafer W is ground so that the dividing groove G is exposed on the back surface Wb side. As a result, the plurality of chip forming portions 10 are separated from each other while being held by the backgrinding tape T2, and the back surface 13 is formed for each chip forming portion 10.

Next, as shown in FIG. 7C, a sealing material portion 22 (back surface sealing material portion) for sealing the back surface Wb of the wafer W is formed (back surface sealing step). The material, form (liquid, sheet-like), and forming method of the encapsulant portion 22 are the same as those described above for the encapsulant portion 22 in the first embodiment.

Next, as shown in FIG. 8A, the adhesive surface T3a of the dicing tape T3 is bonded to the back surface Wb side (encapsulating material portion 22 side) of the wafer W with the sealing material portions 21 and 22. The configuration of the dicing tape T3 is the same as described above with respect to the above-mentioned dicing tape T3 used in the first embodiment.

Next, as shown in FIG. 8B, the wafer W with the sealing material portions 21 and 22 on the dicing tape T3 is individualized (individualization step). Specifically, a plurality of wafers W with encapsulant portions 21 and 22 held in the dicing tape T3 are cut in the thickness direction along a planned cutting line in the dividing groove G around each chip forming portion 10. (In this embodiment, the tip C with the sealing material portions 21 and 22) is obtained.

Next, the chip C with a sealing material is picked up from the dicing tape T3 by, for example, an adsorption jig (not shown), and then the chip C with the sealing material is placed on a predetermined base material 50 as shown in FIG. 8C. On the other hand, implement it. The bump B of the chip C with a sealing material faces the base material 50, and the chip C with a sealing material is surface-mounted on the base material 50.

As described above, the semiconductor device X2 including the chip C with a sealing material can be manufactured. In the semiconductor device X2, the circuit surface 11 and the side surface 12 of the chip C are sealed by the sealing material portion 21, and the back surface 13 of the chip C is sealed by the sealing material portion 22.

In the method for manufacturing a semiconductor device of the present embodiment, a plurality of chip forming portions 10 are formed on the wafer W in the half-cut step (shown in FIG. 5D), and in the subsequent back grind step (shown in FIG. 7B). Therefore, the plurality of chip forming portions 10 are separated into chips. That is, according to this manufacturing method, the wafer W can be individually separated into chips C without dicing (full-cut dicing) in the entire thickness direction of the wafer W. Such a method for manufacturing a semiconductor device is suitable for suppressing chipping of the chip C.

In the back grind step (shown in FIG. 7B) of the present manufacturing method, as described above, the back surface Wb side of the wafer W is ground so that the dividing groove G is exposed to the back surface Wb side. In such a back grind step, since the split groove G is exposed on the back surface Wb side, the plurality of chip forming portions 10 are in a state of being separated from each other, and the variation of the grinding pressure with respect to each part of the back surface Wb varies among the individual chip forming portions 10. Is absorbed by. Such a configuration is suitable for suppressing cracks in the wafer W due to variations in grinding pressure during back grind.

In this manufacturing method, the circuit surface Wa side of the wafer W is sealed after the half-cut step (formation of a plurality of chip forming portions 10) and before the back grind step (individualization into chips C). The sealing material portion 21 is formed (sealing step shown in FIG. 6A). In the sealing step, the circuit surface Wa side of the plurality of chip forming portions 10 (parts of the wafer W and the mutual distance is fixed) in the wafer W can be collectively sealed. In this manufacturing method, the step of arranging the semiconductor chips separated from each other is not carried out before the sealing step. Therefore, this manufacturing method is suitable for efficiently manufacturing the semiconductor device X2 in which the circuit surface 11 and the side surface 12 of the chip C are sealed without causing a chip shift.

In the back surface sealing step (shown in FIG. 7C) of the present manufacturing method, the back surface Wb side of the plurality of chip forming portions 10 in the wafer W can be collectively sealed. In this manufacturing method, the step of arranging the semiconductor chips separated from each other is not carried out before the backside sealing step. Therefore, this manufacturing method is suitable for efficiently manufacturing the semiconductor device X2 in which the back surface 13 of the chip C is sealed without causing a chip shift.

As described above, this manufacturing method is suitable for efficiently manufacturing the semiconductor device X2 including the chip C sealed by the sealing material portions 21, 22 while suppressing chip breakage and chip shift.

In the above-mentioned method for manufacturing a semiconductor device, after the back grind step shown in FIG. 7B, the subsequent step may be carried out without carrying out the back surface sealing step shown in FIG. 7C. FIG. 9 shows a part of the steps in such a modification.

In this modification, after the step shown in FIG. 7B, the adhesive surface T3a of the dicing tape T3 is bonded to the back surface Wb side of the wafer W with the sealing material portion 21 as shown in FIG. 9A.

Next, as shown in FIG. 9B, the wafer W with the sealing material portion 21 on the dicing tape T3 is individualized (individualization step). Specifically, the wafer W with the sealing material portion 21 held on the dicing tape T3 is cut in the thickness direction along the planned cutting line in the dividing groove G around each chip forming portion 10, and a plurality of sealed pieces are sealed. A tip C with a stop material (in this modification, a tip C with a sealing material portion 21) is obtained.

Next, the chip C with a sealing material is picked up from the dicing tape T3 by, for example, an adsorption jig (not shown), and then the chip C with the sealing material is placed on a predetermined base material 50 as shown in FIG. 9C. On the other hand, implement it. The bump B of the chip C with a sealing material faces the base material 50, and the chip C with a sealing material is surface-mounted on the base material 50.

As described above, the semiconductor device X2'provided with the chip C with a sealing material can be manufactured. In the semiconductor device X2', the circuit surface 11 and the side surface 12 of the chip C are sealed by the encapsulant portion 21. From the viewpoint of protecting the chip C, the above-mentioned semiconductor device X2 further provided with a sealing material portion 22 for sealing the back surface 13 of the chip C is preferable to such a semiconductor device X2'.

The present invention will be specifically described below with reference to examples. The present invention is not limited to the examples. In addition, the specific numerical values such as the compounding amount (content), the physical property value, the parameter, etc. described below are the compounding amounts corresponding to them described in the above-mentioned "form for carrying out the invention" (forms for carrying out the invention). It can be replaced with an upper limit (numerical value defined as "less than or equal to" or "less than") or a lower limit (numerical value defined as "greater than or equal to" or "greater than or equal to") such as content), physical property value, and parameter.

<Making a sealing resin sheet>
18 parts by mass of acrylic resin (trade name "SG-280EK23", manufactured by Nagase ChemteX), 41 parts by mass of epoxy resin (trade name "HP-7200L", manufactured by DIC), and phenol resin (trade name "LVR8210-DL"). , Gunei Chemical Industry Co., Ltd.) 17 parts by mass, inorganic filler (trade name "SO-C2", spherical silica, manufactured by Admatex) 19 parts by mass, and curing catalyst (trade name "TPP-K", manufactured by Hokuko Chemical Co., Ltd.) 0.1 part by mass was added to the methyl ethyl ketone and mixed to prepare a resin composition having a solid content concentration of 20% by mass. Next, the resin composition was applied on the silicone release-treated surface of the PET separator (thickness 50 μm) having the silicone release-treated surface to form a coating film. Next, this coating film was dried by heating at 130 ° C. for 2 minutes to prepare a sheet having a thickness of 40 μm on a PET separator. By laminating the three sheets, a sealing resin sheet S having a thickness of 120 μm was produced. In the bonding, a laminator was used, the temperature condition was 70 ° C., the bonding speed was 10 mm / sec, and the pressure condition was 0.2 MPa. After that, a polytetrafluoroethylene (PTFE) film (thickness 300 μm) as a protective film was attached to one side of the sealing resin sheet S. As a result, a sealing resin sheet S with a protective film was obtained.

[Example 1]
First, as shown in FIG. 1B, a wafer W with a bump B was prepared. The wafer W has a circuit surface Wa and a back surface Wb on the opposite side of the circuit surface Wa. The bump B is a tin-silver alloy bump and is formed on the circuit surface Wa. In the wafer W with bump B, the wafer diameter is 8 inches, the wafer thickness is 725 μm, the bump height (height from the circuit surface Wa) is 160 to 170 μm, and the bump pitch is 300 μm. These configurations regarding the wafer W with the bump B are the same in Comparative Examples 1 to 3 described later.

Next, as shown in FIG. 1C, a dicing tape T1 (trade name “V series”, thickness 110 μm, manufactured by Nitto Denko) was attached to the back surface Wb of the wafer W with bump B. In the bonding, a laminator was used, the temperature condition was 40 ° C., the bonding speed was 10 mm / sec, and the pressure condition was 0.2 MPa.

Next, as shown in FIG. 1D, a dividing groove G (a depth of 100 μm, forming a grid of 9 mm × 9 mm in one section) was formed by cutting the wafer W from the circuit surface Wa (half-cut step). In this process, a dicing device (trade name "DFD6361", manufactured by Disco) is used, and the wafer W is cut by a rotating blade (trade name "ZH05-SD2000-N1-90 JJ", blade width 80 to 90 μm, manufactured by Disco). bottom. For the rotary blade, the rotation speed was 45,000 rpm and the feed rate was 30 mm / sec. After this step, the dicing tape T1 was peeled off from the wafer W.

Next, as shown in FIG. 2A, a sealing material portion 21 for sealing the circuit surface Wa side of the wafer W with bump B was formed (sealing step). Specifically, first, the sheet side of the sealing resin sheet S with the protective film described above was bonded to the circuit surface Wa side of the wafer W with bump B by a vacuum press. A vacuum press machine (trade name "VS30-2525", manufactured by Mikado Technos) was used for the vacuum press. In the vacuum press, the degree of vacuum (decompression pressure) was set to −100 kPa, the temperature condition was set to 90 ° C, and the pressure condition was set to 0.2 MPa. By the vacuum press, a part of the sealing resin sheet S enters the dividing groove G to fill the dividing groove G, and a part of each bump B (having a bump height larger than the above thickness of the sealing resin sheet S). However, it penetrated the sealing resin sheet S and went out of the sheet. Next, after the protective film was peeled off, the sealing resin sheet S was cured by heating at 150 ° C. for 1 hour. As described above, the sealing material portion 21 for sealing the circuit surface Wa side of the wafer W was formed.

Next, as shown in FIG. 2B, a backgrinding tape T2 (trade name "UB series", adhesive layer thickness 156 μm, manufactured by Nitto Denko) was attached to the wafer W with the sealing material portion 21. In the bonding, a laminator was used, the temperature condition was 25 ° C., the bonding speed was 10 mm / sec, and the pressure condition was 0.2 MPa (the backgrinding tape T2 in Comparative Examples 1 to 3 described later). The same applies to bonding).

Next, as shown in FIG. 2C, the wafer W was thinned by backgrinding (backgrinding step). Specifically, the wafer W held on the backgrinding tape T2 was thinned to a thickness of 50 μm by grinding from the back surface Wb side. In this step, a back grinding machine (trade name “DGP8760”, manufactured by DISCO) was used, and the back surface Wb side of the wafer W was ground by a grinding machine. The rotation speed of the grinding machine was 3200 rpm, and the feed rate was 3 μm / sec (first grinding for a thickness of 625 μm from the start of grinding) and 3 μm / sec (second grinding for a thickness of 50 μm after the first grinding).

Next, as shown in FIG. 4A, a dicing tape T3 (trade name “V series”, manufactured by Nitto Denko) was attached to the back surface Wb side of the wafer W with the sealing material portion 21. In the bonding, a laminator was used, the temperature condition was 40 ° C., the bonding speed was 10 mm / sec, and the pressure condition was 0.2 MPa (bonding of the dicing tape T3 in Comparative Examples 1 to 3 described later). The same applies to). After that, the backgrinding tape T2 was peeled off from the wafer W.

Next, as shown in FIG. 4B, the wafer W with the sealing material portion 21 on the dicing tape T3 is cut into a planned cutting line (in this embodiment, the dividing groove G) in the dividing groove G around each chip forming portion 10. By cutting in the thickness direction along (passing through the center in the width direction), a plurality of chips C with a sealing material were obtained (individualization step). In this process, a dicing device (trade name "DFD6361", manufactured by DISCO) is used, and a rotating blade (trade name "ZH05-SD2000-N1-90 BB", blade width 20 to 25 μm, manufactured by DISCO) is used to seal the sealing material. The wafer W with 21 was diced. In dicing, the rotation speed of the rotary blade was 45,000 rpm, and the feed rate of the rotary blade was 30 mm / sec.

[Comparative Example 1]
First, as shown in FIG. 10A, a wafer W with a bump B was prepared. Next, as shown in FIG. 10B, a backgrinding tape T2 (trade name “UB series”, adhesive layer thickness 156 μm, manufactured by Nitto Denko) was attached to the back surface Wb of the wafer W. Next, as shown in FIG. 10C, the wafer W was thinned to a thickness of 50 μm by backgrinding. The back grind conditions are the same as the back grind conditions in the back grind step of Example 1. After that, the backgrinding tape T2 was peeled off from the wafer W.

Next, as shown in FIG. 11A, the sealing material portion 22 was formed on the back surface Wb of the wafer W. Specifically, first, the sheet side of the sealing resin sheet S with a protective film was bonded to the back surface Wb of the wafer W. In the bonding, a laminator was used, the temperature condition was 60 ° C., the bonding speed was 10 mm / sec, and the pressure condition was 0.2 MPa. Next, after the protective film was peeled off, the sealing resin sheet S was cured by heating at 150 ° C. for 1 hour. As described above, the sealing material portion 22 for sealing the back surface Wb side of the wafer W was formed.

Next, as shown in FIG. 11B, the dicing tape T3 (trade name "V series", manufactured by Nitto Denko) is bonded to the back surface Wb side (sealing material portion 22 side) of the wafer W with the sealing material portion 22. rice field.

Next, as shown in FIG. 11C, the wafer W with the encapsulant portion 21 on the dicing tape T3 was cut in the thickness direction along the planned cutting line to obtain a plurality of chips C with the encapsulant. Disinfection process). The equipment used and dicing conditions in this step are the same as the equipment used and dicing conditions in the individualization step of Example 1.

[Comparative Example 2]
First, as shown in FIG. 12A, a wafer W with a bump B was prepared. Next, as shown in FIG. 12B, the sealing material portion 21 was formed on the circuit surface Wa side of the wafer W with the bump B. Specifically, first, the sheet side of the sealing resin sheet S with the protective film described above was bonded to the circuit surface Wa side of the wafer W with bump B by a vacuum press. The equipment and conditions used in the vacuum press are the same as the equipment and conditions used in the vacuum press in the sealing step in Example 1. By the vacuum press, a part of each bump B penetrated the sealing resin sheet S and came out of the sheet. Next, after the protective film was peeled off, the sealing resin sheet S was cured by heating at 150 ° C. for 1 hour. Next, as shown in FIG. 12C, a backgrinding tape T2 (trade name “UB series”, adhesive layer thickness 156 μm, manufactured by Nitto Denko) was attached to the wafer W with the sealing material portion 21.

Next, as shown in FIG. 13A, the wafer W was thinned to a thickness of 50 by backgrinding. The back grind conditions are the same as the back grind conditions in the back grind step of Example 1. Next, as shown in FIG. 13B, a dicing tape T3 (trade name “V series”, manufactured by Nitto Denko) was attached to the back surface Wb side of the wafer W with the sealing material portion 21. Next, as shown in FIG. 13C, the wafer W with the encapsulant portion 21 on the dicing tape T3 was cut in the thickness direction along the planned cutting line to obtain a plurality of chips C with the encapsulant. Disinfection process). The equipment used and dicing conditions in this step are the same as the equipment used and dicing conditions in the individualization step of Example 1.

[Comparative Example 3]
First, as shown in FIG. 14A, a wafer W with a bump B was prepared. Next, as shown in FIG. 14B, a backgrinding tape T2 (trade name “UB series”, adhesive layer thickness 156 μm, manufactured by Nitto Denko) was attached to the circuit surface Wa side of the wafer W. Next, as shown in FIG. 14C, the wafer W was thinned to a thickness of 50 μm by backgrinding. The back grind conditions are the same as the back grind conditions in the back grind step of Example 1. After that, the backgrinding tape T2 was peeled off from the wafer W.

Next, as shown in FIG. 15A, a dicing tape T3 (trade name “V series”, manufactured by Nitto Denko) was attached to the back surface Wb side of the wafer W. Next, as shown in FIG. 15B, the wafer W with the encapsulant portion 21 on the dicing tape T3 was cut in the thickness direction along the planned cutting line to obtain a plurality of chips C with the encapsulant. The equipment used and dicing conditions in this step are the same as the equipment used and dicing conditions in the individualization step of Example 1.

Next, as shown in FIG. 15C, a plurality of chips C with a sealing material were placed on the support tape T4 (trade name “HR series”, manufactured by Nitto Denko). The support tape T4 is a pressure-sensitive adhesive sheet including a base material 41 and a pressure-sensitive adhesive layer 42 on one surface in the thickness direction thereof. In this step, specifically, the chip C with the encapsulant is opposed to the circuit surface 11 of the support tape T4 at a distance, and the tip of the bump B enters the pressure-sensitive adhesive layer 42. A plurality of chips C with a sealing material were arranged on the support tape T4. The distance between adjacent chips on the support tape T4 was set to 500 μm.

Next, as shown in FIG. 16A, a sealing material portion 23 for sealing a plurality of chips C with a sealing material on the support tape T4 was formed. Specifically, first, a plurality of chips C with a sealing material on the support tape T4 were covered with the sheet side of the sealing resin sheet S with the protective film described above by a vacuum press. A vacuum press machine (trade name "VS30-2525", manufactured by Mikado Technos) was used for the vacuum press. In the vacuum press, the degree of vacuum (decompression pressure) was set to −100 kPa, the temperature condition was set to 120 ° C, and the pressure condition was set to 0.2 MPa. By the vacuum press, a part of the sealing resin sheet S enters between the circuit surface 11 of the chip C and the support tape T4, and covers the circumference of the bump B on the circuit surface 11 and the circuit surface 11. Next, after peeling off the protective film, the sealing resin sheet S was cured by heating at 150 ° C. for 1 hour. As described above, the sealing body E including the plurality of chips C with bumps B and the sealing material portion 23 was formed.

Next, as shown in FIG. 16B, the sealing body E was transferred from the support tape T4 to a dicing tape T5 (trade name “V series”, manufactured by Nitto Denko) having an adhesive surface T5a.

Next, as shown in FIG. 16C, the encapsulant E on the dicing tape T5 was cut in the thickness direction along the planned cutting line around each chip C to obtain a plurality of inserts C with an encapsulant. Individualization process). The equipment used and dicing conditions in this step are the same as the equipment used and dicing conditions in the individualization step of Example 1.

<Chip sealing property>
In each of the methods of Example 1 and Comparative Examples 1 to 3, when the circuit surface of the obtained chip with encapsulant is sealed, the chip encapsulation property is evaluated as "good", and the chip circuit surface is evaluated. When it was not sealed, the chip sealing property was evaluated as "poor". The results are shown in Table 1.

<crack>
The back surface (Example 1 and Comparative Examples 2 and 3) or the side surface (Comparative Example 1) of the chip with a sealing material obtained by each method of Example 1 and Comparative Examples 1 to 3 was observed with a microscope, and the presence or absence of cracks was observed. And examined the length. One chip with a sealing material is collected from the vicinity of the center of the work (chips with a plurality of sealing materials separated on the dicing tape) after the individualization process, and the chips with the sealing material are collected at approximately equal intervals near the outer periphery of the work. Four distant chips with encapsulant were collected and used as observation chips. Regarding the suppression of cracks, the case where the length of the crack generated in the chip is less than 20 μm is evaluated as “good”, and the case where the length of the crack generated in the chip is 20 μm or more is evaluated as “bad”. evaluated. The results are shown in Table 1.

<Chip shift>
The chip shift in each method of Example 1 and Comparative Examples 1 to 3 was investigated. One chip with a sealing material is selected from the vicinity of the center of the work (chips with a plurality of sealing materials separated on the dicing tape) after the individualization process, and the chips with the sealing material are selected at approximately equal intervals near the outer periphery of the work. Four distant chips with encapsulant were selected and used as the target chips for the chip shift survey. Regarding the suppression of chip shift, when the difference between the maximum distance and the minimum distance between the target chip and its four adjacent chips is less than 10 μm, it is evaluated as “good”, and when the difference is 10 μm or more. Was evaluated as "defective". The results are shown in Table 1.

W Wafer Wa Circuit surface Wb Back surface B Bump Ba Exposed part G Divided groove 10 Chip forming part 11 Chip circuit surface 12 Side surface 13 Back surface 14 Pillar 21 Encapsulant part 22 Encapsulant part (back surface encapsulant part)
C Chip with encapsulant X1, X1', X2, X2'Semiconductor device

Claims (4)

It has a circuit surface and a back surface opposite to the circuit surface, and has a thickness between the circuit surface and the back surface, and has a depth from the circuit surface to the middle of the thickness with respect to the wafer. A half-cut process that forms a dividing groove that divides a plurality of chip forming portions.
A sealing step of forming a sealing material portion for sealing the circuit surface side of the wafer, and a back grind step of grinding the back surface side of the wafer so that the dividing groove is exposed on the back surface side.
A method for manufacturing a semiconductor device, comprising an individualization step of cutting the encapsulant portion in the thickness direction along the dividing groove around each chip forming portion to obtain a plurality of chips with encapsulant. The wafer comprises a plurality of bumps on the circuit surface.
The method for manufacturing a semiconductor device according to claim 1, wherein each of the plurality of bumps has an exposed portion exposed from the sealing material portion on the side opposite to the circuit surface after the sealing step. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein in the sealing step, the circuit surface side of the wafer is sealed with a sealing resin sheet to form the sealing material portion. A back surface sealing step of forming a back surface encapsulating material portion for sealing the back surface side of the wafer is further included between the back grind step and the individualization step.
In the individualization step, the encapsulant portion and the back surface encapsulant portion are cut in the thickness direction along the dividing groove around each chip forming portion, according to any one of claims 1 to 3. The method for manufacturing a semiconductor device according to the description.

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