JP2022063513A - Pulse application control circuit - Google Patents

Abstract

To provide a pulse application control circuit that can apply a pulse current to a plurality of loads with high repetition with one pulse power supply.SOLUTION: In a pulse application control circuit 1 that selects and controls a load to be applied from a plurality of loads L1 to Ln by a control circuit 10, reset circuits 1 to n have a function of switching the direction of a reset current flowing in a direction in which saturable inductors Sl1 to Sln are saturated or unsaturated. The control circuit 10 controls the direction of the reset current of the reset circuit in the direction in which the saturable inductor connected to the load to which a pulse current is applied saturates during a pulse current Io output from the pulse power supply 20 at regular time intervals, such that a single pulse power supply applies a pulse current with high repetition for each of the plurality of loads.SELECTED DRAWING: Figure 2

Description

The present invention relates to a pulse application control circuit, and more particularly to a pulse application control circuit for applying a pulse high voltage and a pulse large current to a plurality of loads in a time series with one pulse power supply.

Conventionally, a pulse power supply stores energy in a capacitor or an inductor with low power, and instantaneously extracts and outputs a pulse high voltage and a pulse large current (hereinafter, simply referred to as pulse current) in a short time of microseconds or nanoseconds. Therefore, a pulse generation circuit is configured with a capacitor, an inductor, a semiconductor switch, a magnetic pulse compression circuit (saturable reactor), etc., so that a highly accurate and stable high-repetition pulse current can be generated.

Further, as a control circuit for applying a pulse current to a load using such a pulse power supply, a control circuit is configured by combining a saturable inductor and a reset circuit, and the current of the reset circuit is used as the magnetic field of the saturable inductor. A pulse current is applied to the load by energizing in the direction of saturation.

In order to generate a high-repetition pulse current, a charger, a first-stage capacitor unit equipped with a capacitor charged by this charger, and a magnetic pulse current generated by the discharge of this first-stage capacitor unit are magnetically pulsed and output. A pulse power supply provided with a pulse compression circuit and a pulse power supply capable of being highly repeatable by improving the throughput of the pulse power supply and an exposure apparatus provided with the pulse power supply are disclosed (see Patent Document 1).

Japanese Patent Application No. 2009-507477

The exposure apparatus provided with the highly repeatable pulse power supply disclosed in Patent Document 1 applies a pulse current to only one EUV lamp (that is, a load) by using one highly repeatable pulse power supply. You can only do it. Further, in order to apply a pulse current to a plurality of loads, it is necessary to prepare an exposure apparatus equipped with a highly repeatable pulse power supply according to the number of the plurality of loads.

That is, in a device (circuit) that applies the pulse current of one pulse power supply to one load, it is possible to apply the pulse current of the capacity limit of the pulse power supply to one load, but a plurality of. Since pulse power supplies are required for each load, the cost is high and it is necessary to secure a space for installing multiple pulse power supplies and devices.

Therefore, one pulse power supply and a plurality of loads are connected in parallel by a plurality of high voltage relays, respectively, and by controlling this high voltage relay, a pulse current is applied to a plurality of loads by one pulse power supply. A method of applying to is also conceivable. However, since the high voltage relay has a contact life, it needs to be replaced (maintenance). Further, since the high voltage relay has a limit in the switching speed, it cannot cope with high repetition such that the pulse current is sequentially switched to a plurality of loads for each pulse current.

In the present invention, in order to solve the above-mentioned problems, a saturable inductor and a reset circuit are connected in parallel as a set between one pulse power supply and a plurality of loads, respectively, and the current of the reset circuit is saturable. By controlling the flow so that it flows in a direction different from the direction in which the magnetic field of the inductor is saturated and the direction in which the magnetic field of the saturable inductor is unsaturated, a single pulse power supply can repeatedly apply a pulse current to multiple loads. It is an object of the present invention to provide a pulse application control circuit capable of performing.

In order to achieve the above object, in the present invention, a saturable inductor and a reset circuit are interposed in parallel between one pulse power supply and a plurality of loads as a set, and a plurality of loads are connected by a control circuit. It is a pulse application control circuit that selects and controls the load applied from the above, and the reset circuit has a function of switching the direction of the reset current flowing in the direction in which the saturable inductor becomes saturated or unsaturated. The control circuit controls the direction of the reset current of the reset circuit in the direction in which the saturable inductor connected to the load to which the pulse current is applied saturates during the pulse current output from the pulse power supply at regular time intervals. By doing so, the pulse application control circuit is characterized in that the pulse current is applied at high repetition rate for each of a plurality of loads by one pulse power supply.

Further, the control circuit is characterized by having a plurality of types of pulse current application patterns and application times for the plurality of loads.

According to the present invention, among a plurality of loads connected to one pulse power supply, the load to which the pulse current is applied is selected between the pulse currents output from the pulse power supply at regular time intervals, and the pulse current is selected. By controlling the direction of the reset current with a reset circuit in the direction in which the saturable inductor connected to the load to which is applied saturates, the saturable inductor functions as a magnetic relay without using consumables such as high voltage relays. It becomes possible.

Further, since a plurality of application patterns and application times of a plurality of loads to which a pulse current is applied are provided, various application patterns and application times can be selectively used for a plurality of loads, and for a plurality of loads. On the other hand, it is possible to realize the optimum pulse current application according to the application.

It is a figure which shows the outline of the structure of the pulse application control circuit of this embodiment. It is a circuit diagram explaining the details of the reset circuit of the pulse application control circuit of this embodiment. It is a figure explaining the time chart of various signals for controlling the pulse power source and the reset circuit of the pulse application control circuit of this embodiment. It is a figure explaining the load pattern of the pulse current and the number of times of application in the pulse application control circuit of this embodiment. It is a flowchart explaining the application control process of the pulse current in the pulse application control circuit of this embodiment.

In the present invention, a saturable inductor and a reset circuit are interposed in parallel between one pulse power supply and a plurality of loads, respectively, as a set, and a control circuit selects a load to be applied from the plurality of loads. A pulse application control circuit for applying and controlling, the reset circuit has a function of switching the direction of a reset current flowing in a direction in which the saturable inductor becomes saturated or unsaturated, and the control circuit is from the pulse power supply. One pulse by controlling the direction of the reset current of the reset circuit in the direction in which the saturable inductor connected to the load to which the pulse current is applied is saturated during the pulse current output at regular time intervals. The present invention relates to a pulse application control circuit characterized in that a pulse current is applied at high repetition rate for each of a plurality of loads by a power source.

Hereinafter, an example of the pulse application control circuit according to the present embodiment will be described with reference to the drawings. FIG. 1 is a diagram showing an outline of the configuration of the pulse application control circuit of the present embodiment. FIG. 2 is a circuit diagram illustrating the details of the reset circuit of the pulse application control circuit of the present embodiment. FIG. 3 is a diagram illustrating a time chart of various signals for controlling a pulse power supply and a reset circuit of the pulse application control circuit of the present embodiment. FIG. 4 is a diagram illustrating a load pattern of a pulse current and the number of times of application in the pulse application control circuit of the present embodiment. FIG. 5 is a flowchart illustrating a pulse current application control process in the pulse application control circuit of the present embodiment.

[1. Outline of pulse application control circuit configuration]
As shown in FIG. 1, the pulse application control circuit 1 is configured by connecting a plurality of loads L1 to Ln (n is an integer) in parallel to one pulse power supply 20. As the pulse power supply 20, a well-known pulse power supply that generates a pulse current having a high voltage and a large current required for application to the loads L1 to Ln is preferably used.

A plurality of saturable inductors SI1 to SIn (n is an integer) are interposed and connected between the pulse power supply 20 and the plurality of loads L1 to Ln, respectively. Reset circuits R1 to Rn (n is an integer) are connected to the saturable inductors SI1 to SIn, respectively. That is, in the present embodiment, the saturable inductors SI1 to SIn and the reset circuits R1 to Rn are interposed between the pulse power supply 20 and the plurality of loads L1 to Ln as a set.

A control circuit 10 is arranged in the pulse application control circuit 1. As the control circuit 10, for example, a microcomputer in which an arithmetic / control device (CPU), a memory device (ROM, RAM, flash memory), an input / output circuit, a timer circuit, and the like are mounted in one integrated circuit is preferably used. Then, in the ROM, in the pulse application control circuit 1, a plurality of programs (such as application control processing described later) for controlling the application of pulse currents to the plurality of loads L1 to Ln and application patterns to the plurality of loads L1 to Ln are obtained. Various data tables that store (load order), the number of times of application, etc. are stored. The input / output circuit of the control circuit 10 includes a trigger signal Tr that is turned on / off at regular time intervals (for example, 0.1 s) when the pulse power supply 20 outputs a pulse current, and a plurality of saturable inductors SI1 to SIn. Signals (B1 to Bn, F1 to Fn) that control the flow direction of the reset currents Ir1 to Irn flowing through the plurality of connected reset circuits R1 to Rn are connected.

With this configuration, the control circuit 10 of the pulse application control circuit 1 is also stored in the memory device based on the application pattern and the number of times of application to the plurality of loads L1 to Ln stored in the memory device (for example, ROM). By executing the program, one of the plurality of loads L1 to Ln is selected and the control of applying the pulse current Io is executed. That is, the control circuit 10 executes the program stored in the ROM to reset the reset currents Ir1 to Irn (reset currents Ir1 to Irn) of the reset circuits R1 to Rn connected to the loads L1 to Ln to which the pulse current applied by the pulse power supply 20 is applied. The direction in which n (n is an integer) flows (vertical direction in the figure) is controlled. The directions in which the reset currents Ir1 to Irn flow are the direction in which the saturable inductors SI1 to SIn are saturated (down arrow in the figure) and the direction in which they are not saturated (hereinafter referred to as unsaturated) (up arrow in the figure).

For example, when the control circuit 10 controls the load L1 to apply a pulse current, the reset current Ir1 of the reset circuit R1 connected to the saturable inductor SI1 is oriented so that the saturable inductor SI1 saturates (in the figure, in the figure). The reset currents Ir2 to Irn of the reset circuits R2 to Rn controlled to flow in the downward arrow) and connected to the saturable inductors SI2 to SI of other loads L2 to Ln are not saturated with the saturable inductors SI2 to SIn. Control the flow so that it flows in the direction (up arrow in the figure). Then, by controlling so as to generate a pulse current by the pulse power supply 20 in this state, the pulse current is applied only to the load L1.

The pulse application control circuit 1 of the present embodiment is connected to the saturable inductors SI1 to SIn connected to the loads L1 to Ln to which the pulse current is applied among the plurality of loads L1 to Ln connected to one pulse power supply 20. By controlling the directions of the reset currents Ir1 to Irn (down arrow in the figure) in the direction of saturation, the saturable inductors SI1 to SIn can function as magnetic relays without using consumables such as high voltage relays. Is possible.

[2. Details of pulse application control circuit configuration]
Hereinafter, the configuration of the pulse application control circuit 1 of the present embodiment will be described in detail with reference to FIG. As shown in FIG. 2, in the pulse application control circuit 1, a plurality of loads L1 to Ln (n is an integer) are connected in parallel to the output terminal 20a of one pulse power supply 20. At this time, assuming that the integer n is 5, five loads (loads L1 to L5) are connected in parallel. The number of loads connected by the pulse application control circuit 1 of the present embodiment (that is, a numerical value of an integer n) is not particularly limited, but one pulse power supply 20 can be used to connect a plurality of loads L1 to Ln. Since the pulse current is applied individually, if the number of connected loads L1 to Ln is too large, the frequency of applying the pulse current per unit decreases. Therefore, the number of the loads L1 to Ln (numerical value of the integer n) to be connected may be set to an upper limit (for example, 10).

As shown in FIG. 2, the pulse power supply 20 and the load L1 are connected via the saturable inductor SI1, and the reset circuit R1 is connected to the saturable inductor SI1. Similarly, the pulse power supply 20 and the load L2 are connected via the saturable inductor SI2, and the reset circuit R2 is connected to the saturable inductor SI2. The pulse power supply 20 and the load Ln (n is an integer) are connected via the saturable inductor SIn, and the reset circuit Rn is connected to the saturable inductor SIn. That is, between the pulse power supply 20 and the loads L1 to Ln, the saturable inductors SI1 to SIn and the reset circuits R1 to Rn are connected to each other as a set.

Hereinafter, the configurations of the reset circuits R1 to Rn will be described. Since the reset circuits R1 to Rn are the same circuit, only the reset circuit R1 will be described below. The reset circuit R1 is a DC power supply, four drive circuits, four isolated gate type high polar transistors (hereinafter referred to as IGBTs) Q1-1 to Q1-4, and a resistor Rr1 for stabilizing the reset current Ir1. , The circuit is composed of the iron core-filled inductance Lr1. The reset circuit R1 is connected to the control circuit 10 by two signals B1 and F1, and the control circuit 10 resets by controlling the outputs (High or Low) of the two signals B1 and F1. The direction in which the reset current Ir1 of the circuit R1 flows is controlled in the direction in which the saturable inductor SI1 to which the reset circuit R1 is connected is saturated or unsaturated.

In the above configuration, the control circuit 10 of the pulse application control circuit 1 applies pulse currents Io1 to Ion to the loads L1 to Ln as follows. That is, the control circuit 10 determines the loads L1 to Ln to which the pulse currents Io1 to Ion are applied among the saturable inductors SI1 to SIn interposed between the pulse power supply 20 and the plurality of loads L1 to Ln, respectively. Next, the flow direction of the reset currents Ir1 to Irn of the reset circuits R1 to Rn connected to the saturable inductors SI1 to SIn interposed between the pulse power supply 20 and the loads L1 to Ln to which the pulse currents Io1 to Ion are applied. To control.

Specifically, the control circuit 10 controls the load L1 to apply the pulse current Io1. The control circuit 10 controls the signal B1 to Low and the signal F1 to High. As a result, the reset current Ir1 of the reset circuit R1 flows in the direction in which the connected saturable inductor SI1 is saturated (down arrow in the figure). At this time, the control circuit 10 controls the signals B2 to Bn to High and the signals F2 to Fn to Low in the other reset circuits R2 to Rn. As a result, the reset currents Ir2 to Irn of the reset circuits R2 to Rn flow in the direction in which the connected saturable inductors SI2 to SIn are unsaturated (upper arrow in the figure).

The control circuit 10 and the pulse power supply 20 are connected to the trigger signal Tr (see FIG. 3), and the pulse power supply 20 turns on the trigger signal Tr at regular time intervals when outputting the pulse current. After turning on the trigger signal Tr, the pulse power supply 20 outputs the pulse current Io from the output terminal 20a of the pulse power supply 20 after a certain delay time (pulse formation time). When the pulse power supply 20 outputs the pulse current Io, the pulse power supply 20 turns off the trigger signal Tr. The pulse current Io output from the output terminal 20a of the pulse power supply 20 is possible because the reset current Ir1 of the reset circuit R1 flows in the direction in which the connected saturable inductor SI1 is saturated (lower arrow in the figure). The saturated inductor SI1 is saturated and the pulse current Io1 is applied to the load L1.

As described above, in the present embodiment, the control circuit 10 is controlled so that the pulse current Io is applied to one load from the plurality of loads L1 to Ln. That is, the control circuit 10 controls the flow directions of the reset currents Ir1 to Irn of the reset circuits R1 to Rn, thereby causing the saturable inductors SI1 to SIn to function as magnetic relays.

[3. Time chart of various signals by the control circuit in the pulse application control circuit]
Hereinafter, in the pulse application control circuit 1 of the present embodiment with reference to FIG. 3, a time chart of output control of various signals by the control circuit 10 will be described. In the following description, the control of applying the pulse current Io in the order of the loads L1 to Ln will be described as an example.

The control circuit 10 controls the signal B1 connected to the reset circuit R1 to Low and the signal F1 to High. As a result, the reset current Ir1 of the reset circuit R1 is allowed to flow in the direction of the down arrow (see FIG. 2) to saturate the saturable inductor SI1 (turn on like a magnetic switch). At this time, in the other saturable inductors SI2 to SIn, the reset currents Ir2 to Irn of the reset circuits R2 to Rn are kept in a non-saturated state (off in a magnetic switch) by flowing in the direction of the up arrow (see FIG. 2). Therefore, the signals B2 to Bn connected to the reset circuits R2 to Rn are controlled to High, and the signals F2 to Fn are controlled to Low. As a result, only the saturable inductor SI1 connected in series with the load L1 to which the pulse current Io is to be applied is saturated (on on the magnetic switch), and the others are unsaturated (off on the magnetic switch).

The pulse power supply 20 turns on the trigger signal Tr when outputting the pulse current Io. As a result, the pulse current Io is output from the output terminal 20a of the pulse power supply 20 after a certain delay time (pulse formation time). At this time, the pulse current Io passes through the saturable inductor SI1 which is saturated (the magnetic switch is turned on) among the saturable inductors SI1 to SIn, and the pulse current Io1 is applied to the load L1. Further, since the saturable inductors SI2 to SIn are unsaturated (the magnetic switch is off), the pulse current Io is blocked and the pulse currents Io2 to Ion are not applied to the other loads L2 to Ln.

After applying the first pulse current, the control circuit 10 detects the off of the trigger signal Tr from the pulse power supply 20, and at the same time, sets the signal F1 of the reset circuit R1 of the load L1 to which the pulse current is applied to High. Switch to Low (preparation for applying a pulse to the load L2). As a result, the reset current Ir1 of the reset circuit R1 connected to the saturable inductor SI1 is allowed to flow in the direction of the up arrow (see FIG. 2) to bring the saturable inductor SI1 into an unsaturated state (turned off like a magnetic switch). ..

The control circuit 10 controls the signal B2 connected to the reset circuit R2 to Low and the signal F2 to High. As a result, the reset current Ir2 of the reset circuit R2 is allowed to flow in the direction of the down arrow (see FIG. 2) to saturate the saturable inductor SI2 (turn on like a magnetic switch). The other saturable inductors SI1 and SI3 to SIn maintain an unsaturated state (turned off in terms of a magnetic switch).

The pulse power supply 20 turns on the trigger signal Tr when outputting the pulse current. As a result, the pulse current Io is output from the output terminal 20a of the pulse power supply 20 after a certain delay time (pulse formation time). At this time, the pulse current Io passes through the saturable inductor SI2 which is saturated (the magnetic switch is turned on) among the saturable inductors SI1 to SIn, and the pulse current Io2 is applied to the load L2. Since the saturable inductors SI1 and SI3 to SIn are unsaturated (the magnetic switch is off), the pulse current Io is blocked and the pulse currents Io1 and Io3 to Ion are not applied to the other loads L1 and L3 to Ln.

After applying the second pulse current to the load L2, the control circuit 10 detects that the trigger signal Tr from the pulse power supply 20 is turned off, and at the same time, switches the signal B2 of the reset circuit R2 to High and the signal F2 to Low (next). Preparation for applying a pulse to the load L3).

The control circuit 10 also controls the directions of the reset currents Ir1 to Irn flowing through the reset circuits R1 to Rn connected to the saturable inductors SI1 to SIn even after the second pulse current is output (the pulse current is applied). The direction in which only the reset current flowing in the reset circuit of the saturable inductor connected to the load is saturated (magnetic switch is on), and the direction in which the reset current flowing in the other reset circuits is unsaturated (magnetic switch is off). After finally applying the pulse current to the nth load Ln, the pulse current is returned to the application to the load L1 and controlled to be repeatedly applied to the loads L1 to Ln once in order.

As described above, in the present embodiment, the control circuit 10 is turned on / off from the pulse power supply 20 to the control circuit 10 at regular time intervals (for example, 0.1S) between off and on of the trigger signal Tr. The loads L1 to Ln to which the pulse current Io is applied are determined, only the saturable inductors SI1 to SIn of the applied loads L1 to Ln are saturated (the magnetic switch is turned on), and the other loads L1 to Ln are subjected to. Control is performed so that the saturable inductors SI1 to SIn are unsaturated (the magnetic switch is turned off).

Hereinafter, in the pulse application control circuit 1 of the present embodiment with reference to FIG. 4, a plurality of types of pulse current application patterns and application times of the pulse currents to the plurality of loads L1 to Ln by the control circuit 10 will be described. In the following description, for ease of understanding, a plurality of loads will be described as 5 units (loads L1 to L5, that is, n = 5). As described above, the control circuit 10 is a microcomputer including an arithmetic / control device (CPU), a memory device (ROM, RAM, flash memory), an input / output circuit, a timer circuit, and the like. Further, in the memory device, a plurality of types of load pattern tables in which application patterns (load order) and application times for the plurality of loads L1 to L5 are set are stored in advance as data tables.

In the load pattern table shown in FIG. 4A, the load order for the plurality of loads L1 to L5 is applied to the uppermost stage, and the pulse current is applied to the lower stage among the plurality of loads L1 to L5 according to the load order. The applied load of the above is further set, and the number of times of application of the pulse current is set in the lower stage thereof. That is, it is set that the pulse current is applied to the plurality of loads L1 to L5 once in the order of load L1 → load L2 → load L3 → load L4 → load L5.

In the load pattern table shown in FIG. 4B, the load order for the plurality of loads L1 to L5 is applied to the uppermost stage, and the pulse current is applied to the lower stage among the plurality of loads L1 to L5 according to the load order. The applied load of the above is further set, and the number of times of application of the pulse current is set in the lower stage thereof. That is, pulse currents are applied to a plurality of loads L1 to L5 five times in the order of load L5 → load L4 → load L3 → load L2 → load L1 (that is, the reverse order of the load pattern shown in FIG. 4A). Is set to apply.

In the load pattern table shown in FIG. 4C, the load order for the plurality of loads L1 to L5 is applied to the uppermost stage, and the pulse current is applied to the lower stage among the plurality of loads L1 to L5 according to the load order. The applied load of the above is further set, and the number of times of application of the pulse current is set in the lower stage thereof. That is, the number of times of application to the plurality of loads L1 to L5 is different in the order of load L1 → load L2 → load L3 → load L4 → load L5 (5 times for L1 and L2). Is set to apply the pulse current 10 times, 8 times to L3, 3 times to L4, and 7 times to L5).

In the load pattern table shown in FIG. 4D, the load order for the plurality of loads L1 to L5 is applied to the uppermost stage, and the pulse current is applied to the lower stage among the plurality of loads L1 to L5 according to the load order. The applied load of the above is further set, and the number of times of application of the pulse current is set in the lower stage thereof. That is, of the plurality of loads L1 to L5, the load L1 → the load L3 → the load L5 → the load L2 → the load L4 are applied three times each for the load L1, the load L3, and the load L4, and the load L2 and the load L4 are applied in this order. It is set to apply the pulse current twice.

As described above, according to the load pattern table of the present embodiment, by controlling the directions of the reset currents Ir1 to Ir5 in the reset circuits R1 to R5 by the control circuit 10, a plurality of loads L1 → load L5 as described above. The pulse current can be applied in order by the number of times of application once to each (FIG. 4A). Further, it is also possible to apply a pulse current (FIG. 4 (b)) by applying the pulse current five times in the order of a plurality of loads L5 → load L1.

Further, pulse currents are applied in the order of load L1 → load L5 to a plurality of loads L1 to L5 at different application times (5, 10, 8, 3, 7 times) (FIG. 4 (c)). You can also. Further, pulse currents are applied to a plurality of loads L1 to L5 in a different order (load L1 → load L3 → load L5 → load L2 → load L4) with different application times (3 or 2 times) (3 or 2 times). FIG. 4 (d)) can also be performed. The plurality of types of load pattern tables shown in FIG. 4 are merely examples, and are not limited to these, and various application patterns and application times can be appropriately set and used. Further, one type of load pattern table may be used repeatedly, or a plurality of types may be used in combination. This makes it possible to apply pulse currents to a plurality of loads L1 to L5 having more variations.

As described above, in the pulse application control circuit 1 of the present embodiment, the order of the plurality of applied loads L1 to L5 to which the pulse current is applied and the pulse to be applied are according to the installation positions (arrangements) of the plurality of loads L1 to L5. Since the number of times the current is applied can be appropriately set, it is possible to efficiently apply the pulse current according to the application of various devices (devices) in which the pulse application control circuit 1 is used.

Hereinafter, in the pulse application control circuit 1 of the present embodiment with reference to FIG. 5, the pulse current application control process for a plurality of loads L1 to Ln by the control circuit 10 will be described. This process is a program stored in the memory device (ROM, RAM) constituting the control circuit 10, and is read from the memory device (ROM, RAM) by the arithmetic / control device (CPU) constituting the control circuit 10. It is a process that is executed.

The calculation / control device of the control circuit 10 (hereinafter simply referred to as the control circuit 10) determines a load pattern for executing the application of the pulse current from a plurality of types of load pattern tables (see FIG. 4) stored in the memory device. (Step S10). That is, a load pattern table (multiple patterns can be selected) to be used is selected from a plurality of types of load pattern tables, and the order of loads L1 to Ln to which a pulse current is applied and the number of times of application are combined with the number of executions of the selected load pattern table. Is determined and temporarily stored in the memory device (RAM).

The control circuit 10 controls the directions of the reset currents Ir1 to Irn of the reset circuits R1 to Rn according to the order and the number of times of the loads L1 to Ln stored in the memory device (RAM), and applies the pulse current to the load L1. Only the saturable inductors SI1 to SIn connected in series with the to Ln are set to the saturated state (magnetic switch on), and the other saturable inductors SI1 to SIn are set to the unsaturated state (magnetic switch off) (step S11).

The control circuit 10 detects the on of the trigger signal Tr from the pulse power supply 20 (step S12). As a result, a pulse current is output from the pulse power supply 20 after a certain delay time (pulse formation time), and is saturated from among the saturable inductors SI1 to SI (magnetic switch) connected in series with the applied loads L1 to Ln. The pulse current is applied only to the loads L1 to Ln controlled in the state (magnetic switch on).

When the control circuit 10 detects that the trigger signal Tr from the pulse power supply 20 is turned off, the saturable inductors SI1 to SIn to which the pulse current is applied are brought into an unsaturated state (magnetic switch off) (step S13). As a result, all the saturable inductors SI1 to SIn connected in series to all the loads L1 to Ln become unsaturated (magnetic switch off), and the pulse current is not applied to the loads L1 to Ln.

The control circuit 10 determines whether or not the control for applying the pulse current is completed (step S14), and if it is determined that the control is completed (step S14: Yes), the control circuit 10 ends the application control process. On the other hand, when it is determined that the process has not been completed (step S14: No), the process proceeds to step S11, and the pulse current is repeatedly applied to the loads L1 to Ln to which the next pulse current is applied. The determination of the end of the control for applying the pulse current in step 14 is whether or not all the execution times of the load pattern table temporarily stored in the memory device (RAM) have been completed in step S10.

As described above, the control circuit 10 of the pulse application control circuit 1 is a reset circuit R1 to Rn according to the order and the number of times of application of the pulse current to the loads L1 to Ln stored in the memory device (RAM). Only the saturable inductors SI1 to SI connected in series with the loads L1 to Ln to which the pulse current is applied are set to the saturated state (magnetic switch on) by controlling the flow direction of the reset currents Ir1 to Irn, and the other saturable inductors SI1 to SI1 to By setting the SIn to an unsaturated state (magnetic switch off), the control of applying a pulse current to one of the plurality of loads L1 to Ln is repeatedly executed. In this way, by making the saturable inductors SI1 to SIn function as magnetic switches, it is possible to obtain a pulse application control circuit 1 capable of sequentially switching and applying a pulse current to a plurality of loads L1 to Ln at high speed. can.

Although the present invention has been described above through the above embodiments, the present invention is not limited thereto. Moreover, each of the above-mentioned effects is merely a list of the most suitable effects resulting from the present invention, and the effects according to the present invention are not limited to those described in the present embodiment.

1 Pulse application control circuit 10 Control circuit 20 Pulse power supply R1 to Rn Reset circuit SI1 to SIn Saturable inductor L1 to Ln Load Io1 to Ion Applied current

Claims (2)

A pulse that connects a saturable inductor and a reset circuit as a set between one pulse power supply and multiple loads in parallel, and selects and controls the load to be applied from multiple loads by the control circuit. It is an application control circuit,
The reset circuit has a function of switching the direction of the reset current flowing in the direction in which the saturable inductor becomes saturated or unsaturated.
The control circuit directs the reset current of the reset circuit in the direction in which the saturable inductor connected to the load to which the pulse current is applied saturates during the pulse current output from the pulse power supply at regular time intervals. A pulse application control circuit characterized in that a pulse current is applied at high repetition rate for each of a plurality of loads by one pulse power supply by controlling. The pulse application control circuit according to claim 1, wherein the control circuit includes a plurality of types of pulse current application patterns and application times for the plurality of loads.

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