JP2022062133A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device capable of achieving high definition.

SOLUTION: A display device according to an embodiment includes: a semiconductor layer; a scanning line opposed to the semiconductor layer; a signal line connected to the semiconductor layer; a pedestal electrode in contact with the semiconductor layer; and a pixel electrode connected to the pedestal electrode. Thickness of the pedestal electrode is smaller than that of the signal line.

SELECTED DRAWING: Figure 4

COPYRIGHT: (C)2022,JPO&INPIT

Description

Embodiments of the present invention relate to display devices.

The display device includes a signal line to which a video signal is supplied, a pixel electrode arranged in a pixel, and a switching element interposed between the signal line and the pixel electrode. The switching element includes a semiconductor layer electrically connected to each of the signal line and the pixel electrode.

The pixel electrode may be formed of a transparent conductive material such as ITO (indium tin oxide). In this case, it is difficult to directly connect the semiconductor layer and the pixel electrode because the adhesion between the semiconductor layer and the transparent conductive material is low. Therefore, in the conventional display device, a metal pedestal formed by simultaneously patterning with the same material as the signal line is interposed between the semiconductor layer and the pixel electrode, and both are indirectly connected.

Japanese Unexamined Patent Publication No. 7-13180

In recent years, there has been an increasing demand for higher definition display devices and improved moving image display capabilities. The moving image display ability is improved by increasing the drive frequency, for example, but in this case, it is necessary to make the signal line sufficiently thick in order to prevent the delay of the video signal. Then, the layer that is the source of the signal line and the pedestal must be finely patterned, which is accompanied by manufacturing technical difficulties. Therefore, the display device cannot be sufficiently high-definition.

Therefore, one of the purposes of the present disclosure is to provide a display device capable of high definition.

The display device according to the embodiment is connected to the semiconductor layer, the scanning line facing the semiconductor layer, the signal line connected to the semiconductor layer, the pedestal electrode in contact with the semiconductor layer, and the pedestal electrode. It is equipped with a pixel electrode. The thickness of the pedestal electrode is smaller than the thickness of the signal line.

FIG. 1 is a perspective view showing an example of the appearance of the liquid crystal display device according to the first embodiment. FIG. 2 is a perspective view schematically showing an example of the first substrate in the first embodiment. FIG. 3 is a plan view schematically showing an example of the sub-pixels in the first embodiment. FIG. 4 is a schematic cross-sectional view of the display panel along line IV-IV in FIG. FIG. 5 is a schematic cross-sectional view of the display panel along the VV line in FIG. FIG. 6A is a schematic cross-sectional view showing the manufacturing process of the first substrate in the first embodiment. FIG. 6B is a schematic cross-sectional view showing the manufacturing process following FIG. 6A. FIG. 6C is a schematic cross-sectional view showing the manufacturing process following FIG. 6B. FIG. 6D is a schematic cross-sectional view showing the manufacturing process following FIG. 6C. FIG. 6E is a schematic cross-sectional view showing the manufacturing process following FIG. 6D. FIG. 6F is a schematic cross-sectional view showing the manufacturing process following FIG. 6E. FIG. 7 is a schematic cross-sectional view of the display panel according to the comparative example. FIG. 8 is a schematic plan view of the elements included in the display panel according to the comparative example. FIG. 9 is a schematic plan view of the elements included in the display panel according to the first embodiment. FIG. 10 is a schematic cross-sectional view of a display panel included in the display device according to the second embodiment. FIG. 11A is a schematic cross-sectional view showing the manufacturing process of the first substrate in the second embodiment. 11B is a schematic cross-sectional view showing the manufacturing process following FIG. 11A. 11C is a schematic cross-sectional view showing the manufacturing process following FIG. 11B. 11D is a schematic cross-sectional view showing the manufacturing process following FIG. 11C. 11E is a schematic cross-sectional view showing the manufacturing process following FIG. 11D. 11F is a schematic cross-sectional view showing the manufacturing process following FIG. 11E. FIG. 12A is a schematic plan view showing the manufacturing process of the first substrate in the second embodiment. 12B is a schematic plan view showing the manufacturing process following FIG. 12A. 12C is a schematic plan view showing the manufacturing process following FIG. 12B. FIG. 13 is a schematic cross-sectional view of a display panel included in the display device according to the third embodiment. FIG. 14A is a schematic cross-sectional view showing the manufacturing process of the first substrate in the third embodiment. FIG. 14B is a schematic cross-sectional view showing the manufacturing process following FIG. 14A. 14C is a schematic cross-sectional view showing the manufacturing process following FIG. 14B. FIG. 14D is a schematic cross-sectional view showing the manufacturing process following FIG. 14C. FIG. 14E is a schematic cross-sectional view showing the manufacturing process following FIG. 14D. FIG. 14F is a schematic cross-sectional view showing the manufacturing process following FIG. 14E. FIG. 14G is a schematic cross-sectional view showing the manufacturing process following FIG. 14F. FIG. 14H is a schematic cross-sectional view showing the manufacturing process following FIG. 14G. FIG. 15 is a schematic cross-sectional view of a display panel included in the display device according to the fourth embodiment. FIG. 16 is a schematic cross-sectional view of a display panel included in the display device according to the fifth embodiment. FIG. 17 is a schematic cross-sectional view of the display panel at a position different from that of FIG. FIG. 18 is a schematic cross-sectional view of a display panel included in the display device according to the sixth embodiment.

Some embodiments will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention, which are naturally included in the scope of the present invention. Further, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but the drawings are merely examples and are merely examples of the present invention. It does not limit the interpretation. Further, in the present specification and each figure, components exhibiting the same or similar functions as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and duplicate detailed description may be omitted as appropriate. ..

In each embodiment, a transmissive liquid crystal display device is disclosed as an example of the display device. This liquid crystal display device can be used in various devices such as a Virtual Reality (VR) viewer, a smartphone, a tablet terminal, a mobile phone terminal, a personal computer, a television receiving device, an in-vehicle device, a game device, and a monitor for a digital camera. can.

It should be noted that each embodiment does not prevent the application of the individual technical ideas disclosed in each embodiment to other types of display devices. For example, at least a part of the configurations disclosed in each embodiment is a reflective liquid crystal display device, a self-luminous display device including an organic electroluminescence element, an electronic paper type display device having an electrophoresis element, and Micro Electro. It can also be applied to a display device to which a mechanical system (MEMS) is applied, a display device to which electrochromism is applied, and the like.

[First Embodiment]
FIG. 1 is a perspective view showing an example of the appearance of a liquid crystal display device DSP (hereinafter, referred to as a display device DSP) according to the first embodiment. In the following description, the first direction X, the second direction Y and the third direction Z are defined as illustrated. The first direction X, the second direction Y, and the third direction Z are, for example, directions that intersect each other perpendicularly, but may intersect at an angle other than vertical. The direction indicated by the arrow in the third direction Z may be referred to as up or up, and the opposite direction may be referred to as down or down.

The display device DSP includes a display panel PNL, a lighting device BL, and a first polarizing plate PL1. The display panel PNL, the lighting device BL, and the first polarizing plate PL1 are laminated in the third direction Z. A second polarizing plate PL2, which will be described later, is arranged between the display panel PNL and the lighting device BL.

The display panel PNL includes a first substrate SU1, a second substrate SU2, and a liquid crystal layer (liquid crystal layer LC described later) arranged between the first substrate SU1 and the second substrate SU2. The first substrate SU1 includes a connection portion CN. The connection portion CN includes a terminal for connecting a signal supply source such as a flexible circuit board or an IC chip.

For example, the lighting device BL is between a light guide plate facing the first substrate SU1 and a light source such as a plurality of light emitting diodes (LEDs) arranged along the end of the light guide plate, and between the light guide plate and the display panel PNL. It is equipped with an optical sheet such as a prism sheet or a diffusion sheet arranged in. However, the configuration of the lighting device BL is not limited to this example.

FIG. 2 is a perspective view schematically showing an example of the first substrate SU1. The first substrate SU1 includes a display area DA and a pair of drive circuit PCs arranged outside the display area DA. The display area DA includes a large number of pixels PX arranged in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP displaying, for example, red, green, and blue. The pixel PX may include a sub-pixel SP that displays another color such as white. The drive circuit PC supplies a signal (a scanning signal described later) for driving the sub-pixel SP.

FIG. 3 is a plan view schematically showing an example of the sub-pixel SP. The first substrate SU1 includes a plurality of scanning lines G and a plurality of signal lines S. The plurality of scanning lines G extend in the first direction X and are arranged in the second direction Y. The plurality of signal lines S extend in the second direction Y and are arranged in the first direction X.

In the example of this figure, the region partitioned by the two adjacent scanning lines G and the two adjacent signal lines S corresponds to one sub-pixel SP. The first substrate SU1 includes a pixel electrode EL1 provided for each sub-pixel SP, a switching element SW, and a pedestal MB. In the illustrated example, the pixel electrode EL1 has a shape extending linearly, but may have such a shape extending linearly or a comb tooth shape including a plurality of slits.

The switching element SW includes a semiconductor layer SC. The semiconductor layer SC can be formed of, for example, polysilicon, but is not limited to this example. The semiconductor layer SC extends while bending and intersects the scanning line G once. The semiconductor layer SC may intersect the scanning line G twice.

The pedestal MB is superimposed on the pixel electrode EL1 and the semiconductor layer SC in a plan view. In the illustrated example, the pedestal MB has a rectangular shape, but is not limited to this example.

The signal line S is electrically connected to the semiconductor layer SC through the first contact hole CH1. The pedestal MB is electrically connected to the semiconductor layer SC through the second contact hole CH2. The pixel electrode EL1 is electrically connected to the pedestal MB through the third contact hole CH3.

FIG. 4 is a schematic cross-sectional view of the display panel PNL along the IV-IV line in FIG. FIG. 5 is a schematic cross-sectional view of the display panel PNL along the VV line in FIG. As shown in FIGS. 4 and 5, the first substrate SU1 includes a first base material B1, undercoat layers UC1 and UC2, insulating layers IL1 to IL6, an alignment film AL1, a light-shielding layer LS, and a semiconductor layer. It includes an SC, a scanning line G, a signal line S, a pixel electrode EL1, and a common electrode EL2.

The light-shielding layer LS is provided on the upper surface of the first base material B1. The undercoat layer UC1 covers the upper surfaces of the light-shielding layer LS and the first base material B1. The undercoat layer UC2 covers the undercoat layer UC1. The semiconductor layer SC is provided on the undercoat layer UC2 and faces the scanning line G. Further, the region of the semiconductor layer SC facing the scanning line G faces the light-shielding layer LS. The insulating layer IL1 covers the semiconductor layer SC and the undercoat layer UC2. The scanning line G is provided on the insulating layer IL1. The insulating layer IL2 covers the scanning line G and the insulating layer IL1. The insulating layer IL3 covers the insulating layer IL2.

The signal line S is provided on the insulating layer IL3. The insulating layer IL4 covers the signal line S and the insulating layer IL3. The pedestal MB is provided on the insulating layer IL4. The insulating layer IL5 covers the pedestal MB and the insulating layer IL4. The common electrode EL2 is provided on the insulating layer IL5 and extends over a plurality of sub-pixels SP. The insulating layer IL6 covers the common electrode EL2 and the insulating layer IL5. The pixel electrode EL1 is provided on the insulating layer IL6. The alignment film AL1 covers the pixel electrode EL1 and the insulating layer IL6.

As shown in FIGS. 4 and 5, the second substrate SU2 includes a second base material B2, a black matrix BM (light-shielding layer), a color filter layer CF, an overcoat layer OC, and an alignment film AL2. ing. The black matrix BM is provided on the lower surface of the second base material B2 and faces the scanning line G and the signal line S. The color filter layer CF covers the lower surfaces of the black matrix BM and the second base material B2. The color filter layer CF includes a plurality of color filters of colors corresponding to the sub-pixel SP. The black matrix BM may be provided below the color filter layer CF. The overcoat layer OC covers the color filter layer CF. The alignment film AL2 covers the overcoat layer OC.

The liquid crystal layer LC described above is arranged between the alignment film AL1 and the alignment film AL2. The liquid crystal layer LC has a positive or negative dielectric anisotropy. The first polarizing plate PL1 is arranged on the upper surface of the second base material B2. The second polarizing plate PL2 is arranged on the lower surface of the first base material B1. The absorption axes of the first polarizing plate PL1 and the second polarizing plate PL2 are orthogonal to each other.

The first base material B1 and the second base material B2 can be made of, for example, Hokeisan glass having a thickness of about 0.2 mm, but may be made of a resin such as polyimide. The alignment films AL1 and AL2 are, for example, polyimide films subjected to photo-alignment treatment, but may be polyimide films subjected to rubbing alignment treatment. The undercoat layer UC1 is, for example, a silicon oxide film, and the undercoat layer UC2 is, for example, a silicon nitride film. The insulating layers IL1 and IL2 are, for example, silicon oxide films. The insulating layers IL3, IL4, and IL6 are, for example, silicon nitride films. The insulating layer IL5 is, for example, a positive organic insulating film. The overcoat layer OC is, for example, a non-photosensitive organic film. The color filter of each color included in the color filter layer CF is, for example, a negative resist containing a pigment of each color. The black matrix BM is, for example, a negative resist containing a black pigment.

The pixel electrode EL1 and the common electrode EL2 can be formed of a transparent conductive material such as ITO (indium tin oxide). The scanning line G and the light-shielding layer LS are made of, for example, a molybdenum-tungsten alloy. The semiconductor layer SC is, for example, polysilicon obtained by polycrystallizing amorphous silicon by a laser annealing method.

The signal line S has, for example, a three-layer structure in which titanium, aluminum, and titanium are laminated in this order. The pedestal MB has, for example, a single-layer structure made of titanium, but may have a multi-layer structure. The thickness of the pedestal MB is smaller than the thickness of the signal line S. As an example, the thickness of the pedestal MB is less than half the thickness of the signal line S. Further, as an example, the thickness of the pedestal MB is 0.1 μm or more and 0.2 μm or less. In FIG. 4, the thickness of the signal line S is larger than the thickness of the scanning line G, but the present invention is not limited to this example.

The materials of the first substrate SU1 and the second substrate SU2 exemplified above are not limited, and each element can be formed of various materials.

The first contact hole CH1 penetrates the insulating layers IL1 to IL3. The second contact hole CH2 penetrates the insulating layers IL1 to IL4. The third contact hole CH3 penetrates the insulating layers IL5 and IL6. The signal line S is in contact with the semiconductor layer SC through the first contact hole CH1. The pedestal MB is in contact with the semiconductor layer SC through the second contact hole CH2. The pixel electrode EL1 is in contact with the pedestal MB through the third contact hole CH3.

As described above, in the present embodiment, the signal line S is electrically connected to the semiconductor layer SC through the first contact hole CH1 penetrating the first insulating layer (insulating layers IL1 to IL3), and the pedestal MB is the first. It is electrically connected to the semiconductor layer SC through the second contact hole CH2 penetrating the insulating layer, and the pixel electrode EL1 is electrically connected to the pedestal MB through the third contact hole CH3 penetrating the second insulating layer (insulating layer IL5, IL6). It is connected to the. Further, the first substrate SU1 includes a third insulating layer (insulating layer IL4) provided between the first insulating layer and the second insulating layer, and the second contact hole CH2 has the first insulating layer. In addition, it penetrates the third insulating layer. At least a part (a part outside the first contact hole CH1) of the signal line S is located between the first insulating layer and the third insulating layer, and the pedestal MB is at least a part (a part of the second contact hole CH2). The outer portion) is located between the third insulating layer and the second insulating layer. That is, in the present embodiment, the signal line S and the pedestal MB are provided in different layers.

Since a transparent conductive material such as ITO has low adhesion to the semiconductor layer SC, conduction failure may occur if the structure is such that the pixel electrode EL1 and the semiconductor layer SC are directly connected. On the other hand, in the present embodiment, the metal pedestal MB is interposed between the pixel electrode EL1 and the semiconductor layer SC. Since the adhesion between the pixel electrode EL1 and the pedestal MB and the adhesion between the pedestal MB and the semiconductor layer SC are both good, the conduction failure can be suppressed.

A common voltage is applied to the common electrode EL2. When a scanning signal is supplied to the scanning line G and a video signal is supplied to the signal line S, this video signal is applied to the pixel electrode EL1 via the semiconductor layer SC and the pedestal MB. As shown in FIG. 5, a fringe electric field EF is generated based on the potential difference between the pixel electrode EL1 and the common electrode EL2. This fringe electric field EF acts on the liquid crystal layer LC to rotate the liquid crystal molecules contained in the liquid crystal layer LC from the initial orientation direction. The display device DSP may be a normal black mode in which the sub-pixel SP on which the fringe electric field EF acts is a bright display, or a normal white mode in which the sub-pixel SP on which the fringe electric field EF acts is a dark display. You may.

The structure of the display panel PNL is not limited to the examples shown in FIGS. 4 and 5. For example, the pixel electrode EL1 and the common electrode EL2 may be arranged in the same layer, or the common electrode EL2 may be arranged between the liquid crystal layer LC and the pixel electrode EL1. Further, the display panel PNL may be in a mode in which a vertical electric field parallel to the third direction Z is used instead of the fringe electric field EF. In this case, the common electrode EL2 is arranged on the second substrate SU2. In addition, various modes can be applied to the display panel PNL.

Here, an example of the manufacturing process of the first substrate SU1 will be described. 6A to 6F are schematic cross-sectional views showing a manufacturing process of the first substrate SU1. In FIG. 6A, the undercoat layers UC1 and UC2, the insulating layers IL1 to IL3, the light-shielding layer LS, the semiconductor layer SC, and the scanning line G are formed on the first base material B1.

In FIG. 6B, the first contact hole CH1 penetrating the insulating layers IL1 to IL3 is formed. In this state, a part of the semiconductor layer SC is exposed through the first contact hole CH1. In FIG. 6C, the signal line S is formed so as to pass through the first contact hole CH1. As a result, the signal line S comes into contact with the semiconductor layer SC through the first contact hole CH1.

In FIG. 6D, the insulating layer IL4 covering the signal line S and the insulating layer IL3 is formed. In FIG. 6E, the second contact hole CH2 penetrating the insulating layers IL1 to IL4 is formed. In this state, a part of the semiconductor layer SC is exposed through the second contact hole CH2.

In FIG. 6F, the pedestal MB is formed so as to cover the second contact hole CH2. The pedestal MB contacts the semiconductor layer SC through the second contact hole CH2. After that, the insulating layer IL5, the common electrode EL2, the insulating layer IL6, the pixel electrode EL1 and the alignment film AL1 are formed in this order, and the first substrate SU1 shown in FIG. 4 is completed.

As described above, in the present embodiment, the signal line S and the pedestal MB, which function as the source electrode and the drain electrode of the switching element SW including the semiconductor layer SC, are formed in different layers and different materials in different manufacturing processes. To.

Here, the effects of this embodiment will be described below. FIG. 7 is a schematic cross-sectional view of the display panel XPNL according to a comparative example with the present embodiment. The display panel XPNL is different from the display panel PNL according to the present embodiment shown in FIG. 4 in that the pedestal MB is provided in the same layer as the signal line S and does not include the insulating layer IL4. The pedestal MB is made of the same material in the same manufacturing process as the signal line S. Therefore, in the display panel XPNL, the thickness of the pedestal MB is the same as the thickness of the signal line S.

FIG. 8 is a schematic plan view of the signal line S, the pedestal MB, the first contact hole CH1 and the second contact hole CH2 included in the display panel XPNL. In order to realize the high-definition sub-pixel SP, it is necessary to reduce the distance D1 between the adjacent signal lines S. However, in this comparative example, since the signal line S and the pedestal MB are formed in the same layer, a sufficient distance D2 must be secured between them in order to prevent a short circuit between the signal line S and the pedestal MB. When the distance D2 is made extremely small to make the sub-pixel SP high-definition, extremely high processing accuracy is required, and there is a limit to the improvement of the fineness.

Further, in order to prevent signal delay in the signal line S, it is necessary to increase the thickness of the signal line S. In particular, in an electronic device such as a VR viewer, the drive frequency may be increased to enhance the moving image display capability, and in this case, there is a great demand for suppressing signal delay. In the comparative example, when the thickness of the signal line S is increased, the thickness of the pedestal MB is also increased, and it is more difficult to improve the processing accuracy of these.

FIG. 9 is a schematic plan view of the signal line S, the pedestal MB, the first contact hole CH1 and the second contact hole CH2 included in the display panel PNL according to the present embodiment. In the present embodiment, since the signal line S and the pedestal MB are formed in different layers, even if the distance D2 is reduced, the two are not short-circuited. Further, even when the thickness of the signal line S is increased, high processing accuracy is not required as in the comparative example.

In the case of the present embodiment, the distance D1 between the adjacent signal lines S and the distance D3 between the adjacent pedestals MB are factors that determine the definition of the sub-pixel SP. As an example, the diameter of the second contact hole CH2 is set to 2.0 μm, and the width of the pedestal MB in the first direction X is set to 3.0 μm so as to cover the entire second contact hole CH2. Further, when the width of the signal line S in the first direction X is 1.5 μm and the distance D2 is set to a very small value of 1.5 μm, the width of the sub-pixel SP in the first direction X is 7.5 μm. This corresponds to a high definition of 1100 ppi or higher.

As described above, in the present embodiment, the sub-pixel SP can be made high-definition by forming the pedestal MB in a layer different from the signal line S. Further, since the effect of this high definition can be obtained even if the signal line S is made thicker, it is possible to suppress the signal delay in the signal line S. Further, since the pedestal MB is thinner than the signal line S, unevenness caused by the pedestal MB is unlikely to occur.

[Second Embodiment]
The second embodiment will be described below. The same configuration as in the first embodiment can be applied to the configuration not particularly mentioned.

FIG. 10 is a schematic cross-sectional view of a display panel PNL included in the display device DSP according to the present embodiment. The display panel PNL shown in FIG. 10 is different from the display panel PNL shown in FIG. 4 in that the wiring connection layer SE and the insulating layer IL7 (fourth insulating layer) are further provided and the insulating layer IL4 is not provided.

For example, the wiring connection layer SE can be formed in the same layer as the pedestal MB with the same material as the pedestal MB. The wiring connection layer SE has, for example, a single-layer structure made of titanium, but is not limited to this example. The wiring connection layer SE covers the first contact hole CH1 and is electrically connected to the semiconductor layer SC through the first contact hole CH1.

The thickness of the wiring connection layer SE and the pedestal MB is smaller than the thickness of the signal line S. As an example, the thickness of the wiring connection layer SE and the pedestal MB is less than half the thickness of the signal line S. Further, as an example, the thickness of the wiring connection layer SE and the pedestal MB is 0.1 μm or more and 0.2 μm or less.

The insulating layer IL7 is provided between the insulating layers IL3 and IL5 and covers the pedestal MB and the insulating layer IL3. The insulating layer IL7 also covers a part of the wiring connection layer SE. The first contact hole CH1 penetrates the insulating layer IL7 in addition to the insulating layers IL2 and IL3. The signal line S is provided on the insulating layer IL7 and is in contact with the wiring connection layer SE in the first contact hole CH1. In this way, the signal line S and the semiconductor layer SC are electrically connected through the first contact hole CH1 and via the wiring connection layer SE.

The third contact hole CH3 penetrates the insulating layer IL7 in addition to the insulating layer IL5. The pixel electrode EL1 is electrically connected to the pedestal MB through the third contact hole CH3.

Here, an example of the manufacturing process of the first substrate SU1 in the present embodiment will be described. 11A to 11F are schematic cross-sectional views showing a manufacturing process of the first substrate SU1. 12A to 12C are schematic plan views showing a manufacturing process of the first substrate SU1.

In FIG. 11A, the undercoat layers UC1 and UC2, the insulating layers IL1 to IL3, the light-shielding layer LS, the semiconductor layer SC, and the scanning line G are formed on the first base material B1. In FIG. 11B, the first contact hole CH1 and the second contact hole CH2 penetrating the insulating layers IL1 to IL3 are formed. These first contact hole CH1 and second contact hole CH2 can be formed simultaneously by the same process.

In FIG. 11C, for example, the wiring connection layer SE and the pedestal MB are formed by patterning a titanium film formed entirely on the insulating layer IL3. The wiring connection layer SE contacts the semiconductor layer SC through the first contact hole CH1, and the pedestal MB contacts the semiconductor layer SC through the second contact hole CH2. For example, as shown in FIG. 12A, the wiring connection layer SE and the pedestal MB are misaligned in the second direction Y. The area of the wiring connection layer SE is smaller than the area of the pedestal MB, but the area is not limited to this example.

In FIG. 11D, the insulating layer IL3, the wiring connection layer SE, and the insulating layer IL7 covering the pedestal MB are formed. In FIG. 11E, by opening the insulating layer IL7 above the wiring connection layer SE, the first contact hole CH1 penetrating the insulating layers IL1 to IL3 and IL7 is completed, and the signal line S is formed. As shown in FIG. 12B, the signal line S is formed so as to pass through the wiring connection layer SE.

In FIG. 11F, the insulating layer IL5, the common electrode EL2, and the insulating layer IL6 are sequentially formed above the insulating layer IL7 and the signal line S, and the third contact hole CH3 penetrating the insulating layers IL5 to IL7 is formed. .. After that, by forming the pixel electrode EL1 as shown in FIG. 12C and further forming the alignment film AL1, the first substrate SU1 shown in FIG. 10 is completed.

Both the wiring connection layer SE and the pedestal MB are island-shaped as shown in FIGS. 12A to 12C, and are displaced in the second direction Y. Therefore, the distance D3 between the pedestals MB adjacent to the first direction X (see FIG. 12C) and the distance D4 between the wiring connection layers SE adjacent to the first direction X (also see FIG. 12C) are reduced. However, the wiring connection layer SE and the pedestal MB are not short-circuited.

Further, in the present embodiment, since the first contact hole CH1 and the second contact hole CH2 are formed at the same time, the positional accuracy of both can be improved as compared with the case where both are formed by different processes. This facilitates the design of a high-definition sub-pixel SP.

As an example, the diameter of the first contact hole CH1 and the second contact hole CH2 is 2.0 μm. Further, the width of the wiring connection layer SE in the first direction X is set to 3.0 μm so as to cover the entire first contact hole CH1, and the width of the pedestal MB in the first direction X is set to the entire width of the second contact hole CH2. The thickness should be 3.0 μm so that it can cover the area. Assuming that the distances D3 and D4 are both 3.0 μm, the repetition cycle of the wiring connection layer SE and the repetition cycle of the pedestal MB are both 6.0 μm. In this case, the width of the sub-pixel SP in the first direction X is 6.0 μm. This corresponds to a high definition of 1400 ppi or more.

The width of the wiring connection layer SE and the pedestal MB in the first direction X is not limited to the above example, and can be appropriately determined, for example, in the range of 2.0 μm or more and 3.0 μm or less.

[Third Embodiment]
The third embodiment will be described below. The same configurations as those of the above-described embodiments can be applied to the configurations not particularly mentioned.

FIG. 13 is a schematic cross-sectional view of a display panel PNL included in the display device DSP according to the present embodiment. The display panel PNL shown in FIG. 13 is different from the display panel PNL shown in FIG. 4 in that the signal line S is formed in the groove GR provided in the insulating layer IL3 and is thin.

The first contact hole CH1 is provided from the bottom surface of the groove GR to the upper surface of the semiconductor layer SC. The signal line S is formed of copper or an alloy containing copper, and has a single-layer structure. For example, except for the position of the first contact hole CH1, the upper surface of the signal line S is a plane connected to the upper surface of the insulating layer IL3 around the groove GR. However, the upper surface of the signal line S may be located above the upper surface of the insulating layer IL3 around the groove GR, or may be located below the upper surface of the insulating layer IL3. In FIG. 13, the thickness of the signal line S is slightly larger than the thickness of the pedestal MB, but the thickness of the signal line S may be less than or equal to the thickness of the pedestal MB.

Here, an example of the manufacturing process of the first substrate SU1 in the present embodiment will be described. 14A to 14H are schematic cross-sectional views showing a manufacturing process of the first substrate SU1. In FIG. 14A, the undercoat layers UC1 and UC2, the insulating layers IL1 to IL3, the light-shielding layer LS, the semiconductor layer SC, and the scanning line G are formed on the first base material B1.

In FIG. 14B, a groove GR is formed on the upper surface of the insulating layer IL3. The groove GR has a planar shape similar to that of the signal line S. Such a groove GR can be formed by partially reducing the thickness of the insulating layer IL3 by patterning using, for example, a halftone mask.

In FIG. 14C, the first contact hole CH1 is formed at a position overlapping with the groove GR. In FIG. 14D, a continuous copper film SX is formed on the insulating layer IL3 and inside the first contact hole CH1.

In FIG. 14E, the signal line S is formed by, for example, mechanically scraping off the copper film SX outside the groove GR. As described above, in the present embodiment, the signal line S is formed by the damascene method, but the signal line S may be formed by another method.

In FIG. 14F, the insulating layer IL4 covering the signal line S and the insulating layer IL3 is formed. In FIG. 14G, a second contact hole CH2 penetrating the insulating layers IL1 to IL4 is formed. In FIG. 14H, the pedestal MB is formed so as to cover the second contact hole CH2. The pedestal MB contacts the semiconductor layer SC through the second contact hole CH2. After that, the insulating layer IL5, the common electrode EL2, the insulating layer IL6, the pixel electrode EL1 and the alignment film AL1 are formed in this order, and the first substrate SU1 shown in FIG. 13 is completed.

Copper has a resistance of about 60% as compared with aluminum. Further, since copper is thermally stable, it is not necessary to form titanium films on the upper and lower surfaces. Therefore, in the present embodiment, even if the thickness of the signal line S is reduced to half or less as compared with each of the above-described embodiments, the above-mentioned signal delay can be suitably suppressed.

When the signal line S is formed in the groove GR as shown in FIG. 13, the unevenness of the insulating layer IL4 above the signal line S is suppressed. For example, in the example shown in FIG. 4, the insulating layer IL4 projects above the signal line S. In this case, the pedestal MB will be arranged between the protruding portions caused by the signal lines S adjacent to the first direction X. On the other hand, if the insulating layer IL4 is flat above the signal line S as shown in FIG. 13, the signal line S and the pedestal MB can be arranged closer to each other, and the sub-pixel SP can be made higher in definition. It becomes possible to do.

[Fourth Embodiment]
The fourth embodiment will be described below. The same configurations as those of the above-described embodiments can be applied to the configurations not particularly mentioned.

FIG. 15 is a schematic cross-sectional view of a display panel PNL included in the display device DSP according to the present embodiment. The display device DSP according to the present embodiment has the same basic configuration as the example of FIG. 10, but the signal line S is formed of copper or an alloy containing copper.

As described above, since copper has a low resistance, the signal line S in the present embodiment has a smaller thickness than the example of FIG. In FIG. 15, the thickness of the signal line S is slightly larger than the thickness of the wiring connection layer SE and the pedestal MB, but even if the thickness of the signal line S is less than or equal to the thickness of the wiring connection layer SE and the pedestal MB. good.

The manufacturing process of the first substrate SU1 is the same as that described with reference to FIGS. 11A to 11F. In the present embodiment, the first contact hole CH1 and the second contact hole CH2 are formed at the same time. Therefore, if a groove for the damascene method is to be provided, the first contact hole CH1 will be excessively etched. The same applies even if the formation order of the groove and the first contact hole CH1 is reversed. Therefore, the signal line S can be formed by, for example, wet etching.

Even with the configuration of this embodiment, the thickness of the signal line S can be reduced. Therefore, as in the third embodiment, the signal line S and the pedestal MB can be arranged closer to each other, and the sub-pixel SP can be made high-definition.

[Fifth Embodiment]
The fifth embodiment will be described below. The same configurations as those of the above-described embodiments can be applied to the configurations not particularly mentioned.

FIG. 16 is a schematic cross-sectional view of a display panel PNL included in the display device DSP according to the present embodiment. FIG. 17 is a schematic cross-sectional view of the display panel PNL at a position different from that of FIG. The display panel PNL shown in FIGS. 16 and 17 is different from the display panel PNL shown in FIGS. 4 and 5 in that the insulating layer IL8 (fifth insulating layer) and the electrode connecting layer EC are further provided.

The insulating layer IL8 is provided between the insulating layers IL4 and IL5 and covers the pedestal MB and the insulating layer IL4. The insulating layer IL8 is, for example, a positive organic insulating film, but is not limited to this example. The electrode connection layer EC is provided on the insulating layer IL8 and is electrically connected to the pedestal MB through the fourth contact hole CH4 penetrating the insulating layer IL8. The electrode connection layer EC and the insulating layer IL8 are covered with the insulating layer IL5. The pixel electrode EL1 is electrically connected to the electrode connection layer EC through the third contact hole CH3. The electrode connection layer EC can be formed of a transparent conductive material such as ITO.

Generally, in a contact hole penetrating an insulating layer, the thicker the insulating layer, the larger the dimensional difference between the top and the bottom. Therefore, when the insulating layer is thick, the top area also increases when trying to secure a sufficient bottom area of the contact hole. That is, by thinning the insulating layer, the top area of the contact hole can be reduced, which is advantageous for high definition.

In the structure shown in FIG. 16, the space between the common electrode EL2 and the pedestal MB is divided into two insulating layers IL5 and IL8. Then, the pixel electrode EL1 and the pedestal MB are connected to each other through two contact holes CH3 and CH4 penetrating the two insulating layers IL5 and IL8, respectively. For example, when the thickness of the insulating layer IL5 in each of the above-described embodiments is about the same as the total thickness of the insulating layers IL5 and IL6 in the present embodiment, the thickness of the insulating layer IL5 in the structure of the present embodiment is The third contact hole CH3 can be made smaller by the amount of reduction.

Since the third contact hole CH3 is close to the liquid crystal layer LC, the alignment film AL1 becomes uneven depending on its shape, and the film thickness of the alignment film AL1 becomes unstable. In the present embodiment, since the third contact hole CH3 can be made small, the unevenness generated in the alignment film AL1 can be suppressed, and the film thickness of the alignment film AL1 is also stable. As a result, the orientation of the liquid crystal molecules in the vicinity of the third contact hole CH3 is stabilized, and the size of the sub-pixel SP can be reduced.

As an example, the thickness of the insulating layer IL8 is preferably 2 μm or less, and more preferably 1 μm or less. If the width of the electrode connection layer EC is, for example, 2/3 or more of the width of the sub-pixel SP (the distance between the signal lines S in the first direction X), the pixel electrodes EL1 while insulating the adjacent electrode connection layer ECs from each other. Sufficient area is obtained for electrical connection with.

[Sixth Embodiment]
The sixth embodiment will be described below. The same configurations as those of the above-described embodiments can be applied to the configurations not particularly mentioned.

FIG. 18 is a schematic cross-sectional view of a display panel PNL included in the display device DSP according to the present embodiment. The display panel PNL shown in FIG. 18 is different from the display panel PNL shown in FIG. 16 in that the second substrate SU2 does not have the color filter layer CF and the first substrate SU1 has the color filter layer CF instead of the insulating layer IL8. It's different.

For example, the fourth contact hole CH4 can be formed by forming the color filters of each color included in the color filter layer CF without gaps and then performing dry etching on the color filter layer CF. As another example, when forming a color filter for each color included in the color filter layer CF, a gap region in which none of the color filters is provided may be provided in at least a part above the pedestal MB. In this case, the electrode connection layer EC is electrically connected to the pedestal MB through the gap region. The gap region may have a shape extending in the first direction X or the second direction Y over a plurality of sub-pixels SP, for example. In this case, the color filter layer CF will have a plurality of gap regions arranged in a striped pattern. In the case of realizing such a color filter layer CF, the difference between the mask dimension and the completed dimension when processing the color filter of each color may be, for example, 0.5 μm or less, and more preferably 0.2 μm or less.

In the liquid crystal display device, the light emitted from the lighting device and passing through the sub-pixel may not pass through the color filter corresponding to the sub-pixel. Hereinafter, such light is referred to as non-matched light. Since the non-matching light displays a color different from the color originally intended to be displayed, color mixing of adjacent sub-pixels may occur. This color mixing is likely to occur in a region observed from a direction inclined with respect to the substrate normal direction.

For example, in a VR viewer, a convex lens is arranged between a display panel and a user's eye in order to widen the viewing angle, and the larger the required viewing angle, the larger the curvature of the convex lens. In this case, the closer the region is to the edge of the field of view, the more the light that has passed through the display panel is observed, so that color mixing may occur remarkably. In addition, the higher the definition of the sub-pixels, the more likely it is that color mixing will occur.

The display panel PNL in the present embodiment is a so-called COA (Color Filter on Array) system in which the color filter layer CF is provided on the first substrate SU1 (array substrate). In the COA method, the positions of the color filter layer CF and the sub-pixel SP do not shift even if the color filter layer CF and the pixel electrode EL1 are close to each other and there is an error in the bonding of the first substrate SU1 and the second substrate SU2. There are advantages such as the fact that non-matching light is less likely to occur due to these. Therefore, color mixing can be suppressed. Further, even when the sub-pixel SP is made high-definition, color mixing is unlikely to occur, so that extremely good display quality can be realized.

As described above, all display devices that can be appropriately designed and implemented by those skilled in the art based on the display devices described as the embodiments of the present invention also belong to the scope of the present invention as long as the gist of the present invention is included.
In the scope of the idea of the present invention, those skilled in the art can come up with various modifications, and it is understood that these modifications also belong to the scope of the present invention. For example, a person skilled in the art appropriately adds, deletes, or changes the design of each of the above-described embodiments, or adds, omits, or changes the conditions of the process of the present invention. As long as it has a gist, it is included in the scope of the present invention.
In addition, with respect to other actions and effects brought about by the embodiments described in each embodiment, those apparent from the description of the present specification or those which can be appropriately conceived by those skilled in the art are naturally understood to be brought about by the present invention. Will be done.

DSP ... Display device, PNL ... Display panel, SU1 ... First substrate, SU2 ... Second substrate, LC ... Liquid crystal layer, EL1 ... Pixel electrode, EL2 ... Common electrode, S ... Signal line, G ... Scanning line, SC ... Semiconductor Layer, MB ... pedestal, IL1 to IL8 ... insulating layer, CH1 ... first contact hole, CH2 ... second contact hole, CH3 ... third contact hole, CH4 ... fourth contact hole, CF ... color filter layer, GR ... groove , SE ... Wiring connection layer, EC ... Electrode connection layer.

Claims (5)

With the semiconductor layer,
The scanning line facing the semiconductor layer and
The signal line connected to the semiconductor layer and
The pedestal electrode in contact with the semiconductor layer and
A pixel electrode connected to the pedestal electrode and
The thickness of the pedestal electrode is smaller than the thickness of the signal line.
Display device. The signal line has a laminated structure in which a plurality of metal materials are laminated.
The pedestal electrode has a single-layer structure of one metal material.
The display device according to claim 1. With the base material
A first insulating layer having a first surface and a second surface opposite to the first surface.
A second insulating layer made of organic material and
With an alignment film,
The semiconductor layer, the scanning line, the signal line, and the pedestal electrode are provided between the base material and the second insulating layer.
The pixel electrode is provided between the second insulating layer and the alignment film, and is provided.
The first insulating layer is provided between the base material and the second insulating layer.
The signal line comes into contact with the first surface of the first insulating layer.
The pedestal electrode contacts the second surface of the first insulating layer.
The display device according to claim 1 or 2. A third insulating layer provided between the first insulating layer and the second insulating layer is provided.
The third insulating layer is an organic insulating film.
The third insulating layer comes into contact with the second surface of the first insulating layer and the pedestal electrode.
The display device according to claim 3. A color filter layer provided between the first insulating layer and the second insulating layer is provided.
The color filter layer comes into contact with the second surface of the first insulating layer and the pedestal electrode.
The display device according to claim 3.

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