JP2022049880A - Magnetic memory and method for manufacturing the same - Google Patents

Abstract

To reduce the difficulty of machining magnetoresistance effect element.SOLUTION: According to an embodiment, a magnetic memory includes a first wiring 22 extending in the first direction (X direction), a selector 24 provided above the first wiring, a conductor 25 provided above the selector, a magnetoresistance effect element 26 provided above the conductor, and an insulating layer 23 provided on the same layer as the selector. The area of the first major surface of the selector facing the conductor is smaller than the area of the second major surface of the conductor facing the selector.SELECTED DRAWING: Figure 3

Description

Embodiments of the present invention relate to a magnetic storage device and a method for manufacturing the same.

A magnetic storage device (MRAM: Magnetoresistive Random Access Memory) using a magnetoresistive element as a storage element is known.

U.S. Patent Application Publication No. 2020/0083385

Reduces the difficulty of processing magnetoresistive elements.

The magnetic storage device of the embodiment is provided on the first wiring extending in the first direction, the switching element provided on the first wiring, the conductor provided on the switching element, and the conductor. It includes a provided magnetoresistive effect element and an insulating layer provided in the same layer as the switching element. The area of the first main surface facing the conductor of the switching element is smaller than the area of the second main surface facing the switching element of the conductor.

FIG. 1 is a block diagram of a magnetic storage device according to the first embodiment. FIG. 2 is a circuit diagram of a memory cell array included in the magnetic storage device according to the first embodiment. FIG. 3 is a cross-sectional view of a memory cell array included in the magnetic storage device according to the first embodiment. FIG. 4 is a plan view of an intermediate electrode in a memory cell array included in the magnetic storage device according to the first embodiment. FIG. 5 is a cross-sectional view of a magnetoresistive element included in the magnetic storage device according to the first embodiment. FIG. 6 is a flowchart showing a manufacturing process of a memory cell array included in the magnetic storage device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing process of a memory cell array included in the magnetic storage device according to the first embodiment. FIG. 8 is a cross-sectional view showing a manufacturing process of a memory cell array included in the magnetic storage device according to the first embodiment. FIG. 9 is a cross-sectional view showing a manufacturing process of a memory cell array included in the magnetic storage device according to the first embodiment. FIG. 10 is a cross-sectional view showing a manufacturing process of a memory cell array included in the magnetic storage device according to the first embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of a memory cell array included in the magnetic storage device according to the first embodiment. FIG. 12 is a cross-sectional view showing a manufacturing process of a memory cell array included in the magnetic storage device according to the first embodiment. FIG. 13 is a cross-sectional view showing a manufacturing process of a memory cell array included in the magnetic storage device according to the first embodiment. FIG. 14 is a cross-sectional view showing a manufacturing process of a memory cell array included in the magnetic storage device according to the first embodiment. FIG. 15 is a cross-sectional view of a memory cell array included in the magnetic storage device according to the second embodiment. FIG. 16 is a flowchart showing a manufacturing process of a memory cell array included in the magnetic storage device according to the second embodiment. FIG. 17 is a cross-sectional view showing a manufacturing process of a memory cell array included in the magnetic storage device according to the first embodiment. FIG. 18 is a cross-sectional view showing a manufacturing process of a memory cell array included in the magnetic storage device according to the first embodiment. FIG. 19 is a cross-sectional view showing a manufacturing process of a memory cell array included in the magnetic storage device according to the first embodiment.

Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are designated by a common reference numeral. Further, when distinguishing a plurality of components having a common reference code, a subscript is added to the common reference code to distinguish them. When it is not necessary to distinguish a plurality of components, only a common reference code is attached to the plurality of components, and no subscript is added. Here, the subscript is not limited to the subscript and the superscript, and includes, for example, a lowercase alphabet added to the end of the reference code, an index meaning an array, and the like.

1. 1. First Embodiment The magnetic storage device according to the first embodiment will be described. The magnetic storage device according to the first embodiment uses, for example, an element having a magnetoresistive effect (also referred to as an MTJ element) by a magnetic tunnel junction (MTJ) as a resistance changing element, and is vertical. It is a magnetic storage device using a magnetization method.

In this embodiment and the second embodiment described later, the case where the MTJ element is applied as a resistance changing element will be described, and the description will be given as a magnetoresistive effect element MTJ in the notation.

1.1 Configuration First, the configuration of the magnetic storage device according to the first embodiment will be described.

1.1.1 Configuration of Magnetic Storage Device FIG. 1 is a block diagram showing an example of the configuration of the magnetic storage device according to the first embodiment. As shown in FIG. 1, the magnetic storage device 1 includes a memory cell array 10, a row selection circuit 11, a column selection circuit 12, a decoding circuit 13, a write circuit 14, a read circuit 15, a voltage generation circuit 16, an input / output circuit 17, and an input / output circuit 17. The control circuit 18 is included.

The memory cell array 10 includes a plurality of memory cell MCs, each of which is associated with a set of rows and columns. Specifically, the memory cells MC in the same row are connected to the same word line WL, and the memory cells MC in the same column are connected to the same bit line BL.

The row selection circuit 11 is connected to the memory cell array 10 via the word line WL. The row selection circuit 11 receives the decoding result (low address) of the address ADD from the decoding circuit 13. The row selection circuit 11 sets the word line WL corresponding to the row address to the selected state. In the following, the word line WL set in the selected state is referred to as the selected word line WL. Further, the word line WL other than the selected word line WL is expressed as a non-selected word line WL.

The column selection circuit 12 is connected to the memory cell array 10 via the bit line BL. The column selection circuit 12 receives the decoding result (column address) of the address ADD from the decoding circuit 13. The column selection circuit 12 sets the bit line BL corresponding to the column address in the selected state. In the following, the bit line BL set in the selected state is referred to as the selected bit line BL. Further, the bit line BL other than the selected bit line BL is referred to as a non-selected bit line BL.

The decoding circuit 13 decodes the address ADD received from the input / output circuit 17. The decoding circuit 13 supplies the decoding result of the address ADD to the row selection circuit 11 and the column selection circuit 12. The address ADD includes a column address and a row address.

The writing circuit 14 writes data to the memory cell MC. The write circuit 14 includes, for example, a write driver (not shown).

The read circuit 15 reads data from the memory cell MC. The readout circuit 15 includes, for example, a sense amplifier (not shown).

The voltage generation circuit 16 uses a power supply voltage provided from the outside (not shown) of the magnetic storage device 1 to generate voltages for various operations of the memory cell array 10. For example, the voltage generation circuit 16 generates various voltages required for the writing operation and outputs them to the writing circuit 14. Further, for example, the voltage generation circuit 16 generates various voltages required for the read operation and outputs them to the read circuit 15.

The input / output circuit 17 transfers the address ADD received from the outside of the magnetic storage device 1 to the decoding circuit 13. The input / output circuit 17 transfers the command CMD received from the outside of the magnetic storage device 1 to the control circuit 18. The input / output circuit 17 transmits and receives various control signal CNTs between the outside of the magnetic storage device 1 and the control circuit 18. The input / output circuit 17 transfers the data DAT received from the outside of the magnetic storage device 1 to the writing circuit 14, and outputs the data DAT transferred from the reading circuit 15 to the outside of the magnetic storage device 1.

The control circuit 18 includes a row selection circuit 11 in the magnetic storage device 1, a column selection circuit 12, a decoding circuit 13, a write circuit 14, a read circuit 15, a voltage generation circuit 16, and an input based on the control signal CNT and the command CMD. It controls the operation of the output circuit 17.

1.1.2 Circuit configuration of memory cell array Next, an example of the configuration of the memory cell array 10 will be described with reference to FIG. FIG. 2 is a circuit diagram showing the configuration of the memory cell array 10. In the example of FIG. 2, the word line WL is shown classified by a subscript including an index (“<>”).

As shown in FIG. 2, the memory cell MC is arranged in a matrix in the memory cell array 10, and is one of a plurality of bit lines BL (BL <0>, BL <1>, ..., BL <N>). It is associated with a set of a book and one of a plurality of word lines WL (WL <0>, WL <1>, ..., WL <M>) (M and N are arbitrary integers). That is, the memory cells MC <i, j> (0 ≦ i ≦ M, 0 ≦ j ≦ N) are connected between the word line WL <i> and the bit line BL <j>.

The memory cell MC <i, j> includes a selector SEL <i, j> connected in series and a magnetoresistive effect element MTJ <i, j>. More specifically, one end of the selector SEL <i, j> is connected to one word line WL <i>, and the other end is connected to one end of the magnetoresistive effect element MTJ <i, j>. .. The other end of the magnetoresistive sensor MTJ <i, j> is connected to one bit line BL <j>.

The selector SEL (also referred to as a switching element) has a function as a switch for controlling the supply of current to the magnetoresistive element MTJ during the write operation and the read operation to the corresponding magnetoresistive element MTJ. More specifically, for example, when the voltage applied to the memory cell MC is less than the preset threshold voltage, the selector SEL in the memory cell MC cuts off the current as an insulator having a large resistance value (off). When the voltage is above the threshold voltage, a current flows as a conductor with a small resistance value (turns on). That is, the selector SEL has a function of switching whether to flow or cut off the current according to the magnitude of the voltage applied to the memory cell MC regardless of the direction of the flowing current.

The selector SEL may be, for example, a two-terminal type switching element. When the voltage applied between the two terminals is less than the threshold voltage, the switching element is in a "high resistance" state, for example, an electrically non-conducting state. When the voltage applied between the two terminals is equal to or higher than the threshold voltage, the switching element is in a "low resistance" state, for example, an electrically conductive state. The switching element may have this function regardless of the polarity of the voltage.

The magnetoresistive element MTJ can switch the resistance value between the low resistance state and the high resistance state by the current whose supply is controlled by the selector SEL. The magnetoresistive effect element MTJ can write data by changing its resistance state, holds the written data non-volatilely, and functions as a readable storage element.

1.1.3 Structure of memory cell array Next, an example of the structure of the memory cell array 10 will be described with reference to FIGS. 3 and 4. In the following description, the plane parallel to the surface of the semiconductor substrate 20 is the XY plane, and the direction perpendicular to the XY plane is the Z direction. Further, in the XY plane, the direction along the word line WL is the X direction, and the direction along the bit line BL is the Y direction. Further, in each component, the surface facing the semiconductor substrate in the Z direction is the lower surface, and the facing surface is the upper surface. FIG. 3 is a cross-sectional view of the memory cell array 10 along the Y direction. FIG. 4 shows a plan view of the intermediate electrode ME (conductor 25) in the XY plane.

As shown in FIG. 3, an insulating layer 21 is provided on the semiconductor substrate 20. Then, in the upper region in the insulating layer 21, a plurality of wiring layers 22 extending in the X direction and functioning as the word line WL are provided. The wiring layer 22 is made of a conductive material. The wiring layer 22 may be provided on the upper surface of the semiconductor substrate 20.

An insulating layer 23 is provided on the upper surface of the insulating layer 21. More specifically, the insulating layer 23 is provided between the plurality of elements 24, that is, in the same layer as the elements 24. For the insulating layer 23, for example, SiO ₂ is used.

A plurality of elements 24 that function as selector SELs are provided on each wiring layer 22. One element 24 corresponds to the selector SEL of one memory cell MC. For example, the plurality of elements 24 are arranged in a matrix along the X direction and the Y direction in the XY plane. Then, a plurality of elements 24 arranged in the X direction are provided on the upper surface of one wiring layer 22. An electrode for electrically connecting the wiring layer 22 and the element 24 may be provided between the wiring layer 22 and the element 24. The element 24 is made of a material made of an insulator and contains a dopant introduced by ion implantation. The insulator comprises, for example, an oxide and, for example, a material substantially composed of SiO ₂ or SiO ₂ . Dopants include, for example, arsenic (As) or germanium (Ge).

The element 24 may have, for example, a substantially cylindrical shape. The substantially cylindrical shape includes a case where the upper surface and the lower surface are a perfect circle or a shape substantially equal to a perfect circle. The shape of the element 24 is not limited to the cylindrical shape. The shape of the element 24 depends, for example, on the profile of the dopant. Therefore, for example, the element 24 may be a truncated cone. Further, the upper surface of the element 24 may have a rectangular shape. Hereinafter, in order to simplify the description, a case where the element 24 has a cylindrical shape will be described.

The element 24 of the present embodiment is formed by injecting a dopant into the insulating layer 23. That is, the element 24 is formed without using processing such as dry etching. Therefore, the interface between the insulating layer 23 and the element 24 cannot be observed with, for example, a TEM (Transmission Electron Microscope). However, the element 24 can be confirmed by measuring the distribution of the dopant using, for example, EDX (Energy Dispersive X-ray spectroscopy) analysis of TEM.

On the upper surface of the element 24, a conductor 25 that functions as an intermediate electrode ME (Middle Electrode) between the selector SEL (element 24) and the magnetoresistive element MTJ (element 26) is provided. The conductor 25 is made of a conductive material and contains, for example, titanium nitride (TiN).

An element 26 that functions as a magnetoresistive effect element MTJ is provided on the upper surface of the conductor 25. The element 26 may have, for example, a substantially cylindrical shape. The shape of the element 26 is not limited to the cylindrical shape. For example, the side surface of the element 26 may be tapered depending on the etching characteristics when the element 26 is processed. In such a case, the element 26 may be a truncated cone. Further, the upper surface of the element 26 may have a rectangular shape. Hereinafter, in order to simplify the description, a case where the element 26 has a cylindrical shape will be described. Details of the configuration of the element 26 will be described later.

A hard mask 27 is provided on the upper surface of the element 26. The hard mask 27 functions as a hard mask when processing the element 26. The hard mask 27 is made of a conductive material and contains, for example, TiN.

An insulator 28 is provided on the side surface of the element 26 and the hard mask 27. The insulator 28 functions as a protective film for protecting the element 26 when processing the conductor 25, that is, as a sidewall SW. The insulator 28 provided on the side surface of the cylindrical element 26 and the hard mask 27 has a cylindrical shape. The insulator 28 is made of an insulating material, and for example, silicon nitride (SiN) is used.

The conductor 25 is processed by using the hard mask 27 and the insulator 28 as a hard mask. Therefore, the shape of the outer circumference of the upper surface of the conductor 25 and the shape of the outer circumference of the insulator 28 are substantially the same. Approximately the same may include errors in the manufacturing process, such as differences in etching rate due to differences in materials. Therefore, in the present embodiment, the upper surface of the conductor 25 has a circular shape. Hereinafter, in order to simplify the description, a case where the conductor 25 has a cylindrical shape will be described. The shape of the conductor 25 is not limited to the cylindrical shape. The shape of the conductor 25 may be, for example, a truncated cone.

An insulating layer 29 is provided on the upper surface of the insulating layer 23. For the insulating layer 29, for example, SiO ₂ is used.

The upper surface of each hard mask 27 is connected to the lower surface of any of the plurality of wiring layers 30 extending in the Y direction. More specifically, a plurality of hard masks 27 (that is, elements 26) arranged along the Y direction are connected to one wiring layer 30. The wiring layer 30 functions as a bit line BL. The wiring layer 30 is made of a conductive material and contains, for example, tungsten (W). An electrode for electrically connecting the hard mask 27 and the wiring layer 30 may be provided between the hard mask 27 and the wiring layer 30.

As shown in FIG. 4, in the present embodiment, for example, when the upper surface of the element 24 is substantially circular, the longest diameter (hereinafter referred to as “major diameter”) is d1. When the lower surface of the conductor 25 facing the element 24 is substantially circular, its major axis is d2. Then, d1 and d2 have a relationship of d1 <d2. In other words, in the present embodiment, the area of the upper surface of the element 24 (the surface facing the conductor 25) is smaller than the area of the lower surface of the conductor 25 (the surface facing the element 24). Therefore, the distance between the upper surfaces of the adjacent elements 24 is d3, and the distance between the lower surfaces of the adjacent conductors 25 is d4. Then, d3 and d4 have a relationship of d3> d4. The shape of the upper surface of the element 24 and the shape of the lower surface of the conductor 25 in contact with the element 24 may not be the same. For example, either the upper surface of the element 24 or the lower surface of the conductor 25 may be circular and the other may be rectangular.

Further, in the present embodiment, the case where the magnetoresistive effect element MTJ and the bit line BL are arranged above the word line WL has been described, but the present invention is not limited to this. For example, the magnetoresistive effect element MTJ and the word line WL may be arranged above the bit line BL. In this case, the wiring layer 22 functions as the bit line BL, and the wiring layer 30 functions as the word line WL.

1.1.4 Configuration of Magneto Resistive Sensor Next, an example of the configuration of the magnetoresistive sensor MTJ will be described with reference to FIG. FIG. 5 is a cross-sectional view showing the configuration of the element 26, that is, the magnetoresistive effect element MTJ.

As shown in FIG. 5, the magnetoresistive effect element MTJ includes, for example, a non-magnetic material 31 that functions as an under layer UL (Under layer), a ferromagnetic material 32 that functions as a shift canceling layer (SCL), and a spacer layer. A non-magnetic material 33 that functions as an SP (Spacer layer), a ferromagnetic material 34 that functions as a reference layer RL (Reference layer), a non-magnetic material 35 that functions as a tunnel barrier layer TB (Tunnel barrier layer), and a storage layer SL (Storage). It includes a ferromagnetic material 36 that functions as a layer), a non-magnetic material 37 that functions as a cap layer CAP (Capping layer), and a non-magnetic material 38 that functions as a top layer TOP (Top layer).

The magnetoresistive effect element MTJ is, for example, a non-magnetic material 31, a ferromagnetic material 32, a non-magnetic material 33, and a ferromagnetic material from the word line WL (wiring layer 22) side toward the bit line BL (wiring layer 30) side. A plurality of films are laminated in the order of 34, non-magnetic material 35, ferromagnetic material 36, non-magnetic material 37, and non-magnetic material 38. From the word wire WL (wiring layer 22) side to the bit wire BL (wiring layer 30) side, the non-magnetic material 38, the non-magnetic material 37, the ferromagnetic material 36, the non-magnetic material 35, the ferromagnetic material 34, A plurality of films may be laminated in the order of the non-magnetic material 33, the ferromagnetic material 32, and the non-magnetic material 31.

The magnetoresistive sensor MTJ is, for example, a magnetoresistive sensor of a vertical magnetization type in which the magnetization direction of the magnetic material constituting the magnetoresistive sensor MTJ is perpendicular to the film surface (Z direction in the example of FIG. 5). Function. The magnetoresistive sensor MTJ may include a further layer (not shown) between the above-mentioned layers 31 to 38.

The non-magnetic material 31 is a non-magnetic conductor and has a function as an electrode for improving electrical connectivity with the selector SEL (element 24). Further, the non-magnetic material 31 contains, for example, a refractory metal. The refractory metal means, for example, a material having a higher melting point than iron (Fe) and cobalt (Co), and for example, zirconium (Zr), hafnium (Hf), tungsten (W), chromium (Cr), molybdenum (Mo). ), Niob (Nb), Tungsten (Ti), Tantal (Ta), Vanadium (V), Ruthenium (Ru), and Platinum (Pt).

The ferromagnet 32 has ferromagnetism and has an axial direction for easy magnetization in a direction perpendicular to the film surface. The magnetization direction of the ferromagnet 32 is fixed, and in the example of FIG. 5, it faces the direction of the ferromagnet 34. Note that "the magnetization direction is fixed" means that the magnetization direction does not change due to a current (spin torque) having a magnitude that can reverse the magnetization direction of the ferromagnetic material 36 (storage layer SL). The ferromagnet 32 comprises at least one alloy selected from, for example, cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd). The ferromagnet 32 may be a laminated body composed of a plurality of layers. In that case, the ferromagnetic material 32 is, for example, a multilayer film of cobalt (Co) and platinum (Pt) (Co / Pt multilayer film) or a multilayer film of cobalt (Co) and nickel (Ni) (Co / Ni multilayer film). Membranes) and at least one multilayer film selected from a multilayer film of cobalt (Co) and palladium (Pd) (Co / Pd multilayer film).

The non-magnetic material 33 is provided between the ferromagnetic material 32 (shift canceling layer SCL) and the ferromagnetic material 34 (reference layer RL). The non-magnetic material 33 is a non-magnetic conductor and contains at least one element selected from, for example, ruthenium (Ru), osmium (Os), iridium (Ir), vanadium (V), and chromium (Cr). ..

The ferromagnet 34 has ferromagnetism and has an easy axial direction of magnetization in a direction perpendicular to the film surface. The magnetization direction of the ferromagnet 34 is fixed, and in the example of FIG. 5, it faces the direction of the ferromagnet 32. The ferromagnet 34 contains, for example, at least one of iron (Fe), cobalt (Co), and nickel (Ni). Further, the ferromagnet 34 may further contain boron (B). More specifically, for example, the ferromagnet 34 may contain iron cobalt boron (FeCoB) or iron tetraboride (FeB) and may have a body-centered cubic crystal structure.

Although not shown in FIG. 5, the ferromagnetic material 34 may be a laminated body composed of a plurality of layers. Specifically, for example, the laminate constituting the ferromagnet 34 has the above-mentioned layer containing iron cobalt boron (FeCoB) or iron borate (FeB) as an interface layer with the non-magnetic material 35, and is said to be the same. The structure may be such that a further ferromagnet is laminated between the interface layer and the non-magnetic material 33 via a non-magnetic conductor. The non-magnetic conductors in the laminate constituting the ferromagnetic material 34 include, for example, tantalum (Ta), hafnium (Hf), tungsten (W), zirconium (Zr), molybdenum (Mo), niobium (Nb), and It may contain at least one metal selected from titanium (Ti). Further ferromagnetic materials in the laminate constituting the ferromagnetic material 34 include, for example, a multilayer film of cobalt (Co) and platinum (Pt) (Co / Pt multilayer film), cobalt (Co) and nickel (Ni). It may include at least one multilayer film selected from the multilayer film (Co / Ni multilayer film) and the multilayer film of cobalt (Co) and palladium (Pd) (Co / Pd multilayer film).

The ferromagnets 32 and 34 are antiferromagnetically coupled by the non-magnetic material 33. That is, the ferromagnets 32 and 34 are coupled so as to have magnetization directions antiparallel to each other. Therefore, in the example of FIG. 5, the magnetization directions of the ferromagnets 32 and 34 face each other. Such a coupled structure of the ferromagnetic material 32, the non-magnetic material 33, and the ferromagnetic material 34 is called a SAF (Synthetic Anti-Ferromagnetic) structure. Thereby, the ferromagnet 32 can cancel the influence of the leakage magnetic field of the ferromagnet 34 on the magnetization direction of the ferromagnet 36. Therefore, asymmetry occurs in the easiness of reversing the magnetization of the ferromagnet 36 due to the leakage magnetic field of the ferromagnet 34 (that is, the easiness of reversing when the direction of magnetization of the ferromagnet 36 is reversed. However, it is different between the case of reversing from one side to the other and the case of reversing in the opposite direction).

The non-magnetic material 35 is a non-magnetic insulator and contains, for example, magnesium oxide (MgO). The non-magnetic material 35 has a NaCl crystal structure in which the film surface is oriented toward the (001) plane, for example, and in order to grow a crystalline film from the interface with the ferromagnetic material 36 in the crystallization treatment of the ferromagnetic material 36. It functions as a seed material that is the core of. The non-magnetic material 35 is provided between the ferromagnet 34 and the ferromagnet 36, and forms a magnetic tunnel junction together with these two ferromagnets.

The ferromagnet 36 has ferromagnetism and has an easy axial direction of magnetization in a direction perpendicular to the film surface. In other words, the ferromagnet 36 has a magnetization direction toward either the bit line BL side or the word line WL side along the Z direction. The ferromagnet 36 contains at least one of iron (Fe), cobalt (Co), and nickel (Ni). Ferromagnet 36 further comprises boron (B). More specifically, for example, the ferromagnet 36 may contain iron cobalt boron (FeCoB) or iron tetraboride (FeB) and may have a body-centered cubic crystal structure.

The non-magnetic material 37 has a function of suppressing an increase in the damping constant of the ferromagnetic material 36 and reducing the writing current. The non-magnetic material 37 includes, for example, magnesium oxide (MgO), magnesium nitride (MgN), zirconite nitride (ZrN), niobium nitride (NbN), silicon nitride (SiN), aluminum nitride (AlN), and hafnium nitride (HfN). Includes at least one nitride or oxide selected from tantalum nitride (TaN), tungsten nitride (WN), chromium nitride (CrN), molybdenum nitride (MoN), titanium nitride (TiN), vanadium nitride (VN). Further, the non-magnetic material 37 may be a mixture of these nitrides or oxides. That is, the non-magnetic material 37 is not limited to the binary compound composed of two kinds of elements, but may contain a ternary compound composed of three kinds of elements, for example, titanium nitride aluminum (AlTiN) and the like.

The non-magnetic material 38 is a non-magnetic conductor and has a function as a top electrode for improving the electrical connectivity between the upper end of the magnetoresistive sensor MTJ and the bit wire BL. The non-magnetic material 38 contains, for example, at least one element or compound selected from tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride (TiN).

In the present embodiment, a write current is passed through the magnetoresistive element MTJ, and the spin torque is injected into the storage layer SL by this write current. Then, a spin injection writing method is adopted in which the magnetization direction of the storage layer SL is controlled by the injected spin torque. The magnetoresistive element MTJ can take either a low resistance state or a high resistance state depending on whether the relative relationship between the magnetization directions of the storage layer SL and the reference layer RL is parallel or antiparallel.

When a write current Ic0 of a certain magnitude is passed through the magnetoresistive sensor MTJ in the direction of arrow A1 in FIG. 5, that is, in the direction from the storage layer SL toward the reference layer RL, the magnetization directions of the storage layer SL and the reference layer RL are changed. The relative relationship becomes parallel. In this parallel state, the resistance value of the magnetoresistive element MTJ is the lowest, and the magnetoresistive element MTJ is set to the low resistance state. This low resistance state is called a "P (Parallel) state" and is defined as, for example, a state of data "0".

Further, when the write current Ic1 larger than the write current Ic0 is passed through the magnetic resistance effect element MTJ in the direction of the arrow A2 in FIG. 5, that is, in the direction from the reference layer RL toward the storage layer SL (direction opposite to the arrow A1), the magnetic resistance effect element MTJ is stored. The relative relationship between the magnetization directions of the layer SL and the reference layer RL is antiparallel. In this antiparallel state, the resistance value of the magnetoresistive element MTJ is the highest, and the magnetoresistive element MTJ is set to the high resistance state. This high resistance state is called "AP (Anti-Parallel) state" and is defined as, for example, the state of data "1".

In the following description, the method of defining the data "1" and the data "0" will be described according to the above-mentioned method of defining the data, but the method of defining the data "1" and the data "0" is not limited to the above-mentioned example. For example, the P state may be defined as data “1” and the AP state may be defined as data “0”.

1.2 Method for manufacturing a memory cell array Next, an example of a method for manufacturing the memory cell array 10 will be described with reference to FIGS. 6 to 15. FIG. 6 is a flowchart showing a method of manufacturing the memory cell array 10. 7 to 15 are cross-sectional views of a memory cell array 10 for explaining a method of manufacturing the memory cell array 10. In the following description, the details of the laminated structure constituting the element 26 (magnetoresistive sensor MTJ) will be omitted.

As shown in FIG. 7, the insulating layer 21 is formed on the upper surface of the semiconductor substrate 20. Next, a wiring layer 22 that functions as a word line WL is formed in the insulating layer 21 (step S1 in FIG. 6, WL formation). The wiring layer 22 may be a groove wiring formed by forming a groove pattern on the upper portion of the insulating layer 21 and then embedding the inside of the groove pattern with a conductive material. Alternatively, the wiring layer 22 may be formed by depositing a conductive material on the insulating layer 21 and then processing the conductive material. In this case, after the wiring layer 22 is formed, the insulating layer 21 is formed so as to fill the space between the wiring layers 22.

The insulating layer 23 is deposited on the upper surfaces of the insulating layer 21 and the wiring layer 22 by, for example, CVD (Chemical Vapor deposition) (step S2 in FIG. 6, deposition of the insulator 23).

As shown in FIG. 8, a resist mask 40 for ion implantation (I / I: Ion Implantation) is formed on the upper surface of the insulating layer 23 by using a photolithography technique (for steps S3 and I / I in FIG. 6). Mask formation). The resist mask 40 has a region corresponding to the selector SEL (element 24) open. In this state, for example, ion implantation using As as a dopant is performed. After ion implantation, the resist mask 40 is removed, for example, by _O2 ashing. Next, a heat treatment for activating As is performed. As a result, the element 24 is formed in the As-doped region of the insulating layer 23 (step S4 in FIG. 6, As injection (SEL formation)).

As shown in FIG. 9, the laminated film corresponding to the conductor 25 and the element 26 (that is, the non-magnetic material 31, the ferromagnetic material 32, the non-magnetic material 33, the ferromagnetic material 34, the non-magnetic material 35, the ferromagnetic material 36). , Non-magnetic material 37, and non-magnetic material 38) are sequentially deposited by CVD, sputtering technique, or the like (step S5 in FIG. 6, ME / MTJ deposition).

As shown in FIG. 10, the hard mask 27 is formed on the laminated film corresponding to the element 26 (step S6 in FIG. 6; HM formation).

As shown in FIG. 11, the laminated film corresponding to the element 26 is processed by, for example, IBE (Ion Beam Etching) using the hard mask 27 as a mask to form the element 26. That is, the magnetoresistive effect element MTJ is formed (step S7 in FIG. 6, MJT processing).

As shown in FIG. 12, the insulator 28 is deposited by, for example, CVD so as to cover the upper surface of the conductor 25, the side surface of the element 26, and the upper surface and the side surface of the hard mask 27 (step S8 in FIG. 6, insulator). 28 deposits).

As shown in FIG. 13, for example, the insulator 28 on the upper surface of the conductor 25 and the upper surface of the hard mask 27 is removed by etching back by RIE (Reactive ion etching) (step S9 in FIG. 6, SW etching back). As a result, the sidewall SW of the element 26 and the hard mask 27 made of the insulator 28 is formed.

As shown in FIG. 14, the conductor 25 is processed by, for example, RIE, using the hard mask 27 and the insulator 28 as masks (step S10 in FIG. 6, ME processing). As a result, the intermediate electrode ME is formed.

As shown in FIG. 3, the insulating layer 29 is formed so as to be embedded between the conductor 25 and the insulator 28 (step S11 in FIG. 6, forming the insulating layer 29). After that, the wiring layer 30 is formed on the upper surface of the hard mask 27 (step S12 in FIG. 6, BL formation).

1.3 Effect of the present embodiment With the configuration of the present embodiment, the difficulty of processing the magnetoresistive sensor MTJ can be reduced. Hereinafter, this effect will be described in detail.

In the structure in which the intermediate electrode ME and the magnetoresistive element MTJ are provided on the upper surface of the selector SEL, the magnetoresistive element MTJ and the magnetoresistive element ME are masked by the hard mask 27 formed on the upper surface of the magnetoresistive element MTJ. , And the selector SEL may be processed. Therefore, the hard mask 27 is formed with a relatively thick film thickness that does not disappear during the processing of these materials. As the film thickness of the hard mask 27 becomes thicker, the aspect ratio when processing the magnetoresistive sensor MTJ increases. Therefore, there is a high demand for the shape of the magnetoresistive sensor MTJ (remaining film of the hard mask 27, the angle of the side surface of the magnetoresistive sensor MTJ, etc.) required for processing the intermediate electrode ME and the selector SEL. That is, the difficulty of processing the magnetoresistive sensor MTJ increases.

For example, when the side surfaces of the magnetoresistive sensor MTJ, the intermediate electrode ME, and the selector SEL are tapered, the distance between the adjacent selector SELs is shorter than the distance between the adjacent intermediate electrodes ME. In this case, leakage current is likely to occur between adjacent selector SELs or interference due to capacitive coupling or the like is likely to occur, and there is a high possibility that a malfunction will occur in the write operation and the read operation. Furthermore, since interference between adjacent selector SELs is suppressed, it may not be possible to improve the cell density of the memory cell MC in the XY plane.

On the other hand, in the case of the configuration according to the present embodiment, the selector SEL can be formed before the intermediate electrode ME and the selector SEL are formed. That is, the selector SEL can be formed without using the hard mask 27. Therefore, the hard mask 27 can be made into a thin film that does not disappear during the processing of the magnetoresistive sensor MTJ and the intermediate electrode ME. Therefore, it is possible to suppress an increase in the difficulty of processing the magnetoresistive sensor MTJ due to the thickening of the hard mask 27.

Further, in the configuration according to the present embodiment, the diameter of the upper surface of the selector SEL can be made smaller than the diameter of the lower surface of the intermediate electrode ME. That is, the area of the upper surface of the selector SEL can be made smaller than the area of the lower surface of the intermediate electrode ME. Therefore, the distance between the adjacent selector SELs can be made longer than the distance between the adjacent intermediate electrodes ME. Therefore, it is possible to suppress interference between adjacent selector SELs. That is, it is possible to suppress interference between adjacent magnetoresistive element MTJs. Therefore, it is possible to suppress malfunction and improve the reliability of the magnetic storage device.

Further, in the configuration according to the present embodiment, the increase in the processing difficulty of the magnetoresistive effect element MTJ can be suppressed, and the interference between the adjacent magnetoresistive effect elements MTJ can be suppressed. Therefore, the cell density of the memory cell MC can be reduced. It can be improved and the magnetic storage device can be highly integrated.

2. 2. Second Embodiment Next, the second embodiment will be described. In the second embodiment, a method of manufacturing the memory cell MC different from that of the first embodiment will be described. Hereinafter, the points different from those of the first embodiment will be mainly described.

2.1 Cross-sectional structure of the memory cell array First, an example of the cross-sectional structure of the memory cell array 10 will be described with reference to FIG. FIG. 15 shows an example of a cross-sectional view for explaining the configuration of the memory cell array.

As shown in FIG. 15, in the present embodiment, the insulating layer 50 is provided on the upper surface of the insulating layer 21. The insulating layer 50 is, for example, a layer in which a dopant of the selector SEL (for example, As) and a dopant for inactivating the dopant (for example, As) of the selector SEL are injected into the insulating layer 23 described in the first embodiment. Hereinafter, the case where boron (B) is used as the dopant for inactivating As, which is the dopant of the selector SEL, will be described. For example, the concentration of B is preferably equal to or higher than the concentration of As in order to inactivate As, and is preferably a concentration that does not precipitate on the surface of the insulating layer 50 and does not deteriorate the roughness of the surface of the insulating layer 50. In other words, the concentration of B may be any concentration that can electrically separate the adjacent elements 24.

The insulating layer 50 of the present embodiment is formed by injecting B into the layer corresponding to the element 24. That is, the element 24 and the insulating layer 50 are formed without using processing such as dry etching. Therefore, the interface between the insulating layer 50 and the element 24 cannot be observed by, for example, TEM. However, the insulating layer 50 can be confirmed by measuring the distribution of the dopant using, for example, EDX analysis of TEM.

In the present embodiment, the ion implantation of B is performed in the region corresponding to the insulating layer 50 using the hard mask 27, the insulator 28, and the conductor 25 as masks. For example, due to the influence of ion implantation conditions (ion incident angle, etc.) or the diffusion of B due to heat treatment, the major axis d1 on the upper surface of the element 24 and the major axis d2 on the lower surface of the conductor 25 have a relationship of d1 ≦ d2. It is in.

2.2 Method for manufacturing a memory cell array Next, an example of a method for manufacturing the memory cell array 10 will be described with reference to FIGS. 16 to 19. FIG. 16 is a flowchart showing a method of manufacturing the memory cell array 10. 17 to 19 are cross-sectional views of the memory cell array 10 for explaining the method of manufacturing the memory cell array 10. In the following description, the details of the laminated structure constituting the element 26 (magnetoresistive sensor MTJ) will be omitted.

As shown in FIG. 16, the steps (steps S1 and S2) until the insulating layer 23 is deposited are the same as those in the first embodiment.

As shown in FIG. 17, after the insulating layer 23 is deposited, ion implantation using As as a dopant is performed (step S21 in FIG. 16, As injection). Next, a heat treatment for activating As is performed. As a result, the layer 51 corresponding to the element 24 is formed on the upper surfaces of the insulating layer 21 and the wiring layer 22. As may be diffused to the vicinity of the surface of the insulating layer 21, that is, to a position below the upper surface of the wiring layer 22 (a position close to the semiconductor substrate 20).

As shown in FIG. 18, the conductor 25, the element 26, the hard mask 27, and the insulator 28 are formed in the same manner as in steps S5 to S10 of FIG. 6 and FIGS. 9 to 14 of the first embodiment. That is, the magnetoresistive effect element MTJ and the intermediate electrode ME are formed.

As shown in FIG. 19, after processing the conductor 25, ion implantation using B as a dopant is performed (step S22 in FIG. 16, B implantation). As a result, B is injected into the region of the layer 51 that is not masked by the hard mask 27, the insulator 28, and the conductor 25. Next, a heat treatment for activation of B (inactivation of As) is performed. As a result, the insulating layer 50 is formed in the region where B is injected in the layer 51, and the element 24 is formed in the region where B is not injected. Since the elements 24 are separated from each other, the concentration profile of B in the depth direction (Z direction) after the heat treatment is deeper than the concentration profile of As, that is, B diffuses toward the semiconductor substrate 20 closer to the semiconductor substrate 20 than As. Is preferable. The profiles of As and B can be measured by, for example, EDX analysis of TEM.

After that, the insulating layer 29 and the wiring layer 30 are formed in the same manner as in steps S11 and S12 of FIG. 6 of the first embodiment.

2.3 Effect of the present embodiment If the configuration is of the present embodiment, the same as that of the first embodiment can be obtained.

Further, in the configuration according to the present embodiment, since a resist mask is not required when injecting As, it is possible to suppress an increase in the photolithography process.

3. 3. Modifications and the like Not limited to the above-described embodiment, various modifications can be applied.

For example, in the above-described embodiment, the top-free magnetoresistive element MTJ in which the storage layer SL is provided above the reference layer RL has been described, but the present invention is not limited thereto. For example, the magnetoresistive effect element MTJ may be a bottom-free type in which the storage layer SL is provided below the reference layer RL.

Further, in the above-described embodiment, the memory cell array 10 in which all the memory cells MC are provided in the same layer has been described, but the present invention is not limited to this. A plurality of memory cells MC may be stacked in the Z direction.

Further, in the above-described embodiment, the structure in which the intermediate electrode ME and the magnetoresistive sensor MTJ are provided on the upper surface of the selector SEL has been described, but the present invention is not limited thereto. For example, the structure may be such that the intermediate electrode ME and the selector SEL are provided on the upper surface of the magnetoresistive effect element.

Further, the method for manufacturing the intermediate electrode ME and the magnetoresistive sensor MTJ is not limited to the above-described embodiment. If the method for manufacturing the selector SEL is the same as that of the above-described embodiment, the intermediate electrode ME and the magnetoresistive sensor MTJ can be manufactured by any method.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

1 ... Magnetic storage device, 10 ... Memory cell array, 11 ... Row selection circuit, 12 ... Column selection circuit, 13 ... Decoding circuit, 14 ... Write circuit, 15 ... Read circuit, 16 ... Voltage generation circuit, 17 ... Input / output circuit, 18 ... control circuit, 20 ... semiconductor substrate, 21, 23, 29, 50 ... insulating layer, 22, 30 ... wiring layer, 24, 26 ... element, 25 ... conductor, 27 ... hard mask, 28 ... insulator, 31 , 33, 35, 37, 38 ... non-magnetic material, 32, 34, 36 ... ferromagnetic material, 40 ... resist mask, 51 ... layer.

Claims (20)

The first wiring extending in the first direction and
The switching element provided on the first wiring and
A conductor provided on the switching element and
The magnetoresistive sensor provided on the conductor and
It is provided with an insulating layer provided in the same layer as the switching element.
The area of the first main surface of the switching element facing the conductor is smaller than the area of the second main surface of the conductor facing the switching element.
Magnetic storage device. The major axis of the first main surface is shorter than the major axis of the second main surface.
The magnetic storage device according to claim 1. The switching element contains silicon and arsenic.
The insulating layer contains silicon and does not contain arsenic.
The magnetic storage device according to claim 1. A hard mask provided on the magnetoresistive sensor and
Further provided with a second wiring provided on the hard mask and extending in a second direction intersecting the first direction.
The magnetic storage device according to claim 1. The magnetoresistive sensor includes a reference layer, a storage layer, and a tunnel barrier layer provided between the reference layer and the storage layer.
The magnetic storage device according to claim 1. The first wiring extending in the first direction and
The switching element provided on the first wiring and
A conductor provided on the switching element and
The magnetoresistive sensor provided on the conductor and
It is provided in the same layer as the switching element and includes an insulating layer containing arsenic and boron.
Magnetic storage device. The switching element contains arsenic and does not contain boron.
The magnetic storage device according to claim 6. The major axis of the first main surface of the switching element facing the conductor is equal to or smaller than the major axis of the second main surface of the conductor facing the switching element.
The magnetic storage device according to claim 6. A hard mask provided on the magnetoresistive sensor and
Further provided with the magnetoresistive element and the second wiring provided on the hard mask.
The magnetic storage device according to claim 6. The magnetoresistive sensor includes a reference layer, a storage layer, and a tunnel barrier layer provided between the reference layer and the storage layer.
The magnetic storage device according to claim 6. A step of forming a first wiring extending in the first direction in the first insulating layer,
A step of forming a second insulating layer on the first insulating layer and the first wiring, and
A step of forming a resist mask corresponding to the switching element provided on the first wiring on the second insulating layer, and a step of forming the resist mask.
A step of injecting arsenic into a region of the second insulating layer where the resist mask is not formed to form the switching element, and a step of forming the switching element.
A step of forming a conductor and a magnetoresistive effect element on the switching element is provided.
Manufacturing method of magnetic storage device. The step of forming the conductor and the magnetoresistive sensor is
The step of depositing the laminated film corresponding to the conductor and the magnetoresistive sensor, and
The process of forming a hard mask on the laminated film and
The step of processing the laminated film using the hard mask as a mask to form the magnetoresistive effect element, and
The step of forming an insulator on the side surface of the hard mask and the magnetoresistive sensor, and
A step of processing the conductor using the hard mask and the insulator as a mask.
The method for manufacturing a magnetic storage device according to claim 11. The laminated film includes a first ferromagnet, a second ferromagnet, and a non-magnetic material provided between the first ferromagnet and the second ferromagnet.
The method for manufacturing a magnetic storage device according to claim 12. A step of forming a second wiring extending in a second direction intersecting the first direction is further provided on the hard mask.
The method for manufacturing a magnetic storage device according to claim 12. A step of forming wiring extending in the first direction in the first insulating layer,
The step of forming the second insulating layer on the first insulating layer and the wiring, and
A step of injecting arsenic contained in a switching element into the second insulating layer to form the first layer,
A step of forming a conductor and a magnetoresistive sensor above the wiring,
A step of injecting boron into the first layer to form a third insulating layer is provided.
Manufacturing method of magnetic storage device. The step of forming the conductor and the magnetoresistive sensor is
The step of depositing the laminated film corresponding to the conductor and the magnetoresistive sensor, and
The process of forming a hard mask on the laminated film and
The step of processing the laminated film using the hard mask as a mask to form the magnetoresistive effect element, and
The step of forming an insulator on the side surface of the hard mask and the magnetoresistive sensor, and
A step of processing the conductor using the hard mask and the insulator as a mask.
The method for manufacturing a magnetic storage device according to claim 15. The step of injecting boron into the first layer to form the third insulating layer is carried out using the hard mask, the insulator, and the conductor as masks.
The method for manufacturing a magnetic storage device according to claim 16. The region containing arsenic and boron in the first layer functions as the third insulating layer, and the region containing arsenic and not containing boron functions as the switching element.
The method for manufacturing a magnetic storage device according to claim 15. The laminated film includes a first ferromagnet, a second ferromagnet, and a non-magnetic material provided between the first ferromagnet and the second ferromagnet.
The method for manufacturing a magnetic storage device according to claim 16. A step of forming a second wiring extending in a second direction intersecting the first direction is further provided on the hard mask.
The method for manufacturing a magnetic storage device according to claim 16.

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