JP2022041766A - Voltage amplifier circuit - Google Patents

Abstract

To provide a voltage amplifier circuit that does not saturate an output voltage by a DC offset voltage without increasing the circuit area.SOLUTION: A voltage amplifier circuit 1A includes an arithmetic amplifier circuit 2, a feedback capacitance 3, an input capacitance 4, a first pseudo-resistance circuit 5, an integrator circuit 7A, a control circuit 10, and an adder circuit 11. The arithmetic amplifier circuit 2 includes an inverting input terminal 2a, a non-inverting input terminal 2b, and an output terminal 2c. The feedback capacitance 3 and the first pseudo-resistance circuit 5 are connected between the inverting input terminal 2a and the output terminal 2c, and the input capacitance 4 is connected to the inverting input terminal 2a. The integrator circuit 7A includes a second pseudo-resistance circuit 6 and outputs a signal in which a signal band of an output voltage appearing in the output terminal 2c of the arithmetic amplifier circuit 2 or a frequency component higher than the signal band is attenuated. The control circuit 10 compensates for each voltage dependence of the first and second pseudo-resistance circuits 5 and 6. The adder circuit 11 adds the output of the integrator circuit 7A to the potential of the non-inverting input terminal 2b.SELECTED DRAWING: Figure 1

Description

The present invention relates to a voltage amplifier circuit configured by using an arithmetic amplifier circuit including an inverting input terminal, a non-inverting input terminal and an output terminal.

Conventionally, as a voltage amplification circuit of this kind, for example, there is one used in the charge detection circuit disclosed in Patent Document 1. As shown in FIG. 3 of the same document, the charge detection circuit includes a pseudo-resistance circuit, a third operational amplifier, and a capacitor. This charge detection circuit outputs a voltage-amplified detection signal to the output terminal when the detection signal from the charge output sensor is input to the inverting input terminal of the third operational amplifier. At this time, the pseudo-resistance circuit controls the gate voltage of the first field-effect transistor connected between the inverting input terminal and the output terminal of the third operational amplifier, and pseudo-differences between the drain and source thereof. Produces high resistance. The gate voltage is generated by the strain compensation bias source in the pseudoresistor circuit, taking into account the output terminal voltage of the third operational amplifier. This gate voltage improves the non-linearity of the pseudo-resistance value due to the change in the voltage applied to the first field effect transistor.

Further, there is also a voltage amplification circuit conventionally disclosed in Non-Patent Document 1. This voltage amplifier circuit constitutes a DC servo circuit, and among the output voltage appearing in the output terminal of the arithmetic amplifier circuit, the frequency component lower than the signal band is taken out by the low-pass filter in the integration circuit, integrated and integrated into the arithmetic amplifier circuit. By negatively feeding back to one of the input terminals, the offset of the arithmetic amplifier circuit and the low frequency noise are reduced.

International Publication No. 2015/178271

ELECTRONICS LETTERS 20th November 2014 Vol. 50 No. 24 pp. 1808-1809

However, in the third operational amplifier constituting the voltage amplification circuit disclosed in the conventional patent document 1, the DC offset voltage generated at the input terminal is the gain of the entire amplifier circuit including the third operational amplifier in DC. There was a problem that the output voltage that was amplified by the output terminal and appeared at the output terminal was saturated.

Further, in the voltage amplifier circuit disclosed in the above-mentioned conventional patent document 2, the low-pass filter in the DC servo loop must cut off the component of the signal band in the output voltage. Therefore, when the signal frequency is close to direct current, a high resistance of the same level as the pseudo resistance generated by the pseudo resistance circuit disclosed in Patent Document 1 is required as the resistance constituting the low-pass filter in the integrating circuit. .. Therefore, in the voltage amplifier circuit disclosed in the above-mentioned conventional patent document 2, there is a problem that the circuit area becomes large when trying to form the high resistance in the circuit board.

The present invention has been made to solve such a problem.
An arithmetic amplifier circuit having an inverting input terminal, a non-inverting input terminal, and an output terminal,
The feedback capacitance, one terminal connected to the inverting input terminal of the math amplifier circuit and the other terminal connected to the output terminal of the math amplifier circuit,
The input capacitance in which one terminal is connected to the inverting input terminal of the arithmetic amplifier circuit and the other terminal is connected to the signal input terminal,
A first pseudo-resistor circuit in which one terminal is connected to the inverting input terminal of the math amplifier circuit and the other terminal is connected to the output terminal of the math amplifier circuit.
An integrator circuit that is configured with a second pseudo-resistance circuit and outputs a signal in which a frequency component higher than the signal band or signal band of the output voltage appearing at the output terminal of the arithmetic amplifier circuit is attenuated, and
Suppresses the fluctuation of the pseudo-resistance value due to the change in the applied voltage of each pseudo-resistance generated by the first pseudo-resistance circuit and the second pseudo-resistance circuit, and compensates for the voltage dependence of the first pseudo-resistance circuit and the second pseudo-resistance circuit. One control circuit to do
A voltage amplification circuit is configured by including an adder circuit that adds the output of the integrator circuit to the potential of the inverting input terminal or the non-inverting input terminal of the arithmetic amplifier circuit.

According to this configuration, the DC offset voltage appearing at the input terminal of the arithmetic amplifier circuit is the output voltage appearing at the output terminal when the signal band of the output voltage appearing at the output terminal and the higher frequency components are integrated by the integrating circuit. A frequency component lower than the signal band is extracted, and the output of the integrating circuit is reduced by being added to the potential of the inverting input terminal or the non-inverting input terminal of the arithmetic amplifier circuit by the adder circuit and fed back negatively. Therefore, the problem that the output voltage appearing in the output terminal is saturated by the DC offset voltage appearing in the input terminal of the arithmetic amplifier circuit is solved.

At this time, since the high resistance pseudo resistance generated by the second pseudo resistance circuit is used as the resistance used for the low-pass filter in the integrator circuit, the high resistance resistance is not formed by using a large circuit area. , The frequency component lower than the signal band of the output voltage appearing at the output terminal can be effectively extracted in the integrating circuit.

Further, since the other end of the first pseudo-resistance circuit and one end of the second pseudo-resistance circuit are connected to each other, they have the same potential. Further, the inverting input terminal of the math amplifier circuit to which one end of the first pseudo-resistance circuit is connected and the non-inverting input terminal of the math amplifier circuit to which the other end of the second pseudo-resistance circuit is connected via the integrator circuit are The same potential is obtained by an imaginary short between the inverting input terminal and the non-inverting input terminal of the math amplifier circuit. Further, an integrator circuit exists between the other end of the second pseudo-resistance circuit and the non-inverting input terminal of the arithmetic amplifier circuit, and the frequency component lower than the signal band of the output voltage is arithmetically amplified by this integrator circuit. The voltage that is negatively fed back to the non-inverting input terminal of the circuit is reduced to a very small value by the loop gain in the negative feedback loop. Therefore, since the voltage drop between the other end of the second pseudo-resistance circuit and the non-inverting input terminal of the arithmetic amplifier circuit is very small, what is the other end of the second pseudo-resistance circuit and the non-inverting input terminal of the arithmetic amplifier circuit? It is considered that the potential is almost the same. As a result, the voltage between the terminals of the first pseudo-resistance circuit and the voltage between the terminals of the second pseudo-resistance circuit are substantially equal to each other, and the first pseudo-resistance circuit and the second pseudo-resistance circuit generate pseudo-resistances having substantially the same value. You can think of it as something.

Therefore, the fluctuation due to the applied voltage change of each pseudo-resistance generated by the first pseudo-resistance circuit and the second pseudo-resistance circuit is suppressed by the control of one control circuit, and the first pseudo-resistance circuit and the second pseudo-resistance circuit are suppressed. Each voltage dependence of can be compensated. Therefore, since it is not necessary to separately provide a control circuit for each of the first pseudo-resistance circuit and the second pseudo-resistance circuit, voltage amplification without increasing the circuit area and without saturating the output voltage by the DC offset voltage. The circuit can be configured.

According to the present invention, it is possible to provide a voltage amplifier circuit that does not saturate the output voltage by the DC offset voltage without increasing the circuit area.

It is a circuit diagram which shows the schematic structure of the voltage amplifier circuit by 1st Embodiment of this invention. It is a circuit diagram which shows the schematic structure of the voltage amplifier circuit by 2nd Embodiment of this invention. It is a circuit diagram which shows the schematic structure of the voltage amplifier circuit by the 3rd Embodiment of this invention.

Next, a mode for carrying out the voltage amplifier circuit of the present invention will be described.

FIG. 1 is a circuit diagram showing a schematic configuration of a voltage amplifier circuit 1A according to the first embodiment of the present invention.

The voltage amplifier circuit 1A includes an amplifier circuit 7A, a control circuit 10 and an adder circuit 11 including an arithmetic amplifier circuit 2, a feedback capacitance 3, an input capacitance 4, a first pseudo-resistance circuit 5, and a second pseudo-resistance circuit 6. Be prepared for it.

The arithmetic amplifier circuit 2 includes an inverting input terminal 2a, a non-inverting input terminal 2b, and an output terminal 2c. In the feedback capacitance 3, one terminal is connected to the inverting input terminal 2a of the math amplifier circuit 2, and the other terminal is connected to the output terminal 2c of the math amplifier circuit 2. The output terminal 2c is connected to the signal output terminal Vout of the voltage amplification circuit 1A. In the input capacitance 4, one terminal is connected to the inverting input terminal 2a of the arithmetic amplifier circuit 2, and the other terminal is connected to the signal input terminal Vin. In the first pseudo-resistance circuit 5, one terminal 5a is connected to the inverting input terminal 2a of the arithmetic amplifier circuit 2, and the other terminal 5b is connected to the output terminal 2c of the arithmetic amplification circuit 2.

The integrator circuit 7A is composed of a low-pass filter composed of a second pseudo-resistance circuit 6 and a capacitor 8, and an arithmetic amplifier circuit 9. The arithmetic amplifier circuit 9 includes an inverting input terminal 9a, a non-inverting input terminal 9b, and an output terminal 9c. In the second pseudo-resistance circuit 6, one terminal 6a is connected to the output terminal 2c of the arithmetic amplifier circuit 2, and the other terminal 6b is connected to the inverting input terminal 9a of the arithmetic amplifier circuit 9. One terminal of the capacitor 8 is connected to the inverting input terminal 9a of the math amplifier circuit 9, and the other terminal 6b is connected to the output terminal 9c of the math amplifier circuit 9. The non-inverting input terminal 9b of the math amplifier circuit 9 is connected to a reference potential. The integrator circuit 7A outputs a signal in which a frequency component higher than the signal band or the signal band of the output voltage appearing in the output terminal 2c of the arithmetic amplifier circuit 2 is attenuated. That is, the integrating circuit 7A outputs a frequency component lower than the signal band of the output voltage appearing in the output terminal 2c of the arithmetic amplifier circuit 2.

One control circuit 10 is provided, and the pseudo-resistance value fluctuation due to the change in the applied voltage between the terminals of each pseudo-resistance generated by the first pseudo-resistance circuit 5 and the second pseudo-resistance circuit 6 is suppressed, and the first control circuit 10 is provided. The voltage dependence of the pseudo-resistance circuit 5 and the second pseudo-resistance circuit 6 is compensated. The adder circuit 11 adds the output of the integrator circuit 7A to the potential of the inverting input terminal 2a or the non-inverting input terminal 2b of the arithmetic amplifier circuit 2. In the present embodiment, the adder circuit 11 is composed of a wiring connecting the output terminal 9c of the math amplifier circuit 9 and the non-inverting input terminal 2b of the math amplifier circuit 2 and the non-inverting input terminal 2b of the math amplifier circuit 2 for integration. The output of the circuit 7A is added to the potential of the non-inverting input terminal 2b of the arithmetic amplifier circuit 2.

In the present embodiment, the first pseudo-resistance circuit 5 and the second pseudo-resistance circuit 6 have a resistance component between the drain and the source of the field-effect transistor as a pseudo-resistance, and are the same as those in the voltage amplifier circuit disclosed in Patent Document 1. It has a good structure. That is, the first pseudo-resistance circuit 5 and the second pseudo-resistance circuit 6 are configured to include a first field-effect transistor and a second field-effect transistor (not shown, respectively). The first field effect transistor and the second field effect transistor are typically MOSFETs of the same type. The first field-effect transistor and the second field-effect transistor each function as a high-resistance pseudo-resistance element by operating in a weak inversion region. The drain terminal D of the first field effect transistor constituting the first pseudo-resistance circuit 5 is connected to the other terminal 5b of the first pseudo-resistance circuit 5, and the source terminal S is one of the first pseudo-resistance circuits 5. It is connected to the terminal 5a. Further, the gate terminal G is connected to the control circuit 10. Further, the drain terminal D of the second field effect transistor constituting the second pseudo resistance circuit 6 is connected to the other terminal 6b of the second pseudo resistance circuit 6, and the source terminal S is the second pseudo resistance circuit 6. It is connected to one of the terminals 6a. Further, the gate terminal G is connected to the control circuit 10.

In the control circuit 10, one terminal 10a is connected to one terminal 5a of the first pseudo-resistance circuit 5, and the other terminal 10b is connected to the other terminal 5b of the first pseudo-resistance circuit 5, and is disclosed in Patent Document 1. It operates in the same way as a distortion compensation bias source in a voltage amplification circuit. That is, the control circuit 10 sets each gate voltage of the first field effect transistor and the second field effect transistor from the respective voltages of one terminal 10a and the other terminal 10b based on the characteristics of the first field effect transistor. By generating and applying it to the first field-effect transistor and the second field-effect transistor, the pseudo-resistance values of the first field-effect transistor and the second field-effect transistor are stably maintained at predetermined values.

The first pseudo-resistance circuit 5 and the second pseudo-resistance circuit 6 are drained by controlling the gate voltage applied to the first field-effect transistor and the second field-effect transistor constituting them by the control circuit 10. The resistance value of the channel formed between the sources, that is, the pseudo resistance value is controlled. When the gate voltage applied to the first field effect transistor and the second field effect transistor is set low by the control circuit 10, the inversion state of the channel region under each gate electrode becomes a deeper weak inversion state. The channel resistance component that appears as a pseudo-resistance between each drain source becomes a high resistance. Since this channel resistance component changes according to each gate voltage of the first field effect transistor and the second field effect transistor, it changes according to the voltage change applied between the drain and the source of the first field effect transistor. By controlling each gate voltage of the first field effect transistor and the second field effect transistor by the control circuit 10, it is possible to keep the gate voltage constant.

According to the voltage amplification circuit 1A according to the present embodiment, the DC offset voltage appearing in the inverting input terminal 2a and the non-inverting input terminal 2b of the arithmetic amplification circuit 2 is lower than the signal band of the output voltage appearing in the output terminal 2c. The frequency component is taken out by the amplifier circuit 7A, and the output of the amplifier circuit 7A is added to the potential of the inverting input terminal 2a or the non-inverting input terminal 2b of the arithmetic amplifier circuit 2 by the adder circuit 11 and negatively fed back. It will be reduced. Therefore, the conventional problem that the output voltage appearing in the output terminal 2c is saturated by the DC offset voltage appearing in the inverting input terminal 2a and the non-inverting input terminal 2b of the arithmetic amplifier circuit 2 is solved.

At this time, since the first pseudo-resistance circuit 5 is connected in parallel between the inverting input terminal 2a and the output terminal 2c of the arithmetic amplifier circuit 2, the signal frequency input to the input capacitance 4 connected to the signal input terminal Vin is set. Even when it is low, the cutoff frequency of the arithmetic amplifier circuit 2 can be lowered by the high resistance pseudo-resistance generated by the first pseudo-resistance circuit 5 and the feedback capacitance 3, so that the low-frequency input signal is voltage-amplified. be able to. Further, since the high resistance pseudo resistance generated by the second pseudo resistance circuit 6 is used as the resistance used for the low-pass filter in the integrator circuit 7A, a high resistance resistance is formed by using a large circuit area. Instead, the frequency component lower than the signal band of the output voltage appearing in the output terminal 2c can be effectively taken out in the integrating circuit 7A.

Further, since the other terminal 5b of the first pseudo-resistance circuit 5 and the one terminal 6a of the second pseudo-resistance circuit 6 are connected to each other, they have the same potential. Further, an operation in which the inverting input terminal 2a of the arithmetic amplifier circuit 2 to which one terminal 5a of the first pseudo-resistance circuit 5 is connected and the other terminal 6b of the second pseudo-resistance circuit 6 are connected via the integration circuit 7A. The non-inverting input terminal 2b of the amplifier circuit 2 has the same potential due to an imaginary short circuit between the inverting input terminal 2a and the non-inverting input terminal 2b of the amplifier circuit 2. Further, an integrated circuit 7A exists between the other terminal 6b of the second pseudo-resistance circuit 6 and the non-inverting input terminal 2b of the arithmetic amplifier circuit 2. However, the signal band of the output voltage is provided by the integrated circuit 7A. The voltage at which the lower frequency component is negatively fed back to the non-inverting input terminal 2b of the arithmetic amplifier circuit 2 is reduced to a very small value by the loop gain in the negative feedback loop. Therefore, since the voltage drop between the other terminal 6b of the second pseudo-resistance circuit 6 and the non-inverting input terminal 2b of the arithmetic amplification circuit 2 is very small, the other terminal 6b of the second pseudo-resistance circuit 6 and the arithmetic amplification are amplified. It is considered that the potential is substantially the same as that of the non-inverting input terminal 2b of the circuit 2. As a result, the voltage between the terminals of the first pseudo-resistance circuit 5 Va and the voltage Vb between the terminals of the second pseudo-resistance circuit 6 are substantially equal to each other, and the values are substantially the same depending on the first pseudo-resistance circuit 5 and the second pseudo-resistance circuit 6. It can be considered that a pseudo resistance is generated.

Therefore, the fluctuation of the pseudo-resistance value due to the change in the applied voltage between the terminals of the pseudo-resistance generated by the first pseudo-resistance circuit 5 and the second pseudo-resistance circuit 6 is suppressed by the control of one control circuit 10, and the second pseudo-resistance circuit 10 is controlled. It is possible to compensate for each voltage dependence of the 1 pseudo-resistance circuit 5 and the 2nd pseudo-resistance circuit 6. Therefore, since it is not necessary to separately provide the control circuit 10 for each of the first pseudo-resistance circuit 5 and the second pseudo-resistance circuit 6, the output voltage can be saturated by the DC offset voltage without increasing the circuit area. No voltage amplification circuit 1A can be configured.

Next, the voltage amplifier circuit according to the second embodiment of the present invention will be described.

FIG. 2 is a circuit diagram showing a schematic configuration of a voltage amplifier circuit 1B according to a second embodiment of the present invention. In FIG. 2, the same or corresponding parts as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

In the voltage amplification circuit 1B according to the second embodiment, the configuration of the integrator circuit 7B is different from the configuration of the integrator circuit 7A of the voltage amplification circuit 1A according to the first embodiment. Further, in the voltage amplification circuit 1A according to the first embodiment, the negative feedback by the DC servo loop is inverted by the arithmetic amplifier circuit 9 in the output of the arithmetic amplification circuit 2, and the non-inverting input of the arithmetic amplification circuit 2 by the addition circuit 11. This was done by feeding back to the terminal 2b, but in the voltage amplifier circuit 1B according to the second embodiment, the output of the math amplifier circuit 2 is not inverted by the math amplifier circuit 9, but the math amplifier circuit 2 is connected by the adder circuit 11. This is done by feeding back to the inverting input terminal 2a. The voltage amplification circuit 1B according to the second embodiment has the same configuration as the voltage amplification circuit 1A according to the first embodiment except for these.

The integrator circuit 7B is provided with a primary CR filter 12 having a pseudo-resistance generated by the second pseudo-resistance circuit 6 as a resistance component between the output terminal 2c of the arithmetic amplifier circuit 2 and the output terminal 2c of the arithmetic amplifier circuit 2. The primary CR filter 12 is composed of a second pseudo-resistance circuit 6 and a capacitor 13. The output of the primary CR filter 12 is given to the non-inverting input terminal 9b of the arithmetic amplifier circuit 9. A capacitor 14 is connected between the output terminal 9c of the math amplifier circuit 9 and the inverting input terminal 9a, and a resistor 15 is connected between the inverting input terminal 9a of the math amplifier circuit 9 and the reference potential. Further, the voltage output to the output terminal 9c of the math amplifier circuit 9 is divided by the resistors 16 and 17 connected in series and given to the inverting input terminal 2a of the math amplifier circuit 2.

Even in the voltage amplification circuit 1B according to the second embodiment, the DC offset voltage appearing in the inverting input terminal 2a and the non-inverting input terminal 2b of the arithmetic amplification circuit 2 is from the signal band of the output voltage appearing in the output terminal 2c. The low frequency component is taken out by the amplifier circuit 7B, and the output of the amplifier circuit 7B is reduced by being added to the potential of the inverting input terminal 2a of the amplifier circuit 2 by the amplifier circuit 11 and negatively fed back. Therefore, the conventional problem that the output voltage appearing in the output terminal 2c is saturated by the DC offset voltage appearing in the inverting input terminal 2a and the non-inverting input terminal 2b of the arithmetic amplifier circuit 2 is solved.

Further, since the high resistance pseudo-resistance generated by the second pseudo-resistance circuit 6 is used for the resistance of the primary CR filter 12 used as the low-pass filter in the integrator circuit 7B, a large circuit area is used to obtain high resistance. The frequency component lower than the signal band of the output voltage appearing in the output terminal 2c can be effectively taken out in the integrating circuit 7B without forming a resistor.

Further, the fluctuation of the pseudo-resistance value due to the change in the applied voltage between the terminals of the pseudo-resistance generated by the first pseudo-resistance circuit 5 and the second pseudo-resistance circuit 6 is suppressed by the control of one control circuit 10, and the first pseudo-resistance circuit 10 is controlled. It is possible to compensate for each voltage dependence of the 1 pseudo-resistance circuit 5 and the 2nd pseudo-resistance circuit 6. Therefore, since it is not necessary to separately provide the control circuit 10 for each of the first pseudo-resistance circuit 5 and the second pseudo-resistance circuit 6, the output voltage can be saturated by the DC offset voltage without increasing the circuit area. No voltage amplification circuit 1B can be configured.

Further, according to the voltage amplification circuit 1B according to the second embodiment, the AC component of the output voltage appearing in the output terminal 2c of the arithmetic amplification circuit 2 is attenuated by the primary CR filter 12 having a resistance component of high resistance. Therefore, since the amplitude of the AC signal component input to the integrating circuit 7B becomes small, the configuration of the integrating circuit 7B can be simplified, the circuit area can be reduced, and the power consumption can be reduced.

Next, the voltage amplifier circuit according to the third embodiment of the present invention will be described.

FIG. 3 is a circuit diagram showing a schematic configuration of a voltage amplifier circuit 1C according to a third embodiment of the present invention. In FIG. 3, the same or corresponding parts as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

In the voltage amplification circuit 1C according to the third embodiment, the point that the piezoelectric element 18 is connected to the inverting input terminal 2a of the arithmetic amplification circuit 2 instead of the input capacitance 4 is the same as the voltage amplification circuit 1A according to the first embodiment. different. Other configurations are the same as those of the voltage amplifier circuit 1A according to the first embodiment.

In the voltage amplifier circuit 1C according to the third embodiment, the input capacitance 4 is configured by the capacitance of the piezoelectric element 18. The voltage amplifier circuit 1C according to the third embodiment also has the same effect as the voltage amplifier circuit 1A according to the first embodiment.

Further, according to the voltage amplification circuit 1C according to the third embodiment, the charge detection signal detected by the piezoelectric element 18 is voltage-amplified by the arithmetic amplification circuit 2 with the capacitance of the piezoelectric element 18 as the input capacitance. Therefore, since the voltage amplifier circuit 1C simultaneously configures the charge detection circuit, it is possible to realize the charge detection circuit with a small number of circuit elements. Further, when the piezoelectric element 18 having a low insulating resistance is used for the input capacitance, the signal amplification factor of the arithmetic amplifier circuit 2 is the high resistance generated by the first pseudo-resistance circuit 5 and the low resistance of the insulating resistance of the piezoelectric element 18. It becomes a large value depending on the minute. Therefore, the DC offset voltage is amplified by this large amplification factor and appears at the output terminal 2c of the arithmetic amplifier circuit 2. However, the DC offset voltage is taken out by the integrating circuit 7A in the DC servo loop, and the operational amplifier circuit 2 By negatively feeding back to the non-inverting input terminal 2b of, the influence of the DC offset voltage on the output is reduced. Therefore, even if the piezoelectric element 18 having a low insulation resistance is used for the input capacitance, the signal can be amplified without the output voltage appearing in the output terminal 2c of the arithmetic amplifier circuit 2 being saturated.

1A, 1B, 1C ... Voltage amplifier circuit 2, 9 ... Arithmetic amplifier circuit 2a, 9a ... Inverted input terminal 2b, 9b ... Non-inverting input terminal 3c, 9c ... Output terminal 3 ... Capacitor (feedback capacity)
4 ... Capacitor (input capacity)
5 ... 1st pseudo-resistance circuit 6 ... 2nd pseudo-resistance circuit 7A, 7B ... Integrator circuit 8, 13, 14 ... Capacitor 10 ... Control circuit 11 ... Addition circuit 12 ... Primary CR filter 15, 16, 17 ... Resistance 18 ... Piezoelectric element

Claims (4)

An arithmetic amplifier circuit having an inverting input terminal, a non-inverting input terminal, and an output terminal,
The feedback capacitance in which one terminal is connected to the inverting input terminal of the arithmetic amplifier circuit and the other terminal is connected to the output terminal of the arithmetic amplifier circuit.
The input capacitance in which one terminal is connected to the inverting input terminal of the arithmetic amplifier circuit and the other terminal is connected to the signal input terminal,
A first pseudo-resistance circuit in which one terminal is connected to the inverting input terminal of the math amplifier circuit and the other terminal is connected to the output terminal of the math amplifier circuit.
An integrator circuit that is configured to include a second pseudo-resistance circuit and outputs a signal in which a frequency component higher than the signal band or the signal band of the output voltage appearing at the output terminal of the arithmetic amplifier circuit is attenuated, and an integrated circuit.
The voltage of each of the first pseudo-resistance circuit and the second pseudo-resistance circuit is suppressed by suppressing the fluctuation of the pseudo-resistance value due to the change in the applied voltage of each pseudo-resistance generated by the first pseudo-resistance circuit and the second pseudo-resistance circuit. One control circuit that compensates for the dependency,
A voltage amplification circuit including an adder circuit that adds the output of the integrator circuit to the potential of the inverting input terminal or the non-inverting input terminal of the arithmetic amplifier circuit. The voltage amplification circuit according to claim 1, wherein the first pseudo-resistance circuit and the second pseudo-resistance circuit have a resistance component between a drain / source terminal in a field-effect transistor as a pseudo-resistance. The first or second aspect of the integrated circuit is characterized in that a CR filter having a pseudo-resistance generated by the second pseudo-resistance circuit as a resistance component is provided between the integrated circuit and the output terminal of the arithmetic amplifier circuit. The voltage amplification circuit described. The voltage amplification circuit according to any one of claims 1 to 3, wherein the input capacitance is composed of the capacitance of the piezoelectric element.

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