JP2022033357A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of providing a player with a novel performance.

SOLUTION: Each time a preset period 16 ms elapses, a peripheral control MPU of a peripheral control part of a peripheral control board 4140 validates from a contact part detected first to a contact part detected secondly, and repetitively acquires coordinate values, with the respective contact parts as a contact face of the touch panel 480; and can determine whether or not coordinate values acquired last time when the preset period 16 ms elapses match the coordinate values acquired this time when the 16 ms elapses. Consequently, when the coordinate values acquired last time when the 16 ms elapses match the coordinate values acquired this time when the 16 ms elapses, reliability of the coordinate values can be improved. Further, on the basis of the coordinate values having high reliability, an image to be displayed on a display area of an upper tray-side liquid crystal display device can be changed by the contact with the touch panel 480.

SELECTED DRAWING: Figure 17

COPYRIGHT: (C)2022,JPO&INPIT

Description

The present invention relates to a gaming machine.

Conventionally, a gaming machine has been proposed in which a player can change the content displayed on a liquid crystal display by operating an effect button (for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2011-200685 (paragraph [0033] and FIG. 4).

However, it has been difficult to further improve the convenience with the gaming machine configuration as described in Patent Document 1.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a gaming machine having improved convenience as compared with the prior art.

The present invention
It is a gaming machine equipped with a gaming area where gaming balls can flow down.
The front component that constitutes the front side of the gaming machine,
A main control means for controlling the progress of the game based on the entry of the ball into the starting port provided in the game area, and
Production control means to control the production related to the game,
A specific operation unit provided below the game area of the front component and operated by the player, and a specific operation unit.
A calling operation executing means for executing a calling operation capable of calling a staff member of the game hall by operating the specific operation unit by the player, and a calling operation executing means.
A call notification display execution means for displaying a call notification to inform the player that it is possible to call a staff member of the game hall by operating the specific operation unit.
Equipped with
By displaying the call notification, it is possible to make the player recognize that it is possible to call the staff of the game hall by the operation of the specific operation unit provided in the game machine instead of the external device.
The call notification display executing means is controlled by the effect control means instead of the main control means.

According to the present invention, convenience can be improved as compared with the prior art.

It is a perspective view which shows the state which opened the main body frame with respect to the outer frame of a pachinko gaming machine, and opened the door frame with respect to the main body frame. It is a front view of a pachinko machine. It is a rear view of a pachinko machine. It is a front perspective view of the outer frame. It is a front perspective view of the main body frame. It is a rear perspective view of the board unit in the main body frame. It is a perspective view of a door frame. It is a front view of a game board. FIG. 8 is an exploded perspective view of the game board of FIG. 8 as viewed from the front by disassembling. It is a front view which shows the function display unit in a game board enlarged in the state which attached to a pachinko machine. It is a block diagram of a main control board, a payout control board, and a peripheral control board. It is a block diagram which shows the continuation of FIG. It is a schematic diagram of various detection signals input / output to a game ball rental device connection terminal board which relays an electric connection between a payout control board constituting a main board, a CR unit, and a frequency display board. It is a block diagram which shows the continuation of FIG. It is a block diagram which shows the outline of the peripheral control MPU. It is a block diagram around the sound source built-in VDP in a liquid crystal display and a sound control unit. It is a block diagram of a touch panel control board. It is a schematic diagram which detects the position where a finger is touching a touch panel. It is the schematic which shows the continuation of FIG. It is a block diagram which shows the power-source system of a pachinko machine. It is a block diagram which shows the continuation of FIG. It is a circuit diagram which shows the circuit of a main control board. It is a circuit diagram which shows the power failure monitoring circuit. It is a circuit diagram which shows the communication interface circuit between the main control board and the peripheral control board. It is a circuit diagram which shows the circuit and the like of a payout control unit. It is a circuit diagram which shows the payout control input circuit. It is a circuit diagram which shows the continuation of FIG. It is a circuit diagram which shows the payout motor drive circuit. It is a circuit diagram which shows the CR unit input / output circuit. It is an input / output diagram which shows various input / output signals with a main control board, and various output signals to an external terminal board. It is a table showing an example of various commands transmitted from a main control board to a payout control board. It is a table showing an example of various commands transmitted from a main control board to a peripheral control board. It is a table which shows the continuation of various commands transmitted from the main control board of FIG. 32 to the peripheral control board. It is a table which shows an example of various commands from a payout control board received by a main control board. It is a flowchart which shows an example of the processing at the time of power-on of the main control side. It is a flowchart which shows the continuation of the process at the time of power-on of the main control side of FIG. It is a flowchart which shows an example of the timer interrupt processing on the main control side. It is a flowchart which shows an example of the processing at the time of power-on of a payout control unit. It is a flowchart which shows the continuation of the process at the time of power-on of the payout control unit of FIG. 38. It is a flowchart which shows the continuation of the process at the time of power-on of a payout control unit following FIG. 39. It is a flowchart which shows an example of the payout control part timer interrupt processing. It is a flowchart which shows an example of the rotation angle switch history creation processing. It is a flowchart which shows an example of the sprocket fixed position determination skip process. It is a flowchart which shows an example of the ball squeeze determination process. It is a flowchart which shows an example of the prize ball stock number addition processing for prize balls. It is a flowchart which shows an example of the prize ball stock number addition processing for rental ball. It is a flowchart which shows an example of a stock monitoring process. It is a flowchart which shows an example of the payout ball operation determination setting process. It is a flowchart which shows an example of a payout setting process. It is a flowchart which shows an example of a sphere movement setting process. It is a flowchart which shows an example of a retry operation monitoring process. It is a flowchart which shows an example of the inconsistency counter reset determination process. It is a flowchart which shows an example of error cancellation operation determination processing. It is a timing chart which shows the signal processing (a) at the time of payout operation by ball lending, and the input signal confirmation processing (b) from a CR unit. It is a flowchart which shows an example of the processing at the time of power-on of a peripheral control unit. It is a flowchart which shows an example of the peripheral control part V blank interrupt processing. It is a flowchart which shows an example of the peripheral control part 1ms timer interrupt processing. It is a flowchart which shows an example of the peripheral control part command reception interrupt processing. It is a flowchart which shows an example of the peripheral control part power failure advance notice signal interrupt processing. It is a figure which shows an example of the display contents of a maintenance screen. It is a figure which shows the display content that the clerk should be called during a big hit. It is a figure which shows an example of the display contents of a service mode screen. It is a figure which shows an example of the display contents of a break timer setting screen. It is a figure which shows an example of the display content of the screen during a break. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example which the title of the selected display object is displayed. It is a figure which shows an example which the title of the selected display object is displayed. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of a volume adjustment screen. It is a figure which shows an example of a volume adjustment screen. It is a figure which shows an example of a volume adjustment screen. It is a figure which shows an example of a volume adjustment screen. It is a figure which shows an example of a volume adjustment screen.

[1. Overall configuration of pachinko game machines]
Hereinafter, the pachinko gaming machine as the gaming machine of the present invention will be described with reference to the drawings. First, the entire pachinko gaming machine according to the embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is a perspective view showing a state in which the main body frame is opened with respect to the outer frame of the pachinko gaming machine according to the embodiment and the door frame is opened with respect to the main body frame, and FIG. 2 is a front view of the pachinko gaming machine. Yes, FIG. 3 is a rear view of the pachinko gaming machine.

As shown in FIGS. 1 to 3, the pachinko gaming machine 1 has an outer frame 2 installed in an island facility (not shown) of a game hall, and a box that is openably and closably supported by the outer frame 2 and has an open front side. A game board 4 having a frame-shaped main body frame 3, a game board 4 having a game area 1100 mounted and fixed to the main body frame 3 from the front side and into which a game ball as a game medium is driven, and a player side of the main body frame 3 and the front surface of the game board 4 It is provided with a door frame 5 that is pivotally supported with respect to the main body frame 3 so as to be closed from the door frame 3. In the door frame 5 of the pachinko game machine 1, a game window 101 formed so that the game area 1100 of the game board 4 can be visually recognized from the player side, and a game ball arranged below the game window 101 are stored. The dish-shaped upper plate 301 and lower plate 302 (see FIG. 7), and the handle device 500 operated by the player to drive the game ball stored in the upper plate 301 into the game area 1100 of the game board 4. , Is equipped.

Further, in the pachinko gaming machine 1, when viewed from the front, the outer frame 2, the main body frame 3, and the door frame 5 are each formed in a vertically long rectangular shape extending in the vertical direction, and the horizontal widths in the left and right directions are substantially the same. In addition to the dimensions, the vertical width dimension in the vertical direction is formed so that the main body frame 3 and the door frame 5 are slightly shorter than the outer frame 2. A decorative cover 23 is attached to the front surface of the outer frame 2 at a position below the main body frame 3 and the door frame 5, and the front surface of the outer frame 2 is completely closed by the door frame 5 and the decorative cover 23. It has become so. Further, the outer frame 2, the main body frame 3, and the door frame 5 are arranged so that the upper ends are substantially aligned, and the main body frame 3 and the door frame 5 can rotate at the position on the front side of the left end of the outer frame 2. It is supported, and the right end of the main body frame 3 and the door frame 5 moves to the front side with respect to the outer frame 2 to open the door frame 2.

Further, in the pachinko gaming machine 1, in front view, the gaming area 1100 in which the gaming ball is driven is facing through the substantially circular gaming window 101, and the pachinko gaming machine 1 projects forward to the lower side of the gaming window 101. Two upper plates 301 and lower plates 302 are arranged one above the other. Further, a handle device 500 for the player to operate is arranged in the lower right corner of the front surface of the door frame 5, and the player holds the handle device 500 in a state where the game ball is stored in the upper plate 301. When the rotation operation is performed, the game ball in the upper plate 301 is driven into the game area 1100 of the game board 4 with the hitting strength corresponding to the rotation angle, and the game can be played.

The game window 101 of the door frame 5 is closed by a transparent glass unit 590, and although the inside of the game area 1100 can be visually recognized by the player, the player inserts a hand or the like into the game area 1100 to play the game. It is not possible to touch the game balls, obstacle nails, various winning openings, and accessories in the area 1100.

[2. Overall composition of the outer frame]
Next, the outer frame 2 installed in the island equipment of the game hall will be described with reference to FIG. FIG. 4 is a front perspective view of the outer frame. As shown in FIG. 4, the outer frame 2 includes upper and lower upper frame plates 10 and lower frame plates 11 extending in the horizontal direction, left and right side frame plates 12 and 13 extending in the vertical (up and down) direction, and their respective frame plates. It is provided with four connecting members 14 that connect the ends of 10, 11, 12, and 13, and by connecting the frame plates 10, 11, 12, and 13 to each other with the connecting member 14, a vertically long rectangular shape ( It is assembled in a square shape). The upper frame plate 10 and the lower frame plate 11 in the outer frame 2 are made of solid wood (for example, wood, plywood, etc.) having a predetermined thickness. An upper support metal fitting 20, which will be described later, is attached to the upper surface and the front surface of the left end portion of the upper frame plate 10.

On the other hand, the side frame plates 12 and 13 are made of a lightweight metal mold material (for example, an aluminum alloy) having a constant cross-sectional shape. A plurality of grooves extending in the vertical direction are formed on the outer side surface and the inner side surface of the side frame plates 12 and 13, and work is performed when the pachinko gaming machine 1 is installed in the pachinko island facility of the gaming hall. The pachinko gaming machine 1 can be easily held by a person's finger, and the design of the appearance can be enhanced.

The outer frame 2 is arranged so as to face the upper support metal fitting 20 fixed to the upper surface of the left end of the upper frame plate 10 and the upper support metal fitting 20, and is fixed to a predetermined position on the inner lower side of the left side frame plate 12. The support metal fitting 21, the reinforcing metal fitting 22 arranged to support the lower surface of the lower support metal fitting 21 and fixed so as to connect the left and right side frame plates 12, 13 and the decorative cover fixed to the front surface of the reinforcing metal fitting 22. 23 and. The upper support metal fitting 20 and the lower support metal fitting 21 are for pivotally supporting the main body frame 3 and the door frame 5 so as to be openable and closable. The shaft support pin 633 (see FIG. 5) of the upper shaft support metal fitting 630 in the main body frame 3, which will be described later, is detachably engaged with the support hook hole 20c in the upper support metal fitting 20. The main body frame shaft support formed on the main body frame shaft support metal fitting 644 of the main body frame 3 described later is inserted into the support protrusion 21d of the lower support metal fitting 21, and the support protrusion 21d of the lower support metal fitting 21 is inserted. After inserting into the support hole of the main body frame shaft support metal fitting 644 in the main body frame 3, the main body frame 3 can be easily engaged by locking the shaft support pin 633 of the upper shaft support metal fitting 630 of the main body frame 3 to the support hook hole 20c. It can be opened and closed freely.

Further, the outer frame 2 is attached and fixed to the inside of the right side frame plate 13 by two closing plates 24, 25 (see FIG. 1) arranged vertically separated by a predetermined distance. These closing plates 24 and 25 are formed in a substantially L shape in a plan view. The closing plates 24 and 25 are hook portions 1054, 1065 (FIG. 1) of the locking device 1000 (locking device) attached along the open side of the main body frame 3 when the main body frame 3 is closed with respect to the outer frame 2. The hook portion 1054, 1065 and the closing plates 24, 25 are formed by inserting a key into the cylinder lock 1010 of the locking device 1000 and rotating the key in one direction, which will be described in detail later. The engagement can be disengaged and the closed state of the main body frame 3 with respect to the outer frame 2 can be released.

[3. Overall configuration of the main body frame]
Next, the main body frame 3 provided on the front side of the outer frame 2 so as to be openable and closable will be described with reference to FIGS. 5 and 6. FIG. 5 is a front perspective view of the main body frame, and FIG. 6 is a rear perspective view of the substrate unit in the main body frame. As shown in FIG. 5, the main body frame 3 has a main body frame base 600 having a rectangular game board holding port 601 for forming the skeleton of the main body frame 3 and penetrating in the front-rear direction to hold the game board 4. The upper shaft support bracket 630 and the lower shaft support bracket 640, which are attached to the upper and lower ends of the left end portion of the main body frame base 600 in front view and are pivotally supported by the outer frame 2 and pivotally support the door frame 5, A hitting ball launching device 650 attached to the lower front surface of the main body frame base 600 to drive a game ball into the game area 1100 of the game board 4, and a game to the upper plate 301 of the plate unit 300 attached to the rear side of the main body frame base 600. A prize ball unit 700 for paying out balls and a game ball from the prize ball unit 700 to the plate unit 300 of the door frame 5 when the door frame 5 is opened with respect to the main body frame 3 attached to the front surface of the main body frame base 600. It is equipped with a ball outlet opening / closing unit 790 that blocks the flow of the ball.

Further, the main body frame 3 is attached to the lower rear surface of the main body frame base 600, and various control boards, power supply boards 851, etc. for controlling the door frame 5 excluding the game board 4 and the electrical parts provided in the main body frame 3 and the like. The board unit 800 that is unitized as a unit, the back cover 900 that covers the rear opening of the game board holding port 601 in the main body frame base 600, and the side security plate 950 that covers the left end of the main body frame base 600 in front view. A lock device 1000 attached to the right end of the front view of the main body frame base to open and close the main body frame 3 to the outer frame 2 and to open and close the door frame 5 to the main body frame 3 is mainly provided.

[3-1. Body frame base]
Next, the main body frame base 600 will be described. The main body frame base 600 is integrally molded with synthetic resin, and the outer shape of the front view is a vertically long rectangular shape along the outer shape of the door frame 5, and is formed so as to have a predetermined amount of depth in the front-rear direction. Has been done. The main body frame base 600 has a game board holding port 601 capable of fitting and holding the outer periphery of the game board 4 so as to penetrate in a rectangular shape in the front-rear direction within a range of about 3/4 of the whole from the upper part to the lower part, and the main body frame. The U-shaped front end frame portion 602 forming the outer periphery of the front end excluding the left side of the front view of the base 600 and the front end frame portion 602 are recessed from the front to the rear, and from the lower end of the door frame base main body 110 in the door frame 5 to the rear. The protruding door frame projecting piece 110c (see FIG. 1), the upper bent projecting piece 167 (see FIG. 1) projecting rearward from the upper reinforcing sheet metal 151 in the reinforcing unit 150 of the door frame 5, and the open side reinforcing sheet metal 153. It comprises an engaging groove 603 into which an open side outer bending protrusion 164 (see FIG. 1) projecting rearward is inserted and engaged.

Further, the main body frame base 600 extends from the lower side of the game board holding port 601 to the lower end of the main body frame base 600, and is recessed from the front end of the front end frame portion 602 to the rear side by a predetermined amount and spreads in a plate shape in the left-right direction. It includes a peripheral wall portion 605 that projects rearward inside the front end frame portion 602 and forms an inner peripheral wall of the game board holding port 601. The peripheral wall portion 605 connects the free ends (upper and lower left end portions of the upper and lower left ends) of the U-shaped front end frame portion 602 so that the outer shape of the main body frame base 600 becomes a frame shape. It has become.

Further, the main body frame base 600 forms a lower side of the game board holding port 601 at the upper end of the lower rear wall portion 604, and the game board mounting portion 606 on which the game board 4 is mounted and the game board mounting portion 606. A positioning protrusion 607 that protrudes upward from approximately the center in the left-right direction and engages with the out-ball discharge groove of the game panel 1150 in the game board 4, and a game board stop of the game board 4 that is formed at a predetermined position on the inner wall on the right side of the front view of the peripheral wall portion 605. A game board locking portion to which the tool 1120 is fastened, and a plate-shaped upper end restricting rib 609 that hangs downward from the upper inner wall of the peripheral wall portion 605 and has a lower end that can contact the upper end of the game board 4 in the left-right direction. And have. By fitting the positioning protrusion 607 of the main body frame base 600 with the out ball discharge groove of the game board 4, it is possible to regulate the lower end of the game board 4 from moving in the left-right direction and the rear direction. There is. Further, the game board locking portion can regulate the movement of the right side of the game board 4 in the front-rear direction by locking the game board stopper 1120 of the game board 4. .. Although the details of the left side of the game board 4 in the front view will be described later, the movement in the front-rear direction is restricted by the positioning member 956 of the side security plate 950.

Further, the main body frame base 600 is formed at a position where the lower rear wall portion 604 is recessed one step to the rear side from the front surface of the front end frame portion 602, and the hit ball launching device is formed on the right front surface of the lower rear wall portion 604 in front view. The hit ball launching device 650 is attached from the front side so that the launching solenoid 654 of the 650 is accommodated in the solenoid accommodating recess. When the ball launcher 650 is attached to the front surface of the lower rear wall portion 604, a foul space 626 extending to the left and downward is formed on the left side of the front view from the upper end of the launch rail 660 in the ball launcher 650. It has become like. In the present embodiment, when the door frame 5 is closed with respect to the main body frame 3, the foul ball inlet 542e (see FIG. 1) in the foul cover unit 540 is located at the lower part of the foul space 626. , The game ball descending from the foul space 626 is received by the foul ball inlet 542e of the foul cover unit 540 and discharged to the lower plate 302 (see FIG. 7) in the plate unit 300.

Further, the main body frame base 600 is formed with a plurality of openings that penetrate in a rectangular shape in the front-rear direction on the left side of the left-right center of the lower rear wall portion 604 in the front view, and a plurality of openings on the upper side of the openings and on both the left and right sides in the front-rear direction. It is provided with a through hole 615 penetrating through. The opening of the main body frame base 600 is closed by the relay terminal board cover 692 from the front side, and the board unit attached to the rear surface of the lower rear wall portion 604 through the opening 692a of the relay terminal board cover 692. The main door relay terminal board 880 of the 800 and the peripheral door relay terminal board 882 face the front side.

Further, the main body frame base 600 detects the opening of the door frame 5 with respect to the main body frame 3 on the lower front surface of the substantially circular cylinder lock through hole 611 penetrating in the front-rear direction through the upper right end of the lower rear wall portion 604 in front view. A door frame opening switch 618 is attached to the door frame, and when the door frame 5 is opened (opened) with respect to the main body frame 3, the pressing is released and the opening of the door frame 5 can be detected. It has become like. Further, the main body frame base 600 is provided with a main body frame opening switch 619 for detecting the opening of the main body frame 3 with respect to the outer frame 2 on the rear surface below the position where the door frame opening switch 618 is attached. When the main body frame 3 is opened (opened) with respect to the outer frame 2, the pressing is released so that the opening of the main body frame 3 can be detected.

[3-2. Upper shaft support and lower shaft support]
Next, the upper shaft support metal fitting 630 and the lower shaft support metal fitting 640 will be described. The upper shaft support bracket 630 and the lower shaft support bracket 640 are attached to the metal fitting mounting portions on the upper and lower rear surfaces of the left end of the main body frame base 600 by using predetermined screws, so that the door frame 5 can be attached to the main body frame 3. The main body frame 3 can be pivotally supported with respect to the outer frame 2 while being able to be pivotally supported so as to be openable and closable.

The upper shaft support bracket 630 has a plate-shaped mounting portion 631 that is attached to the upper bracket mounting portion of the main body frame base 600 and extends in the vertical and horizontal directions, and a plate-shaped forward extension that extends forward from the upper end of the mounting portion 631. Section 632, a shaft support pin 633 projecting upward from the vicinity of the front end of the front extension portion 632, and a shaft pin 155 of the door frame 5 arranged on the left side of the front view of the shaft support pin 633 (FIG. 7). The door frame shaft support hole 634 that penetrates in the vertical direction into which the door frame 5 is inserted, and the front extension portion 632 that hangs downward from the left end portion of the front view to regulate the rotation end of the door frame 5 toward the open side. It is equipped with a stopper. The upper shaft support metal fitting 630 is integrally formed with a mounting portion 631, a forward extending portion 632, and a stopper by bending and molding a single metal plate.

The lower shaft support bracket 640 is arranged below the door frame shaft support bracket 642 for pivotally supporting the door frame 5 and the door frame shaft support bracket 642 to pivotally support the main body frame 3 with respect to the outer frame 2. The main body frame shaft support metal fitting 644 and. The door frame shaft support bracket 642 in the lower shaft support bracket 640 has a plate-shaped mounting portion that is attached to the lower bracket mounting portion of the main body frame base 600 and extends in the vertical and horizontal directions, and extends forward from the lower end of the mounting portion. A plate-shaped front extension portion 642b, a door frame shaft support hole 642c that penetrates vertically near the front end of the front extension portion 642b and into which a shaft pin 157 of the door frame 5 (see FIG. 7) is inserted, and a front It is provided with a stopper 642d which is erected upward from the left end portion of the extension portion 642b in the front view and regulates the rotation end of the door frame 5 toward the open side. The door frame shaft support bracket 642 has a mounting portion, a forward extending portion 642b, and a stopper 642d integrally formed by bending and molding a single metal plate.

Further, the main body frame shaft support metal fitting 644 in the lower shaft support metal fitting 640 has a plate-shaped mounting portion that is attached to the metal fitting mounting portion on the lower side of the main body frame base 600 and extends in the vertical and horizontal directions, and extends forward from the lower end of the mounting portion. It is provided with a front extending portion 644b to be extended and a main body frame shaft support hole penetrating in the vertical direction near the front end of the front extending portion 644b. The main body frame shaft support bracket 644 also has a mounting portion and a front extending portion 644b integrally formed by bending and molding a single metal plate.

The lower shaft support bracket 640 is in a state where the mounting portion of the door frame shaft support bracket 642 and the mounting portion of the main body frame shaft support bracket 644 are overlapped (contacted) in the front-rear direction, and the door frame shaft support bracket 642 is in a state of being overlapped (contacted). The front extension portion 642b and the front extension portion 644b of the main body frame shaft support metal fitting 644 are separated from each other by a predetermined distance in the vertical direction so as to be attached to the lower metal fitting mounting portion of the main body frame base 600.

When the upper shaft support bracket 630 and the lower shaft support bracket 640 are attached to the main body frame base 600, the shaft support pin 633 of the upper shaft support bracket 630 and the main body frame shaft support hole of the lower shaft support bracket 640 are coaxially above each other. The main body frame shaft support hole of the main body frame shaft support metal fitting 644 in the lower shaft support metal fitting 640 fits into the support protrusion 21d (see FIG. 4) of the lower support metal fitting 21 in the outer frame 2. The front extension portion 644b of the main body frame shaft support bracket 644 is placed on the support protrusion 21c (see FIG. 4) of the lower support bracket 21 so as to be inserted, and then the shaft of the upper shaft support bracket 630 is placed. By inserting the support pin 633 into the support hook hole 20c (see FIG. 4) of the upper support metal fitting 20 in the outer frame 2, the main body frame 3 can be pivotally supported with respect to the outer frame 2. It has become like.

Further, the upper shaft support metal fitting 630 and the lower shaft support metal fitting 640 are attached to the main body frame base 600, and the door frame shaft support hole 634 of the upper shaft support metal fitting 630 and the door frame shaft support hole of the lower shaft support metal fitting 640 are provided. The door frame is positioned coaxially with 642c, and the door frame is inserted so that the shaft pin 157 of the door frame 5 is inserted into the door frame shaft support hole 642c of the door frame shaft support metal fitting 642 in the lower shaft support metal fitting 640. The lower shaft support portion 158 of the door frame 5 (see FIG. 7) is placed on the front extension portion 642b of the door frame shaft support bracket 642, and then the shaft pin 155 of the door frame 5 is mounted on the door frame of the upper shaft support bracket 630. By inserting it into the shaft support hole 634, the door frame 5 can be pivotally supported with respect to the main body frame 3. In the present embodiment, the upper shaft pin 155 of the door frame 5 is slidable in the vertical direction, and the shaft pin 155 is inserted into the door frame shaft support hole 634 of the upper shaft support bracket 630. Is once slid downward so that the upper shaft support portion 156 of the door frame 5 and the front extension portion 632 of the upper shaft support bracket 630 overlap vertically, and then the shaft pin 155 is slid upward. It can be inserted into the door frame shaft support hole 634.

[3-3. Hit ball launcher]
Next, the hitting ball launching device 650 will be described. The hit ball launcher 650 is attached to the launch base 652 of a metal plate attached to the front predetermined position of the lower rear wall portion 604 of the main body frame base 600 so that the rotation drive shaft 654a projects forward on the lower rear surface of the launch base 652. The launching solenoid 654, the hitting mallet 656 fixed to the rotary drive shaft 654a of the launching solenoid 654 so as to be integrally rotatable, the mallet tip 658 fixed to the tip of the hitting mallet 656, and the predetermined position on the movement trajectory of the mallet tip 658. The hammer tip 658 at the tip of the ball mallet 656 passes between the launch rail 660 attached to the front of the launch base 652 and the launch rail 660 extending diagonally to the upper left of the front view from the position as the base end. At the same time as it is possible, a ball stop piece 662 that forms a gap through which the game ball cannot pass and holds the game ball at the base end of the launch rail 660, and a game held at the base end of the launch rail 660 by the ball stop piece 662. It is equipped with a stopper 664 that restricts the hammer 656 (hammer tip 658) from rotating toward the launch rail 660 side from the hitting position where the ball can be hit.

Although detailed illustration is omitted, the firing solenoid 654 in the hitting ball launching device 650 is configured such that the rotation drive shaft 654a reciprocates with a strength (speed) according to the rotation operation angle of the handle device 500. .. Further, the hitting mallet 656 of the hitting ball launching device 650 has a fixed portion 656a fixed to the rotary drive shaft 654a of the launch solenoid 654 and a tip extending in a gentle arc shape from the fixed portion 656a to the axis of the rotary drive shaft 654a. On the other hand, a solenoid portion 656b that faces the normal direction and has a mallet tip 658 fixed to the tip, and a stopper portion 656c that extends to the opposite side of the rod portion 656b with the fixing portion 656a sandwiched and can come into contact with the stopper 664. It is equipped with. When the stopper portion 656c of the hitting mallet 656 comes into contact with the stopper 664, the mallet tip 658 at the tip rotates toward the launch rail 660 from the hitting position (rotating end in the counterclockwise direction when viewed from the front). It is becoming regulated.

When the hit ball launcher 650 is attached to the lower rear wall portion 604 of the main body frame base 600, the upper end of the launch rail 660 is substantially in the center in the left-right direction and the upper end of the lower rear wall portion 604, that is, the game board mounting portion. It is located below 606 (the lower side of the game board holding port 601), and has a predetermined width in the left-right direction between the lower end of the outer rail 1111 in the game board 4 held by the game board holding port 601. A foul space 626 that extends downward is formed at. Then, the hit ball launching device 650 can hit the game ball into the game area 1100 of the game board 4 by launching the game ball so as to jump over the foul space 626 on the left side of the front view from the launch rail 660. It has become. In the state where the door frame 5 is closed with respect to the main body frame 3, the foul ball entrance 542e of the foul cover unit 540 attached to the door frame 5 is located at the lower part of the foul space 626, and the game is played. A game ball that has become a foul ball without being driven into the area 1100 falls in the foul space 626, is received by the foul ball entrance 542e, and is discharged to the lower plate 302.

[3-4. Prize ball unit]
Next, the prize ball unit 700 will be described. In the pachinko island facility in the hall where the pachinko gaming machine 1 is installed, after storing the gaming balls supplied from the pachinko island facility side to the pachinko gaming machine 1, the upper plate 301 of the pachinko gaming machine 1 is stored based on a predetermined payout instruction. It is to be paid out to. The prize ball unit 700 receives and stores the prize ball base 710 attached to the rear surface of the main body frame base 600 and the game balls attached to the upper part of the rear surface of the prize ball base 710 and supplied from the Pachinko Island facility side. The 720, the tank rail unit 730 arranged under the prize ball tank 720 and the game balls stored in the prize ball tank 720 are aligned and sent to the downstream side, and the game balls arranged by the tank rail unit 730 are specified. The prize ball device 740 to be paid out based on the payout instruction and the game ball paid out by the prize ball device 740 can be guided to the upper plate 301 of the plate unit, and the upper plate 301 is paid out when the game ball is full. It mainly includes a full tank branch unit 770 that can branch and guide the game ball to the lower plate 302 side.

Further, the prize ball unit 700 includes an external terminal board 784 attached to the rear surface of the prize ball base 710, and an external terminal board cover 786 that covers the rear side of the external terminal board 784.

[3-4-1. Prize ball tank]
In the prize ball tank 720, the outer periphery of the bottom wall portion 721 is surrounded by the outer peripheral wall portion 722, and a predetermined amount of game balls can be stored on the bottom wall portion 721. Further, the prize ball tank 720 is inclined so that the upper surface of the bottom wall portion 721 is lowered toward the discharge port 723, so that the game ball on the bottom wall portion 721 rolls toward the discharge port 723. It has become.

Further, the prize ball tank 720 includes two ball leveling members 727 that are rotatably supported by the shaft portion 725. The ball leveling member 727 has one end side pivotally supported by the shaft portion 725 and holds a weight inside, so that the other end side hangs down due to its own weight. The ball leveling member 727 hangs down in the tank rail unit 730, which will be described later, and can smooth and align the game balls circulating in the tank rail unit 730.

[3-4-2. Tank rail unit]
The tank rail unit 730 includes a tank rail 731 that is arranged below the prize ball tank 720 and extends long in the left-right direction. The tank rail 731 has a gutter shape with an open upper part and a predetermined depth, and has a width (depth) that allows the game balls to be aligned in two rows in the front-rear direction. The bottom is tilted so that it is low.

Further, the tank rail unit 730 is continuously connected to the alignment gear 732 rotatably supported on the upper portion of the discharge port of the tank rail 731, the gear cover 733 covering the upper portion of the alignment gear 732, and the right end of the gear cover 733 when viewed from the front. A ball holding plate 734 that closes the upper part of the rail 731, and a ball stop piece 735 that can advance and retreat into the tank rail 731 and stop the game ball in the tank rail 731 from rolling toward the discharge port side. , Is equipped. Two alignment gears 732 are provided side by side in the front-rear direction so as to correspond to the two flow paths of the game balls partitioned in two rows by the partition wall of the tank rail 731.

[3-4-3. Prize ball device]
The prize ball device 740 is for discharging the game balls discharged and supplied from the discharge port of the tank rail unit 730 to the upper plate 301 of the plate unit 300 based on a predetermined payout instruction. The prize ball device 740 has a supply passage that opens at the upper end and extends to a position slightly lower than the center in the vertical direction with a width slightly wider than the outer shape of the game ball, and a predetermined width that communicates with the lower end of the supply passage. A distribution space with a space, a prize ball passage that communicates with the lower end of the left side (open side) of the distribution space and bends in a substantially square shape to open on the left side of the rear view, and the right side of the back view of the distribution space. (Shaft support side) It is equipped with a ball-extracting passage that communicates with the lower end and extends downward to open at the lower end. The supply passage, the distribution space, the prize ball passage, and the ball removal passage are formed in a state of being open to the rear.

The prize ball device 740 is integrally rotatably fixed to the rotating shaft of the payout motor 744 and is arranged on the rear side of the motor support plate. The third gear, the payout rotating body that rotates integrally with the third gear and is arranged in the distribution space, and the payout rotating body are fixed to the opposite side of the third gear so as to be integrally rotatable and are fixed in the circumferential direction, etc. It is equipped with a rotation detection board in which a plurality of (three in this embodiment) detection slits are formed at intervals, a ball-out switch 750 for detecting the presence or absence of a game ball in the supply passage, and a prize ball passage. Holds a counting switch 751 for detecting a game ball flowing down inside, a rotation angle switch 752 for detecting a detection slit formed in a rotation detection board that rotates integrally with a payout rotating body, and a rotation angle switch 752. It includes a rotation angle switch board 753, a payout motor 744, a ball out switch 750, a counting switch 751, and a prize ball case inner board 754 that relays the connection between the rotation angle switch 752 and the payout control board described later.

The payout rotating body is provided with three recesses having a size capable of accommodating one game ball at equal intervals in the circumferential direction. By rotating the payout rotating body, the game ball supplied from the supply passage is one. Each ball is housed in a recess and can be discharged to the prize ball passage or the ball removal passage side. Further, the three detection slits formed in the rotation detection board that rotates integrally with the payout rotating body are formed in equal parts (every 120 degrees) on the outer periphery of the rotation detection board, and correspond to the recesses of the payout rotating body. It is provided at each position, and by detecting the detection slit with the rotation angle switch 752, the rotation position of the payout rotating body can be detected. In this embodiment, the rotation between the detection slits (120 degrees) of the rotation detection board (payout rotating body) is designed to correspond to the rotation of 18 steps of the payout motor 744.

In the prize ball device 740, when the payout rotating body is rotated in the counterclockwise direction in the rear view by the payout motor 744, the game balls in the supply passage are paid out to the prize ball passage, and the payout rotation is performed. The game balls paid out to the prize ball passage by the rotation of the body are counted one by one by the counting switch 751 and then delivered to the prize ball passage. On the other hand, when the ball removal operation member is operated by a clerk in the hall or the like, the game balls in the supply passage are discharged to the ball removal passage, and the game balls discharged to the ball removal passage are discharged to the ball removal passage. It can be discharged from the lower end of the passage to the outside of the rear side of the pachinko gaming machine 1 via the full tank branch unit 770 described later.

[3-4-4. Full tank branch unit]
The full tank branch unit 770 is formed in a box shape so as to be lowered from the rear end to the front end as a whole, and is opened upward in the substantially center of the left-right direction at the upper part of the rear end to win the prize of the prize ball device 740. The prize ball receiving port that receives the game ball that has flowed down the ball passage, the branch space that is placed under the prize ball receiving port and spreads in the left-right direction, and the game from directly below the prize ball receiving port in the branch space to the front side. The normal passage that guides the ball, the normal ball outlet 774 that discharges the game ball that has flowed through the normal passage forward and opens at the right end of the front view, and the normal ball outlet 774 that opens to the right end of the front view, and the back view to the right of the prize ball receiving port in the branch space. It is equipped with a full tank passage that guides the game ball from the position to the front side, and a full tank outlet 776 that discharges the game ball that has flowed through the full tank passage to the front and opens on the left side of the front view of the normal ball outlet 774. ing.

Further, the full tank branch unit 770 has a ball ejection port that opens upward to the left end portion of the upper part of the rear end in front view and receives a game ball that has flowed down the ball ejection passage of the prize ball device 740, and a ball ejection port. A ball-extracting passage that guides the game ball received in the mouth to the front side, and a game ball that has passed through the ball-extracting passage are discharged forward, and at the left end of the front view, at a position behind the normal ball exit 774 and the full tank exit 776. It is equipped with an open ball outlet.

In the full tank branch unit 770, assuming that the door frame 5 is closed with respect to the main body frame 3, the normal ball outlet 774 and the full tank outlet 776 are the first ball inlets 542a of the foul cover unit 540 in the door frame 5, respectively. And the second ball inlet 542c (see FIG. 1) are opposed to each other, and the game ball released from the normal ball outlet 774 passes through the first ball inlet 542a of the foul cover unit 540 and serves as a dish. The game ball supplied to the upper plate 301 of the unit 300 and discharged from the full tank outlet 776 is supplied to the lower plate 302 of the plate unit 300 through the second ball inlet 542c of the foul cover unit 540. ing. Further, the ball ejection port is formed so as to communicate with the upper right end of the rear view of the main body frame base ball extraction passage in the main body frame base 600, and the game ball released from the ball extraction outlet is the main body frame of the main body frame base 600. It is designed to be handed over to the base ball removal passage.

When the upper plate 301 of the plate unit 300 is filled with the game balls and the game balls are further discharged from the prize ball unit 700 (prize ball device 740), the foul cover unit 540 is moved up from the first ball outlet. The game ball that cannot go out to the plate 301 side stagnates in the first ball passage of the foul cover unit 540, and eventually fills the upstream normal passage through the normal ball outlet 774 in the full tank branch unit 770. In this state, the game ball that has entered the branch space from the prize ball receiving port cannot normally enter the passage, starts to move laterally in the branch space, and the game ball that has moved laterally is full. It enters the tongue passage and is supplied from the full tank outlet to the lower plate 302 of the plate unit 300 via the second ball inlet 542c of the foul cover unit 540, the second ball passage, and the second ball outlet. It has become.

[3-5. Board unit]
Next, the substrate unit 800 will be described. As shown in FIG. 6, the board unit 800 includes a board unit base 810 attached to the rear surface of the lower rear wall portion of the main body frame base 600, a speaker box 820 attached to the left rear surface of the board unit base 810 in front view, and a substrate. A power supply board box holder 840 attached to the rear surface of the unit base 810 and a power supply board box attached to the rear surface of the power supply board box holder 840 so that the rear end is substantially flush with the rear end of the speaker box 820. The 850, the payout control board box 860 attached to the rear surface of the power supply board box 850 and the speaker box 820, and the terminal board box 870 attached to the rear surface of the speaker box 820 so as to cover the left end of the payout control board box 860 in the front view. A main door relay terminal board 880 and a peripheral door relay terminal board 882 attached to the front surface of the board unit base 810 are provided.

The power supply board box holder 840 has a discharge ball receiving portion 841 that is opened upward on the left front side of the center on the left and right sides and receives the game balls discharged downward from the out ball discharge portion of the game board 4. The discharge passage 842 that guides and discharges the game ball received by the discharge ball receiving portion 841 downward, and the discharge passage 842 and the discharge ball receiving portion 841 are opened forward and upward in front of the side (right side in front view). The entire rear surface of the power supply board box holder 840 is formed so as to be recessed toward the front side, and includes a box accommodating portion capable of accommodating the front end of the power supply board box 850.

Further, in the power supply board box holder 840, the open front end side of the discharge passage 842 is closed by the rear surface of the board unit base 810, and the opening of the board unit base 810 faces the discharge passage 842. It is formed and flows through the main body frame base ball ejection passage formed on the rear surface of the lower rear wall portion of the main body frame base 600, passes through the opening of the board unit base 810, and flows down to the rear side of the board unit base 810. The game ball and the game ball discharged from the out ball discharging section of the game board 4 and received by the discharging ball receiving section 841 can be discharged downward to the rear side of the pachinko gaming machine 1 through the discharging passage 842. It has become.

The power supply board box 850 is formed in a horizontally long box shape with an open front, and includes a power supply board 851 attached so as to close the front end opening thereof. The power supply board box 850 accommodates various electronic components attached to the power supply board 851, and externally receives heat from the electronic components and the like through a plurality of slits 850a formed on the upper surface and the lower surface. It can be released to. The power switch 852 attached to the power supply board 851 faces the rear surface of the power supply board box 850.

The payout control board box 860 is a horizontally long thin box-shaped box base 861 with an open rear, a thin box-shaped cover 862 fitted into the box base 861 from the rear side and an open front, and a box base 861. A payout control board 4110, which is attached to the rear surface and whose rear surface is covered by the cover 862, is provided. Further, the payout control board box 860 is provided with a plurality of separated cutting portions 863 formed on both the box base 861 and the cover 862 protruding outward from the left end of the rear view, and is provided at one location of the plurality of separated cutting portions 863. The box base 861 and the cover 862 are caulked and fixed. As a result, in order to separate the box base 861 and the cover 862, it cannot be separated unless the separation cutting portion 863 is cut, and when the payout control board box 860 is opened, the trace remains. .. Therefore, it is possible to know whether or not the payout control board box 860 has been opened or closed illegally. In this embodiment, the payout control board box 860 can be opened and closed only once for inspection and the like.

Further, in the payout control board box 860, the operation switch 860a (error canceling unit) attached to the payout control board 4110, the inspection output terminal 860c, and the like face rearward through the cover 862. Further, in the payout control board box 860, terminals for various connections for connecting to the main control board 4100 and the like face rearward through the cover 862. The operation switch 860a is operated when the RAM built in the microprocessor of the payout control board 4110 and the RAM built in the microprocessor of the main control board 4100 are cleared when the power is turned on, or after the power is turned on. When an error is notified, it is operated to clear the error, and the function to clear the RAM at the time of turning on the power and the period to play the function as clearing the RAM have passed after turning on the power. It has a function to cancel the error in (later). A detailed description of this point will be described later.

The terminal board box 870 includes a board base 871 attached to the rear surface of the speaker box 820, a frame peripheral relay terminal board 868 attached to the rear surface of the board base 871 and to which peripheral panel relay terminals 872 are fixed toward the rear, and a board base. A board so that the game ball rental device connection terminal board 869, which is attached to the rear surface of the 871 and the CR unit relay terminal 873 is fixed to the rear, and the peripheral panel relay terminal 872 and the CR unit relay terminal 873 face the rear side. It includes a substrate cover 874 that covers the rear side of the base 871. The peripheral panel relay terminal 872 is for connecting to a frequency display for displaying the operating status of the pachinko gaming machine 1 provided on the pachinko island facility side where the pachinko gaming machine 1 is installed, and is for connecting to a CR unit relay. The terminal 873 is for connecting to a CR unit installed adjacent to the pachinko gaming machine 1.

The main door relay terminal board 880 and the peripheral door relay terminal board 882 are provided on the door frame 5 and the peripheral control board 4140 provided on the game board 4 attached to the main body frame 3, the payout control board 4110 of the board unit 800, and the like. The purpose is to relay the connection with the handle device 500, each decorative board, the operation unit 400, and the like. These main door relay terminal boards 880 and peripheral door relay terminal boards 882 are attached to a board mounting portion formed on the front surface of the board unit base 810 so that they face the front side from the front surface of the main body frame base 600. Wiring extending from the door frame 5 can be connected.

The front side of the main door relay terminal plate 880 and the peripheral door relay terminal plate 882 is covered by the relay terminal plate cover 692 attached to the front surface of the main body frame base 600, and the relay terminal plate cover 692 Only the connection terminal faces the front side through the opening 692a, so that the front surface of the main body frame 3 has a neat appearance.

Further, the main door relay terminal plate 880 includes a ball rental button 361, a return button 362, a rental balance display unit 363, a potentiometer 512 of the handle device 500, and a touch of the ball rental unit 360 in the dish unit 300 arranged on the door frame 5 side. This is for relaying the connection between the full tank switch 550 of the switch 516, the launch stop switch 518, and the foul cover unit 540, and the payout control board 4110 arranged on the main body frame 3 side. Regarding the ball rental button 361 of the ball rental unit 360, the return button 362, the loan balance display unit 363, the potentiometer 512 of the handle device 500, the touch switch 516, the launch stop switch 518, and the full tank switch 550 of the foul cover unit 540. The explanation will be described later.

Further, the peripheral door relay terminal plate 882 is provided in each decorative unit 200, 240, 280 arranged on the door frame 5 side, each decorative board provided in the dish unit 300 and the operation unit 400, and the operation unit 400. , To relay the connection between various switches that detect the operations of the dial drive motor 414, the dial operation unit 401, and the pressing operation unit 405, and the peripheral control board 4140 of the game board 4 arranged on the main body frame 3 side. Is. The decorative units 200, 240, 280 arranged on the door frame 5 side, the decorative boards provided in the dish unit 300 and the operation unit 400, and the dial drive motor 414 and dial operation provided in the operation unit 400. A description of various switches for detecting the operation of the unit 401 and the pressing operation unit 405 will be described later.

[4. Overall configuration of door frame]
Next, the door frame 5 provided on the front side of the main body frame 3 so as to be openable and closable will be described with reference to FIG. 7. FIG. 7 is a perspective view of the door frame. As shown in FIG. 7, the door frame 5 includes a door frame base unit 100 having a game window 101 having an outer shape formed into a vertically long rectangular shape and an inner peripheral shape having a slightly vertically long circular shape (elliptical shape), and a door. The right side decoration unit 200 attached to the right outer circumference of the game window 101 on the front surface of the frame base unit 100, and the left side attached to the left outer circumference of the game window 101 on the front surface of the door frame base unit 100 facing the right side decoration unit 200. The decoration unit 240, the upper decoration unit 280 attached to the upper outer periphery of the game window 101 on the front surface of the door frame base unit 100, and the door frame base unit arranged below the lower ends of the right side decoration unit 200 and the left side decoration unit 240. It comprises a pair of side speaker covers 290 attached to the front of the 100.

Further, the door frame 5 is attached to the right side of the dish unit 300 attached to the lower part of the game window 101 on the front surface of the door frame base unit 100, the operation unit 400 attached to the center of the upper part of the dish unit 300, and the dish unit 300. The upper plate side liquid crystal display device 470, which is provided so as to cover the display area of the upper plate side liquid crystal display device 470 (second display device) and has a contact surface capable of detecting a contact state. The touch panel 480 (contact type input device), the handle device 500 attached to the lower right corner of the door frame base unit 100 through the dish unit 300, and the door frame base unit 100 are sandwiched between the handle device 500 for driving the game ball. A foul cover unit 540 arranged on the rear side of the dish unit 300 and attached to the rear surface of the door frame base unit 100, a ball feed unit 580 attached to the rear surface of the door frame base unit 100 on the right side of the foul cover unit 540, and a door. A glass unit 590 attached to the rear side of the frame base unit 100 so as to close the game window 101 is provided. In the present embodiment, the touch panel 480 is a type with a resolution of 10 × 20 and 4.3 inches, and a touch panel control board 450 for detecting and controlling a contact state is housed in a liquid crystal display device 470 on the upper plate side.

[4-1. Door frame base unit]
Next, the door frame base unit 100 will be described. The door frame base unit 100 has a door frame base main body 110 having a game window 101 having an outer shape formed in a vertically long rectangular shape and a game window 101 having a substantially elliptical shape with an inner circumference penetrating in the front-rear direction and a door frame. An upper bracket 120 attached to the center of the upper part of the game window 101 on the front surface of the base body 110 to fix the upper decorative unit, and a pair of sides attached to the lower left and right sides of the game window 101 on the front surface of the door frame base body 110. It includes a speaker 130 and a handle bracket attached to the lower right corner of the front view on the front surface of the door frame base main body 110 to support the handle device 500.

Further, the door frame base unit 100 is a metal frame-shaped reinforcing unit 150 (see FIG. 1) fixed to the rear side of the door frame base main body 110, and a game window 101 on the rear surface of the door frame base main body 110. A security cover 180 attached so as to cover the lower portion (see FIG. 1) and a glass unit locking member 190 rotatably attached to a predetermined position on the outer periphery of the game window 101 on the rear surface of the door frame base main body 110 (FIG. 1). 1) and the launch cover 191 (see FIG. 1) arranged on the left side (open side) from the center in the left-right direction and attached to the rear surface of the door frame base body 110 along the lower end of the game window 101 in the rear view. , A handle relay terminal plate that is attached to the rear surface of the door frame base main body 110 under the launch cover 191 and relays the connection between the potential meter 512 of the handle device 500 described later and the main control board 4100 provided in the game board 4 described later. 192 (see FIG. 1), the handle relay terminal plate cover 193 (see FIG. 1) that covers the rear side of the handle relay terminal plate 192, and the launch cover 191 and the handle relay terminal plate 192 sandwiching the center in the left-right direction. The frame decoration drive amplifier board 194 (see Fig. 1), which is located on the opposite side of the door frame base body (on the right side (shaft support side) from the center in the left-right direction) and is attached to the rear surface of the door frame base body, and the frame decoration drive. It includes a frame-decorated drive amplifier board cover 195 (see FIG. 1) that covers the rear side of the amplifier board 194.

The frame decoration drive amplifier board 194 is electrically connected to the side speakers 130 and the upper speakers of the left and right side decoration units 200 and 240, and is also electrically connected to the peripheral control board 4140 provided in the game board 4 described later. It is provided with an amplifier circuit that amplifies the acoustic signal sent from the peripheral control board 4140 and outputs it to each speaker 130. Although specific illustration is omitted, in the present embodiment, each of the decorative units 200, 240, 280, the decorative board provided in the dish unit 300 and the operation unit 400, and the dial drive motor provided in the operation unit 400. The wiring that electrically connects the switch, the handle relay terminal board 192, the ball rental unit 360 of the dish unit 300, the payout control board 4110, the peripheral control board 4140, etc. is the rear view of the frame decoration drive amplifier board 194. It is gathered at the position on the right side (shaft support side), bundled, and extended rearward so as to be connected to the main door relay terminal board 880 and the peripheral door relay terminal board 882 of the main body frame 3.

[4-1-1. Door frame base body]
The door frame base main body 110 is formed of a synthetic resin in a vertically long frame shape, and is formed in such a form that the game window 101 having a vertically long inner shape and a substantially elliptical shape is offset upward as a whole. Has been done. In the game window 101, the left and right side and the upper inner peripheral edge are formed in a continuous smooth curved line, while the lower inner peripheral edge is formed in a straight line extending to the left and right. Further, on the inner peripheral edge of the lower side of the game window 101 in the door frame base main body 110, a square notch through which the first ball outlet of the foul cover unit 540 can be inserted is formed on the shaft support side (left side when viewed from the front). A speaker mounting part for mounting and fixing the side speaker 130 placed on both the left and right sides of the lower side of the game window 101, and a right (open side) end of the front surface placed in the lower right corner when viewed from the front and bulging forward. A handle mounting part for mounting the handle bracket, a wiring passage port that penetrates in the front-rear direction at a predetermined position of the handle mounting part and allows wiring from the handle device 500 to pass through, and an upper side of the handle mounting part. A lock hole 116 is formed, which is formed in a tubular shape extending shortly toward the front and through which a cylinder lock 1010, which will be described later, can be inserted. In the door frame base main body 110, the widths of the upper side and the left and right side sides formed by the game window 101 are the upper reinforcing sheet metal 151, the shaft support side reinforcing sheet metal 152, and the open side reinforcing sheet metal 153 of the reinforcing unit 150 described later. The width is substantially the same as the width of the game window 101, and the game window 101 is formed as large as possible with respect to the size of the door frame base body in the front view.

[4-1-2. Reinforcement unit]
The reinforcing unit 150 includes an upper reinforcing sheet metal 151 (see FIG. 1) attached along the back surface of the upper side of the door frame base body 110 and a shaft support attached along the back surface of the shaft support side of the door frame base body 110. The side reinforcing sheet metal 152 (see FIG. 1), the open side reinforcing sheet metal 153 attached along the back surface of the open side of the door frame base body 110 (see FIG. 1), and the game window 101 of the door frame base body 110. It is provided with a lower reinforcing sheet metal 154 (see FIG. 1) attached along the back surface of the lower side, and they are fastened to each other with screws, rivets, or the like to form a square shape.

At the upper and lower ends of the shaft support side reinforcing sheet metal 152, an upper shaft support portion 156 having a shaft pin 155 slidably provided on the upper surface thereof in the vertical direction and a lower shaft branch portion 158 having a shaft pin 157 on the lower surface thereof are provided. It is provided integrally. Then, the upper and lower shaft pins 155 and 157 are pivotally supported by the upper shaft support bracket 630 and the lower shaft support bracket 640 formed above and below the shaft support side of the main body frame 3, so that the door frame 5 is pivotally supported with respect to the main body frame 3. It is designed to be freely opened and closed.

Further, a hook cover 165 that comes into contact with the door frame hook portion 1041 of the lock device 1000 is provided in the lower rear portion of the open side reinforcing sheet metal 153. This hook cover 165 engages with the door frame hook portion 1041 of the lock device 1000 (locking device) attached along the open side of the main body frame 3 when the door frame 5 is closed with respect to the main body frame 3. By inserting the key into the cylinder lock 1010 of the lock device 1000 and rotating it in one direction (rotating the main body frame 3 in the direction opposite to the opening direction with respect to the outer frame 2), the hook portion for the door frame The engagement between the 1041 and the hook cover 165 is disengaged, and the closed state of the door frame 5 with respect to the main body frame 3 can be released.

[4-2. Dish unit]
Next, the dish unit 300 will be described. The plate unit 300 includes an upper plate 301 and a lower plate 302 for storing the game balls paid out from the prize ball device 740, and launches the game balls stored in the upper plate 301 via the ball feeding unit. It can be supplied to the device 650.

The shape of the upper plate upper panel 314 of the plate unit 300 is formed in a curved shape so as to project forward from the left to the center when viewed from the front, and is linearly forward from the center to the right. It is formed protruding. An operation unit mounting portion to which the operation unit 400 is mounted is formed in the upper center of the dish unit 300, and a liquid crystal mounting portion 314d for mounting the upper plate side liquid crystal display device 470 is formed on the right side of the operation unit mounting portion. .. The shape of the upper plate upper panel 314 on which the liquid crystal mounting portion 314d is formed is formed in a plate shape, and when a player presses this portion downward by hand, for example, the upper plate panel 314 bends downward. When the pressing force exceeds a predetermined force, the upper plate upper panel 314 is broken. This is because the upper plate side liquid crystal display device 470 is expensive, and when the player presses the screen of the upper plate side liquid crystal display device 470, the force is received by the upper plate side panel 314. By bending the upper plate upper panel 314, the upper plate side liquid crystal display device 470 is prevented from being damaged. That is, a structure is adopted in which the upper plate upper panel 314 is damaged before the upper plate side liquid crystal display device 470 is damaged. If the upper plate upper panel 314 is damaged, the plate unit 300 will be replaced. In this case, the upper plate side liquid crystal display device 470 is removed from the broken upper plate upper panel 314 and attached to the upper plate upper panel 314 of the plate unit 300 to be replaced for reuse.

Further, the plate unit 300 has an upper plate ball removing mechanism 340 for pulling out the game balls stored in the upper plate 301 to the lower plate 302 in response to the operation of the upper plate ball removing button 341, and a lower plate ball removing button 354. A lower plate ball removing mechanism 350 for pulling out the game ball stored in the lower plate 302 downward through the lower plate ball removing hole 324b in response to the operation of, and a lower plate ball removing mechanism 350 installed adjacent to the pachinko gaming machine 1 (not shown). It is equipped with a ball rental unit 360 that operates a CR unit.

[4-2-1. Operation unit]
The operation unit 400 is arranged in front of the upper plate 301 at substantially the center in the left-right direction of the front view, and has a dial operation unit 401 (operation unit) that can be rotated by the player and a pressing operation unit 405 (operation unit) that the player can press. The operation unit) is provided, and the operation of the player can be received according to the game state, and the dial operation unit 401 can be moved. , It is intended to be able to participate in the production during the game. The rotation (rotation direction) of the dial operation unit 401 is detected by the rotation detection switch provided in the operation unit 400, and the operation of the pressing operation unit 405 is detected by the pressure detection switch provided in the operation unit 400.

Further, the operation unit 400 can rotate the dial operation unit 401 in the clockwise direction or the counterclockwise direction by the driving force of the dial drive motor 414. Further, the operation unit 400 rotates the dial operation unit 401 step by step by the driving force of the dial drive motor 414 using the stepping motor, or when the player rotates the dial operation unit 401, the operation unit 400 rotates. It is possible to assist the rotation, prevent it from rotating intentionally, and give a click feeling to the rotation. Further, the operation unit 400 can vibrate the dial operation unit 401 by alternately repeating the rotation of rotating the dial drive motor 414 in the forward direction and the rotation of the dial drive motor 414 in the reverse direction in small steps.

[4-2-2. Ball rental unit]
The ball lending unit 360 includes a ball lending button 361 and a return button 362 that can be pressed backward, and also has a lending balance display unit 363 between the ball lending button 361 and the return button 362. When the ball lending button 361 is operated, it is detected by the ball lending switch 365a, and when the return button 362 is operated, it is detected by the return switch 365b. The display content of the residual frequency display 365c can be visually recognized via the rental residual frequency display unit 363. The CR unit lamp 365d is arranged adjacent to the residual frequency display 365c, and the light emitting mode of the CR unit lamp 365d can be visually recognized via the rental residual display unit 363. The ball rental switch 365a, the return switch 365b, the remaining frequency display 365c, and the CR unit lamp 365d are mounted on the frequency display plate 365, and the frequency display plate 365 is mounted inside the ball rental unit 360. .. When the ball lending unit 360 inserts cash or a prepaid card into the ball lending machine provided adjacent to the pachinko gaming machine 1 and then presses the ball lending button 361, a predetermined number of game balls are placed in the dish unit. You can rent (pay out) into the upper plate 301 of 300, and when you press the return button 362, the balance of cash and prepaid cards that you put in after deducting the rest of the rented amount will be returned. ing. In addition, the loan balance display unit 363 displays the remaining number of cash and prepaid cards inserted into the ball lending machine.

[4-3. Ball feed unit]
Next, the ball feeding unit 580 will be described. The ball feeding unit 580 can supply the game balls supplied from the upper plate 301 in the plate unit 300 to the hitting ball launching device 650 one by one, and the game balls stored in the upper plate 301 can be used as the upper plate balls. It can be pulled out to the lower dish 302 by operating the upper dish ball pulling button 341 of the pulling mechanism 340.

In the ball feed unit 580, the game ball stored in the upper plate 301 of the plate unit 300 is supplied through the upper plate ball discharge port of the upper plate 301 and the ball feed opening of the door frame base main body 110, and penetrates in the front-rear direction. , And a box-shaped front cover that has a ball outlet that opens under the entrance and is open at the rear, and a box-shaped that closes the rear end of the front cover and is open at the front, penetrating in the front-back direction. Rotates around an axis extending in the front-rear direction between the rear cover having a hitting ball supply port 582a for supplying the game ball invading from the entry port of the front cover to the hitting ball launching device 650, and the rear cover and the front cover. A ball pulling member that is pivotally supported and has a partition portion between the entrance and the ball pulling port on the rear side of the front cover, and a game ball on the partition portion of the ball pulling member are hit by the rear cover one by one. It is provided with a ball feed member rotatably supported around an axis extending in the vertical direction between the front cover and the rear cover to the supply port 582a, and a ball feed solenoid 585 that rotates the ball feed member. There is.

When the ball feeding solenoid 585 is driven (ON state), the ball feeding member accepts one game ball, while when the driving of the ball feeding solenoid 585 is released (OFF state), the ball feeding member accepts it. The game ball is sent (supplied) to the hit ball launching device 650 side.

[4-4. Handle device]
Next, the handle device 500 will be described. The handle device 500 includes a handle base that is fixed to a handle bracket attached to the front surface of the door frame base main body 110 and has a cylindrical shape and a front end that bulges round in the direction perpendicular to the axis, and a handle base that can rotate relative to the handle base. It is placed in front of the rotary handle body front 506, which is fixed to the front of the rotary handle body and fixed to the front of the rotary handle body, and the rotary handle body front 506, which is fixed to the front of the rotary handle body and can rotate integrally with the rotary handle body. It also has a front end cover 508 that is fixed to the handle base and rotatably supports the front 506 of the rotary handle body and the rear of the rotary handle body in cooperation with the handle base.

Further, the handle device 500 is attached and fixed to the center of rotation in front of the rotary handle body so as to project from the front side to the rear side, and is fitted with a shaft member having a non-circular bearing portion at the rear end and a bearing portion of the shaft member. Detection of the potential meter 512, which has a detection shaft portion that can be rotated together and is non-rotatably fitted to the front surface of the handle base, and the potential meter 512, which is fixed to the front surface of the handle base so as to sandwich the potential meter 512 with the handle base. A switch support member having a through hole through which the shaft can pass, a touch switch 516 attached to the rear surface of the switch support member, and a launch stop switch 518 attached to a different position on the rear surface of the switch support member from the touch switch 516. , A single-shot button that is rotatably supported by the switch support member and activates the launch stop switch 518, and is arranged so as to cover the outer periphery of the shaft member. It is equipped with a handle return spring that urges the user to return to the (rotating end in the counterclockwise direction). The potentiometer 512 is for electrically adjusting the strength of launching the game ball toward the game area 1100 according to the rotation position of the rotation handle main body front 506. Further, the front 506 of the rotary handle body and the rear of the rotary handle body rotate from the original rotation position to the limit rotation position (rotation end in the clockwise direction in the front view) which is the maximum rotation position in the clockwise direction in the front view. do.

Further, in the handle device 500, the potentiometer 512 is a variable resistor, and when the front 506 of the rotary handle body and the rear of the rotary handle body are rotated, the detection shaft portion of the potentiometer 512 is rotated via the shaft member. .. Then, the internal resistance of the potential meter 512 changes according to the rotation position (rotation angle) of the detection shaft portion, and the driving force of the firing solenoid 654 in the hitting ball launching device 650 changes according to the internal resistance of the potential meter 512. The game ball is driven into the game area 1100 with a firing strength corresponding to the rotation angle in front of the main body 506 and after the main body of the rotary handle, that is, the rotation position in front of the main body of the rotary handle 506 and after the main body of the rotary handle. There is.

[4-5. Foul cover unit]
Next, the foul cover unit 540 will be described. The foul cover unit 540 is attached to the rear surface below the game window 101 in the door frame base unit 100, and is a game despite being fired by the game ball paid out from the prize ball unit 700 or the hit ball launching device 650. A game ball (foul ball) that has not reached the area 1100 is guided to the upper plate 301 or the lower plate 302 of the plate unit 300. The foul cover unit 540 includes a cover base whose front side is open and which has a plurality of game ball flow paths inside, and a front cover which closes the front end of the cover base.

The cover base of the foul cover unit 540 is arranged in the upper right corner in the rear view and penetrates in the front-rear direction. Inside the one-ball passage, the second ball entrance 542c, which is located outside the first ball entrance 542a (on the right side when viewed from the rear) and is larger than the first ball entrance 542a, and inside the cover base that communicates with the second ball passage. The second ball entrance 542c, which extends downward and is inclined so as to be lowered toward the lower right corner of the front view, is provided. The first ball inlet 542a and the second ball inlet 542c have the normal ball outlet 774 and the full tank outlet 77 of the full tank branch unit 770 in the prize ball unit 700 in a state where the door frame 5 is closed with respect to the main body frame 3. It is formed at a position facing each other. In the second ball passage in the cover base, the height of the portion extending in the left-right direction along the lower end is about three times as high as the outer diameter of the game ball, and a predetermined amount of the game ball can be used. A storage space that can be accommodated is formed.

Further, the cover base 542 communicates with the foul ball inlet 542e, which is arranged in the upper center in the left-right direction and opens upward, and the foul ball inlet 542e, and is capable of guiding the game ball to the upper part near the downstream of the second ball passage. It has a ball passage and. Further, the cover base is provided with an opening / closing actuating piece for operating the opening / closing shutter 792 of the ball outlet opening / closing unit 790 on the rear surface below the second ball entrance. When the door frame 5 is closed with respect to the main body frame 3, the opening / closing actuating piece comes into contact with the spherical contact portion of the opening / closing crank in the ball outlet opening / closing unit 790 to rotate the opening / closing crank to open / close the shutter 792. It can be opened.

The front cover of the foul cover unit 540 is formed in a substantially plate shape that closes the front surface of the cover base. It includes an exit and a second ball outlet that communicates with the downstream end of the second ball passage of the cover base 542 and penetrates in the front-rear direction, which is arranged in the lower right corner of the front view. The first ball outlet of the front cover is connected to the upper plate ball supply port of the plate unit 300 through the notch of the door frame base unit 100. Further, the second ball outlet is connected to the rear end of the lower plate ball supply gutter in the plate unit 300 through the ball passage port of the door frame base main body 110.

The foul cover unit 540 is a dish unit 300 from the first ball outlet through the first ball passage through the game ball supplied from the normal ball outlet 774 of the full tank branch unit 770 in the prize ball unit 700 to the first ball inlet 542a. It can be supplied to the upper plate 301 through the upper plate ball supply port. Further, the foul cover unit 540 allows the game ball supplied from the full tank outlet 767 of the full tank branch unit 770 in the prize ball unit 700 to the second ball inlet 542c from the second ball outlet through the second ball passage. It can be supplied to the lower plate 302 through the lower plate ball supply gutter and the lower plate ball supply port of the plate unit 300.

Further, in the foul cover unit 540, when the door frame 5 is closed with respect to the main body frame 3, the foul ball inlet 542e is located at the lower part of the foul space 626 of the main body frame 3, and the hit ball launching device. When the game ball launched by the 650 does not reach the game area 1100 but becomes a foul ball and falls in the foul space 626, it is received by the foul ball entrance 542e. Then, the foul cover unit 540 may discharge (supply) the game ball received at the foul ball entrance 542e from the second ball outlet to the lower plate 302 of the plate unit 300 through the foul ball passage and the second ball passage. You can do it.

Further, the foul cover unit 540 forms an upstream side (left side in front view) of the accommodation space in the second ball passage, and is oscillated by a game ball stored in the accommodation space and is pivotally supported by the cover base. It includes a member, a full tank switch 550 for detecting the swing of the swing member, and a spring for urging the swing member in a direction in which the swing member is not detected by the full tank switch 550. The lower end of this swing member is rotatably supported with respect to the cover base, and the upper end rotates to the left side when viewed from the front. It is designed to form. Further, the swing member is urged to a position where it is in a substantially vertical state by a spring. Further, the rocking member is formed with a detection piece projecting outward on the side surface opposite to the accommodation space side, and this detection piece is detected by the full tank switch 550. That is, based on the detection signal from the full tank switch 550, it is possible to determine whether or not the game ball in which the accommodation space is stored is full.

[5. Overall configuration of the game board]
Next, the overall configuration of the game board 4 will be described with reference to FIGS. 8 and 9. FIG. 8 is a front view of the game board, and FIG. 9 is an exploded perspective view of the game board of FIG. 8 as viewed from the front. As shown in FIGS. 8 and 9, the gaming board 4 has an outer rail 1111 and an inner rail 1112, and the gaming area 1100 in which a gaming ball as a gaming medium is driven by a player operating the handle device 500. A frame-shaped front component 1110 that forms an outer periphery, and a position that can be visually recognized by the player from the game window 101 of the door frame 5 when attached to the pachinko gaming machine 1 at the lower right corner of the front view of the front component 1110. A function display unit 1180 arranged in the above, and a plurality of openings 1158 attached to the rear side of the front component 1110 so as to close the game area 1100 and penetrating in the front-rear direction at a position corresponding to the game area 1100. It includes a plate-shaped gaming panel 1150, a front unit 2000 attached to the opening 1158 of the gaming panel 1150 from the front side, and a back unit 3000 attached to the rear surface of the gaming panel 1150.

Further, the game board 4 is arranged between the game panel 1150 and the back unit 3000, and is inserted from the rear side of the game panel 1150 into a plurality of light emitting decorative holes formed so as to penetrate the game panel 1150. A liquid crystal display device that can display a predetermined effect image that is detachably attached to the rear side of the panel lens member 2500 and the back unit 3000 and is visible from the player side according to the game state, and the lower part of the back unit 3000. It is provided with a board holder 1160 attached to the lower part of the rear surface of the game panel 1150 so as to cover the game panel 1150 from the rear side, and a main control board box 1170 attached to the rear surface of the board holder 1160.

[5-1. Front component]
Next, the front component 1110 will be described. The outer component 1110 has a substantially rectangular shape that can be inserted into the game board holding port 601 of the main body frame 3, and the inner shape penetrates in a substantially circular shape in the front-rear direction. The outer periphery of the region 1100 is partitioned. The front component 1111 includes an outer rail 1111 extending in an arc shape from the lower end to the left from the center in the left-right direction in a front view, passing through the upper end in the center in the left-right direction in the front view, and extending to the upper right diagonally. The inner rail 1112, which is arranged inside the outer rail 1111 substantially along the outer rail 1111 and extends in an arc shape from the lower center in the left-right direction of the front view to the diagonally upper left side of the front view, and the inner rail 1112 so as to be smoothly continuous from the lower end of the inner rail 1112. The inner peripheral rail 1113 extending in an arc shape to a position below the end (upper end) of the outer rail 1111 along the circumferential direction counterclockwise when viewed from the front, and the end (upper end) and outer rail 1111 of the inner peripheral rail 1113. At the boundary between the abutment portion 1114 where the game ball that has been rolled along the outer rail 1111 and the end (upper end) of the inner rail 1111 can come into contact with the abutment portion 1114, and the boundary portion between the inner rail 1112 and the inner peripheral rail 1113, the game area 1100 From the upper end of the inner rail 1112 so as to close between the out port guide surface 1115 arranged at the lowermost end and lowered toward the rear and the outer rail 1111 rotatably supported by the upper end of the inner rail 1112. It is rotatable only between the closed position extending upward and the open position that rotates in the clockwise direction and opens between the outer rail 1111 and returns to the closed position side. It includes a backflow prevention member 1116 urged by a spring.

Assuming that the game board 4 is attached to the main body frame 3 of the front component 1110, the lower end opening between the outer rail 1111 and the inner rail 1112 is the launch rail 660 in the ball launching device 650 of the main body frame 3 (FIG. 1). It is designed to be located on the extension line of). A space extending in the left-right direction and downward is formed between the lower end of the outer rail 1111 and the upper end of the launch rail 660, and the game ball launched along the launch rail 660 of the hit ball launcher 650 is formed. The space is jumped over, and the lower end opening between the outer rail 1111 and the inner rail 1112 is driven into the space between the outer rail 1111 and the inner rail 1112. The game ball driven between the outer rail 1111 and the inner rail 1112 rolls upward along the outer rail 1111 according to the momentum, and the backflow prevention member 1116 pivotally supported at the upper end of the inner rail 1112. By rotating to the open position side against the urging force, it is possible to invade the game area 1100.

Further, when the game ball is strongly hit by the hit ball launcher 650, the game ball rolled along the outer rail 1111 in the game area 1100 abuts on the abutment portion 1114 provided at the end of the outer rail 1111. When the game ball comes into contact with the abutment portion 1114, the rolling direction of the game ball can be forcibly changed, and the game ball continuously rolls from the outer rail 1111 to the inner rail 1113. It is designed to prevent it from moving. Even if the game ball that has entered (dried) into the game area 1100 tries to return between the outer rail 1111 and the inner rail 1112, the backflow prevention member 1116 returns to the closed position by the urging force before that. As a result, the backflow prevention member 1116 prevents the backflow of the game ball.

Further, if the game ball driven into the game area 1100 is not accepted by the start ports 2101, 1022 of the table unit 2000, the winning openings 2103, 2104, 2201, etc., it flows down to the lower end of the game area 1100. The out port guide surface 1115 at the boundary between the inner rail 1112 and the inner peripheral rail 1113 guides the game panel 1150 to the out port 1151 and discharges the game panel 4 from the out port 1151 to the rear lower side of the game board 4. ..

On the other hand, when the game ball launched from the hit ball launching device 650 cannot enter the game area 1100 beyond the backflow prevention member 1116 at the tip of the inner rail 1112, the outer rail 1111 and the inner rail 1112 are used. A foul space 626 formed between the upper end of the launch rail 660 and the lower end of the outer rail 1111 from the lower end opening between the outer rail 1111 and the inner rail 1112, rolling downward in the opposite direction. (See FIG. 1) will fall and will be accepted by the foul ball inlet 542e (see FIG. 1) of the foul cover unit 540 attached to the door frame 5 located at the bottom of the foul space 626 in the dish unit 300. It is designed to be discharged to the lower plate 302 (see FIG. 7).

A metal plate is attached to the surface of the outer rail 1111 of the front component 1110 to improve the wear resistance due to the rolling of the game ball, and the game ball rolls smoothly. ing. Further, the impact portion 1114 has an elastic body such as rubber or synthetic resin arranged on the surface thereof, and even if the game ball vigorously rolls along the outer rail 1111 and collides with the abutment portion 1114, the impact is alleviated. It is also possible to repel the game ball inward.

Further, the front component 1110 is vertically separated from the left end of the front view and is vertically separated from the pair of positioning recesses 1119 which are recessed from the front to the rear and opened to the left end. A pair of game board stoppers 1120 arranged, a fixed recess 1121 arranged on the left side of the outer rail 1111 on the left side of the front view and opened downward, and the upper side formed in an arc shape and recessed from the front side, and the lower end of the front view. In the vicinity of the left end portion of the above, a notch portion 1122 for a ball passage, which is notched in a rectangular shape extending upward from the lower end in the left-right direction, is provided. The positioning recess 1119 of the front component 1110 is fitted with the positioning member 956 (see FIG. 5) attached to the inside of the side security plate 950 in the main body frame 3, so that the game board holding port 601 (see FIG. 5) is fitted. ), The left end of the front view of the game board 4 can be restricted from moving in the front-rear direction. Further, the game board stopper 1120 can be detachably locked to the game board locking portion of the main body frame base 600 in the main body frame 3, and the game board stopper 1120 can be engaged with the game board. By locking it to the stop portion, it is possible to restrict the right end of the game board 4 inserted into the game board holding port 601 of the main body frame 3 from moving in the front-rear direction.

Further, the fixing recess 1121 of the front component 1110 is a game board fixing tool 690 (FIG. 5) pivotally supported on the front surface of the main body frame 3 with the game board 4 inserted into the game board holding port 601 of the main body frame 3. (See) is rotated clockwise in front view to insert the fixing piece 690a (see FIG. 5) of the game board fixative 690, and the game board 4 by the game board fixative 690. The lower end of the is restricted from moving forward. Further, in the ball passage notch 1122 of the front component 1110, a similar ball passage notch 1152 is formed at the same position of the game panel 1150, and the game board 4 is used as the game board holding port 601 of the main body frame 3. In the state of being inserted into, the front end of the full tank branch unit 770 (see FIG. 5) is inserted into the notch 1122, 1152 for the ball passage.

A function display unit 1180, which will be described later, is arranged at the lower right of the front view of the front component 1110.

[5-2. Table unit]
Next, the table unit 2000 of the game board 4 will be described. The table unit 200 is arranged above the out port 1151 at the lower center in the left-right direction in the game area 1100 and is supported on the front surface of the game panel 1150, and the outer periphery of the game area 1100 on the left side of the attacker unit 2100. A side winning opening member 2200 arranged along the above and supported on the front surface of the game panel 1150, and a frame-shaped center accessory 2300 arranged along a substantially central portion of the game area 1100 and supported by the game panel 1150. There is.

The table unit 2000 is inserted from the front side into the opening 1158 formed at a position corresponding to the game area 1100 in the game panel 1150, and is attached to the front surface of the game panel 1150. The portion protruding forward from the game panel 1150 is located within the game area 1100. As a result, the front unit 2000 comes into contact with the game ball driven into the game area 1100 at an appropriate position, and with respect to the movement of the game ball together with the obstacle nails planted on the front surface of the game panel 1150. It is possible to give a change. Further, the table unit 2000 can decorate the inside of the game area 1100.

[5-2-1. Attacker unit]
Next, the attacker unit 2100 of the table unit 2000 will be described. The attacker unit 2100 has a plurality of entrances (winning openings) in which a game ball driven into the game area 1100 can be received, and specifically, the attacker unit 2100 is arranged substantially in the center in the left-right direction. A rectangle that is located below the starting port 2101, the lower starting port 2102 located below the upper starting port 2101, and is located below the lower starting port 2102, and extends significantly in the left-right direction from the upper starting port 2101 and the lower starting port 2102. It is provided with a large winning opening 2103 having a shape and a general winning opening 2104 arranged slightly above the left and right sides of the large winning opening 2103. The game balls accepted by the upper starting port 2101, the lower starting port 2102, the large winning opening 2103, and the general winning opening 2104 are guided from the front side to the rear side of the game panel 1150.

The upper start port 2101 of the attacker unit 2100 is open on the upper side so that a game ball can always be accepted (winning). On the other hand, the lower start port 2102 arranged below the upper start port 2101 has a pair of movable pieces 2106 that can be expanded by the start port solenoid 2105 (see FIG. 99) between the upper start port 2101 and the upper start port 2101. In a state where the pair of movable pieces 2106 stands up substantially vertically, the upper starting port 2101 and the pair of movable pieces 2106 make the game ball unacceptable to the lower starting port 2102, whereas the pair of movable pieces are movable. When the piece 2106 is expanded in the left-right direction, the game ball can be accepted into the lower starting port 2102. That is, the lower starting port 2102 is a variable winning opening due to the pair of movable pieces 2106. The pair of movable pieces 2106 are opened and closed by driving the start port solenoid 2105 based on the detection of the passage of the game ball by the gate switch 2352 of the gate portion 2350 in the center accessory 2300 described later.

Further, the large winning opening 2103 of the attacker unit 2100 can be opened and closed by a horizontally long rectangular opening / closing member 2107 whose opening can be closed. The lower side of the opening / closing member 2107 is rotatably supported by the shaft, and in a substantially vertical state, the large winning opening 2103 can be closed to make it difficult to accept the game ball, and the upper side moves to the front side. When it is rotated to, the large winning opening 2103 is opened so that the game ball can be easily accepted. The opening / closing member 2107 is in a state where the large winning opening 2103 is closed in a normal gaming state, and a special lottery is drawn when the game ball is accepted (starting prize) in the upper starting opening 2101 and the lower starting opening 2102. It opens and closes by driving the attacker solenoid 2108 (see FIG. 99) according to the lottery result (when the result of the special lottery is "big hit" or "small hit").

Further, the general winning opening 2104 of the attacker unit 2100 is opened upward so that the game ball can always be accepted (winning).

Further, although detailed illustration is omitted, the attacker unit 2100 has a lower start port switch 2109 that detects a game ball accepted by the lower start port 2102 and a count switch that detects a game ball accepted by the grand prize opening 2103. 2110 is further provided, and the game ball detected by the lower start port switch 2109 and the count switch 2110 is discharged onto the bottom wall portion of the substrate holder 1160. The upper starting port switch 3022 for detecting the game ball accepted by the upper starting port 2101 and the general winning port switch 3020 for detecting the game ball accepted by the general winning opening 2104 are provided in the back unit 3000. ..

[5-2-2. Side winning opening member]
Next, the side winning opening member 2200 of the table unit 2000 will be described. The side winning opening member 2200 was inserted from the front side into the opening 1158 formed on the left side of the opening 1158 in which the attacker unit 2100 is inserted and fixed at the lower part of the game panel 1150 on the left side from the center in the left-right direction. Above, two are fixed to the front of the game panel 1150 and are oriented so as to face each other along the outer periphery of the game area 1100 so as to be aligned with the general winning opening 2104 on the left side of the front view of the attacker unit 2100. It is equipped with a general winning opening 2201. These two general winning openings 2201 are opened upward so that the game ball can always be accepted (winning), and the game ball accepted into the general winning opening 2201 is guided from the front side to the rear side of the game panel 1150. After that, it is detected by the general winning opening switch 3020 provided in the back unit 3000, which will be described later.

Further, the side winning opening member 2200 is arranged at a position where the left end portion is substantially in contact with the outer periphery of the game area 1100 at the upper left end portion thereof, and is inclined so as to be lowered toward the right end portion. The shelf portion 2202 and the first shelf portion 2202 are arranged on opposite sides and lower sides of the two general winning openings 2201 and are located on the left-right center side of the game area 1100 (the lower starting opening 2102 and the large winning opening of the attacker unit 2100). It is provided with a second shelf portion 2203 that becomes lower toward the 2103 side), and the game ball that has flowed down along the outer periphery of the game area 1100 by the first shelf portion 2202 can be moved toward the center side of the game area 1100. You can do it.

The two general winning openings 2201 are arranged on the right side of the right end of the first shelf portion 2202, and even if the game ball is moved to the center side of the game area 1100 by the first shelf portion 2202, There is a possibility of winning a prize in the general winning opening 2201. Further, a third shelf portion 2204 inclined so as to be lowered toward the center side of the game area 1100 is also provided on the upper side between the two general winning openings 2201.

The side winning opening member 2200 is formed so as to have translucency as a whole, and although detailed illustration is omitted, a side winning opening decorative substrate is provided on the rear side of the second shelf portion 2203. At the same time, the side lamp decorative substrate 3014 in the back unit 3000 described later is arranged behind the side winning opening member 2200, and the side winning opening member 2200 is provided by these side winning opening decorative substrate and the side lamp decorative substrate 3014. Is luminescent and can be decorated.

[5-2-3. Center role]
Next, the center accessory 2300 of the table unit 2000 will be described. The center accessory 2300 is inserted from the front side into an opening 1158 formed so as to penetrate substantially the center of the game panel 1150, and is fixed to the front surface of the game panel 1150. It is formed in a frame shape with a size that occupies most of the area 1100, and the outer peripheral surface on the right side of the front view is arcuate so that a gap slightly larger than the outer diameter of the game ball is formed between the outer peripheral surface and the outer peripheral surface of the game area 1100. In addition to being formed, the outer peripheral surface on the left side is formed on a substantially straight line hanging so as to form a region having a predetermined width from the outer peripheral surface of the game area 1100.

The center accessory 2300 is an upper shelf portion 2301 that is inclined to the left from a position slightly to the right of the center in the left-right direction on the upper outer peripheral surface of the front wall portion located in front of the game panel 1150 so as to be lowered toward the left. When a game ball driven into the upper part of the game area 1100 flows down to the upper shelf portion 2301, it flows down through the left side of the center accessory 2300 and is on the right side of the upper shelf portion 2301. The game ball that has flowed down (invaded) passes to the right of the center accessory 2300 and flows down to the lower part of the game area 1100 at once. In other words, if the game ball is driven so that the game ball invades to the right side of the upper shelf portion 2301 in the center accessory 2300, the chance of enjoying the flow of the game ball is reduced, so that the driving strength of the game ball is reduced. The ball can be adjusted as appropriate, and it is possible to maintain a feeling of tension and suppress the game from becoming a vague game.

Further, the center accessory 2300 has invaded the warp inlet 2302 and the warp inlet 2302 in which the game ball flowing down the game area 1100 can enter the outer peripheral surface on the left side of the front wall portion located on the front side of the game panel 1150. A warp outlet (not shown) that discharges the game ball into the frame, and a center accessory that is released into the game area 1100 above the attacker unit 2100 after rolling the game ball released from the warp outlet in the left-right direction. It mainly includes a stage 2310 formed on the upper surface of the lower side in the frame of the 2300.

Although detailed illustration of the stage 2310 in the center accessory 2300 is omitted, the first stage to which the game ball discharged from the warp outlet is supplied and the game ball arranged in front of the first stage and the game ball from the first stage It is provided with a second stage, which is supplied and is capable of releasing a game ball into the game area 1100. The stage 2310 is formed in a curved surface shape so that the substantially center in the left-right direction is lowered. In addition, a chance entrance 2313 through which a game ball can enter is formed on the rear side of the first stage substantially in the center in the left-right direction, and the game ball that has entered the chance entrance 2313 is a chance on the lowermost front surface of the center accessory 2300. It is designed to be discharged into the game area 1100 from the exit 2314. The chance exit 2314 is arranged directly above the upper starting port 2101 in the attacker unit 2100, and the game ball released from the chance exit 2314 is accepted (winning) by the upper starting port 2101 with a high probability. ing.

The stage 2310 in the center accessory 2300 is formed of a transparent member, and the decorative body arranged below the stage 2310 in the back unit 3000 can be visually recognized from the player side through the stage 2310. It has become.

Further, the center accessory 2300 has a transparent outer peripheral surface on the left side of the front wall portion located on the front side of the game panel 1150, which extends to the left so as to be substantially in contact with the inner rail 1112 above the warp entrance 2302. The arch portion 2315 is further provided. The arch portion 2315 extends in a thin plate shape from a substantially front end of the front wall portion, and forms a space through which a game ball can pass between the arch portion 2315 and the front surface of the game panel 1150. As a result, the game ball that has been driven into the upper part of the game area 1100 and guided to the left of the center accessory 2300 by the upper shelf portion 2301 flows down to the downstream side through the rear side of the arch portion 2315. ..

Further, the center accessory 2300 is provided with a gate portion 2350 for detecting the passage of the game ball near the arch portion 2315 on the outer peripheral surface on the left side of the front wall portion located on the front side of the game panel 1150. The gate portion 2350 detects a gate entrance, which is arranged on the outer peripheral surface on the left side of the front wall portion and above the arch portion 2315 and allows a game ball flowing down the game area 1100 to enter, and a game ball that has entered the gate entrance. The gate switch 2352 and the gate outlet for discharging the game ball detected by the gate switch 2352 from the outer peripheral surface of the front wall portion to the game area 1100 are provided. In the present embodiment, although detailed illustration is omitted, the gate exit of the gate portion 2350 is formed at the same height as the arch portion 2315, and the game ball detected by the gate switch 2352 is an arch. It looks as if the part 2315 was submerged.

[5-3. Panel lens member]
Next, the panel lens member 2500 of the game board 4 will be described. The panel lens member 2500 is formed to penetrate in the front-rear direction in a circular or × shape at a position outside the opening 1158 in which the center accessory 2300 is inserted in the game area 1100 of the game panel 1150. The decorative holes are luminescently decorated. The panel lens member 2500 includes a transparent upper panel lens 2510 corresponding to a plurality of light emitting decorative holes formed on the upper left side on the outer periphery of the center accessory 2300, and a plurality of panels arranged on the rear side of the upper panel lens 2510 on the surface. The upper panel lens substrate on which the LED is mounted, the transparent lower panel lens 2520 corresponding to a plurality of light emitting decorative holes formed on the lower left side on the outer periphery of the center accessory 2300, and the rear side of the lower panel lens 2520 are arranged. It is equipped with a lower panel lens substrate on which a plurality of LEDs are mounted on the surface.

The upper panel lens 2510 and the lower panel lens 2520 in the panel lens member 2500 project forward from the plate-shaped lens base portion and have a plurality of rod-shaped insertion guides having substantially the same shape as the shape of the light emitting decorative hole to be inserted. It has a part. When the insertion light guide portion is inserted into the light emitting decorative hole of the game panel 1150 from the rear side, the tip thereof is formed so as to substantially coincide with the front surface of the game panel 1150, and the game flows down the front surface of the game panel 1150. It is designed to have as little effect on the sphere as possible.

By appropriately emitting the LEDs of the upper panel lens substrate and the lower panel lens substrate, the panel lens member 2500 can illuminate and decorate the area where the gaming ball flows down even if an opaque gaming panel 1150 such as veneer plywood is used. The decoration of the gaming panel 1150, which has never been seen before, can be shown to the player, and the pachinko gaming machine 1 can be made to stand out to be differentiated from other pachinko gaming machines.

[5-4. Back unit]
Next, the back unit 3000 of the game board 4 will be described. The back unit 3000 is attached and fixed to the rear surface of the game panel 1150, and is described as a liquid crystal display device 1900 (hereinafter, "game board side liquid crystal display device 1900") at a position separated from the game panel 1150 to the rear side by a predetermined distance. The back box 3001 that supports the back box 3001, the upper unit 3100 that is arranged above the liquid crystal display device 1900 in the back box 3001, and the character unit that is arranged on the right side of the liquid crystal display device 1900 in the back box 3001. It mainly includes a 3400 and a gear decoration unit 3500 arranged on the left side of the liquid crystal display device 1900 in the back box 3001.

Further, the back unit 3000 is arranged at a position corresponding to the side winning opening member 2200 in the front unit 2000 mounted on the front surface of the game panel 1150 near the lower left front end of the back box 3001, and a plurality of LEDs are mounted on the surface. A game ball attached to the side lamp decorative substrate 3014 and the lower front end of the back box 3001 and accepted by the general winning opening 2201 of the side winning opening member 2200, and a game accepted by the general winning opening 2104 on the left side of the attacker unit 2100. The left guiding member 3016 that guides the ball downward, and the right that guides the game ball that is arranged on the right side of the left guiding member 3016 and is accepted to the upper starting port 2101 and the general winning opening 2104 on the right side of the attacker unit 2100. It mainly includes a guide member 3018.

Further, although detailed illustration is omitted, the back unit 3000 is arranged in the lower rear side of the back box 3001 and accommodates the lamp drive board 4170, and is below the horizontally long rectangular lamp drive board box 3423 and the lamp drive board box 3423. The horizontally long rectangular motor drive board box 3430 arranged on the side and accommodating the motor drive board 4180, and the lamp drive board box 3423 and the motor drive board box 3430 fixed to the rear side of the back box 3001 and arranged on the left side in the rear view. A panel relay terminal plate 4161, a horizontally long rectangular upper resistance board arranged on the rear upper part of the back box 3001, and a lock member attached to the rear side of the back box 3001 to hold the liquid crystal display device 1900 detachably. , Is further equipped.

In the present embodiment, the back unit 3000 can be visually recognized from the player side through the frame of the center accessory 2300 in the front unit 2000, and the units 3100 and 3400 are shaped into a predetermined shape. , 3500, etc. can be used to characterize the concept of the pachinko gaming machine 1. Further, in the back unit 3000, each unit 3100, 3400, and 3500 can move independently or in cooperation with each other according to the game state, and the movement causes the player to change the game state. It is possible to suggest the arrival of a chance or the like, and it is possible to entertain the player.

[5-4-1. Back box]
Next, the back box 3001 of the back unit 3000 will be described. The back box 3001 is formed in a box shape with the front side open, and is provided with a plurality of flange-shaped fixing portions 3001a protruding outward at the front end, and is provided on the rear side of the game panel 1150 via the fixing portions 3001a. It is designed to be fixed. Further, the back box 3001 has a rectangular opening formed substantially in the center of the rear wall, and the liquid crystal display device 1900 supported on the rear side through this opening can be visually recognized from the player side. Further, the back box 3001 is formed with mounting portions for mounting and fixing the units 3100, 3400, 3500, the boards 3014, and the like at appropriate positions.

Further, although not shown, the back box 3001 inserts and locks a fixed piece 1902 on the right side of the opening in the rear view, which protrudes outward from both the left and right sides of the liquid crystal display device 1900 (the right side in the rear view). Along with having a liquid crystal support, a lock member is attached to the left side when viewed from the rear of the opening. The display device 1900 is detachably attached to the rear side of the back box 3001.

[5-4-2. Guidance member]
Next, the left guide member 3016 and the right guide member 3018 will be described. The left guide member 3016 guides and discharges the game ball received into the general winning opening 2201 of the side winning opening member 2200 and the general winning opening 2104 on the left side of the attacker unit 2100 through different flow paths. Each flow path is provided with a general winning opening switch 3020 for detecting the passage of a game ball. On the other hand, the right guiding member 3018 guides and discharges the game balls received by the upper starting port 2101 of the attacker unit 2100 and the general winning opening 2104 on the right side through different flow paths up to the vicinity of the lower end. The flow path corresponding to the upper starting port 2101 is provided with the upper starting port switch 3022, and the flow path corresponding to the general winning opening 2104 on the right side is provided with the general winning port switch 3020. Further, the right guide member 3018 is provided with a magnetic detection switch 3024 capable of detecting magnetism.

The game balls guided downward by the left guide member 3016 and the right guide member 3018 are discharged onto the bottom wall portion of the board holder 1160, and are discharged downward from the out ball discharge portion 1161 of the board holder 1160 to the lower side of the game board 4. It has become so.

[5-4-3. Upper unit]
Next, the upper unit 3100 will be described. The upper unit 3100 is formed horizontally as a whole, and is attached and fixed to the upper side of the opening facing the liquid crystal display device 1900 in the back box 3001. The upper unit 3100 is arranged in the front in the substantially center in the left-right direction and has a circular shape in front view. Mainly provided with 3250, a swinging decorative unit 3300 arranged substantially in the center in the left-right direction on the rear side of the elevating mechanism 3250, and movable ceiling units 3350 arranged on both left and right sides of the swinging decorative unit 3300. ing.

The rotary decorative unit 3200 can be moved in the vertical direction between the ascending position located at the upper part of the liquid crystal display device 1900 and the descending position located at substantially the center of the liquid crystal display device 1900 by the elevating mechanism 3250. It has become. In the rotating decoration unit 3200, the rotating decoration formed in the shape of a shuriken arranged on the front surface is rotated, and the rotation radius of the rotating decoration is expanded by the centrifugal force. It has become like.

Further, in the rotating decoration unit 3200, not only the rotating decoration rotates at the end but also the rotating decoration unit protrudes outward in the radial direction, so that the turning radius of the entire rotating decoration body is expanded and the appearance is greatly changed. It is possible to make the player have a strong impact, entertain the player, suppress the decline in the interest in the game, and strongly attract the interest of the player. This makes it easier to select the pachinko gaming machine 1 as a pachinko gaming machine that is greatly differentiated from other pachinko gaming machines.

The swinging decoration unit 3300 is provided with swinging decorations arranged on the left and right sides of the rear side so as to be adjacent to the rotating decoration unit 3200 located at the raised position, and the swinging decorations on the left and right are arranged according to the gaming state. The body can be swung in the left-right direction all at once.

The movable ceiling unit 3350 is provided with a plate-shaped ceiling decoration body extending in the horizontal direction at both left and right ends of the upper unit 3100. The ceiling decoration is rotatably formed around an axis extending in the left-right direction around the front end side, and the rear end side of the ceiling decoration rotates in the descending direction according to the gaming state. It has become.

[5-4-4. Character unit]
Next, the character unit 3400 of the back unit 3000 will be described. The character unit 3400 is provided with a character body that is modeled and three-dimensionally shaped as a ninja, and the character body moves from the rightmost position to the position closer to the center side in the left-right direction according to the game state. Can be done. Further, when the character body of the character unit 3400 moves in the left-right direction, the character body rotates by a predetermined angle around an axis extending in the up-down direction with the movement.

In addition, the character body of the character unit 3400 can reciprocate around an axis whose head extends in the left-right direction, and reciprocates around an axis whose right arm extends in the vertical direction. Can be done. As a result, by reciprocating the head, it is possible to make the character move as if it were nodding. In addition, by rotating the right arm back and forth in the horizontal direction, it is possible to make the character act as if he were throwing a shuriken.

[5-4-5. Gear decoration unit]
Next, the gear decoration unit 3500 of the back unit 3000 will be described. The gear decoration unit 3500 includes gear-shaped gear decorations that are rotatable around an axis extending in the left-right direction and are arranged in a plurality of vertical directions, and the gear decorations are simultaneously arranged according to the game state. It is designed to rotate.

[5-4-6. Liquid crystal display device]
Next, the liquid crystal display device 1900 of the game board 4 will be described. The liquid crystal display device 1900 is detachably attached to the rear surface of the back box 3001 of the back unit 3000, and can display a predetermined effect image according to the gaming state. The liquid crystal display device 1900 includes a fixed piece 1902 protruding outward from both the left and right sides, and can be attached to the back box 3001 via the fixed piece 1902.

Further, although detailed illustration is omitted, the liquid crystal display device 1900 includes a peripheral substrate box 1905 accommodating a peripheral control substrate 4140 on the rear side thereof.

[6. Function display unit]
Next, the function display unit 1180 in the game board 4 will be described with reference to FIG. The function display unit 1180 is attached and arranged at a predetermined position of the front component member 1110. FIG. 10 is an enlarged front view showing a function display unit in a gaming board in a state of being attached to a pachinko gaming machine.

As shown in an enlarged manner in FIG. 10, the function display unit 1180 is a game state display including one LED for displaying a game state changed by a game ball driven into the game area 1100 at the left end portion of the front view. It consists of a device 1183 and two LEDs arranged in the vertical direction on the right side of the game status display 1183. The upper special symbol, which is located on the right side of the special symbol storage display 1184 and consists of one 7-segment LED for displaying the first special lottery result drawn by accepting the game ball to the upper start port 2101 as the first special symbol. One 7 for displaying the result of the second special lottery, which is arranged diagonally above the right of the display 1185 and the upper special symbol display 1185 and is drawn by accepting the game ball to the lower starting port 2102, as the second special symbol. The lower special symbol display 1186 consisting of segment LEDs and the lower special symbol display 1186 consisting of two LEDs arranged in the vertical direction on the right side to display the number of holdings related to the acceptance of the game ball to the lower starting port 2102. It is equipped with a special symbol storage display 1187.

The display unit 1181 of the function display unit 1180 is arranged side by side in an arc shape substantially along the inner peripheral rail 1113 from directly above the lower special symbol display 1186 to display the number of holdings related to the passage of the gate unit 2350 by the game ball. The normal symbol storage display 1188 consisting of the four LEDs of the above, and the normal symbol lottery result that is arranged under the normal symbol storage display and the game ball passes through the gate portion 2350 to display the normal symbol as a normal symbol. The normal symbol display 1189 consisting of one LED and the normal symbol storage display 1188 are arranged side by side on the diagonally upper right side, and when the first special lottery result or the second special lottery result is a "big hit", the big winning opening 2103 is opened and closed. It includes a round display 1190 composed of two LEDs for displaying the number of times the pattern is repeated (the number of rounds).

The game status display 1183 is a full-color LED capable of changing the emission color of red, green, and orange, and various gaming states (depending on the combination of the emission color and lighting / blinking). For example, it is possible to display a probability fluctuation state, a time reduction state, a probability change time reduction state, a big hit game state, a small hit game state, etc.).

The upper special symbol storage display 1184 suspends the start of the variable display when the game ball is accepted by the upper start opening 2101 when the first special symbol cannot be variablely displayed on the upper special symbol display 1185. The number of reserved first special symbols (stored) is displayed. Further, the special symbol storage display 1184 has a first special symbol storage lamp 1184a composed of a predetermined LED and a first special symbol storage lamp 1184b, and the first special symbol storage lamps 1184a and 1184b are turned on. The number of holds can be displayed by the blinking pattern. Specifically, for example, when the number of holdings is one, the first special symbol storage lamp 1184a is turned on and the first special symbol storage lamp 1184b is turned off, and when the number of holdings is two, the first special symbol storage lamps 1184a, 1184b are turned on. 1184a blinks and the first special symbol storage lamp 1184b lights up when the number of holdings is three, and the first special symbol storage lamps 1184a and 1184b both light when the number of holdings is four. It is designed to blink. In this embodiment, up to four are reserved.

The lower special symbol storage display 1187 suspends the start of the variable display when the game ball is accepted by the lower start opening 2102 when the lower special symbol display 1186 cannot display the second special symbol in a variable manner ( It displays the number of reserved second special symbols (stored). The lower special symbol storage display 1187 has a second special symbol storage lamp 1187a and a second special symbol storage lamp 1187b made of predetermined LEDs, and the second special symbol storage lamps 1187a and 1187b are turned on. The number of holds can be displayed by the blinking pattern. Specifically, for example, when the number of holdings is one, the second special symbol storage lamp 1187a is turned on and the second special symbol storage lamp 1187b is turned off, and when the number of holdings is two, the second special symbol storage indicator lamp 1187a, When 1187b is lit together, the second special symbol storage lamp 1187a blinks and the second special symbol storage lamp 1187b is lit when the number of holdings is three, and when the number of holdings is four, the second special symbol storage lamps 1187a and 1187b are lit. Both are designed to blink. In this embodiment, up to four are reserved.

The upper special symbol display 1185 and the lower special symbol display 1186 display the first special lottery result and the second special lottery result drawn by accepting the game ball to the upper start opening 2101 and the lower start opening 2102. The 7-segment LED is stopped after fluctuating for a predetermined time according to the special lottery result, and the first special lottery result and the second special lottery result are played by the light emission pattern (special symbol) of the stopped 7-segment LED. It is designed to be recognized by the person.

The ordinary symbol display 1189 is a full-color LED that can change the emission color of red, green, and orange, and the gate portion 2350 is played by combining the emission color and lighting / blinking. It is possible to display the result of a normal lottery that is drawn by passing a ball. As with the special symbol, the display of the normal symbol by the normal symbol display 1189 is also stopped and displayed in a light emission pattern corresponding to the normal lottery result after the display is varied for a predetermined time.

In the normal symbol storage display 1188, when the game ball passes through the gate portion 2350 when the normal symbol cannot be variablely displayed on the normal symbol display 1189, the start of the variable display is suspended (stored). It displays the number of holds (the number of memories) of. This ordinary symbol storage display 1188 includes four ordinary symbol storage lamps 1188a to 1188d arranged side by side from the bottom, each of which is a predetermined LED, and the ordinary symbol storage lamps 1188a are arranged from the bottom according to the number of holdings. By sequentially lighting up to 1188d, the number of reserved symbols can be displayed. In this embodiment, up to four variable displays of ordinary symbols are reserved (stored).

The round indicator 1190 includes a two-round indicator lamp 1190a and a fifteen-round indicator lamp 1190b composed of predetermined LEDs, and each lamp can be turned on to display the number of rounds in a "big hit" game. It has become like.

Further, as shown in FIG. 10, the function display unit 1180 can be visually recognized from the player side through the game window 101 of the door frame 5 in a state where the game board 4 is attached to the pachinko gaming machine 1. There is. Game status display 1183, upper special symbol storage display 1184, upper special symbol display 1185, lower special symbol display 1186, lower special symbol storage display 1187, normal symbol storage display 1188, normal symbol display 1189, and The round display 1190 is attached to the front surface of the function display board 1191. A connection terminal for connecting the function display board 1191 and the main control board 4100 is attached to the rear end of the rear protrusion of the function display unit 1180.

In the present embodiment, since the function display unit 1180 is provided in the front component 1110 of the gaming board 4, compared with the case where the front unit 2000 and the back unit 3000 attached to the gaming panel 1150 are provided. The function display unit 1180 can be diverted as the basic configuration of the gaming board 4, the configuration related to the pachinko gaming machine 1 can be simplified to prevent the cost from increasing, and the model of the pachinko gaming machine 1 (table). Even if the detailed configuration of the gaming board 4, which is embodied by the unit 2000 and the back unit 3000 and can characterize the model of the pachinko gaming machine 1, is different, the position of the function display unit 1180 does not change, so that the player and the game The position of the function display unit 1180 can be recognized by a clerk in the hall without any confusion.

[7. Main control board, payout control board and peripheral control board]
Next, a control board that performs various controls of the pachinko gaming machine 1 will be described with reference to FIGS. 11 to 16. 11 is a block diagram of a main control board, a payout control board, and a peripheral control board, FIG. 12 is a block diagram showing a continuation of FIG. 11, and FIG. 13 is a payout control board, a CR unit, and a frequency constituting the main board. FIG. 14 is a schematic diagram of various detection signals input / output to / from a game ball rental device connection terminal board that relays an electrical connection with a display board, FIG. 14 is a block diagram showing a continuation of FIG. 11, and FIG. 15 is a block diagram. It is a block diagram which shows the outline of a peripheral control MPU, and FIG. 16 is a block diagram around a VDP with a built-in sound source in a liquid crystal and a sound control unit.

As shown in FIG. 11, the control configuration of the pachinko gaming machine 1 is mainly composed of a main control board 4100, a payout control board 4110, and a peripheral control board 4140, and various controls are shared. First, the main control board will be described, and then the payout control board, the power supply board, and the peripheral control board will be described.

[7-1. Main control board]
As shown in FIG. 11, the main control board 4100 that controls the progress of the game controls the power-on processing executed at the time of turning on the power, and is executed after a predetermined time has elapsed from the time of turning on the power, and also performs the game operation. The main control MPU4100a, which is a microprocessor with a built-in ROM for storing various control programs such as the main control program to be controlled, a ROM for storing various commands, and a RAM for temporarily storing data, and detection signals from various detection switches are input. Main control input circuit 4100b, main control output circuit 4100c for outputting various signals to an external board, etc., main control solenoid drive circuit 4100d for driving various solenoids, and a predetermined voltage power failure or momentary It is mainly equipped with a power failure monitoring circuit 4100e that monitors signs of stoppage.

In addition to the built-in RAM (hereinafter, referred to as "main control built-in RAM") and the built-in ROM (hereinafter, referred to as "main control built-in ROM") of the main control MPU4100a. It also has a built-in watchdog timer that monitors its operation (system) and a function to prevent fraud.

Further, the main control MPU4100a has a built-in non-volatile RAM. In this non-volatile RAM, a unique ID code with a unique code (a code that exists only one in the world) for identifying an individual by the manufacturer of the main control MPU4100a is stored in advance. Since the ID code once attached is stored in the non-volatile RAM, it cannot be rewritten even by using an external device. The main control MPU4100a can take out the ID code from the non-volatile RAM and refer to it.

The main control input circuit 4100b is not provided with a reset terminal for forcibly resetting the information input by the detection signals from the various detection switches to the various input terminals, and does not have a reset function. Therefore, the main control input circuit 4100b is configured as a circuit in which the system reset signal from the main control system reset described later is not input. That is, in the main control input circuit 4100b, the information based on the detection signals from the various detection switches input to the various input terminals is not reset by the main control system reset described later, so that various signals based on the information are various. It is configured as a circuit that is output from the output terminal.

The main control output circuit 4100c is configured as an open collector output type in which the emitter terminal is grounded to ground (GND), and various signals for outputting various signals to an external board or the like are input to the various input terminals. Main control output circuit 4100ca with reset function equipped with a reset terminal for forcibly resetting the input information, and main control output circuit 4100cc without reset function without reset terminal. And, it is composed of. The main control output circuit 4100ca with a reset function is configured as a circuit to which a system reset signal from the main control system reset described later is input. That is, the main control output circuit 4100ca with a reset function is reset by the main control system reset described later, so that the information for outputting various signals input to the various input terminals to an external board or the like is reset. It is configured as a circuit in which signals based on the above are not output from the various output terminals at all. On the other hand, the main control output circuit 4100cc without a reset function is configured as a circuit in which a system reset signal from a main control system reset, which will be described later, is not input. That is, the main control output circuit 4100cc without a reset function is converted to the information because the information for outputting various signals input to the various input terminals to an external board or the like is not reset by the main control system reset described later. It is configured as a circuit in which the based signal is output from its various output terminals.

The upper start port switch 3022 for detecting the game ball entering the upper start port 2101, the lower start port switch 2109 for detecting the game ball entering the lower start port 2102, and the general winning opening 2104 shown in FIG. The detection signal from the general winning opening switch 3020 for detecting the entered game ball and the signal from the power failure monitoring circuit 4100e are input to the input terminal of the predetermined input port of the main control MPU 4100a via the main control input circuit 4100b. There is. Further, as shown in FIG. 8, the gate switch 2352 for detecting the game ball passing through the gate portion 2350, the general winning opening switch 3020 for detecting the game ball entering the general winning opening 2201, and the large winning opening 2103 are entered. The detection signals from the count switch 2110 that detects the game ball and the magnetic detection switch 3024 that is attached to the back unit 3000 shown in FIG. 9 and detects fraudulent activity using a magnet are relayed to the panel attached to the game board 4. It is input to the input terminal of the predetermined input port of the main control MPU 4100a via the terminal plate 4161 and the main control input circuit 4100b.

The main control MPU 4100a is a main control output circuit with a reset function by outputting a drive signal from the output terminal of the predetermined output port to the main control output circuit 4100ca with a reset function based on the detection signals from each of these switches. A control signal is output from the 4100ca to the main control solenoid drive circuit 4100d, and a drive signal is output from the main control solenoid drive circuit 4100d to the start port solenoid 2105 and the attacker solenoid 2108 via the panel relay terminal plate 4161, or a predetermined output thereof. By outputting a drive signal from the output terminal of the port to the main control output circuit 4100ca with a reset function, the upper special symbol display is displayed from the main control output circuit 4100ca with a reset function via the panel relay terminal board 4161 and the function display board 1191. 1185, lower special symbol display 1186, upper special symbol storage display 1184, lower special symbol storage display 1187, normal symbol display 1189, normal symbol storage display 1188, game status display 1183, and round display 1190 It outputs a drive signal.

Further, the main control MPU 4100a outputs various information (game information) related to the game from the output terminal of the predetermined output port to the main control output circuit 4100ca with a reset function, thereby controlling the payout from the main control output circuit 4100ca with a reset function. Main control output with reset function by outputting various information (game information) to the board 4110 and outputting a signal (power failure clear signal) to the main control output circuit 4100ca with reset function from the output terminal of the predetermined output port. A signal (power failure clear signal) is output from the circuit 4100ca to the power failure monitoring circuit 4100e.

In this embodiment, the upper start port switch 3022, the lower start port switch 2109, the gate switch 2352, and the count switch 2110 use a non-contact type electromagnetic proximity switch, whereas they are generally used. A contact type ON / OFF operation type mechanical switch is used for the winning opening switches 3020 and 3020. This is because the game ball frequently enters the upper start port 2101 and the lower start port 2102 and frequently passes through the gate portion 2350, so that the upper start port switch 3022, the lower start port switch 2109, and the gate switch 2352 are used. The detection of game balls also occurs frequently. Therefore, a proximity switch having a long life is used for the upper start port switch 3022, the lower start port switch 2109, and the gate switch 2352. Further, when a big hit game state that is advantageous to the player occurs, the big winning opening 2103 is opened and the game ball frequently enters, so that the game ball is frequently detected by the count switch 2110. Therefore, the count switch 2110 also uses a proximity switch having a long life. On the other hand, in the general winning openings 2104 and 2201 where the game ball does not enter frequently, the detection by the general winning opening switches 3020 and 3020 does not occur frequently. For this reason, mechanical switches having a shorter life than proximity switches are used for the general winning opening switches 3020 and 3020.

Further, the main control MPU 4100a sends various commands related to payout as serial data from the output terminal of the predetermined serial output port to the main control output circuit 4100 cab without a reset function, thereby controlling the payout from the main control output circuit 4100 cc without a reset function. Various commands are transmitted as serial data to the board 4110. When the payout control board 4110 normally completes receiving various commands from the main control board 4100 as serial data, the payout control board 4110 outputs a signal (payer ACK signal) to that effect to the main control board 4100. This signal (payer ACK signal) is input to the input terminal of the predetermined input port of the main control MPU 4100a via the main control input circuit 4100b.

Further, the main control MPU 4100a receives various commands related to the state of the pachinko gaming machine 1 from the payout control board 4110 as serial data in the main control input circuit 4100b, so that the main control input circuit 4100b can be used for the predetermined serial input port. Receive various commands as serial data at the input terminal. When the main control MPU4100a normally receives various commands from the payout control board 4110 as serial data, the main control output with a reset function outputs a signal (main payment ACK signal) to that effect from the output terminal of the predetermined output port. It is output to the circuit 4100ca, and a signal (main payment ACK signal) is output from the main control output circuit 4100ca with a reset function to the payout control board 4110.

Further, the main control MPU 4100a transmits various commands related to the control of the game effect and various commands related to the state of the pachinko gaming machine 1 as serial data from the output terminal of the predetermined serial output port to the main control output circuit 4100 kb without the reset function. As a result, various commands are transmitted as serial data from the main control output circuit 4100cc without the reset function to the peripheral control board 4140.

Here, the main peripheral serial transmission port that transmits various commands as serial data to the peripheral control board 4140 will be briefly described. The main control MPU 4100a is configured around the main control CPU core 4100aa, and in addition to the main control built-in RAM, the main peripheral serial transmission port 4100ae, which is one of the main control various serial I / O ports, provides a bus 4100ah. Circuits are connected via (see FIG. 24). The main peripheral serial transmission port 4100ae transmits various commands to the peripheral control board 4140 as main peripheral serial data, and is mainly composed of a transmission shift register 4100aea, a transmission buffer register 4100aeb, a serial management unit 4100aec, and the like (FIG. FIG. 24). When the main control CPU core 4100aa sets a command in the transmission buffer register 4100aeb and outputs a transmission start signal to the serial management unit 4100aec, the serial management unit 4100aec issues a command set in the transmission buffer register 4100aeb from the transmission buffer register 4100aeb. The data is transferred to the transmission shift register 4100ea and transmission is started to the peripheral control board 4140 as main peripheral serial data. In the present embodiment, the transmission buffer register 4100aeb has 32 bytes as a storage capacity. The main control CPU core 4100aa continuously transmits a plurality of commands to the peripheral control board 4140 by outputting a transmission start signal to the serial management unit 4100aec after setting a plurality of commands in the transmission buffer register 4100aeb.

The power supply board 851 that supplies various voltages to the main control board 4100 is an electric double layer capacitor (hereinafter, simply "capacitor") as a backup power source for supplying power to the main control board 4100 for a predetermined time even when the power is cut off. It is provided with BC0 (see FIG. 20). The capacitor BC0 allows the main control MPU4100a to store various information in the main control built-in RAM in the power off processing even when the power is cut off. Various information stored in the main control built-in RAM is an operation signal (RAM clear signal) from the operation switch 860a when the operation switch 860a of the payout control board 4110 described later is operated within a predetermined period from the time when the power is turned on. Is output from the payout control board 4110 and is input to the input terminal of the predetermined input port of the main control MPU 4100a via the main control input circuit 4100b. It is supposed to be (cleared).

[7-2. Payout control board]
As shown in FIG. 12, the payout control board 4110 that controls payout of game balls and the like has a payout control unit 4120 that performs various controls related to payout, an operation switch 860a that also has various functions, and a state of the pachinko gaming machine 1. It is equipped with an error LED display 860b for displaying. Further, the operation switch 860a having a function as a RAM clear switch is described as a RAM built in the main control MPU 4100a (hereinafter, referred to as "main control built-in RAM") based on a detection signal output by the operation. .) Outputs a RAM clear signal for completely erasing the information stored in.

[7-2-1. Payout control unit]
As shown in FIG. 12, the payout control unit 4120 that performs various controls related to payout controls the power-on process executed when the power is turned on, and pays out the game medium executed after a predetermined time has elapsed from the time when the power is turned on. Detection from the payout control MPU4120a, which is a microprocessor with a built-in ROM that stores various control programs including payout control programs that control operations, a ROM that stores various commands, and a RAM that temporarily stores data, and various detection switches related to payout. The drive signal is output to the payout control input circuit 4120b to which the signal is input, the payout control output circuit 4120c for outputting various signals to an external board or the like, and the payout motor 744 of the prize ball device 740 shown in FIG. It is provided with a payout motor drive circuit 4120d for the purpose and a CR unit input / output circuit 4120e for exchanging various signals with the CR unit 6. The payout control MPU4120a includes a built-in RAM (hereinafter referred to as "payout control built-in RAM"), a built-in ROM thereof (hereinafter referred to as "payout control built-in ROM"), and the like. It also has a built-in watchdog timer that monitors its operation (system) and a function to prevent fraud.

Under the control of the payout control MPU4120a, the payout control program outputs various information (game information) related to the game from the main control board 4100 and various commands related to the payout as payer serial data transmission signals via the payout control I / O port 4120b. Receive serial data in a serial manner. Further, the payout control program generates a frame state 1 command (corresponding to the first error occurrence command) when an error occurs in the payout operation of the game ball, or operates the operation switch 860a as an error canceling unit. A 16-bit (2-byte) error cancellation navigation command (corresponding to the first error cancellation command) is created based on the signal (detection signal), and these error occurrence commands and error cancellation navigation commands are transmitted to the payer serial data, respectively. As a signal, serial data is output to the receiving port of the main control board 4100 via the payout control I / O port 4120b (command transmission means). Further, this payout control program is to be paid out after a predetermined time has elapsed from the time when the power is turned on, that is, after the payout control unit main process is executed or the payout control unit timer interrupt process is executed and the payout control is started. When an error occurs in operation, the error is canceled based on the detection signal generated by the operation of the operation switch 860a, and the output of warning information corresponding to the error is stopped (error cancellation control means).

Further, this payout control program outputs a door frame opening command (first door opening command) when a detection signal (door frame opening detection signal) accompanying the opening operation is input from the door frame opening switch 618. When the detection signal (main body frame opening detection signal) accompanying the opening operation is input from the main body frame opening switch 619, the main body frame opening command (first main body frame opening command) is output. On the other hand, this payout control program issues a door frame closing command (first door frame closing command) when a detection signal (door frame closing detection signal) accompanying the closing operation is input from the door frame opening switch 618. At the same time, when the detection signal (main body frame closing detection signal) accompanying the closing operation is input from the main body frame opening switch 619, the main body frame closing command (first main body frame closing command) is output.

The payout control input circuit 4120b is not provided with a reset terminal for forcibly resetting the information input by the detection signals from the various detection switches to the various input terminals, and does not have the reset function. Therefore, the payout control input circuit 4120b is configured as a circuit in which the system reset signal from the payout control system reset described later is not input. That is, in the payout control input circuit 4120b, the information based on the detection signals from the various detection switches input to the various input terminals is not reset by the payout control system reset described later, so that the various signals based on the information are various. It is configured as a circuit that is output from the output terminal.

The payout control output circuit 4120c is configured as an open collector output type in which the emitter terminal is grounded to ground (GND), and various signals for outputting various signals to an external board or the like are input to the various input terminals. A payout control output circuit 4120ca with a reset function having a reset function provided with a reset terminal for forcibly resetting the input information, and a payout control output circuit 4120cab without a reset function having no reset function without a reset terminal. And, it is composed of. The payout control output circuit 4120ca with a reset function is configured as a circuit to which a system reset signal from the payout control system reset described later is input. That is, the payout control output circuit 4120ca with a reset function has information for outputting various signals input to the various input terminals to an external board or the like by resetting the payout control system reset described later. It is configured as a circuit in which signals based on the above are not output from the various output terminals at all. On the other hand, the payout control output circuit 4120cc without a reset function is configured as a circuit in which the system reset signal from the payout control system reset described later is not input. That is, the payout control output circuit 4120 bb without a reset function is converted to the information because the information for outputting various signals input to the various input terminals to an external board or the like is not reset by the payout control system reset described later. It is configured as a circuit in which the based signal is output from its various output terminals.

The detection signals from the ball-out switch 750 that detects the presence or absence of a game ball in the supply passage of the prize ball device 740 and the counting switch 751 that detects the game ball flowing down in the prize ball passage of the prize ball device 740 are first awarded. It is input to the input terminal of the predetermined input port of the payout control MPU 4120a via the board 754 in the prize ball case of the ball device 740 and the payout control input circuit 4120b. The detection signals from the rotation angle switch 752 for detecting the detection slit formed in the rotation detection board of the prize ball device 740 are, first, the rotation angle switch board 753 of the prize ball device 740, and then the board 754 in the prize ball case. It is input to the input terminal of the predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

Further, the detection signals from the door frame opening switch 618 for detecting the opening of the door frame 5 with respect to the main body frame 3 and the main body frame opening switch 619 for detecting the opening of the main body frame 3 with respect to the outer frame 2 use the payout control input circuit 4120b. It is input to the input terminal of the predetermined input port of the payout control MPU4120a via the payout control MPU4120a.

Further, the detection signal from the full tank switch 550 that detects whether or not the accommodation space of the foul cover unit 540 shown in FIG. 1 is full in the stored game ball is first of the handle relay terminal board 192 and the power supply board. It is input to the input terminal of the predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

The payout control MPU 4120a receives various commands related to payout from the main control board 4100 via the payout control input circuit 4120b at the input terminal of the serial input port in a serial data manner, or receives an operation signal (detection) of the operation switch 860a. The signal) is output to the main control board 4100 via the payout control input circuit 4120b. When the payout control MPU4120a normally receives various commands from the main control board 4100 as serial data, a signal (payer ACK signal) to that effect is sent from the output terminal of the predetermined output port to the payout control output with a reset function. By outputting to the circuit 4120ca, a signal (payer ACK signal) is output from the payout control output circuit 4120ca with a reset function to the main control board 4100.

Further, the payout control MPU 4120a sends various commands for indicating the state of the pachinko gaming machine 1 as serial data from the output terminal of the serial output port to the payout control output circuit 4120 kb without a reset function, thereby paying out without a reset function. Various commands are transmitted as serial data from the control output circuit 4120cc to the main control board 4100. When the main control board 4100 normally completes receiving various commands from the payout control board 4110 as serial data, the main control board 4100 outputs a signal (main payment ACK signal) to that effect to the payout control board 4110. This signal (main payment ACK signal) is input to the input terminal of the predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

Further, the payout control MPU 4120a outputs a drive signal for driving the payout motor 744 to the payout control output circuit 4120ca with a reset function from the output terminal of the predetermined output port, whereby the payout control output circuit 4120ca with a reset function is output. Is output to the payout motor drive circuit 4120d, and the drive signal is output from the payout motor drive circuit 4120d to the payout motor 744 via the board 754 in the prize ball case, or from the output terminal of the predetermined output port of the pachinko machine. By outputting the drive signal for displaying the status of the gaming machine 1 to the error LED display 860b to the payout control output circuit 4120ca with a reset function, the drive signal is output from the payout control output circuit 4120ca with a reset function to the error LED display 860b. Output to.

The error LED display 860b is a segment display, and displays alphanumericals, figures, and the like to display the status of the pachinko gaming machine 1. The contents displayed and notified by the error LED display 860b include the following. For example, when the figure "-" is displayed, it is notified that it is "normal", and when the number "0" is displayed, it means that it is "connection abnormality" (specifically, with the main control board 4100). Notifies that there is an abnormality in the electrical connection between the payout control board 4110 and the board, and when the number "1" is displayed, it means that the ball is out (specifically, the ball is out). Based on the detection signal from the switch 750, it notifies that there is no game ball in the supply passage of the prize ball device 740, and when the number "2" is displayed, it means that the ball is "ball" (specifically). Is that the payout rotating body and the game ball are engaged near the entrance of the distribution space communicating with the supply passage of the prize ball device 740 based on the detection signal from the rotation angle switch 752, and the payout rotating body is difficult to rotate. When the number "3" is displayed, it means that there is a "counting switch error" (specifically, a problem occurs in the counting switch 751 based on the detection signal from the counting switch 751). When the number "5" is displayed, a "retry error" is notified (specifically, the number of retries for the payout operation has reached a preset upper limit). However, when the number "6" is displayed, it means that the tank is "full" (specifically, in a game ball in which the accommodation space of the foul cover unit 540 is stored based on the detection signal from the full tank switch 550. It notifies that the tank is full), and when the number "7" is displayed, it means that "CR is not connected" (the electrical connection is cut off in any of the payout control board 4110 to the CR unit 6). When the number "9" is displayed, it means that the game is in stock (there is a prize ball stock (unpaid)) (specifically, the number of game balls that have not been paid out yet). Has reached a predetermined number of balls).

Further, the payout control MPU 4120a outputs the number of balls of the game ball actually paid out from the output terminal of the predetermined output port to the payout control output circuit 4120ca with a reset function, whereby the payout control output circuit 4120ca with a reset function is output. The number of game balls actually paid out to the external terminal board 784 is output via a resistor (not shown).

Further, the payout control board 4110 outputs various information (game information) related to the game from the main control board 4100 to the external terminal board 784 via a resistor (not shown). The external terminal board 784 is provided with a plurality of photocouplers (which are configured by incorporating an infrared LED and a photo IC) (not shown), and the playground (hall) is provided via the plurality of photocouplers. ), The number of balls of the game ball and various information (game information, error content or error related to the payout operation of the game ball) are transmitted to the hall computer installed in). The external terminal plate 784 and the hall computer are electrically insulated by a plurality of photocouplers, and an abnormal voltage is applied to the hall computer via the external terminal plate 784 of the pachinko gaming machine 1. The hall computer does not malfunction or break down, and the payout control board that controls the payout, etc., and the main control board 4100 that advances the game from the hall computer via the external terminal plate 784 of the pachinko gaming machine 1. An abnormal voltage is applied to the 4110 to prevent malfunction or failure. The hall computer monitors the player's game by grasping the number of game balls paid out by the pachinko game machine 1 and the game information of the pachinko game machine 1.

The ball lending request signal for the game ball from the ball lending switch 365a of the ball lending unit 360 shown in FIG. 2 and the return request signal for the prepaid card from the return switch 365b are, first, the frequency display board 365 and the main door relay terminal board 880. , And it is designed to be input to the CR unit 6 via the game ball or the like rental device connection terminal board 869. The CR unit 6 serially transmits a signal specifying the number of game balls to be rented according to the ball lending request signal to the payout control board 4110 via the game ball lending device connection terminal board 869, and this signal is the CR unit. It is input to the input terminal of a predetermined input port of the payout control MPU 4120a via the input / output circuit 4120e. Further, the CR unit 6 updates the remaining amount of the inserted prepaid card according to the number of balls of the rented game ball, and displays a signal for displaying the remaining amount on the remaining degree display 365c, such as a game ball. It is output to the rental device connection terminal board 869, the main door relay terminal board 880, and the frequency display board 365, and this signal is input to the remaining frequency display 365c. Further, in the CR unit lamp 365d adjacent to the residual frequency display 365c, the supply voltage from the CR unit 6 is input via the game ball rental device connection terminal board 869 and the main door relay terminal board 880. There is.

The power supply board 851 that supplies various voltages to the payout control board 4110 includes a capacitor BC1 (see FIG. 20) as a backup power source for supplying power to the payout control board 4110 for a predetermined time even when the power supply is cut off. There is. With this capacitor BC1, the payout control MPU4120a can store various information in the payout control built-in RAM (payout storage unit) in the power cutoff process even when the power is cut off. When the operation switch 860a is operated within a predetermined period from the time when the power is turned on, the various information stored in the payout control built-in RAM is sent to a predetermined payout control MPU 4120a via the payout control input circuit 4120b. The payout control MPU4120a, which is input to the input terminal of the input port, determines as a RAM clear signal for completely erasing the information stored in the payout control built-in RAM, and is triggered by the payout control MPU4120a from the payout control built-in RAM. It is designed to be completely erased (cleared). This operation signal (RAM clear signal) is also output to the payout control output circuit 4120 cab without a reset function, and is also output to the main control board 4100 from the payout control output circuit 4120 cc without a reset function.

[7-2-2. Exchange of various signals with the terminal board for renting game balls, etc.]
Here, the exchange of various signals between the payout control unit 4120 and the CR unit 6 and the exchange of various signals between the CR unit 6 and the frequency display board 365 will be described with reference to FIG. As shown in FIG. 13, the game ball rental device connection terminal board 869 relays the electrical connection between the CR unit 6 and the payout control board 4110, as well as the CR unit 6 and the frequency display board 365. (To be exact, the game ball rental device connection terminal board 869 is electrically connected to the frequency display board 365 via the main door relay terminal board 880. , The CR unit 6 and the game ball rental device connection terminal board 869 are electrically connected, the game ball rental device connection terminal board 869 and the main door relay terminal board 880 are electrically connected, and the main door relay. The terminal board 880 and the frequency display board 365 are electrically connected). Between the boards of the CR unit 6 and the game ball rental device connection terminal board 869, between the boards of the game ball rental device connection terminal board 869 and the payout control board 4110, the game ball rental device connection terminal board 869 and the main door relay. The boards of the terminal board 880 and the boards of the game ball rental device connection terminal board 869 and the frequency display board 365 are electrically connected by each wiring (harness). Further, AC24V, which will be described later, from the power supply board 851 is supplied to the CR unit 6 via a game ball or the like rental device connection terminal board 869. The CR unit 6 creates a predetermined voltage VL (in this embodiment, DC + 12V (hereinafter referred to as “+ 12V”)) from the supplied AC24V by a built-in voltage creation circuit (not shown) together with the ground LG. , The game ball rental device connection terminal board 869 is supplied to the payout control board 4110, while the game ball rental device connection terminal board 869 and the main door relay terminal board 880 are supplied to the frequency display board 365. ..

The frequency display board 365 has a ball rental switch 365a, which is a push button switch, mounted on the component surface at a position corresponding to the ball rental button 361 of the ball rental unit 360 shown in FIG. 2, and the ball rental unit 360 is returned. A return switch 365b, which is a push button switch, is mounted at a position corresponding to the button 362, and a residual frequency indicator 365c, which is a segment display, is mounted at a position corresponding to the rental balance display unit 363 of the ball rental unit 360.

In the ball rental switch 365a and the return switch 365b, the ground LG from the CR unit 6 is electrically connected via the game ball rental device connection terminal board 869 and the main door relay terminal board 880. When the ball lending switch 365a is pressed, the ball lending switch 365a is switched on (ON), and the ball lending operation signal TDS from the ball lending switch 365a is the main door relay terminal plate 880 and the game. It is designed to be input to the CR unit 6 via the ball rental device connection terminal plate 869. When the return button 362 is pressed, the return switch 365b is switched on (ON), and the return operation signal RES from the return switch 365b is connected to the main door relay terminal board 880 and a game ball rental device. It is designed to be input to the CR unit 6 via the terminal board 869.

The residual frequency indicator 365c has three segment indicators arranged side by side in a row, and three digits are driven by a so-called dynamic lighting method in which one digit segment indicator is sequentially driven among these three digit segment indicators. The segment display of is controlled to be lit. By such lighting control, the remaining frequency display 365c displays the remaining amount of the prepaid card inserted in the CR unit 6 and displays the error of the CR unit 6. The residual frequency display 365c uses the digit signals DG0 to DG2 (three signals in total) for designating the one-digit segment display among the three-digit segment display and the designated one-digit segment display. The segment drive signals SEG-A to SEG-G (7 signals in total) for designating the contents to be turned on and displayed are from the CR unit 6 to the game ball rental device connection terminal board 869 and the main door relay terminal board. When input via 880, the 1-digit segment display is sequentially emitted according to the input digit signals DG0 to DG2 and the segment drive signals SEG-A to SEG-G, and these 3-digit segment indicators are emitted. The contents of the light emitted can be visually recognized through the loan balance display unit 363.

A CR unit lamp 365d is mounted on the frequency display board 365 adjacent to the residual frequency display 365c. In this CR unit lamp 365d, a predetermined voltage VL from the CR unit 6 is input via a game ball or the like rental device connection terminal board 869 and a main door relay terminal board 880. The predetermined voltage VL is input to the CR unit 6 as a ball lending signal TDL through a current limiting resistor mounted on the game ball lending device connection terminal board 869 via the CR unit lamp 365d. The CR unit 6 creates a predetermined voltage VL from AC24V supplied from the power supply board 851 by the built-in voltage creation circuit, and the ball lending switch 365a and the return switch 365b are in a ball lending state in which they are effective. Controls the logic of the ball lending signal TDL to make the CR unit lamp 365d emit light, and this light emission can be visually recognized through the loan balance display unit 363. Further, the segment drive signals SEG-A to SEG-G are input to the residual frequency display 365c through the current limiting resistor mounted on the terminal board 869 for renting a game ball or the like.

In the CR unit 6, the ball lending button 361 is pressed and the ball lending operation signal TDS from the ball lending switch 365a is transmitted from the frequency display board 365 via the main door relay terminal board 880 and the game ball lending device connection terminal board 869. When input, BRDY, which is a ball lending request signal, is output to the payout control board 4110 (payout control MPU4120a) via the game ball or the like lending device connection terminal board 869. Then, the CR unit 6 is a one-time payout operation start request signal for paying out a predetermined number of loaned balls (in this embodiment, 25 balls, which corresponds to an amount of 100 yen) in one payout operation. The BRQ is output to the payout control board 4110 (payout control MPU4120a) via the game ball or the like rental device connection terminal board 869. The payout control board 4110 (payout control MPU4120a) into which BRDY and BRQ are input is a signal for notifying that one payout operation has started or ended, and is used as a game ball or the like rental device connection terminal board 869. PRDY, which is a signal to output to the CR unit 6 or to convey that the payout operation for paying out the ball is possible or impossible, is transmitted to the game ball rental device connection terminal board. It is output to the CR unit 6 via 869. For example, if the hall clerk or the like presets the CR unit 6 so that 200 yen worth of game balls are paid out when the ball rental button 361 is pressed, one payout operation is performed. Is to be performed twice in a row, and if 25 balls for 100 yen are paid out, 25 balls for 100 yen will be paid out in succession, and 50 balls for a total of 200 yen will be paid out. Become.

In the CR unit 6, the return button 362 is pressed and the return operation signal RES from the return switch 365b is input from the frequency display board 365 via the main door relay terminal board 880 and the game ball rental device connection terminal board 869. The prepaid card is ejected from an insertion slot (not shown) and returned. The returned prepaid card stores the remaining amount obtained by subtracting the amount corresponding to the number of balls of the game ball paid out as a result of pressing the ball lending button 361.

[7-3. Power supply board]
Next, the power supply board 851 will be briefly described. The power supply board 851 includes a power supply switch 852 supplied from the pachinko island facility and capable of electrically connecting or electrically disconnecting an alternating current 24 volt (AC24V), and a power supply control unit 855 that generates various power sources. , The launch control unit 857 that controls the launch by the launch solenoid 654 of the ball launching device 650 shown in FIG. 5 and the ball feed control by the ball feed solenoid 585 of the ball feed unit 580 shown in FIG.

[7-3-1. Power control unit]
The power supply control unit 855 improves the power factor of the power factor rectified by the synchronous rectifier circuit 855a and the synchronous rectifier circuit 855a in which the power switch 852 is operated to rectify the AC 24 volt (AC24V) supplied from the Pachinko Island facility. The power factor improvement circuit 855b, the smoothing circuit 855c for smoothing the power with the power factor improved by the power factor improvement circuit 855b, and various alternating currents for supplying the power smoothed by the smoothing circuit 855c to various boards. It is equipped with a power supply creating circuit 855d for creating a power source.

[7-3-2. Launch control unit]
The launch control unit 857 that performs launch control by the launch solenoid 654 and ball feed control by the ball feed solenoid 585 mainly includes a launch control circuit 857a. The launch control circuit 857a includes an operation signal from the potentiometer 512 that electrically adjusts the strength (launch strength) of launching the game ball toward the game area 1100 according to the rotation position of the rotation handle main body front 506 shown in FIG. , The detection signal from the touch switch 516 that detects whether or not the palm or finger is touching the front 506 of the rotary handle body, and whether or not to forcibly stop the launch (launch) of the game ball by the player's will. The detection signal from the launch stop switch 518 to be detected is input via the handle relay terminal board 192. Further, in the launch control circuit 857a, when the CR unit 6 and the game ball rental device connection terminal board 869 are electrically connected, a CR connection signal to that effect is input via the payout control board 4110. ..

The launch control circuit 857a adjusts the drive current for launching (launching) the game ball toward the game area 1100 based on the operation signal from the potentiometer 512, and controls the output to the launch solenoid 654. By outputting a constant current to the ball feed solenoid 585 via the handle relay terminal plate 192, the ball feed member of the ball feed unit 580 throws one game ball stored in the upper plate 301 of the dish unit 300 shown in FIG. It controls to send the game ball received by the ball feeding member to the hitting ball launching device 650 side.

[7-4. Peripheral control board]
As shown in FIG. 14, the peripheral control board 4140 is provided so as to perform effect control based on various commands from the main control board 4100 and to cover the display area of the upper plate side liquid crystal display device 470 shown in FIG. The peripheral control unit 4150 that exchanges control commands and various information (various data) with the touch panel control board 450 that detects and controls the contact state of the capacitive touch panel 480, the liquid crystal display device 1900 on the game board side, and the precision plate side. While controlling the drawing of the liquid crystal display device 470, it controls the sound of music, sound effects, etc. flowing from the speaker housed in the speaker box 820 shown in FIG. 5 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. A liquid crystal display and sound control unit 4160, a real-time clock (hereinafter referred to as "RTC") control unit 4165 that holds calendar information that specifies the date and time information that specifies the hour, minute, and second, and a main body frame. It is provided with a volume adjusting volume 4140a for adjusting the volume of music, sound effects, etc. flowing from the speaker housed in the speaker box 820 provided in 3 and the speaker 130 provided in the door frame 5 by rotating the knob portion. ing.

[7-4-1. Peripheral control unit]
As shown in FIG. 14, the peripheral control unit 4150 that performs the effect control controls the peripheral control MPU4150a as a microprocessor and the power-on processing executed at the time of power-on, and after a predetermined time has elapsed from the time of power-on. From the peripheral control ROM 4150b that stores various control programs such as sub-control programs that are executed and controls the production operation, various data, various control data, and various schedule data, and the VDP4160a with a built-in sound source of the liquid crystal and sound control unit 4160 described later. Peripheral control unit that is executed each time a V-blank signal is input Various information that is continued across the steady processing (for example, schedule data that defines the screen to be drawn on the game board side liquid crystal display device 1900, light emission of various LEDs, etc. Peripheral control RAM 4150c that stores information for managing schedule data that defines the mode, etc., and various information that is continued over days (for example, information for managing the history of occurrence of big hit game states and special Peripheral control SRAM 4150d for storing information for managing various effect flags, and peripheral control external watch dock timer 4150e for monitoring whether peripheral control MPU4150a is operating normally (hereinafter, "peripheral control external"). WDT4150e ”) and.

The peripheral control RAM 4150c can hold the stored contents only for a time when a momentary power failure occurs and the power is immediately restored, and the power is cut off for a long time (when a long-time power interruption occurs). ), The peripheral control SRAM 4150d is supplied with backup power by a large-capacity electrolytic capacitor (hereinafter, referred to as "electrolytic capacitor for SRAM") provided on the power supply board 851. As a result, the stored contents can be retained for about 50 hours. Since the power supply board 851 is provided with the electrolytic capacitor for SRAM, when the gaming board 4 is removed from the pachinko gaming machine 1, the backup power is not supplied to the peripheral control SRAM 4150d. Therefore, the peripheral control SRAM 4150d has stored contents. Can no longer hold and lose its contents.

The peripheral control external WDT4150e is a timer for monitoring whether the system of the peripheral control MPU4150a is out of control, and when the timer is up, it is reset in terms of hardware. That is, when the peripheral control MPU4150a does not output a clear signal for clearing the timer of the peripheral control external WDT4150e to the peripheral control external WDT4150e within a certain period (until the timer is up), the peripheral control MPU4150a is reset. When the peripheral control MPU4150a outputs a clear signal to the peripheral control external WDT4150e within a certain period of time, the timer count of the peripheral control external WDT4150e can be restarted, so that the reset is not applied.

The peripheral control MPU4150a has a plurality of parallel I / O ports, serial I / O ports, etc. built-in, and when various commands from the main control board 4100 are received, each decorative board of the game board 4 is based on these various commands. The game board side light emission data for outputting the lighting signal, blinking signal, or gradation lighting signal to a plurality of LEDs provided in the lamp is transmitted from the serial I / O port for the lamp drive board to the lamp via a peripheral control output circuit (not shown). Serial for motor drive board side motor drive data for transmitting to drive board 4170 and outputting drive signals to electric drive sources such as motors and solenoids that operate various movable bodies provided on game board 4. Door-side motor drive for transmitting from the I / O port to the motor drive board 4180 via the peripheral control output circuit, or for outputting a drive signal to an electrical drive source such as a dial drive motor 414 provided on the door frame 5. Data can be transmitted from the serial I / O port for the frame decorative drive amplifier board motor to the frame decorative drive amplifier board 194 via the peripheral control output circuit, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882, or the door frame. Peripheral control output of light emission data on the door side for outputting lighting signals, blinking signals, or gradation lighting signals to a plurality of LEDs provided on each decorative board of 5 from the serial I / O port for the frame decorative drive amplifier board LED. Control commands for transmitting to the frame decoration drive amplifier board 194 via the circuit, the frame peripheral relay terminal plate 868, and the peripheral door relay terminal plate 882, and for detecting and controlling the contact state of the touch panel 480 (for example, the touch panel 480). A detection control start command for starting the detection control of the contact state, a power saving mode transition command for shifting to the power saving mode, etc.) is issued from the serial I / O port for the touch panel control board via a peripheral control output circuit (not shown). And send it to the touch panel control board 450.

Various commands from the main control board 4100 are input to the serial I / O port for the main control board of the peripheral control MPU 4150a via a peripheral control input circuit (not shown). Further, a detection signal from a rotation detection switch for detecting the rotation (rotation direction) of the dial operation unit 401 and a press detection switch for detecting the operation of the press operation unit 405 provided on the operation unit 400. The detection signal is serialized by a door-side serial transmission circuit (not shown) provided on the frame decoration drive amplifier board 194, and the serialized operation unit detection data is transmitted from the door-side serial transmission circuit to the peripheral door relay terminal board 882 and the frame. It is input to the serial I / O port for detecting the operation unit of the peripheral control MPU4150a via the peripheral relay terminal board 868 and the peripheral control input circuit. Further, various data (sensing data) from the touch panel control board 450 that detects and controls the contact state of the touch panel 480 are serialized and input to the serial I / O port for the touch panel control board of the peripheral control MPU 4150a.

Detection signals from various detection switches (for example, a photo sensor) for detecting the original position, movable position, etc. of various movable bodies provided on the game board 4 are on the game board side (not shown) provided on the motor drive board 4180. It is serialized by the serial transmission circuit, and this serialized movable body detection data is input from the game board side serial transmission circuit to the serial I / O port for the motor drive board of the peripheral control MPU4150a via the peripheral control input circuit. There is. The peripheral control MPU 4150a exchanges various data between the peripheral control board 4140 and the motor drive board 4180 by switching the input / output of the serial I / O port for the motor drive board.

The peripheral control MPU4150a has a built-in watchdog timer (hereinafter referred to as "peripheral control built-in WDT"), and its own system goes out of control by using the peripheral control built-in WDT and the peripheral control external WDT4150e together. It is diagnosing whether or not it is.

[7-4-1a. Peripheral control MPU]
Next, the peripheral control MPU4150a, which is a microcomputer, will be described. As shown in FIG. 15, the peripheral control MPU 4150a has a peripheral control built-in RAM 4150ab, a peripheral control DMA (abbreviation of Direct Memory Access) controller 4150ac, a peripheral control bus controller 4150ad, and various serials I for peripheral control, centering on the peripheral control CPU core 4150aa. It is composed of a / O port 4150ae, a WDT4150af with built-in peripheral control, various parallel I / O ports 4150ag for peripheral control, and a peripheral control analog / digital converter (hereinafter referred to as peripheral control A / D converter) 4150ak.

Peripheral control CPU core 4150aa reads and writes various data to peripheral control built-in RAM 4150ab and peripheral control DMA controller 4150ac via internal bus 4150ah, while peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT4150af, Peripheral control Various data are read / written to / from the various parallel I / O ports 4150ag and the peripheral control A / D converter 4150ak via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai.

Further, the peripheral control CPU core 4150aa reads various data to the peripheral control ROM 4150b via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h, while reading the peripheral control RAM 4150c and the peripheral control SRAM 4150d. Then, various data are read and written via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h.

The peripheral control DMA controller 4150ac includes storage devices such as peripheral control built-in RAM 4150ab, peripheral control ROM 4150b, peripheral control RAM 4150c, and peripheral control SRAM 4150d, peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT4150af, and peripheral control parallel I. It is a dedicated controller that independently transfers data between the / O port 4150ag and the input / output device such as the peripheral control A / D converter 4150ak without going through the peripheral control CPU core 4150aa, and is DMA0. It has four channels called DMA3.

Specifically, the peripheral control DMA controller 4150ac includes a storage device of the peripheral control built-in RAM 4150ab built in the peripheral control MPU 4150a, various peripheral control serial I / O ports 4150ae built in the peripheral control MPU 4150a, and a peripheral control built-in WDT4150af. , Peripheral control Various parallel I / O ports 4150ag, and input / output devices such as peripheral control A / D converter 4150ak, to independently transfer data between devices without going through the peripheral control CPU core 4150aa. In addition, while reading and writing to the storage device of the RAM 4150ab with built-in peripheral control via the internal bus 4150ah, various serial I / O ports 4150ae with peripheral control, WDT4150af with built-in peripheral control, various parallel I / O ports 4150ag with peripheral control, and Reads and outputs to / from an input / output device such as a peripheral control A / D converter 4150ak via the peripheral control bus controller 4150ad and the peripheral bus 4150ai.

Further, the peripheral control DMA controller 4150ac includes a storage device such as a peripheral control ROM 4150b, a peripheral control RAM 4150c, and a peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a, and various peripheral control serial I / Os built in the peripheral control MPU 4150a. I / O devices such as O port 4150ae, WDT4150af with built-in peripheral control, various parallel I / O ports 4150ag for peripheral control, and input / output devices such as peripheral control A / D converter 4150ak, without going through the peripheral control CPU core 4150aa. In order to perform data transfer independently, while reading and outputting to storage devices such as peripheral control ROM 4150b, peripheral control RAM 4150c, and peripheral control SRAM 4150d via peripheral control bus controller 4150ad and external bus 4150h, various peripheral controls are performed. For input / output devices such as serial I / O port 4150ae, WDT4150af with built-in peripheral control, various parallel I / O ports 4150ag for peripheral control, and peripheral control A / D converter 4150ak, via peripheral control bus controller 4150ad and peripheral bus 4150ai. And read and write.

The peripheral control bus controller 4150ad controls the internal bus 4150ah, the peripheral bus 4150ai, and the external bus 4150h to control the central processing unit of the peripheral control MPU core 4150aa, the peripheral control built-in RAM 4150ab, the peripheral control ROM 4150b, the peripheral control RAM 4150c, and the peripheral control. Various devices such as a storage device such as SRAM 4150d, various peripheral control serial I / O ports 4150ae, WDT4150af with built-in peripheral control, various parallel I / O ports 4150ag for peripheral control, and input / output devices such as peripheral control A / D converter 4150ak. It is a dedicated controller that exchanges various data between them.

Peripheral control Various serial I / O ports 4150ae are a serial I / O port for a lamp drive board, a serial I / O port for a motor drive board, a serial I / O port for a frame decoration drive amplifier board motor, and a frame decoration drive amplifier board LED. Serial I / O port, frame decoration drive amplifier board motor serial I / O port, main control board serial I / O port, operation unit information acquisition serial I / O port, and touch panel control board serial I / O Has a port.

The peripheral control built-in watchdog timer (WDT with built-in peripheral control) 4150af is a timer for monitoring whether the system of the peripheral control MPU4150a is out of control. It has become. That is, when the peripheral control CPU core 4150aa does not output a clear signal for clearing the timer within a certain period of time (until the timer is up) to the peripheral control built-in WDT4150a when the watchdog timer is started, the peripheral control CPU core 4150aa is reset. Will be taken. When the peripheral control CPU core 4150aa starts the watchdog timer and outputs a clear signal to the peripheral control built-in WDT4150af within a certain period of time, the timer count can be restarted, so that the reset is not applied.

Peripheral control Various parallel I / O ports 4150ag output various latch signals such as game board side motor drive latch signal and door side motor drive light emission latch signal, as well as output clear signal to peripheral control external WDT4150e, and play games. Detection signals from various detection switches for detecting the original position, movable position, etc. of various movable bodies provided on the board 4 are serialized by a game board side serial transmission circuit provided on the motor drive board 4180, and this serialization is performed. The movable body information acquisition latch signal for receiving the converted movable body detection data from the serial transmission circuit on the game board side at the serial I / O port for the motor drive board of the peripheral control MPU4150a can be output, and the upper decoration on the door frame 5 can be output. It outputs the lighting signal of the LED mounted on the upper decorative board of the unit 280. This LED is a high-brightness white LED, and is a confirmation lamp for notifying that the occurrence of a big hit game state is confirmed. In the present embodiment, the path between the LED and the various peripheral control parallel I / O ports 4150ag is shortened by adopting a configuration in which the LED and the peripheral control various parallel I / O ports 4150ag are directly connected electrically. It is possible to take noise countermeasures for LED lighting control, which has a heavy meaning in terms of games. The LED lighting control is executed in the peripheral control unit 1 ms timer interrupt process described later, and other LEDs and the like other than this LED are executed in the peripheral control unit steady process described later. It has become.

The peripheral control A / D converter 4150ak is electrically connected to the volume adjustment volume 4140a, and the resistance value is changed by rotating the knob portion of the volume adjustment volume 4140a, and the resistance at the rotation position of the knob portion is changed. The voltage divided by the value is converted from an analog value to a digital value, and converted into a value in 1024 steps from a value 0 to a value 1023. In this embodiment, the value of 1024 steps is divided into seven and managed as a substrate volume 0 to 6. The board volume 0 is set to mute, the board volume 6 is set to the maximum volume, and the volume is set so as to increase from the board volume 0 to the board volume 6. The liquid crystal display and the sound control unit 4160 (VDP4160a with a built-in sound source, which will be described later) are controlled so that the volume is set to the board volumes 0 to 6, and the speaker and the door frame 5 accommodated in the speaker box 820 provided in the main body frame 3 Music and sound effects are played from the provided speaker 130. In this way, music and sound effects are played from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 by adjusting the volume based on the rotation operation of the knob portion. ..

In the present embodiment, in addition to music and sound effects, a notification sound for notifying the clerk of the hall of the occurrence of a malfunction of the pachinko gaming machine 1 or an illegal act against the pachinko gaming machine 1, content related to the game production, etc. (For example, the screen unfolded on the liquid crystal display device 1900 on the gaming board side may be produced as more powerful, or it may be announced that there is a high possibility that the gaming state will be favorable to the player. The notification sound for) also flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the notification sound and the notification sound are adjusted in volume based on the rotation operation of the knob portion. It is a mechanism that flows independently of the sound, and the volume from mute to maximum volume can be adjusted by controlling the liquid crystal display and the sound control unit 4160 (VDP4160a with built-in sound source described later) by a program. .. The volume adjusted by this program is different from the substrate volume divided into the above-mentioned seven stages, and can smoothly change from mute to maximum volume. As a result, for example, even when a hall clerk or the like rotates the knob portion of the volume adjustment volume 4140a to set the volume to a low level, the speaker and the door housed in the speaker box 820 provided in the main body frame 3 are accommodated. Although the production sounds such as music and sound effects flowing from the speaker 130 provided in the frame 5 are reduced, the volume is loud when the pachinko gaming machine 1 has a problem or when the player is cheating. In the form, the notification sound set to the maximum volume) can be played. Therefore, even if the volume of the effect sound is reduced, it is possible to prevent the hall clerk and the like from becoming less likely to notice the occurrence of a problem or the player's fraudulent activity due to the notification sound. In addition, based on the current board volume set by adjusting the volume based on the rotation operation of the knob, the volume at which the advertising sound is played is reduced so that it does not interfere with music or sound effects, while the advertising sound is played. In addition to music and sound effects, there is a possibility that the screen unfolded by the liquid crystal display device 1900 on the game board side will be produced as more powerful, or the game will be in a game state that is advantageous to the player. You can also announce that it is expensive.

[7-4-1b. Peripheral control ROM]
The peripheral control ROM 4150b stores in advance various control programs, various data, various control data, and various schedule data for controlling the peripheral control unit 4150, the liquid crystal display and the sound control unit 4160, the RTC control unit 4165, and the like. The various schedule data include screen generation schedule data for generating a screen to be drawn on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470, light emission mode generation schedule data for generating light emission modes of various LEDs, and music. There are schedule data for sound generation that generates sound effects, and schedule data for electric drive sources that generate drive modes of electric drive sources such as motors and solenoids. The screen generation schedule data is configured by arranging screen data that defines the screen configuration in chronological order, and defines the order of screens to be drawn on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470. Has been done. The light emission mode generation schedule data is configured by arranging light emission data defining the light emission modes of various LEDs in time series. The sound generation schedule data is composed of sound command data arranged in chronological order, and the order in which music and sound effects are played is defined. The sound command data includes an output channel number for instructing which output channel to use among a plurality of output channels in the built-in sound source of the liquid crystal and the built-in sound source VDP4160a of the sound control unit 4160, which will be described later, and the built-in sound source VDP4160a. Of the plurality of tracks in the built-in sound source of the above, a track number for instructing which track to incorporate sound data such as music and sound effects is specified. The electric drive source schedule data is configured by arranging the drive data of the electric drive source such as a motor or a solenoid in a time series, and defines the operation of the electric drive source such as a motor or a solenoid.

Some of the control programs stored in the peripheral control ROM 4150b are directly read from the peripheral control ROM 4150b and executed, and some are copied to the various control program copy areas of the peripheral control RAM 4150c described later when the power is turned on. Some of them are read out and executed. Further, various data, various control data, and various schedule data stored in the peripheral control ROM 4150b may be read directly from the peripheral control ROM 4150b, or when the power is turned on in the various control data copy areas of the peripheral control RAM 4150c described later. In some cases, the copy is read out.

Further, the peripheral control ROM 4150b is used as one of various control programs for controlling the RTC control unit 4165 to correct the brightness of the liquid crystal display device 1900 on the game board side according to the usage time of the liquid crystal display device 1900 on the game board side. A brightness correction program is included. This brightness correction program corrects the decrease in brightness due to aging of the liquid crystal display device 1900 on the game board side when the backlight of the liquid crystal display device 1900 on the game board side is of the LED type. , The date and time when the power of the liquid crystal display device 1900 on the game board side was first turned on, the current date and time, the brightness setting information, etc. are acquired from the built-in RAM of the RTC control unit 4165, which will be described later, and the acquired brightness setting information is based on the correction information. To correct. This correction information is stored in advance in the peripheral control ROM 4150b. As will be described later, the brightness setting information includes brightness adjustment information for adjusting the range in which the brightness of the LED, which is the backlight of the liquid crystal display device 1900 on the game board side, ranges from 100% to 70% in 5% increments. The brightness of the LED that is the backlight of the liquid crystal display device 1900 on the game board side that has been set is included. For example, the date and time when the power of the liquid crystal display device 1900 on the game board side is first turned on and the current date and time. Therefore, if six months have already passed since the date and time when the power of the liquid crystal display device 1900 on the game board side was first turned on, the corresponding correction information (for example, 5%) is acquired from the peripheral control ROM 4150b and the brightness is increased. When the brightness of the LED included in the setting information is 75% and the backlight of the liquid crystal display device 1900 on the game board side is turned on, the brightness is 80%, which is an additional 5% of the correction information acquired for this 75%. The brightness of the backlight of the liquid crystal display device 1900 on the game board side is adjusted and turned on based on the brightness adjustment information included in the brightness setting information, and the power of the liquid crystal display device 1900 on the game board side is turned on for the first time. If December has already passed, the corresponding correction information (for example, 10%) is acquired from the peripheral control ROM 4150b, and the brightness of the LED included in the brightness setting information is 75%, and the liquid crystal display device on the game board side. When the 1900 backlight is turned on, the game board is based on the brightness adjustment information included in the brightness setting information so that the brightness is 85%, which is an additional 10% of the correction information acquired for this 75%. The brightness of the backlight of the side liquid crystal display device 1900 is adjusted and turned on.

[7-4-1c. Peripheral control RAM]
As shown in FIG. 15, the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a is a backup that exclusively stores various information that is updated by executing various control programs and is to be backed up. It is stored in the management target work area 4150ca, the backup first area 4150cc and the backup second area 4150cc, and the peripheral control ROM 4150b, which exclusively store the copy of various information stored in the backup management target work area 4150ca. Various control program copy areas 4150cd that exclusively store copies of various control programs, and various data, various control data, various schedule data, etc. stored in the peripheral control ROM 4150b are copied. Various control data copy areas 4150ce that are exclusively stored, and backup unmanaged work area 4150cf that exclusively stores information that is not backed up among various information updated by executing various control programs. Is provided.

When the power of the pachinko gaming machine 1 is turned on (including when the power is restored due to a momentary power failure or a power failure), a value 0 is forcibly written to the backup unmanaged work area 4150 cf and cleared to zero. For the backup management target work area 4150ca, backup 1st area 4150cc, and backup 2nd area 4150cc, the power on command (see FIG. 32) from the main control board 4100 starts the RAM clear effect when the pachinko gaming machine 1 is turned on. (For example, it is instructed to start the effect when the operation switch 860a shown in FIG. 11 is operated within a predetermined period from the time when the power is turned on. ), It is cleared to zero.

The backup management target work area 4150ca is various information updated in the peripheral control unit steady processing executed every time a V blank signal is input from the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160, which will be described later. Bank0 (1fr) that exclusively stores 1fr) as a backup target, and effect information (1ms) that is updated in the peripheral control unit 1ms timer interrupt processing that is executed every time a 1ms timer interrupt, which will be described later, occurs. It is composed of Bank0 (1 ms), which is exclusively stored as a backup target. Here, to briefly explain the names of Bank0 (1fr) and Bank0 (1ms), "Bank" is a minimum management unit representing the size of a storage area for storing various information, and is referred to as "Bank". Subsequent "0" means that it is a normally used storage area for storing various information updated by executing various control programs. That is, "Bank 0" means that the size of the storage area normally used is set as the minimum management unit. The "Bank1", "Bank2", "Bank3", and "Bank4" provided in the area extending from the backup first area 4150cc to the backup second area 4150cc, which will be described later, are the same storage areas as the "Bank0". It means that it has a size. As will be described later, when the VDP4160a with built-in sound source outputs drawing data for one screen (one frame) to the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the precision plate side, "(1fr)" is a peripheral control MPU4150a. Since the V blank signal indicating that the screen data from the above can be accepted is output to the peripheral control MPU4150a, in other words, one frame (1 frame) each time the V blank signal is input. Since the peripheral control unit routine processing is executed for each, it is added to "Bank0", "Bank1", "Bank2", "Bank3", and "Bank4", respectively (effect information (1fr) and effects described later). The backup information (1fr) is also used with the same meaning). As described later, "(1ms)" means "Bank0", "Bank1", "Bank2", "Bank3", and the like, since the peripheral control unit 1ms timer interrupt processing is executed every time a 1ms timer interrupt occurs. And "Bank 4", respectively (the effect information (1 ms) and the effect backup information (1 ms) described later are also used with the same meaning).

Bank0 (1fr) includes a lamp drive board side transmission data storage area 4150caa, a frame decoration drive amplifier board side LED transmission data storage area 4150cab, a reception command storage area 4150cac, an RTC information acquisition storage area 4150cad, and a schedule data storage area 4150cae. Etc. are provided. The game board side light emission data SL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs provided on each decorative board of the game board 4 in the transmission data storage area 4150caa on the lamp drive board side. Is a storage area in which is set, and in the transmission data storage area 4150cab for the LED on the frame decoration drive amplifier board side, a lighting signal, a blinking signal, or a gradation lighting to a plurality of LEDs provided on each decoration board of the door frame 5 is lit. It is a storage area in which the door-side light emission data STL-DAT for outputting a signal is set, and in the reception command storage area 4150cc, various commands transmitted from the main control board 4100 are received and the received commands are stored. It is a storage area to be set, and the RTC information acquisition storage area 4150cad is a storage area in which various information acquired from the RTC control unit 4165 (RTC built-in RAM4165aa of RTC41654a described later) is set, and is set in the schedule data storage area 4150cae. Is a storage area in which various schedule data corresponding to the received command are set based on the command received from the main control board 4100 (main control MPU4100a). In the schedule data storage area 4150cae, various schedule data copied from the peripheral control ROM 4150b to the various control data copy areas 4150ce may be read and set, and various schedule data may be directly read from the peripheral control ROM 4150b. Some are set.

Bank0 (1 ms) is provided with a frame decoration drive amplifier board side motor transmission data storage area 4150 caf, a motor drive board side transmission data storage area 4150 cag, a movable body information acquisition storage area 4150 cah, an operation unit information acquisition storage area 4150 cai, and the like. Has been done. In the transmission data storage area 4150 caf for the frame decorative drive amplifier board side motor, the door side motor drive data STM-DAT for outputting a drive signal to an electric drive source such as the dial drive motor 414 provided in the door frame 5 is provided. It is a storage area to be set, and is for outputting a drive signal to an electric drive source such as a motor or a solenoid for operating various movable bodies provided on the game board 4 in the transmission data storage area 4150 cg on the motor drive board side. It is a storage area in which the motor drive data SM-DAT on the game board side is set, and the movable body information acquisition storage area 4150cah is provided in the game board 4 based on the detection signals from various detection switches provided in the game board 4. It is a storage area in which various information acquired such as the original position and the movable position of various movable bodies is set, and the operation unit information acquisition storage area 4150kai is based on detection signals from various detection switches provided in the operation unit 400. Dial operation unit 401 created based on various information acquired from the rotation (rotation direction) of the dial operation unit 401 and the operation of the pressing operation unit 405 (for example, detection signals from various detection switches provided in the operation unit 400). (Rotation direction) history information, operation history information of the pressing operation unit 405, etc.) is set in this storage area.

Bank0 (1fr) lamp drive board side transmission data storage area 4150caa, frame decoration drive amplifier board side LED transmission data storage area 4150cab, and Bank0 (1ms) frame decoration drive amplifier board side motor transmission data storage area 4150caf. And the motor drive board side transmission data storage area 4150 cag is divided into two areas, a first area and a second area, respectively.

In the lamp drive board side transmission data storage area 4150caa, when the peripheral control unit steady processing described later is executed, the game board side light emission data SL-DAT is set in the first area of the lamp drive board side transmission data storage area 4150caa. When the next peripheral control unit steady processing is executed, the game board side light emission data SL-DAT is set in the second area of the lamp drive board side transmission data storage area 4150caa, and the peripheral control unit steady processing is performed. Each time the process is executed, the game board side light emission data SL-DAT is alternately set in the first area and the second area of the lamp drive board side transmission data storage area 4150caa. Peripheral control unit steady processing is executed. For example, when the game board side light emission data SL-DAT is set in the second area of the lamp drive board side transmission data storage area 4150caa in the peripheral control unit steady processing this time, the peripheral area of the previous time is executed. When the control unit steady processing is executed, the processing proceeds based on the game board side light emission data SL-DAT set in the first area of the lamp drive board side transmission data storage area 4150caa.

When the peripheral control unit steady processing is executed, the frame decoration drive amplifier board side LED transmission data storage area 4150cab is located in the first area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab. -When DAT is set and the next peripheral control unit steady processing is executed, the door side emission data STL-DAT is set in the second area of the transmission data storage area 4150cab for the frame decoration drive amplifier board side LED. The door-side emission data STL-DAT is alternately set in the first area and the second area of the transmission data storage area 4150cab for the LED on the frame decoration drive amplifier board side every time the peripheral control unit steady processing is executed. Ru. Peripheral control unit steady processing is executed, for example, when the door side light emission data STL-DAT is set in the second area of the transmission data storage area 4150cab for the frame decoration drive amplifier board side LED in the peripheral control unit steady processing this time. When the previous peripheral control unit steady processing is executed, the processing proceeds based on the door-side emission data STL-DAT set in the first area of the transmission data storage area 4150cab for the frame decoration drive amplifier board side LED. It has become.

The frame decoration drive amplifier board side motor transmission data storage area 4150 caf is doord to the first area of the frame decoration drive amplifier board side motor transmission data storage area 4150 caf when the peripheral control unit 1 ms timer interrupt process described later is executed. When the side motor drive data STM-DAT is set and the next peripheral control unit 1 ms timer interrupt process is executed, the door side motor drive data STM is set in the second area of the transmission data storage area 4150 caf for the frame decoration drive amplifier board side motor. -The DAT is set, and each time the peripheral control unit 1ms timer interrupt processing is executed, the door side is set in the first area and the second area of the transmission data storage area 4150 caf for the motor on the frame decoration drive amplifier board side. Motor drive data STM-DAT are set alternately. Peripheral control unit 1ms timer interrupt processing is executed. For example, in the peripheral control unit 1ms timer interrupt processing this time, the door side motor drive data STM-DAT is generated in the second area of the transmission data storage area 4150 caf for the frame decoration drive amplifier board side motor. When set, the door side motor drive data STM-DAT set in the first area of the frame decoration drive amplifier board side motor transmission data storage area 4150 caf when the previous peripheral control unit 1 ms timer interrupt process was executed. The process is to proceed based on this.

When the peripheral control unit 1 ms timer interrupt process is executed, the motor drive board side transmission data storage area 4150 cap sets the game board side motor drive data SM-DAT in the first area of the motor drive board side transmission data storage area 4150 cap. Then, when the next peripheral control unit 1 ms timer interrupt process is executed, the game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150 cag. Every time the peripheral control unit 1ms timer interrupt process is executed, the game board side motor drive data SM-DAT is alternately set in the first area and the second area of the motor drive board side transmission data storage area 4150 cag. Peripheral control unit 1ms timer interrupt processing is executed. For example, in the peripheral control unit 1ms timer interrupt processing this time, the game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150 cag. Occasionally, when the previous peripheral control unit 1 ms timer interrupt process is executed, the process proceeds based on the game board side motor drive data SM-DAT set in the first area of the motor drive board side transmission data storage area 4150 cag. It has become like.

Next, the backup first area 4150cc and the backup second area 4150cc, which exclusively store the copy of the effect information which is various information stored in the backup management target work area 4150ca, will be described. In the backup first area 4150cc and the backup second area 4150cc, two pairs having two banks as one pair are managed as one page. The effect information (1fr), which is the content stored in Bank0 (1fr), which is a normally used storage area, is used as the effect backup information (1fr) every time the peripheral control unit steady processing is executed for each frame (1frame). The effect information (1 ms) is copied to the backup first area 4150 cc and the backup second area 4150 cc by the peripheral control DMA controller 4150ac at high speed and is stored in the normally used storage area Bank0 (1 ms). As the effect backup information (1 ms), every time a 1 ms timer interrupt is generated, each time the peripheral control unit 1 ms timer interrupt process is executed, the peripheral control DMA controller 4150ac is applied to the backup first area 4150 cc and the backup second area 4150 cc. It is copied at high speed. The consistency of one page is determined by whether or not the contents of the two banks constituting the page match.

Specifically, in the backup first area 4150cc, Bank1 (1fr) and Bank2 (1fr) are set as one pair, and Bank1 (1ms) and Bank2 (1ms) are set as one pair, so that a total of two pairs are managed as one page. ing. The content stored in Bank0 (1fr), which is a normally used storage area, is peripheral control DMA in Bank1 (1fr) and Bank2 (1fr) every time the peripheral control unit steady processing is executed for each frame (1frame). The memory that is copied at high speed by the controller 4150ac and stored in Bank0 (1ms), which is a normally used storage area, is stored every time a 1ms timer interrupt is generated and every time the peripheral control unit 1ms timer interrupt processing is executed. It is copied to Bank1 (1ms) and Bank2 (1ms) at high speed by the peripheral control DMA controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank1 (1fr) and Bank2 (1fr) match. This is performed depending on whether or not the contents of Bank 1 (1 ms) and Bank 2 (1 ms) match.

Further, in the backup second area 4150cc, Bank3 (1fr) and Bank4 (1fr) are set as one pair, and Bank3 (1ms) and Bank4 (1ms) are set as one pair, so that a total of two pairs are managed as one page. The content stored in Bank0 (1fr), which is a normally used storage area, is stored in Bank3 (1fr) and Bank4 (1fr) every time the peripheral control unit steady processing is executed for each frame (1frame). The memory that is copied at high speed by the controller 4150ac and stored in Bank0 (1ms), which is a normally used storage area, is stored every time a 1ms timer interrupt is generated and every time the peripheral control unit 1ms timer interrupt processing is executed. It is copied to Bank3 (1ms) and Bank4 (1ms) at high speed by the peripheral control DMA controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank3 (1fr) and Bank4 (1fr) match. This is performed depending on whether or not the contents of Bank 3 (1 ms) and Bank 4 (1 ms) match.

As described above, in the present embodiment, the backup first area 4150 kb has Bank 1 (1 fr) and Bank 2 (1 fr) as one pair, and Bank 1 (1 ms) and Bank 2 (1 ms) as one pair, for a total of two pairs. It is an area for managing as a page, and the backup second area 4150cc has Bank3 (1fr) and Bank4 (1fr) as one pair, and Bank3 (1ms) and Bank4 (1ms) as one pair, for a total of two pairs. This is an area for managing as one page. Different ID coats are stored at the beginning and end of each page, that is, at the beginning and end of the backup first area 4150cc and the backup second area 4150cc.

Further, in the present embodiment, the effect information (1fr), which is the content stored in the normally used storage area Bank0 (1fr), is used as the effect backup information (1fr), and the peripheral control unit is used for each frame (1frame). Every time the steady processing is executed, the contents are copied to the backup first area 4150cc and the backup second area 4150cc by the peripheral control DMA controller 4150ac at high speed, and are stored in the normally used storage area Bank0 (1ms). The effect information (1 ms) is, as the effect backup information (1 ms), every time a 1 ms timer interrupt is generated and each time the peripheral control unit 1 ms timer interrupt process is executed, the backup first area 4150 cc and the backup second area 4150 cc. The peripheral control DMA controller 4150ac is used to copy at high speed, but the programs that execute the high-speed copy by these peripheral control DMA controllers 4150ac are standardized. That is, in this embodiment, the effect information (1fr) and the effect information (1 ms) are managed by a common management method (execution of a common program).

[7-4-1d. Peripheral control SRAM]
The peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a includes a backup management target work area 4150da that exclusively stores information to be backed up among various information updated by executing various control programs. A backup first area 4150db and a backup second area 4150dc are provided for exclusively storing a copy of various information stored in the backup management target work area 4150da. The content stored in the peripheral control SRAM 4150d is a power-on command (see FIG. 32) from the main control board 4100 when the pachinko gaming machine 1 is turned on (including when the power is restored due to a momentary power failure or a power failure). It is instructed to start the RAM clear effect and the start of each state effect (for example, it is instructed to start the effect when the operation switch 860a shown in FIG. 11 is operated within a predetermined period from the time when the power is turned on. Even when it is done), it is not cleared to zero. This point is completely different from the above-mentioned point that the backup management target work area 4150ca, the backup first area 4150cc, and the backup second area 4150cc of the peripheral control RAM 4150c are cleared to zero. Further, when the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the power of the pachinko gaming machine 1 is turned on, a screen for performing the setting mode is displayed on the liquid crystal display device 1900 on the game board side. It is supposed to be done. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the screen of this setting mode, each content (item) stored in the peripheral control SRAM 4150d (for example, a history of occurrence of a jackpot game state, etc.) On the other hand, the contents (items) stored in the peripheral control RAM 4150c are not displayed at all and cannot be cleared in the setting mode. This point is also completely different between the peripheral control RAM 4150c and the peripheral control SRAM 4150d.

The backup management target work area 4150da is used for managing various information such as effect information (SRAM) (for example, information for managing the history of occurrence of a jackpot game state and special effect flags), which is various information that is continued over days. It is composed of Bank0 (SRAM) that exclusively stores information) as a backup target. Here, to briefly explain the name of Bank0 (SRAM), as described above, "Bank" is a minimum management unit representing the size of a storage area for storing various information, and is referred to as "Bank". Subsequent "0" means that it is a normally used storage area for storing various information updated by executing various control programs. That is, "Bank 0" means that the size of the storage area normally used is set as the minimum management unit. The "Bank1", "Bank2", "Bank3", and "Bank4" provided in the area extending from the backup first area 4150db to the backup second area 4150dc, which will be described later, are the same storage areas as the "Bank0". It means that it has a size. Since various information stored in the peripheral control SRAM 4150d externally attached to the peripheral control SRAM 4150a is to be backed up in "(SRAM)", "Bank0", "Bank1", "Bank2", and "Bank3" , And "Bank 4", respectively (the effect information (SRAM) and the effect backup information (SRAM) described later are also used with the same meaning).

Next, the backup first area 4150db and the backup second area 4150dc, which exclusively store the copy of the effect information (SRAM) which is various information stored in the backup management target work area 4150da, will be described. The backup first area 4150db and the backup second area 4150dc have two banks as one pair, and this one pair is managed as one page. The effect information (SRAM), which is the content stored in Bank0 (SRAM), which is a normally used storage area, is used as the effect backup information (SRAM) every time the peripheral control unit steady processing is executed for each frame (1 frame). In addition, it is copied to the backup first area 4150db and the backup second area 4150dc at high speed by the peripheral control DMA controller 4150ac. The consistency of one page is determined by whether or not the contents of the two banks constituting the page match.

Specifically, the backup first area 4150db has Bank1 (SRAM) and Bank2 (SRAM) as one pair, and this one pair is managed as one page. The content stored in Bank0 (SRAM), which is a normally used storage area, is stored in Bank1 (SRAM) and Bank2 (SRAM) every time the peripheral control unit steady processing is executed for each frame (1 frame). It is copied at high speed by the controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank1 (SRAM) and Bank2 (SRAM) match.

Further, in the backup second area 4150dc, Bank3 (SRAM) and Bank4 (SRAM) are set as one pair, and this one pair is managed as one page. The content stored in Bank0 (SRAM), which is a normally used storage area, is stored in Bank3 (SRAM) and Bank4 (SRAM) every time the peripheral control unit steady processing is executed for each frame (1 frame). It is copied at high speed by the controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank3 (SRAM) and Bank4 (SRAM) match.

As described above, in the present embodiment, the backup first area 4150db is an area for managing Bank1 (SRAM) and Bank2 (SRAM) as one pair, and managing this one pair as one page, and the backup second area. 4150dc is an area for managing Bank3 (SRAM) and Bank4 (SRAM) as one pair, and managing this pair as one page. Different ID coats are stored at the beginning and end of each page, that is, at the beginning and end of the backup first area 4150db and the backup second area 4150dc.

[7-4-2. LCD and sound control unit]
The drawing control of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470, the speaker housed in the speaker box 820 provided in the main body frame 3, and the music, sound effects, etc. played from the speaker 130 provided in the door frame 5. As shown in FIG. 14, the liquid crystal and the sound control unit 4160 that perform sound control include a built-in sound source for controlling sound such as music and sound effects (hereinafter, referred to as "built-in sound source"). Displayed on the VDP (abbreviation of Video Display Speaker) 4160a with built-in sound source that controls drawing of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470, and the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470. A liquid crystal and sound control ROM 4160b that stores various sound data such as music and sound effects in addition to various character data on the screen to be displayed, and a frame decoration drive amplifier board 194 that uses serialized music and sound effects as audio data. It is equipped with an audio data transmission IC 4160c for transmission. In the liquid crystal and the sound control ROM 4160b, as sprite data used for displaying a screen or an image described later, for example, ring-shaped image data used for displaying a ring-shaped display object (annular display object), and an operation menu background image described later can be displayed. Operation menu used Image data, selected display image data used to display at least one selected display object described later, tone adjustment background image data used to display the volume adjustment screen including the volume scale described later, volume adjustment icon described later. In addition to the volume setting icon image data used for display, the image data on the back of the main frame used to display the image of the back of the main frame, which allows the position of each part on the back of the main frame 3 to be visible to the player, and the display of the service mode screen. The service mode screen image data used for, the break timer setting screen image data used for displaying the break timer setting screen, and the break screen image data used for displaying the break screen are stored. The liquid crystal display and the sound control ROM 4160b also store the suggestion display object image data used for displaying the suggestion display object for prompting that the pressing operation unit 405 (operation unit) of the operation unit 400 should be operated.

The peripheral control MPU 4150a of the peripheral control unit 4150 extracts the screen generation schedule data corresponding to the command from the main control board 4100 from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c. Set to 4150cae in the schedule data storage area of the peripheral control RAM 4150c, and set the screen data at the beginning of the screen generation schedule data set in the schedule data storage area 4150cae to the peripheral control ROM 4150b of the peripheral control unit 4150 or various peripheral control RAMs 4150c. After extracting from the control data copy area 4150ce and outputting it to the sound source built-in VDP4160a, the first screen data according to the screen generation schedule data set in the schedule data storage area 4150cae triggered by the input of the V blank signal described later. The next screen data following is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP4160a. In this way, the peripheral control MPU 4150a displays the screen data arranged in time series in the screen generation schedule data according to the screen generation schedule data set in the schedule data storage area 4150 cage, each time a V blank signal is input. In addition, the first screen data is output to the built-in sound source VDP4160a one by one.

Further, the peripheral control MPU 4150a transfers the sound command data at the head of the sound generation schedule data corresponding to the command from the main control board 4100 from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c. Extracted and set in the schedule data storage area of the peripheral control RAM 4150c to 4150cae, and set the sound command data at the beginning of the sound generation schedule data set in the schedule data storage area 4150cae to the peripheral control ROM 4150b or the periphery of the peripheral control unit 4150. After extracting from various control data copy areas 4150ce of the control RAM 4150c and outputting to the sound source built-in VDP4160a, when the V blank signal is input, the head is according to the sound generation schedule data set in the schedule data storage area 4150cae. The next sound command data following the sound command data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP4160a. In this way, the peripheral control MPU4150a inputs the sound command data arranged in time series into the sound generation schedule data according to the sound generation schedule data set in the schedule data storage area 4150cae, and the V blank signal is input. Each time, the first sound command data is output to the built-in sound source VDP4160a one by one.

[7-4-2a. VDP with built-in sound source]
When screen data is input from the peripheral control MPU4150a in addition to the above-mentioned built-in sound source, the sound source built-in VDP4160a is a game board from the liquid crystal and the sound control ROM 4160b as shown in FIG. 16 based on the input screen data. The side character data and the upper plate side character data are extracted to create sprite data, and the drawing data for one screen (one frame) to be displayed on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 is generated. It also has a built-in VRAM (hereinafter referred to as "built-in VRAM"). The sound source built-in VDP4160a outputs the image data for the game board side liquid crystal display device 1900 from the channel CH1 to the game board side liquid crystal display device 1900 among the drawing data generated on the built-in VRAM, and also for the upper plate side liquid crystal display device 470. By outputting the image data from the channel CH2 to the upper plate side liquid crystal display device 470, the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 are synchronized. The screen data from the peripheral control MPU4150a is based on the contact position (coordinate value) where the finger is touching the touch panel 480 (that is, the image is reflected in the position where the finger is touching), and the game board side. In some cases, the order of the screens to be drawn on the liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 is specified.

In this way, when the peripheral control MPU4150a outputs the screen data for one screen (one frame) displayed on the game board side liquid crystal display device 1900 and the precision plate side liquid crystal display device 470 to the sound source built-in VDP4160a, the sound source built-in VDP4160a becomes. Character data is extracted from the liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data, and one screen is displayed on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 (1). The drawing data for the frame) is generated on the built-in VRAM, and among the generated drawing data, the image data for the liquid crystal display device 1900 on the game board side is output from the channel CH1 to the liquid crystal display device 1900 on the game board side, and the precision plate side. The image data for the liquid crystal display device 470 is output from the channel CH2 to the upper plate side liquid crystal display device 470. That is, the "screen data for one screen (one frame)" is the built-in VRAM containing the drawing data for one screen (one frame) to be displayed on the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the upper plate side. It is the data to be generated above.

Further, the VDP4160a with a built-in sound source outputs drawing data for one screen (one frame) from the channel CH1 to the liquid crystal display device 1900 on the game board side, and outputs image data for the liquid crystal display device 470 on the upper plate side from the channel CH2. When the data is output to the liquid crystal display device 470 on the dish side, a V blank signal indicating that the screen data from the peripheral control MPU 4150a can be accepted is output to the peripheral control MPU 4150a. In the present embodiment, since the frame frequency (the number of screen updates per second) of the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the upper plate side is set to approximately 30 fps per second, a V blank signal is output. The interval is about 33.3 ms (= 1000 ms ÷ 30 fps). Peripheral control MPU4150a is configured to execute peripheral control unit V blank signal interrupt processing, which will be described later, when this V blank signal is input. Here, the interval at which the V blank signal is output varies slightly depending on the liquid crystal size of the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the upper plate side. Further, even in the manufacturing lot of the peripheral control board 4140 on which the peripheral control MPU 4150a and the sound source built-in VDP 4160a are mounted, the interval at which the V blank signal is output may change slightly.

The VDP4160a with a built-in sound source adopts a frame buffer method. This "frame buffer method" is to hold the drawing data for one screen (one frame) drawn on the screens of the game board side liquid crystal display device 1900 and the precision plate side liquid crystal display device 470 in the frame buffer (built-in VRAM). This is a method of outputting drawing data for one screen (one frame) held in this frame buffer (built-in VRAM) to the game board side liquid crystal display device 1900 and the precision plate side liquid crystal display device 470.

Further, when the above-mentioned sound command data is input from the peripheral control MPU4150a based on the command from the main control board 4100, the sound source built-in VDP4160a has music stored in the liquid crystal and the sound control ROM 4160b as shown in FIG. By extracting sound data such as and sound effects and controlling the built-in sound source, sound data such as music and sound effects are incorporated into the track according to the track number specified in the sound command data, and used according to the output channel number. The output channel is set and the music, sound effects, etc. flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 are serialized and output to the audio data transmission IC 4160c as audio data. ..

The sound command data also includes a sub-volume value for adjusting the volume of the track that incorporates the sound data, and multiple tracks in the built-in sound source of the built-in sound source VDP4160a include directing sounds such as music and sound effects. In addition to the sound data and the sub-volume value that adjusts the volume, the sound data of the notification sound and its volume for notifying the clerk of the hall of the occurrence of a malfunction of the pachinko game machine 1 or the fraudulent act against the pachinko game machine 1. A sub-volume value that adjusts is incorporated. Specifically, for the production sound, the substrate volume adjusted by rotating the knob portion of the volume adjustment volume 4140a described above is set as the sub-volume value, and for the notification sound, the volume is adjusted. The maximum volume is set as the sub-volume value without depending on the volume adjustment based on the rotation operation of the knob portion of the volume 4140a. The sub-volume value of the effect sound can be adjusted by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 to shift to the setting mode described later.

In addition, the sound designation data also includes a master volume value for adjusting the volume of the output channel, and the plurality of output channels in the built-in sound source of the sound source built-in VDP4160a include a plurality of in the sound source built-in VDP4160a built-in sound source. Of the tracks, the sound data of the effect sound incorporated in the track to be used and the sub-volume value for adjusting the volume of the effect sound incorporated in the track to be used are combined, and the volume of the combined effect sound is calculated. Actually, it is amplified to the master volume value which is the volume flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, and the amplified production sound is serialized as audio data. It is designed to be output to the audio data transmission IC 4160c.

In the present embodiment, the master volume value is set to a constant value, and when the volume of the synthesized effect sound is the maximum volume, the speaker box 820 provided in the main body frame 3 is amplified to the master volume value. The volume flowing from the speaker housed in the door frame 5 and the speaker 130 provided in the door frame 5 is set to be the maximum allowable volume. Specifically, for the effect sound, as a sub-volume value for adjusting the volume of the effect sound incorporated in the track to be used and the volume of the effect sound incorporated in the track to be used among a plurality of tracks. The volume of the set volume adjustment volume 4140a is combined with the board volume adjusted by rotating the knob portion, and the volume of the combined production sound is actually transmitted to the speaker box 820 provided in the main body frame 3. It is amplified to the master volume value that is the volume that flows from the accommodated speaker and the speaker 130 provided in the door frame 5, and this amplified production sound is serialized and output as audio data to the audio data transmission IC 4160c. Is based on the sound data of the notification sound incorporated in the track to be used and the rotation operation of the knob portion of the volume adjustment volume 4140a set as the sub-volume value for adjusting the volume of the notification sound incorporated in the track to be used. The maximum volume, which does not depend on the volume adjustment at all, is combined, and the volume of the combined notification sound is actually combined with the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5. It is amplified from 130 to the master volume value which is the volume to flow, and this amplified notification sound is serialized and output as audio data to the audio data transmission IC 4160c.

Here, when the effect sound is flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, a malfunction occurs in the pachinko game machine 1 or the pachinko game machine 1 is dealt with. To briefly explain the control to play the notification sound to notify the clerk of the hall of the fraudulent activity, first, the sub-volume value of the track in which the production sound is incorporated is forcibly set to mute, and this production sound is incorporated. The sound data of the track, the sub-volume value set for mute, the sound data of the track with the built-in notification sound, and the sub-volume value with the volume of the notification sound set to the maximum volume are combined and this is performed. The volume of the synthesized production sound and the volume of the notification sound are amplified to the master volume value which is the volume actually flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. Then, the amplified production sound and notification sound are serialized and output as audio data to the audio data transmission IC 4160c.

That is, as for the sound actually flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, only the maximum volume notification sound flows. At this time, since the effect sound is muted, the effect sound does not flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the effect sound is for sound generation described above. It is proceeding according to the schedule data. In the present embodiment, the notification sound flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 for a predetermined period (for example, 90 seconds). When the period elapses, the volume of the effect sound that has been progressing according to the sound generation schedule data forcibly set to mute is subordinated to the board volume adjusted by rotating the knob of the volume adjustment volume 4140a. It is set again as a volume value (at this time, if it is adjusted by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 to shift to the setting mode and adjusted, the sub of the adjusted effect sound. (Set to a volume value), the sound flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5.

As described above, when the effect sound is flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, a malfunction occurs in the pachinko game machine 1 or the pachinko game machine 1 occurs. When the notification sound is played to notify the clerk of the hall of the fraudulent act against the above, the volume of the production sound is muted and the notification sound is provided in the speaker and the door frame 5 housed in the speaker box 820 provided in the main body frame 3. Although the sound is played from the speaker 130, the muted production sound is progressing according to the sound generation schedule data, so that the notification sound is housed in the speaker box 820 provided in the main body frame 3 after a predetermined period of time has passed. And when the sound stops flowing from the speaker 130 provided in the door frame 5, the production sound does not start to flow again from the place where the notification sound starts to flow, but follows the sound generation schedule data until the time when the notification sound starts to flow and a predetermined period elapses. It starts to flow again from where it progressed.

[7-4-2b. LCD and sound control ROM]
As shown in FIG. 16, the liquid crystal and sound control ROM 4160b are for drawing on the game board side character data for drawing in the display area of the game board side liquid crystal display device 1900 and in the display area of the upper plate side liquid crystal display device 470. The upper plate side character data is stored in advance, and various sound data such as music, sound effects, notification sounds, and notification sounds are also stored in advance.

[7-4-2c. Audio data transmission IC]
When the serialized audio data from the VDP4160a with a built-in sound source is input, the audio data transmission IC 4160c transmits the right side audio data to the frame decoration drive amplifier board 194 as differential serial data with a positive signal and a negative signal. At the same time, the left side audio data is transmitted to the frame decoration drive amplifier board 194 as differential serial data with a positive signal and a negative signal. As a result, music, sound effects, and the like suitable for various effects are reproduced in stereo from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5.

The audio data transmission IC 4160c outputs audio data as serial data of a difference method between the left and right sides of the board extending from the peripheral control board 4140 to the frame decoration drive amplifier board 194, for example, a positive signal of the left side audio data. Even if the negative signal is affected by noise, when combining the noise component on the positive signal and the noise component on the negative signal on the frame decoration drive amplifier board 194 to make one left side audio data, Since the noise components are removed by canceling each other, it is possible to take measures against noise.

[7-4-3. RTC control unit]
As shown in FIG. 14, the RTC control unit 4165 that holds the calendar information that specifies the date and the time information that specifies the hour, minute, and second is configured around the RTC4165a. The RTC4165a has a built-in RAM4165aa that holds calendar information and time information (hereinafter, referred to as "RTC built-in RAM4165aa"). The RTC4165a is supplied with power from a battery 4165b (a button battery is adopted in this embodiment) as a drive power source and a backup power source for the RTC built-in RAM4165aa. That is, the RTC4165a is not supplied with power from the peripheral control board 4140 (pachinko gaming machine 1) at all, but is supplied with power from the battery 4165b independently of the peripheral control board 4140 (pachinko gaming machine 1). As a result, even if the power of the pachinko gaming machine 1 is cut off, the RTC4165a can update and hold the calendar information and the time information by the power supply from the battery 4165b.

The peripheral control MPU 4150a of the peripheral control unit 4150 acquires calendar information and time information from the RTC built-in RAM4165aa of the RTC4165a, sets them in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c described above, and uses the acquired calendar information and time information as the peripheral control MPU4150a. The effect based on this can be developed by the game board side liquid crystal display device 1900 and the precision plate side liquid crystal display device 470. As such an effect, for example, on December 25, the screen of the Christmas tree or reindeer is unfolded on the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the upper plate side, or on New Year's Eve, the New Year countdown is performed. It can be mentioned that the screen to be executed is unfolded by the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the precision plate side. Calendar information and time information are set at the time of shipment from the factory.

In addition to calendar information and time information, the RTC built-in RAM4165aa stores and holds LED brightness setting information when the backlight of the liquid crystal display device 1900 on the game board side is of the LED type. There is. When the backlight of the liquid crystal display device 1900 on the game board side is an LED type, the peripheral control MPU4150a acquires the brightness setting information from the RTC built-in RAM4165aa and adjusts the brightness of the backlight by PWM control. .. The brightness setting information includes brightness adjustment information for adjusting the range in which the brightness of the LED, which is the backlight of the liquid crystal display device 1900 on the game board side, ranges from 100% to 70% in 5% increments, and the game currently set. The brightness of the LED, which is the backlight of the liquid crystal display device 1900 on the panel side and the liquid crystal display device 470 on the precision plate side, is included.

Further, in the RTC built-in RAM4165aa, in addition to the calendar information, the time information and the brightness setting information, the calendar information, the time information and the brightness setting information are first stored in the RTC built-in RAM4165aa as the date, hour, minute and second information. The input date and time information is also stored.

The peripheral control MPU4150a can be turned on / off or only turned on when the backlight of the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the upper plate side is of the cold cathode tube type. It is designed to do.

Various information such as calendar information, time information, brightness setting information, and input date / time information stored in the RTC built-in RAM4165aa are set in the manufacturing line of the gaming machine maker. In the production line, for example, in order to perform various tests such as a display test of the liquid crystal display device 1900 on the game board side, the year when the input date and time information was input on the production line as the date and time when the power of the liquid crystal display device 1900 on the game board side was first turned on. It is set to the manufacturing date and time, which is the month, day, hour, minute, and second.

In this way, in addition to the calendar information and time information, the RTC built-in RAM4165aa has brightness setting information, input date and time information, etc. when the backlight of the liquid crystal display device 1900 on the gaming board side is of the LED type. , Information that needs to be maintained can be stored and retained independently of the model information of the pachinko gaming machine 1 (for example, the probability that a big hit gaming state occurs at a low probability or a high probability).

Further, the brightness setting information and the like stored and stored in the RTC built-in RAM4165aa are too bright with the brightness of the backlight of the liquid crystal display device 1900 on the game board side set at the manufacturing date and time depending on the environment of the hall where the pachinko gaming machine 1 is installed. Or it may be too dark. Therefore, by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400, it is possible to shift to the setting mode and adjust the brightness of the backlight to a predetermined brightness. When the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the power of the pachinko gaming machine 1 is turned on, a screen for performing the setting mode is displayed on the liquid crystal display device 1900 on the game board side. In addition, when the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 are operated during the period during which the customer is waiting and the demonstration by the liquid crystal display device 1900 on the game board side is being performed, the setting mode is performed. The screen is displayed on the liquid crystal display device 1900 on the game board side. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the screen of this setting mode, the calendar information and the time information can be reset, and the brightness of the backlight of the liquid crystal display device 1900 on the game board side can be desired. It can be adjusted to the brightness. The desired brightness of the backlight of the adjusted liquid crystal display device 1900 on the game board side is overwritten (updated and stored) as the brightness of the LED stored in the brightness setting information.

In the setting mode, the peripheral control MPU4150a executes the above-mentioned luminance correction program, and when the backlight of the liquid crystal display device 1900 on the game board side is an LED type, the liquid crystal display on the game board side is installed. Corrects the decrease in brightness due to aging of the display device 1900. The peripheral control MPU4150a acquires input date and time information from the RTC built-in RAM4165aa of the RTC control unit 4165, specifies the date and time when the liquid crystal display device 1900 on the game board side is first turned on, and the calendar information and time that specify the date and time. The current date and time is specified by acquiring the time information that specifies the minute and second, and the brightness of the LED, which is the backlight of the liquid crystal display device 1900 on the game board side, is adjusted in 5% increments from 100% to 70%. The brightness setting information having the brightness adjustment information for the purpose and the brightness of the LED which is the backlight of the liquid crystal display device 1900 on the game board side which is currently set is acquired. The acquired luminance setting information is corrected based on the correction information stored in advance in the peripheral control ROM 4150b.

For example, if six months have already passed from the date and time when the power of the liquid crystal display device 1900 on the game board side was first turned on and the current date and time, and the date and time when the power of the liquid crystal display device 1900 on the game board side was first turned on. When the corresponding correction information (for example, 5%) is acquired from the peripheral control ROM 4150b and the brightness of the LED included in the brightness setting information is 75% and the backlight of the liquid crystal display device 1900 on the game board side is turned on, this 75%. The brightness of the backlight of the liquid crystal display device 1900 on the game board side is adjusted based on the brightness adjustment information included in the brightness setting information so that the brightness is 80%, which is an additional 5% of the correction information acquired for the above. If 12 months have already passed since the date and time when the power of the liquid crystal display device 1900 on the game board side was first turned on, the corresponding correction information (for example, 10%) is acquired from the peripheral control ROM 4150b. When the brightness of the LED included in the brightness setting information is 75% and the backlight of the liquid crystal display device 1900 on the game board side is turned on, the correction information acquired for this 75% is added by 10% to 85%. The brightness of the backlight of the liquid crystal display device 1900 on the game board side is adjusted and turned on based on the brightness adjustment information included in the brightness setting information so as to be the brightness.

The current date and time may be specified by directly acquiring the calendar information for specifying the date and the time information for specifying the hour, minute, and second from the RTC built-in RAM4165aa of the RTC control unit 4165. Current calendar information set in the calendar information storage unit and updated by the system of the peripheral control board 4140 in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c in the current time information acquisition process of step S1002 in the control unit power-on processing. And the current time information set in the time information storage unit and updated by the system of the peripheral control board 4140 may be acquired to specify the current date and time.

[7-4-4. Volume adjustment volume]
As described above, the volume adjusting volume 4140a rotates the knob portion to control the volume of music, sound effects, etc. flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. It can be adjusted by doing. As described above, the volume adjustment volume 4140a has a variable resistance value when the knob portion is rotated, and an electrically connected peripheral control A / D converter 4150ak is used as the knob portion. The voltage divided by the resistance value at the rotation position is converted from an analog value to a digital value, and converted into a 1024-step value from a value 0 to a value 1023. In this embodiment, as described above, the 1024-step value is divided into seven and managed as the substrate volumes 0 to 6. The board volume 0 is set to mute, the board volume 6 is set to the maximum volume, and the volume is set so as to increase from the board volume 0 to the board volume 6. The liquid crystal display and the sound control unit 4160 (VDP4160a with a built-in sound source) are controlled so that the volume is set to the board volumes 0 to 6, and the speaker and the door frame 5 accommodated in the speaker box 820 provided in the main body frame 3 are provided. Music and sound effects are played from the speaker 130.

In this way, music and sound effects are played from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 by adjusting the volume based on the rotation operation of the knob portion. .. Further, in the present embodiment, as described above, in addition to the music and sound effects, a notification sound for notifying the clerk of the hall of the occurrence of a malfunction of the pachinko gaming machine 1 or an illegal act against the pachinko gaming machine 1 is provided. Announce the contents related to the game production (for example, the screen unfolded on the liquid crystal display device 1900 on the game board side is likely to be produced as more powerful, or the game state is likely to be advantageous to the player. The notification sound for pachinko and the like also flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the notification sound and the notification sound are operated by rotating the knob portion. It is a mechanism that flows without depending on the volume adjustment based on the above, and the volume from mute to the maximum volume can be adjusted by controlling the liquid crystal display and the sound control unit 4160 (VDP4160a with built-in sound source) by a program. ing.

The volume adjusted by this program is different from the substrate volume divided into the above-mentioned seven stages, and can smoothly change from mute to maximum volume. As a result, for example, even when a hall clerk or the like rotates the knob portion of the volume adjustment volume 4140a to set the volume to a low level, the speaker and the door housed in the speaker box 820 provided in the main body frame 3 are accommodated. Although the production sounds such as music and sound effects flowing from the speaker 130 provided in the frame 5 are reduced, the volume is loud when the pachinko gaming machine 1 has a problem or when the player is cheating. In the form, the notification sound set to the maximum volume) can be played. Therefore, even if the volume of the effect sound is reduced, it is possible to prevent the hall clerk and the like from becoming less likely to notice the occurrence of a problem or the player's fraudulent activity due to the notification sound.

In addition, based on the current board volume set by adjusting the volume based on the rotation operation of the knob, the volume at which the advertising sound is played is reduced so that it does not interfere with music or sound effects, while the advertising sound is played. In addition to music and sound effects by increasing the volume of the sound, the screen unfolded by the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the precision plate side can be produced as more powerful, which is advantageous for the player. It is also possible to announce that there is a high possibility of shifting to the gaming state.

In this embodiment, in addition to adjusting the volume of music and sound effects by rotating the knob portion of the volume adjustment volume 4140a, the dial operation portion 401 of the operation unit 400 and pressing are performed. By operating the operation unit 405, it is possible to shift to the setting mode and adjust the volume of music and sound effects. When the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the power of the pachinko gaming machine 1 is turned on, a screen for performing the setting mode is displayed on the liquid crystal display device 1900 on the game board side. In addition, when the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 are operated during the period during which the customer is waiting and the demonstration by the liquid crystal display device 1900 on the game board side is being performed, the setting mode is performed. The screen is displayed on the liquid crystal display device 1900 on the game board side. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the screen of this setting mode, the volume of music and sound effects can be adjusted to a desired volume. Specifically, the peripheral control A / D converter 4150ak converts the voltage divided by the resistance value at the rotation position of the knob of the volume control volume 4140a from an analog value to a digital value, and the converted value is obtained. The value of the board volume can be increased or decreased by adding or subtracting a predetermined value according to the operation of the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400. .. This adjusted volume is set and updated as a sub-volume value for the track in which the sound data of the production sound such as music or sound effect is incorporated among the multiple tracks in the built-in sound source of the built-in sound source VDP4160a. Although it is reflected in the adjustment of the volume of the above-mentioned notification sound and the notification sound, it is not reflected in the adjustment.

As described above, in the present embodiment, the volume of music or sound effect is adjusted by directly rotating the knob portion of the volume adjustment volume 4140a, and the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is used. There are two methods, one is to adjust the volume of music and sound effects by increasing or decreasing the value of the board volume by adding or subtracting a predetermined value according to the operation. Since the volume control volume 4140a is mounted on the peripheral control board 4140, it is necessary to make sure that the main body frame 3 is open from the outer frame 2. Then, it is the clerk in the hall who can rotate the knob portion of the volume adjusting volume 4140a. However, at the volume adjusted by the clerk in the hall, the player may feel small and it may be difficult to hear the music or sound effect, or the player may feel loud and the music or sound effect may be noisy. Therefore, after the power of the pachinko gaming machine 1 is turned on, the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 can be operated within a predetermined time, or the pachinko game machine 1 can be in a customer waiting state for demonstration by the liquid crystal display device 1900 on the game board side. If the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within the period during which the operation unit 400 is being performed, a screen for performing the setting mode is displayed on the liquid crystal display device 1900 on the gaming board side. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the screen of the setting mode, the volume of music and sound effects can be adjusted to a desired volume. As a result, the player can adjust the volume of the music or sound effect to a desired volume. Therefore, if the volume adjusted by the hall clerk feels low and it is difficult to hear the music or sound effect, the operation unit 400 can be used. The dial operation unit 401 and the pressing operation unit 405 can be operated to increase the volume to a desired level, and when the volume adjusted by the hall clerk feels loud and the music or sound effect is noisy, the operation unit 400 can be used. The dial operation unit 401 and the pressing operation unit 405 can be operated to reduce the volume to a desired level.

Further, in the present embodiment, when the pachinko gaming machine 1 is not playing a game for a predetermined time, the pachinko gaming machine 1 is in a waiting state for customers, and the demonstration by the liquid crystal display device 1900 on the gaming board side is repeatedly performed (for example, 10 times). ), The volume adjusted by the player who was sitting on the front of the pachinko gaming machine 1 and playing the game last time is canceled, and the volume is initialized. In this volume initialization, the volume is adjusted by the hall clerk, that is, the volume adjusted by the hall clerk by directly rotating the knob portion of the volume adjusting volume 4140a. As a result, if the player who was sitting in front of the pachinko gaming machine 1 last time feels that the volume adjusted is low and it is difficult to hear the music or sound effects, this time, the front of the pachinko gaming machine 1 is displayed. A player who sits down and plays a game can operate the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 to increase the volume to a desired level. If the player who was playing the game feels the volume adjusted loudly and the music or sound is noisy, this time, the player who sits on the front of the pachinko machine 1 and plays the game is the dial operation unit of the operation unit 400. The volume can be reduced to a desired level by operating the 401 and the pressing operation unit 405.

[8. Touch panel control board]
Next, the touch panel control board 450 for detecting and controlling the contact state of the capacitive touch panel 480 provided so as to cover the display area of the upper plate side liquid crystal display device 470 shown in FIG. 2 is shown in FIGS. 17 to 19. Will be described with reference to. 17 is a block diagram of the touch panel control board, FIG. 18 is a schematic diagram for detecting a position where a finger is touching the touch panel, and FIG. 19 is a schematic diagram showing a continuation of FIG.

As shown in FIG. 17, the touch panel control board 450 is centered on the touch panel controller IC 450b in addition to the power supply circuit 450a that creates and supplies an analog voltage and a digital voltage from a predetermined voltage from the peripheral control board 4140. It mainly comprises an oscillator 450c, a sensing IC 450d, and an amplifier circuit 450e. The touch panel controller IC450b drives and controls the sensing IC450d based on the control command from the peripheral control board 4140 to detect and control the contact state of the touch panel 480 and transmits it as sensing data to the peripheral control board 4140, or a power saving mode. Make a transition to. The oscillator 450c outputs a reference clock signal to the touch panel controller IC450b. The sensing IC 450d is driven and controlled by the touch panel controller IC 450b, senses the contact state of the touch panel 480, and outputs the value of the capacitance of the touch panel 480 as an analog signal. The amplifier circuit 450e amplifies the analog signal from the sensing IC 450d and outputs it to the touch panel controller IC 450b.

The touch panel controller IC 450b is configured around the controller 450ba, and is an analog-digital conversion circuit (hereinafter, "ADC") that converts the contact state of the touch panel 480 sensed by the sensing IC 450d input via the amplifier circuit 450e from an analog signal to a digital signal. () 450bb and various programs (for example, when the power is turned on (including not only when the power is turned on but also when the power is restored due to a power failure or a momentary power failure. The same shall apply hereinafter). Power-on processing to perform power-on processing, detection control program to detect the contact state of the touch panel 480, power-saving mode transition program to shift to power-saving mode, start by canceling power-saving mode A ROM 450bc in which a start program for performing the operation is stored in advance, a phase synchronization circuit (so-called "PLL circuit") 450be that creates a control clock signal from a reference clock signal from the oscillator 450c, and a control clock from the PLL circuit 450be. A synchronization signal output circuit 450bf that outputs a synchronization signal for synchronizing the touch panel controller IC450b and the sensing IC450d based on the signal, and a serial interface for the sensing IC that outputs serial data for indicating the sensing position of the touch panel 480. It mainly consists of 450 bg and a serial interface 450 bh for a peripheral control board that receives various serialized commands from the peripheral control board 4140 and transmits them to the controller 450 ba, while serializing sensing data and transmitting them to the peripheral control board 4140. Has been done.

As described above, the sensing IC 450d is driven and controlled by the touch panel controller IC 450b, senses the contact state of the touch panel 480, and outputs the value of the capacitance of the touch panel 480 as an analog signal. This analog signal is amplified by the amplifier circuit 450e and converted from the analog signal to the digital signal by the ADC 450bb of the touch panel controller IC 450b. The controller 450ba of the touch panel controller IC450b obtains a contact state detection value at the sensing position in the entire area of the touch panel 480 from the digital signal converted by the ADC 450bb, and uses this contact state detection value as the sensing position (X coordinate, Y) of the touch panel 480. Sensing data is created by connecting (that is, adding a sensing position) (coordinates).

The sensing IC 450d has a serial interface 450da that receives serial data for instructing the sensing position of the touch panel 480 transmitted from the serial interface 450bg for the sensing IC of the touch panel controller IC 450b, and a serial interface 450da that receives the serial data received by the serial interface 450da. By inputting the decoder 450db that restores to the sensing position data that indicates the sensing position of the touch panel and the sensing position data restored by the decoder 450db, the electrical connection to the sensing position in the entire area of the touch panel 480 is opened and closed for sensing. It was restored by an analog multiplexer 450dc that outputs the value of the capacitance of the touch panel 480 at the position as an analog signal, a synchronization signal input circuit 450de that inputs a synchronization signal from the synchronization signal output circuit 450bf of the touch panel controller IC450b, and a decoder 450db. Along with inputting sensing position data, a synchronization signal is input to the synchronization signal input circuit 450de, and a sensing unit 450df that senses an analog signal from the analog multiplexer 450dc and outputs it to the amplification circuit 450e is mainly configured.

Here, the operation of the touch panel controller IC450b and the sensing IC450d will be briefly described. For example, the controller 450ba of the touch panel controller IC450b starts the detection control for starting the detection control of the contact state of the touch panel 480 from the peripheral control board 4140. When the command is transmitted via the serial interface 450bh for the peripheral control board, the detection control program for detecting the contact state of the touch panel 480 is read from the ROM 450bc (or when the power is turned on to the RAM (not shown) provided in the touch panel controller IC 450b). When various programs stored in advance in the ROM 450bc are copied, the read detection control program is started (read from this RAM). When this detection control program is started, the controller 450ba transmits serial data for instructing the sensing position of the touch panel 480 from the serial interface 450bg for the sensing IC to the sensing IC 450d.

The sensing IC 450d receives serial data at the serial interface 450da, outputs the serial data to the decoder 450db, and restores the sensing position data at the decoder 450db. The analog multiplexer 450dc opens and closes an electrical connection to the sensing position in the entire area of the touch panel 480 according to the sensing position data from the decoder 450db, and uses the value of the capacitance of the touch panel 480 at the sensing position as an analog signal to be the sensing unit 450df. Output to. The controller 450ba of the touch panel controller IC450b outputs a synchronization signal from the synchronization signal output circuit 450bf to the sensing IC 450d, and when this synchronization signal is input to the synchronization signal input circuit 450de of the sensing IC 450d and transmitted to the sensing unit 450df, this is a trigger. In the sensing unit 450df, the analog signal from the analog multiplexer 450dc opens and closes the electrical connection to the sensing position in the entire area of the touch panel 480 according to the sensing position data from the decoder 450db, and the electrostatic capacity of the touch panel 480 at the sensing position. It is determined that it is the value of, and it is output to the amplification circuit 450e. The analog signal amplified via the amplifier circuit 450e is converted into a digital signal by the ADC 450bb of the touch panel controller IC 450b and input to the controller 450ba.

The controller 450ba obtains a contact state detection value at the sensing position in the entire area of the touch panel 480 from the digital signal converted by the ADC 450bb, and associates the contact state detection value with the sensing position (X coordinate, Y coordinate) of the touch panel 480. By (that is, adding a sensing position), sensing data is created, and the created sensing data is serialized and transmitted from the peripheral control board serial interface 450bh to the peripheral control board 4140.

The controller 450ba transmits serial data indicating the sensing position of the touch panel 480 from the serial interface 450bg for the sensing IC to the sensing IC 450d, outputs the synchronization signal from the synchronization signal output circuit 450bf to the sensing IC 450d, and is digitally converted by the ADC 450bb. Obtaining the contact state detection value at the sensing position in the entire area of the touch panel 480 from the signal, and linking the sensing position (X coordinate, Y coordinate) of the touch panel 480 to this contact state detection value (that is, adding the sensing position). By repeating the control of creating sensing data and serializing the created sensing data and transmitting it from the peripheral control board serial interface 450bh to the peripheral control board 4140, the entire area of the touch panel 480 is sensed and sensed. Data is transmitted to the peripheral control board 4140.

The peripheral control board 4140 that receives the sensing data in which the sensing position (X coordinate, Y coordinate) of the touch panel 480 is linked to the contact state detection value at the sensing position in the entire area of the touch panel 480 is the peripheral control unit shown in FIG. The peripheral control MPU4150a of the 4150 acquires the coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger based on the contact state detection value and the sensing position (X coordinate, Y coordinate). The position represented by the coordinate value is specified as a detection point. Specifically, when the peripheral control MPU4150a determines, for example, that the touch panel 480 is touching only the index finger of the left hand (that is, touching one point), as shown in FIG. 18A, based on the sensing data. As shown in FIG. 18 (b), P0 (x0, y0), which is a contact position of one point, is acquired as a coordinate value, and the position represented by this coordinate value is specified as a detection point, while FIG. 18 (c) ), For example, when it is determined that the index finger and the middle finger of the left hand are touching (that is, touching two points) on the touch panel 480, the contact positions are two points as shown in FIG. 18 (d). P0 (x0, y0) and P1 (x1, y1) are acquired as coordinate values, and the position represented by these coordinate values is specified as a detection point.

The detection control program for detecting the contact state of the touch panel 480 starts detection control in the touch panel processing of the peripheral control unit steady processing, which is repeatedly performed every 16 ms in the peripheral control unit power-on processing of the peripheral control board 4140, which will be described later. When the command is received from the peripheral control board 4140, the power of the pachinko gaming machine 1 is cut off, or the power saving mode transition command for shifting to the power saving mode is not received from the peripheral control board 4140. By the time it elapses, the sensing of the entire area of the touch panel 480 is completed.

When the peripheral control MPU4150a determines that the touch panel 480 is touching three or more points, the contact surface determined as the first point and the contact determined as the second point in the sensing order by a predetermined algorithm are used. While the surface is valid, the contact surface determined as the third point, the contact surface determined as the fourth point, ..., The contact surface determined after the third point is invalidated, and the first point is invalidated. And the contact position of the second point (P0 (x0, y0) and P1 (x1, y1)) is acquired as a coordinate value, and the position represented by these coordinate values is specified as a detection point. ..

Specifically, as shown in FIG. 19E, when the touch panel 480 is touched in the order of the index finger, the middle finger, and the ring finger of the left hand, the peripheral control MPU4150a touches the touch panel 480 with the index finger, the middle finger, and the ring finger of the left hand. When it is determined that the finger is touching (that is, touching three points), the position of the contact surface determined as the first point in the sensing order as shown in FIG. 19 (f) by a predetermined algorithm. (That is, the contact position P0 (x0, y0) of the index finger of the left hand) and the position of the contact surface determined as the second point (that is, the contact position P1 (x1, y2) of the middle finger of the left hand) are valid (that is, , The contact position P0 (x0, y0) of the index finger of the left hand and the contact position P1 (x1, y2) of the middle finger of the left hand are each enabled. ), The position of the contact surface determined as the third point (that is, the contact position P2 (x2, y2) of the ring finger of the left hand) is invalidated (that is, the contact position P2 (x2, y2) of the ring finger of the left hand is invalid. The contact positions of the first and second points (P0 (x0, y0) and P1 (x1, y1))) are acquired as coordinate values, respectively. The position represented by the coordinate value of is specified as a detection point.

In this way, even if it is determined that the peripheral control MPU4150a touches the touch panel 480 at three or more points, the contact position detected first and the contact position detected second by a predetermined algorithm are two points. Since only the contact position of can be acquired as a coordinate value, the contact positions of three or more points can be invalidated. As a result, the number of fingers required by the player to operate the touch panel 480 can be limited to a maximum of two, so that the operation of the touch panel 480 does not impose a burden on the player.

Here, to briefly explain the effect of using two fingers, when a big hit game state is generated, the big hit effect (for example, of a round) is performed in the display area of the liquid crystal display device 1900 on the game board side of the game board 4. (Introduction of numbers and various characters, etc.) is progressing, while in the display area of the liquid crystal display device 470 on the upper plate side of the upper plate 300, a treasure hunting effect that makes a treasure hunt during a big hit is progressing. There is. In this treasure hunting production, the treasure is sealed by a bivalve, and the touch panel 480 is such that the player uses two fingers (for example, the index finger and the middle finger of the left hand) to pry open the upper shell and the lower shell. If you can move while touching and pry open the bivalve and get the treasure, you can be promoted to variable probability, but if you can not pry open the bivalve and you can not get the treasure, it will remain the normal probability. .. In this way, it is possible to give a change due to contact with the touch panel 480 to the image displayed in the display area of the liquid crystal display device 470 on the upper plate side based on the contact state of the finger.

The touch panel provided so as to cover the display area of the display device in a mobile terminal such as a mobile phone can change the posture of the mobile terminal according to the finger operating the touch panel (that is, to make it easy to operate). Therefore, for example, when operating the touch panel using two fingers, it is possible to prevent the other fingers from touching the touch panel. On the other hand, as described above, the touch panel 480 is provided so as to cover the display area of the upper plate side liquid crystal display device 470, so that the touch panel 480 is fixed. Therefore, the posture of the touch panel 480 cannot be changed according to the finger operated by the player (that is, so as to be easy to operate). As a result, for example, even if the player operates the touch panel 480 using two fingers, the touch panel 480 may be touched without being noticed by the other fingers. There is also a method of creating a program that exclusively detects that such another finger is touching the touch panel 480, but the algorithm for distinguishing between a finger necessary for operation and a finger not necessary for operation becomes complicated, and the algorithm becomes complicated. There is a problem that the program becomes huge.

[9. Power system]
Next, the power supply system of the pachinko gaming machine 1 will be described with reference to FIGS. 20 and 21. FIG. 20 is a block diagram showing a power supply system of a pachinko gaming machine, and FIG. 21 is a block diagram showing a continuation of FIG. 20. First, the power supply board will be described, and then the power supply supplied to each control board and the like will be described. The ground (GND) of various boards and the ground (GND) of various terminal boards are electrically connected to the ground (GND) of the power supply board 851 and are the same ground (GND).

[9-1. Power supply board]
The power supply board 851 is electrically connected to the power cord, and the plug of the power cord is inserted into the power outlet of the pachinko island facility. When the power switch 852 shown in FIG. 3 is operated, the electric power supplied from the pachinko island facility is supplied to the power supply board 851, and the pachinko gaming machine 1 can be turned on.

As shown in FIG. 20, the power supply board 851 includes a power supply control unit 855 and a emission control unit 857. The power supply control unit 855 is a circuit that creates various DC voltages from AC 24 volts (AC24V) supplied from the pachinko island equipment and supplies backup power to the main control board 4100 and the payout control board 4110, and is a emission control. The unit 857 is a circuit for driving and controlling the firing solenoid 654 of the ball launching device 650 shown in FIG. 5 and the ball feeding solenoid 585 of the ball feeding unit 580 shown in FIG.

The power supply control unit 855 includes a synchronous rectifier circuit 855a, a power factor improvement circuit 855b, a smoothing circuit 855c, a power supply creation circuit 855d, and capacitors BC0 and BC1. The AC24V supplied from the pachinko island facility is supplied to the game ball rental device connection terminal board 869 via the power supply board 851, and is also supplied to the synchronous rectifier circuit 855a. This synchronous commutator circuit 855a is supplied from the pachinko island facility, rectifies AC 24 volts (AC24V), and supplies it to the power factor improving circuit 855b. The power factor improving circuit 855b improves the power factor of the rectified electric power to create a direct current +37V (DC +37V, hereinafter referred to as “+37V”) and supplies it to the smoothing circuit 855c. The smoothing circuit 855c removes the ripple of + 37V supplied to smooth the + 37V and supplies it to the launch control circuit 857a and the power supply creation circuit 855d of the launch control unit 857, respectively.

The capacitor BC0 supplies backup power to the RAM (main control built-in RAM) built in the main control MPU 4100a of the main control board 4100, and the capacitor BC1 is built in the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110. It supplies backup power to the RAM (RAM with built-in payout control).

The launch control circuit 857a of the launch control unit 857 uses + 37V supplied from the smoothing circuit 855c as a drive power source, and launches a game ball with a launch strength (launch strength) commensurate with the rotation position of the rotary handle main body front 506 shown in FIG. While controlling the drive current for launching (launching) toward the game area 1100 shown in FIG. 1 and outputting it to the firing solenoid 654, a constant current is output to the ball feeding solenoid 585 of the ball feeding unit 580. As a result, the ball feeding member of the ball feeding unit 580 accepts one game ball stored in the upper plate 301 of the dish unit 300 shown in FIG. 7, and sends the game ball received by the ball feeding member to the hitting ball launching device 650 side. Take control.

The power supply making circuit 855d has DC + 5V (DC + 5V, hereinafter referred to as “+ 5V”), DC + 12V (DC + 12V, hereinafter referred to as “+ 12V”), and DC supplied from the smoothing circuit 855c. + 24V (DC + 24V, hereinafter referred to as “+ 24V”) is created and supplied to the payout control board 4110 and the frame peripheral relay terminal board 868, respectively. The power supply system to which + 5V is applied and supplied is the + 5V power supply line, the power supply system to which + 12V is applied and supplied is the + 12V power supply line, and the power supply system to which + 24V is applied and supplied is the + 24V power supply line.

The + 5V created by the power supply creating circuit 855d is supplied to the payout control board 4110 as described later. The + 5V supplied to the payout control board 4110 is applied to the power supply terminal of the payout control MPU 4120a via the payout control filter circuit 4110a, and is also applied to the power supply terminal of the payout control built-in RAM via the diode PD0. ing. The + 12V created by the power supply creating circuit 855d is supplied to the + 5V creating circuit 4100g of the main control board 4100 via the payout control board 4110. This + 5V creation circuit 4100g creates + 5V, which is the control reference voltage of the main control MPU 4100a, from + 12V from the payout control board 4110. The + 5V created by the + 5V creation circuit 4100g is supplied to the power supply terminal of the main control MPU4100a via the main control filter circuit 4100h, and is also supplied to the power supply terminal of the main control built-in RAM via the diode MD0. ing.

The negative terminal of the capacitor BC1 of the power supply board 851 is grounded to the ground (GND), while the positive terminal of the capacitor BC1 is electrically connected to the power supply terminal of the payout control built-in RAM of the payout control board 4110 and is paid out. It is also electrically connected to the cathode terminal of the diode PD0 of the control board 4110. That is, the + 5V created by the power supply creation circuit 855d of the power supply board 851 causes a current to flow toward the power supply terminal of the payout control MPU4120a, and is forwarded by the diode PD0. Current flows toward the positive terminal. As described above, the capacitor BC1 is + 5V by the electrical connection method in which + 5V created by the power supply creation circuit 855d of the power supply board 851 returns from the payout control board 4110 and the payout control board 4110 to the power supply board 851 again. Is supplied and can be charged. As a result, when the + 5V created by the power supply creation circuit 855d is no longer supplied to the payout control board 4110, the charge charged in the capacitor BC1 is supplied to the payout control board 4110 as the payout VBB. Therefore, although the current is obstructed by the diode PD0 and does not flow to the power supply terminal of the payout control MPU4120a and the payout control MPU4120a does not operate, the stored contents are retained by supplying the payout VBB to the power supply terminal of the payout control built-in RAM. It has become so.

The negative terminal of the capacitor BC0 of the power supply board 851 is grounded to the ground (GND), while the positive terminal of the capacitor BC0 is electrically connected to the power supply terminal of the main control built-in RAM of the main control board 4100 via the payout control board 4110. It is also electrically connected to the cathode terminal of the diode MD0 of the main control board 4100. That is, in the + 5V created by the + 5V creation circuit 4100g, a current flows toward the power supply terminal of the main control MPU4100a, and the power supply terminal of the main control built-in RAM in the forward direction by the diode MD0, the positive terminal of the capacitor BC0, and the positive terminal. The current is flowing toward. As described above, the capacitor BC0 is charged with + 5V supplied by the electrical connection method in which + 5V created by the + 5V creation circuit 4100g is supplied from the main control board 4100 and the payout control board 4110 to the power supply board 851. You can do it. As a result, + 12V created by the power supply creation circuit 855d of the power supply board 851 is not supplied to the + 5V creation circuit 4100g of the main control board 4100 via the payout control board 4110, and the + 5V creation circuit 4100g can create + 5V. When it disappears, the electric charge charged in the capacitor BC0 is supplied to the main control board 4100 via the payout control board 4110 as the main VBB, so that the power supply terminal of the main control MPU 4100a is a diode. Although the main control MPU4100a does not operate because the current is obstructed by MD0 and does not flow, the stored contents are retained by supplying the main VBB to the power supply terminal of the main control built-in RAM.

[9-2. Voltage supplied to each control board, etc.]
Next, the outline of the voltage supplied to each control board and the like will be described, and then the voltage mainly supplied to the payout control board and the voltage supplied to the main control board will be described.

As shown in FIG. 20, three types of voltages of + 5V, + 12V, and + 24V created by the power supply creation circuit 855d of the power supply board 851 are supplied to the payout control board 4110, and among these three types of voltages, + 12V and Two types of voltages of + 24V are supplied to the main control board 4100 via the payout control board 4110. Further, three types of voltages, + 5V, + 12V, and + 24V, created by the power supply creation circuit 855d of the power supply board 851, are supplied to the frame peripheral relay terminal board 868 and peripherally via the frame peripheral relay terminal board 868. It is supplied to the control board 4140 and the peripheral door relay terminal board 882, respectively.

As shown in FIG. 21A, the three types of voltages of + 5V, + 12V, and + 24V supplied to the peripheral control board 4140 are the lamp drive circuit 4170a of the lamp drive board 4170 and the drive source drive circuit of the motor drive board 4180. It is supplied to each of the 4180a. The lamp drive circuit 4170a of the lamp drive board 4170 outputs various signals such as a lighting signal, a blinking signal, and a gradation lighting signal to various decorative boards of the game board 4, and the drive source drive circuit 4180a of the motor drive board 4180 is a game. A drive signal is output to an electric drive source such as a motor or a solenoid of the panel 4.

The peripheral control board 4140 includes a + 3.3V creation circuit 4140b that creates a direct current 3.3V (DC + 3.3V, hereinafter referred to as “+ 3.3V”) from + 5V supplied from the frame peripheral relay terminal board 868. ing. The + 3.3V created by the + 3.3V creation circuit 4140b is supplied to the liquid crystal module 1900a of the liquid crystal display device 1900 on the game board side and the liquid crystal module 470a of the liquid crystal display device 470 on the plate side, respectively. Further, + 12V supplied to the peripheral control board 4140 is supplied to the backlight power supply 1900b of the liquid crystal display device 1900 on the game board side and the backlight power supply 470b of the liquid crystal display device 470 on the upper plate side, respectively.

As shown in FIG. 21A, the + 5V voltage supplied to the peripheral control board 4140 is supplied to the power supply circuit 450a of the touch panel control board 450. The power supply circuit 450a creates an analog voltage and a digital voltage from the voltage of + 5V, respectively, and the required voltage among them is, for example, the touch panel controller IC450b, the sensing IC450d, the amplifier circuit 450e, and the touch panel shown in FIG. It is supplied to 480 and the like respectively.

On the other hand, three types of voltages, + 5V, + 12V, and + 24V, which are supplied to the peripheral door relay terminal plate 882, are supplied to the frame decoration drive amplifier board 194 as shown in FIG. 21B. The frame decoration drive amplifier board 194 includes a + 9V creation circuit 194a that creates a direct current + 9V (DC + 9V, hereinafter referred to as “+ 9V”) from + 12V supplied from the peripheral door relay terminal plate 882. Along with + 9V created by the + 9V creation circuit 194a, a total of four types of voltages of + 5V, + 12V, and + 24V supplied from the peripheral door relay terminal board 882 are supplied to various decorative boards of the door frame 5.

[9-2-1. Voltage supplied to the payout control board]
As shown in FIG. 20, the payout control board 4110 includes a payout control filter circuit 4110a and the like in addition to the payout control MPU 4120a and the like. The payout control filter circuit 4110a is supplied with + 5V from the power supply board 851, and noise is removed from this + 5V. This + 5V is supplied to the capacitor BC1 of the power supply board 851 via the diode PD0, and is also supplied to, for example, the payout control MPU4120a of the payout control unit 4120. The + 12V from the power supply board 851 is supplied to, for example, the payout control input circuit 4120b of the payout control unit 4120, and is also supplied to the external communication circuit 784a of the external terminal board 784 via the payout control board 4110. The external communication circuit 784a of the external terminal board 784 outputs a signal for transmitting the number of game balls paid out by the pachinko game machine 1 and the game information of the pachinko game machine 1 to the hall computer installed in the game hall. It is a circuit to do. The hall computer monitors the player's game by grasping the number of game balls paid out by the pachinko game machine 1 and the game information of the pachinko game machine 1 from the signal output from the external communication circuit 784a. .. The +24 from the power supply board 851 is supplied to the main control board 4100 via the payout control board 4110 without being used in the payout control board 4110.

[9-2-2. Voltage supplied to the main control board]
As shown in FIG. 20, the main control board 4100 includes a + 5V creation circuit 4100g, a main control filter circuit 4100h, a power failure monitoring circuit 4100e, and the like, in addition to the main control MPU 4100a and the like. In the + 5V creation circuit 4100g, + 12V from the power supply board 851 is supplied via the payout control board 4110, and + 5V, which is the control reference voltage of the main control MPU 4100a, is created from this + 12V. In the main control board 4100, the power supply system to which + 5V created by the + 5V creation circuit 4100g is applied and supplied becomes the + 5V power supply line. In the present embodiment, the + 5V power supply line created by the power supply creation circuit 855d of the power supply board 851 and the + 5V power supply line created by the + 5V creation circuit 4100g of the main control board 4100 are not electrically connected. Since the circuit is configured as described above, the + 5V power supply line created by the power supply creation circuit 855d of the power supply board 851 is not electrically connected to various electronic components of the main control board 4100, and + 5V of the main control board 4100. The + 5V power supply line created by the creation circuit 4100g is not electrically connected to various electronic components such as other boards other than the main control board 4100.

The main control filter circuit 4100h is supplied with + 5V created by the + 5V creation circuit 4100g, and noise is removed from this + 5V. This + 5V is supplied to the capacitor BC0 of the power supply board 851 via the diode MD0, and is also supplied to, for example, the main control MPU4100a. The + 12V from the payout control board 4110 is supplied to, for example, the main control input circuit 4100b, and the + 24V from the payout control board 4110 is supplied to, for example, the main control solenoid drive circuit 4100d.

The power failure monitoring circuit 4100e supplies + 12V and + 24V from the power supply board 851 via the payout control board 4110, and monitors the signs of power failure or momentary power failure of these + 12V and + 24V. When the power failure monitoring circuit 4100e detects a sign of a power failure or momentary power failure of + 12V and + 24V, it outputs a power failure warning signal to the main control MPU4100a as a power failure warning. The power failure warning signal is input to the payout control MPU 4120a via the payout control input circuit 4120b of the main control board 4100 and the payout control board 4110. Further, the power failure warning signal is input to the peripheral control board 4140 via the main control board 4100. Further, the power failure warning signal is input to the frame decorative drive amplifier board 194 as shown in FIG. 21B via the peripheral control board 4140, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882. At the same time, the input is input to the decorative board of the door frame or the like via the frame decorative drive amplifier board 194.

In the present embodiment, the power failure monitoring circuit 4100e applies to one of the + 12V power supply line or the + 24V power supply line by monitoring the voltage applied to the two power supply lines, the + 12V power supply line and the + 24V power supply line, respectively. Compared to the case of monitoring the voltage to be applied, it is possible to more accurately grasp the signs of power failure such as power failure or momentary power failure.

[10. Main control board circuit]
Next, the circuit and the like of the main control board 4100 shown in FIG. 11 will be described with reference to FIGS. 22 to 24. 22 is a circuit diagram showing a circuit of the main control board, FIG. 23 is a circuit diagram showing a power failure monitoring circuit, and FIG. 24 is a circuit showing a communication interface circuit between the main control board and the peripheral control board. It is a figure. First, the main control filter circuit 4100h shown in FIG. 20 will be described, and then the power supply, main control system reset, main control crystal oscillator, main control input circuit, power failure monitoring circuit, and main control MPU created by the main control board 4100 will be described. Various input / output signals to the main control board 4100 and a communication interface circuit between the main control board 4100 and the peripheral control board 4140 will be described.

The main control board 4100 includes a main control MPU 4100a, a main control input circuit 4100b, a main control output circuit 4100c, a main control solenoid drive circuit 4100d, a power failure monitoring circuit 4100e, a + 5V creation circuit 4100g, and a main control board 4100g shown in FIGS. 11 and 20. In addition to the control filter circuit 4100h, as peripheral circuits, as shown in FIG. 22, the main control system reset MIC1 that outputs a reset signal and the main control crystal oscillator MX0 that outputs a clock signal (in this embodiment, 24 megahertz (MHz)). )) Is mainly composed.

[10-1. Main control filter circuit]
As shown in FIG. 22, the main control filter circuit 4100h mainly includes a main control 3-terminal filter MIC0. This main control 3-terminal filter MIC0 is a T-type filter circuit, and is magnetically shielded with ferrite and has excellent attenuation characteristics. In the main control 3-terminal filter MIC0, + 5V created by the + 5V creation circuit 4100g was applied to the 1st terminal, the 2nd terminal was grounded to the ground (GND), and the noise component was removed from the 3rd terminal. + 5V is output. The + 5V applied to the 1st terminal is electrically connected to the other end of the capacitor MC0 whose one end is grounded to ground (GND), so that the ripple (alternating current component folded by the voltage) is first removed. Is smoothed.

The + 5V output from the 3rd terminal is electrically connected to the other end of the capacitor MC1 and the electrolytic capacitor MC2 (capacitance: 470 microfarad (μF) in this embodiment) whose one end is grounded to ground (GND). By connecting to, the ripple is further removed and smoothed. This smoothed + 5V is applied to the power supply terminal of the main control system reset MIC1, the VDD terminal which is the power supply terminal of the main control crystal oscillator MX0, the VDD terminal which is the power supply terminal of the main control MPU4100a, and the like.

The VDD terminal of the main control MPU4100a is electrically connected to the other end of the capacitor MC3 whose one end is grounded to ground (GND), and the + 5V applied to the VDD terminal is further smoothed by removing ripples. The VSS terminal, which is the ground terminal of the main control MPU4100a, is grounded to ground (GND).

Further, the VDD terminal of the main control MPU4100a is electrically connected to the anode terminal of the diode MD0 in addition to being electrically connected to the capacitor MC3. The cathode terminal of the diode MD0 is electrically connected to the VBB terminal, which is the power supply terminal of the RAM (main control built-in RAM) built in the main control MPU4100a, and one end of the capacitor MC4 is grounded to ground (GND). It is electrically connected to the other end of the. The VBB terminal of the main control built-in RAM is electrically connected to the cathode terminal of the diode MD0 and the other end of the capacitor MC4, and is also the plus of the capacitor BC0 of the power supply board 851 shown in FIG. 20 via the resistor MR0. It is electrically connected to the terminal. That is, + 5V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the VDD terminal of the main control MPU4100a, and is applied to the VBB terminal of the main control built-in RAM and the capacitor BC0 via the diode MD0. It is designed to be applied to the positive terminal of. As a result, as described above, + 12V created by the power supply creating circuit 855d of the power supply board 851 shown in FIG. 20 is not supplied to the + 5V creating circuit 4100g of the main control board 4100 via the payout control board 4110, and + 5V is created. When the circuit 4100g cannot create + 5V, the charge charged in the capacitor BC0 is supplied to the main control board 4100 as the main VBB, so that the VDD terminal of the main control MPU 4100a is used. Although the main control MPU4100a does not operate because the current is obstructed by the diode MD0 and does not flow, the stored contents are retained by applying the main VBB to the VBB terminal of the main control built-in RAM.

[10-2. Main control system reset]
As shown in FIG. 22, + 5V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the power supply terminal of the main control system reset MIC1. The main control system reset MIC1 resets the main control MPU 4100a and the main control output circuit 4100ca with a reset function, respectively, and has a built-in delay circuit. The delay capacitance terminal of the main control system reset MIC1 is electrically connected to the other end of the capacitor MC5 whose one end is grounded to ground (GND), and the delay time by the delay circuit is set by the capacitance of this capacitor MC5. You can do it. Specifically, when the + 5V input to the power supply terminal reaches the threshold value (for example, 4.25V), the main control system reset MIC1 outputs a system reset signal from the output terminal after the delay time elapses.

The output terminal of the main control system reset MIC1 is electrically connected to the SRST terminal which is the reset terminal of the main control MPU 4100a and the reset terminal of the main control output circuit 4100ca with a reset function. The output terminal is an open collector output type, and is a capacitor whose one end is electrically connected to the other end of the pull-up resistor MR1 which is electrically connected to the + 5V power supply line and one end is grounded to ground (GND). It is electrically connected to the other end of the MC6. Ripple is removed and smoothed by this capacitor MC6. When the voltage input to the power supply terminal is larger than the threshold value, the output terminal is pulled up to the + 5V side by the pull-up resistor MR1 and the logic becomes HI, and this logic becomes the SRST terminal of the main control MPU4100a and the main control output with a reset function. While each is input to the reset terminal of the circuit 4100ca, when the voltage input to the power supply terminal is smaller than the threshold value, the logic becomes LOW, and this logic becomes the SRST terminal of the main control MPU 4100a and the main control output circuit 4100ca with a reset function. It is input to each reset terminal. Since the SRST terminal of the main control MPU 4100a and the reset terminal of the main control output circuit 4100ca with a reset function are negative logic inputs, respectively, when the voltage input to the power supply terminal becomes smaller than the threshold value, the main control MPU 4100a and the reset function The main control output circuit 4100ca is reset. The power supply terminal is electrically connected to the other end of the capacitor MC7 whose one end is grounded to ground (GND), and the + 5V input to the power supply terminal is smoothed by removing ripples. Further, the ground terminal is grounded to the grant (GND), and the NC terminal is not electrically connected to the outside.

[10-3. Main control crystal oscillator]
As shown in FIG. 22, + 5V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the VDD terminal which is the power supply terminal of the main control crystal oscillator MX0. This VDD terminal is electrically connected to the other end of the capacitor MC8 whose one end is grounded to ground (GND), and the + 5V input to the VDD terminal is further stripped of ripples and smoothed. Further, this smoothed + 5V is applied not only to the VDD terminal but also to the A terminal, the B terminal, the C terminal, and the ST terminal, which are output frequency selection terminals, respectively. The main control crystal oscillator MX0 outputs a 24 MHz clock signal from the F terminal, which is an output terminal, by applying + 5 V to each of the A terminal, B terminal, C terminal, and ST terminal.

The F terminal of the main control crystal oscillator MX0 is electrically connected to the CLK terminal, which is the clock terminal of the main control MPU4100a, and a 24 MHz clock signal is input. The GND terminal, which is the ground terminal of the main control crystal oscillator MX0, is grounded to ground (GND), and the D terminal, which outputs the frequency division of the F terminal of the main control crystal oscillator MX0, is not electrically connected to the outside. It is in a state.

[10-4. Main control input circuit]
The main control input circuit 4100b is a detection signal from the general winning port switches 3020 and 3020, the upper start port switch 3022, the lower start port switch 2109, the magnetic detection switch 304, the count switch 2110, and the gate switch 2352 shown in FIG. In addition, it is a circuit to which an operation signal (RAM clear signal) or the like from the operation switch 860a provided in the payout control board 4110 shown in FIG. 12 is input. Since the circuit configuration in which the detection signal from each switch is input is the same, a circuit in which the operation signal (RAM clear signal) from the operation switch 860a is input will be described here.

[10-4-1. Circuit to which the operation signal (RAM clear signal) from the operation switch is input]
First, as described above, the operation switch 860a is a RAM (RAM with built-in payout control) built in the payout control MPU 4120a of the payout control board 4110 and a main control of the main control board 4100 within a predetermined period from the time when the power is turned on. It is operated when clearing the RAM (main control built-in RAM) built in the MPU4100a, or when an error is notified after the power is turned on, it is operated to clear the error. The function to clear the RAM within a predetermined period from the time the power is turned on, and the error cancellation after the power is turned on (after the period during which the function as RAM clear has elapsed, that is, after the predetermined period has elapsed from the time the power is turned on). It has a function to perform. Since the main control board 4100 does not have the function of canceling the error that the payout control board 4110 has, when the operation signal from the operation switch 860a is input within a predetermined period from the time when the power is turned on, the main control is performed. A process of clearing the main control built-in RAM is performed by judging as a RAM clear signal for clearing the built-in RAM.

When the operation switch 860a is not operated, the operation signal whose logic is LOW is input to the main control board 4100, while when the operation switch 860a is operated, the logic is input from the payout control board 4110. The operation signal with HI is input from the payout control board 4110 (detailed description of this point will be described later).

As shown in FIG. 22, the transmission line for transmitting the operation signal from the operation switch 860a provided on the payout control board 4110 within a predetermined period from the time when the power is turned on is a pull-up in which one end is electrically connected to the + 12V power supply line. It is electrically connected to the other end of the resistor MR2 and is also electrically connected to the base terminal of the transistor MTR0 via the resistor MR3. In addition to being electrically connected to the resistance MR3, the base terminal of the transistor MTR0 is electrically connected to the other end of the resistance MR4 whose one end is grounded to ground (GND). The emitter terminal of the transistor MTR0 is grounded to ground (GND), and the collector terminal of the transistor MTR0 is electrically connected to the other end of the resistor MR5, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Main control via ICMIC10 (non-inverting buffer ICMIC10 includes eight non-inverting buffer circuits, and the logic of the signal waveform input to one of them (MIC10A) is shaped and output without inverting). It is electrically connected to the input terminal PA0 of the input port PA of the MPU4100a.

The circuit that outputs the operation signal from the operation switch 860a on the payout control board 4110 is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and the transmission that transmits the operation signal from the operation switch 860a. The line is pulled up to the + 12V side by the pull-up resistor MR2. In the main control board 4100, when the operation switch 860a is not operated, the operation signal from the payout control board 4110 is pulled down to the ground (GND) side and the logic is input as LOW, while the operation switch 860a is operated. At this time, the operation signal from the payout control board 4110 is pulled up to the + 12V side by the pull-up resistor MR2, and the logic is input as HI.

The circuit composed of the resistors MR3 and MR4 and the transistor MTR0 is a switch circuit that is turned on / off by an operation signal from the operation switch 860a.

When the operation switch 860a is not operated, the operation signal whose logic is LOW is input to the base terminal of the transistor MTR0, so that the transistor MTR0 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor MTR0 is pulled up to the + 5V side by the resistor MR5, and the operation signal from the operation switch 860a whose logic is HI is input to the input terminal PA0 of the input port PA of the main control MPU4100a. Will be done. The main control MPU4100a must instruct to clear the RAM that erases the information stored in the main control built-in RAM when the logical value of the operation signal from the operation switch 860a input to the input terminal PA0 is HI. to decide.

On the other hand, when the operation switch 860a is operated, the transistor MTR0 is turned on by inputting the operation signal whose logic is HI by being pulled up to the + 12V side by the pull-up resistor MR2 to the base terminal of the transistor MTR0, and the switch is switched. The circuit will also be turned on. As a result, the voltage applied to the collector terminal of the transistor MTR0 is lowered to the ground (GND) side, and the operation signal from the operation switch 860a whose logic is LOW is input to the input terminal PA0 of the input port PA of the main control MPU4100a. Will be done. The main control MPU4100a instructs to clear the RAM that erases the information stored in the main control built-in RAM when the logical value of the operation signal from the operation switch 860a input to the input terminal PA0 is LOW. Judge.

The operation signal from the operation switch 860a is pulled up to the + 12V side by the pull-up resistor MR2. This is because the operation signal from the operation switch 860a is input via the payout control board 4110. That is, between the boards of the main control board 4100 and the payout control board 4110, the voltage is higher than the control reference voltage of + 5V in order to suppress the influence of noise invading the wiring (harness) that electrically connects the boards. The reliability of the signal is enhanced by using + 12V which is a voltage. Therefore, in the present embodiment, the detection signals from the general winning port switch 3020, the upper starting port switch 3022, and the lower starting port switch 2109, which are directly input to the main control board 4100, are pulled up to the + 5V side by the pull-up resistor. On the other hand, the detection signals from the magnetic detection switch 3024, the count switch 2110, the general winning opening switch 3020, and the gate switch 2352, which are input via the panel relay terminal plate 4161 shown in FIG. 11, are directly sent to the main control board 4100. Since it is not input, it is pulled up to the + 12V side by the pull-up resistor like the operation signal from the operation switch 860a.

[10-5. Power failure monitoring circuit]
As shown in FIG. 20, in the main control board 4100, two types of voltages, + 12V and + 24V, are supplied from the power supply board 851 via the payout control board 4110, and + 12V and + 24V are input to the power failure monitoring circuit 4100e. ing. The power failure monitoring circuit 4100e monitors signs of a power failure or momentary power failure of + 12V and + 24V, and when it detects a sign of power failure or momentary power failure, it sends a power failure warning signal as a power failure warning, in addition to the main control MPU4100a, a payout control board. It is output to the payout control MPU 4120a of the 4110 and the peripheral control board 4140. Here, the configuration of the power failure monitoring circuit will be described first, followed by the monitoring of + 24V power failure or momentary power failure, the monitoring of + 12V power failure or momentary power failure, and the output of the power failure warning signal.

[10-5-1. Power failure monitoring circuit configuration]
As shown in FIG. 23, the power failure monitoring circuit 4100e mainly includes a shunt type stabilized power supply circuit MIC20, an open collector output type comparator MIC21, a D type flip-flop MIC22, and transistors MTR20 to MTR23.

The REF terminal, which is the reference voltage input terminal of the shunt-type regulated power supply circuit MIC20, and the K terminal, which is the cathode terminal, are electrically connected to the other end of the resistance MR20 whose one end is electrically connected to the + 5V power supply line. + 5V is applied, and the current input to the REF terminal is limited by the resistance MR20. The K terminal outputs a reference voltage Vref (2.495V is set in this embodiment), which is a reference voltage for comparison of the comparator MIC21. The K terminal is electrically connected to the other end of the capacitor MC20 whose one end is grounded to ground (GND), and the reference voltage Vref output from the K terminal is rippled (folded over the voltage) by the capacitor MC20. The AC component) has been removed and smoothed. The A terminal, which is the anode terminal of the shunt-type regulated power supply circuit MIC20, is grounded to ground (GND).

The comparator MIC21 includes two voltage comparison circuits, one (MIC21A) is used to compare the + 24V monitoring voltage V1 with the reference voltage Vref, and the other one (MIC21B) is used. , + 12V is used to compare the monitoring voltage V2 with the reference voltage Vref. A monitoring voltage V1 of + 24V is applied to the positive terminal 3 of the MIC 21A, and a reference voltage Vref is applied to the negative terminal 2 of the MIC 21A. A monitoring voltage V2 of + 12V is applied to the 5th terminal which is a positive terminal of the MIC21B, and a reference voltage Vref is applied to the 6th terminal which is a negative terminal of the MIC21B. These comparison results are input to the D type flip-flop MIC22. This D-type flip-flop MIC 22 includes two D-type flip-flop circuits, one of which (MIC22A) is used in the present embodiment. The Vcc terminal, which is the power supply terminal of the comparator MIC21, is electrically connected to the other end of the capacitor MC21 whose one end is grounded to ground (GND), and + 5V applied to the Vcc terminal which is the power supply terminal of the comparator MIC21 is Ripple is removed and smoothed by the capacitor MC21, and the GND terminal, which is the ground terminal of the comparator MIC21, is grounded to ground (GND).

[10-5-2. + 24V power outage or momentary power failure monitoring]
As described above, the monitoring of the + 24V power failure or momentary power failure is performed by comparing the monitoring voltage V1 of the comparator MIC21 with the reference voltage Vref by the MIC21A of the comparator MIC21. As shown in FIG. 23, the third terminal, which is the positive terminal of the MIC21A of the comparator MIC21 to which the monitoring voltage V1 of + 24V is applied, has the other end and one end of the resistor MR21 whose one end is electrically connected to the + 24V power supply line. Is electrically connected to the other end of the resistor MR22 which is grounded to the ground (GND), the other end of the resistors MR21 and MR22, and the other end of the capacitor MC23 whose one end is grounded to the ground (GND). Is electrically connected. The + 24V monitoring voltage V1 applied to the positive terminal 3 of the MIC21A of the comparator MIC21 is divided by + 24V by the resistance ratio of the resistors MR21 and MR22, and the ripple is removed by the capacitor MC23 and smoothed. .. The values of the resistors MR21 and MR22 are the power failure detection voltage V1pf (set to 21.40V in this embodiment) set in advance when + 24V starts to drop from + 24V when the power failure or momentary power failure occurs. At that time, the monitoring voltage V1 of + 24V is set to be the same value as the reference voltage Vref.

The first terminal, which is the output terminal of the MIC21A of the comparator MIC21, has an open collector output, and one end is electrically connected to the other end of the pull-up resistor MR23 which is electrically connected to the + 5V power supply line. One end is electrically connected to the other end of the capacitor MC24 whose one end is grounded to ground (GND), and is electrically connected to the PR terminal which is a preset terminal of the D type flip flop MIC22. The capacitor MC24 plays a role as a low-pass filter.

When the voltage of + 24V is larger than the failure detection voltage V1pf, the monitoring voltage V1 of + 24V becomes larger than the reference voltage Vref, and the voltage applied to the first terminal which is the output terminal of the MIC21A of the comparator MIC21 is + 5V by the pull-up resistor MR23. The signal pulled up to the side and whose logic is HI is input to the PR terminal which is the preset terminal of the D type flip-flop MIC22.

On the other hand, when the + 24V voltage is smaller than the power failure detection voltage V1pf, the + 24V monitoring voltage V1 becomes smaller than the reference voltage Vref, and the voltage applied to the first terminal, which is the output terminal of the MIC21A of the comparator MIC21, is ground (GND). The signal pulled down to the side and the logic becomes LOW is input to the PR terminal which is the preset terminal of the D type flip flop MIC22.

[10-5-3. + 12V power outage or momentary power failure monitoring]
As described above, the monitoring of the + 12V power failure or momentary power failure is performed by comparing the monitoring voltage V2 of the comparator MIC21 with the reference voltage Vref by the MIC21B of the comparator MIC21. As shown in FIG. 23, the 5th terminal, which is the positive terminal of the MIC21B of the comparator MIC21 to which the monitoring voltage V2 of + 12V is applied, has the other end and one end of the resistor MR24 whose one end is electrically connected to the + 12V power supply line. The other end of the resistor MR25, which is grounded to the ground (GND), the other end of the resistors MR24, MR25, and the other end of the capacitor MC25, one end of which is grounded to the ground (GND). Is electrically connected. The + 12V monitoring voltage V2 applied to the 5th terminal, which is the positive terminal of the MIC21B of the comparator MIC21, is divided by + 12V by the resistance ratio of the resistors MR24 and MR25, and the ripple is removed by the capacitor MC25 and smoothed. .. The values of the resistors MR24 and MR25 are the power failure detection voltage V2pf (set to 10.47V in this embodiment) set in advance when + 12V starts to drop from + 12V when the power failure or momentary power failure occurs. At that time, the monitoring voltage V2 of + 12V is set to be the same value as the reference voltage Vref.

The 7th terminal, which is the output terminal of the MIC21B of the comparator MIC21, has an open collector output and is electrically connected to the 1st terminal, which is the output terminal of the MIC21A described above. The preset of the D type flip flop MIC22 is electrically connected to the other end of the pull-up resistor MR23 and is electrically connected to the other end of the capacitor MC24 whose one end is grounded to the ground (GND). It is electrically connected to the PR terminal, which is a terminal. As described above, the capacitor MC24 plays a role as a low-pass filter.

When the + 12V voltage is larger than the failure detection voltage V2pf, the + 12V monitoring voltage V2 becomes larger than the reference voltage Vref, and the voltage applied to the 7th terminal, which is the output terminal of the MIC21B of the comparator MIC21, is + 5V by the pull-up resistor MR23. The signal pulled up to the side and whose logic is HI is input to the PR terminal which is the preset terminal of the D type flip-flop MIC22.

On the other hand, when the + 12V voltage is smaller than the power failure detection voltage V2pf, the + 12V monitoring voltage V2 becomes smaller than the reference voltage Vref, and the voltage applied to the 7th terminal which is the output terminal of the MIC21B of the comparator MIC21 is ground (GND). The signal pulled down to the side and the logic becomes LOW is input to the PR terminal which is the preset terminal of the D type flip flop MIC22.

[10-5-4. Output of power failure warning signal]
The D-type flip-flop MIC22 stores the value (logic) of the signal input to the 1D terminal, which is the D input terminal, due to the change in the edge of the clock signal input to the 1CK terminal, which is the clock input terminal, and this stored value. (Logic) is output from the 1Q terminal which is an output terminal, and the value obtained by inverting the stored value (logic) is output from the negative logic 1Q terminal which is an output terminal. Further, the D type flip-flop MIC22 releases the latch state when a signal whose logic is LOW is input to the CLR terminal which is a clear terminal, and inputs the logic of the signal input to the PR terminal which is a preset terminal. The inverted signal is output from the 1Q terminal which is the output terminal (at this time, the logic of the signal output from 1Q is inverted, that is, the logic of the signal input to the PR terminal which is the preset terminal is the same. (The logic signal is output from the negative logic 1Q terminal) On the other hand, when the signal whose logic is HI is input to the CLR terminal which is the clear terminal, the latch state is set. Further, in the D type flip flop MIC22, when a signal whose logic is HI is input to the CLR terminal which is a clear terminal and the latch state is set, the logic is LOW to the PR terminal which is a preset terminal. When the signal becomes Maintain the state of output from the 1Q terminal).

In the D type flip-flop MIC22, in the present embodiment, the 1D terminal which is the D input terminal and the 1CK terminal which is the clock input terminal are grounded to the ground (GND), so that the 1CK terminal which is the clock input terminal is used. The circuit is configured so that the edge of the input clock signal does not change, and the value (logic) of the signal input to the 1D terminal, which is the D input terminal, is not stored and output from the 1Q terminal, which is the output terminal. ing. As described above, the D-type flip-flop MIC22 has a signal from the output terminal 1 of the MIC21A of the comparator MIC21 for monitoring a + 24V power failure or a momentary power failure and a + 12V power failure at the PR terminal which is a preset terminal. Alternatively, a signal from the 7th terminal, which is the output terminal of the MIC21B of the comparator MIC21 that monitors the momentary power failure, is input, and a signal is output from the 1Q terminal, which is the output terminal, based on these signals. The Vcc terminal, which is a power supply terminal, is electrically connected to the other end of the capacitor MC22 whose one end is grounded to ground (GND), and is applied to the Vcc terminal which is the power supply terminal of the D type flip flop MIC22. + 5V is smoothed by removing ripples by the capacitor MC22, the GND terminal, which is the ground terminal, is grounded to ground (GND), and the negative logic 1Q terminal, which inverts the logic of the 1Q terminal, which is the output terminal, is electrical to the outside. It is not connected.

In the D-type flip-flop MIC22, in the present embodiment, a power failure clear signal from the main control MPU 4100a is input to the CLR terminal, which is a clear terminal, via the main control output circuit 4100ca with a reset function. The power failure clear signal is output started and stopped after a predetermined time has elapsed in the main control side power-on processing described later by the main control MPU4100a. Since the CLR terminal is a negative logic input, the power failure clear signal from the main control MPU 4100a is input to the CLR terminal with its logic LOW via the main control output circuit 4100ca with a reset function. The D-type flip-flop MIC22 is designed to release the latch state when a power failure clear signal is input to the CLR terminal. At this time, the logic input to the PR terminal, which is a preset terminal, is inverted and the output terminal is output. It is output from the 1Q terminal.

On the other hand, when the output of the power failure clear signal from the main control MPU 4100a is stopped, the logic becomes HI and is input to the CLR terminal via the main control output circuit 4100ca with a reset function. The D-type flip-flop MIC 22 is designed to set a latch state when a power failure clear signal is not input to the CLR terminal, and latches the state in which the logic is LOW and is input to the PR terminal.

The 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is electrically connected to the input terminal PA1 of the input port PA of the main control MPU4100a via the main control input circuit 4100b, and is an output terminal of the D-type flip-flop MIC22. The signal output from the 1Q terminal is input to the input terminal PA1 of the input port PA of the main control MPU4100a as a power failure warning signal. Further, the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is electrically connected to the main control output circuit 4100cc without a reset function, and the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is reset. No function It is output from the main control output circuit 4100cc to the payout control board 4110 as a payout power failure warning signal, and is also output to the peripheral control board 4140 as a peripheral power failure warning signal.

As shown in FIG. 23, the main control input circuit 4100b that electrically connects the 1Q terminal which is the output terminal of the D type flip-flop MIC 22 and the input terminal PA1 of the input port PA of the main control MPU 4100a is a D type flip-flop. The 1Q terminal, which is the output terminal of the MIC22, is electrically connected to the other end of the resistance MR26, one end of which is electrically connected to the + 5V power supply line, and electrically to the base terminal of the transistor MTR20 via the resistance MR27. It is connected. In addition to being electrically connected to the resistor MR27, the base terminal of the transistor MTR20 is electrically connected to the other end of the resistor MR28 whose one end is grounded to ground (GND). The emitter terminal of the transistor MTR20 is grounded to ground (GND), and the collector terminal of the transistor MTR20 is electrically connected to the other end of the resistor MR29, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Main control via ICMIC23 (non-inverting buffer ICMIC23 includes eight non-inverting buffer circuits, and the logic of the signal waveform input to one of them (MIC23A) is formatted and output without inverting). It is electrically connected to the input terminal PA1 of the input port PA of the MPU4100a.

The circuit composed of the resistors MR27, MR28, and the transistor MTR20 is a switch circuit that is turned on / off by a signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22.

When the logic of the signal output from the 1Q terminal, which is the output terminal of the D type flip-flop MIC22, is LOW, the voltage applied to the base terminal of the transistor MTR20 is lowered to the ground (GND) side, and the transistor MTR20 is turned off. , The switch circuit will also be turned off. On the other hand, when the logic of the signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC 22 is HI, the voltage applied to the base terminal of the transistor MTR 20 is pulled up to the + 5V side and the transistor MTR 20 is turned on. The switch circuit will also be turned on.

When both the condition that the voltage of + 24V is larger than the failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the failure detection voltage V2pf are satisfied, the signal whose logic is HI is the preset of the D type flip-flop MIC22. Since it is input to the PR terminal, which is a terminal, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, has its logic LOW and is input to the base terminal of the transistor MTR20, so that the transistor MTR20 is Turn off. As a result, the voltage applied to the collector terminal of the transistor MTR20 is pulled up to the + 5V side by the resistor MR29, and the power failure warning signal whose logic becomes HI via the non-inverting buffer ICMIC23 is the input terminal of the input port PA of the main control MPU4100a. It is input to PA1.

On the other hand, when either of the condition that the voltage of + 24V is smaller than the failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D. Since it is input to the PR terminal which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22 becomes HI and is input to the base terminal of the transistor MTR20. This turns on the transistor MTR20. As a result, the voltage applied to the collector terminal of the transistor MTR20 is lowered to the ground (GND) side, and the power failure warning signal whose logic becomes LOW via the non-inverting buffer ICMIC23 is the input terminal of the input port PA of the main control MPU4100a. It is input to PA1.

Further, as shown in FIG. 23, the main control output circuit 4100cc without a reset function, which outputs a signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC 22 to the payout control board 4110 as a payout failure warning signal, is open. The circuit is configured as a collector output type, and the 1Q terminal, which is the output terminal of the D type flip-flop MIC22, is electrically connected to the resistor MR26 of the main control input circuit 4100b described above, and the transistor MTR21 in the previous stage is connected via the resistor MR30. It is electrically connected to the base terminal. In addition to being electrically connected to the resistor MR30, the base terminal of the transistor MTR21 in the previous stage is electrically connected to the other end of the resistor MR31 whose one end is grounded to ground (GND). The emitter terminal of the transistor MTR21 in the previous stage is grounded to ground (GND), and the collector terminal of the transistor MTR21 in the previous stage is electrically connected to the other end of the resistor MR32 whose one end is electrically connected to the + 5V power supply line. At the same time, it is electrically connected to the base terminal of the transistor MTR22 in the subsequent stage via the resistor MR33. The base terminal of the transistor MTR22 in the subsequent stage is electrically connected to the resistance MR33, and is also electrically connected to the other end of the resistance MR34 whose one end is grounded to ground (GND). The emitter terminal of the latter transistor MTR22 is grounded to ground (GND), and the collector terminal of the latter transistor MTR22 is electrically connected to the other end of the capacitor MC26 whose one end is grounded to ground (GND), and is wired. It is electrically connected to the payout control board 4110 via (harness). When the collector terminal of the transistor MTR22 in the subsequent stage is electrically connected to the payout control board 4110 via wiring (harness), the payout control input of the payout control unit 4120 shown in FIG. 12 on the payout control board 4110. In circuit 4120b, one end is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the + 12V power supply line, and the input terminal and electricity of the predetermined input port of the payout control MPU 4120a shown in FIG. Is connected.

The circuit composed of the resistors MR30, MR31, and the transistor MTR21 in the front stage is the switch circuit in the front stage, and the circuit composed of the resistors MR33, MR34, and the transistor MTR22 in the rear stage is the switch circuit in the rear stage, and is a D type flip-flop. It is turned ON / OFF by the signal output from the 1Q terminal which is the output terminal of the MIC 22.

When the logic of the signal output from the 1Q terminal, which is the output terminal of the D type flip flop MIC22, is LOW, the voltage applied to the base terminal of the transistor MTR21 in the previous stage is pulled down to the ground (GND) side, and the transistor in the previous stage The MTR 21 is turned off, the switch circuit in the front stage is also turned off, and the voltage applied to the collector terminal of the transistor MTR 21 in the front stage, which is the voltage applied to the base terminal of the transistor MTR 22 in the rear stage, is raised to the + 5V side by the resistor MR32. By doing so, the transistor MTR22 in the subsequent stage is turned on, and the switch circuit in the subsequent stage is also turned on. On the other hand, when the logic of the signal output from the 1Q terminal, which is the output terminal of the D type flip flop MIC22, is HI, the voltage applied to the base terminal of the transistor MTR21 is pulled up to the + 5V side, and the transistor MTR21 is turned on. The switch circuit in the front stage is also turned on, and the voltage applied to the collector terminal of the transistor MTR21 in the front stage, which is the voltage applied to the base terminal of the transistor MTR22 in the rear stage, is lowered to the ground (GND) side, so that the switch circuit in the rear stage is turned on. The transistor MTR22 is turned off, and the switch circuit in the subsequent stage is also turned off.

When both the condition that the voltage of + 24V is larger than the failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the failure detection voltage V2pf are satisfied, the signal whose logic is HI is the preset of the D type flip-flop MIC22. Since it is input to the PR terminal, which is a terminal, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, has its logic LOW and is input to the base terminal of the transistor MTR21 in the previous stage. Transistor MTR21 is turned off. As a result, the voltage applied to the collector terminal of the transistor MTR21 in the front stage is pulled up to the + 5V side by the resistor MR32 and applied to the base terminal of the transistor MTR22 in the rear stage, so that the transistor MTR22 in the rear stage is turned on. As a result, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is lowered to the ground (GND) side in the payout control board 4110 via the wiring (harness), so that the payout power failure warning signal whose logic is LOW is paid out. It is input to the control board 4110.

On the other hand, when either of the condition that the voltage of + 24V is smaller than the failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D. Since it is input to the PR terminal, which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, has its logic as HI and becomes the base terminal of the transistor MTR21 in the previous stage. Upon input, the transistor MTR21 in the previous stage is turned on. As a result, the voltage applied to the collector terminal of the transistor MTR 21 in the previous stage is lowered to ground (GND) and applied to the base terminal of the transistor MTR 22 in the subsequent stage, so that the transistor MTR 22 in the subsequent stage is turned off. As a result, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is pulled up to the + 12V side by the pull-up resistor in the payout control input circuit 4120b of the payout control unit 4120 in the payout control board 4110 via the wiring (harness). The payout power failure warning signal whose logic is HI is input to the payout control board 4110.

Further, as shown in FIG. 23, the main control output circuit 4100cc without a reset function that outputs the signal output from the 1Q terminal, which is the output terminal of the D type flip-flop MIC 22, to the peripheral control board 4140 as a peripheral power failure warning signal is open. The circuit is configured as a collector output type, and the 1Q terminal, which is the output terminal of the D type flip-flop MIC22, is electrically connected to the resistor MR26 of the main control input circuit 4100b described above, and is the base terminal of the transistor MTR23 via the resistor MR35. Is electrically connected to. In addition to being electrically connected to the resistor MR35, the base terminal of the transistor MTR23 is electrically connected to the other end of the resistor MR36 whose one end is grounded to ground (GND). The emitter terminal of the transistor MTR23 is grounded to ground (GND), and the collector terminal of the transistor MTR23 is electrically connected to the peripheral control board 4140 via wiring (harness). When the collector terminal of the transistor MTR23 is electrically connected to the peripheral control board 4140 via wiring (harness), a peripheral control input circuit (not shown) of the peripheral control unit 4150 in the peripheral control board 4140 shown in FIG. 14 In, one end is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the + 12V power supply line, and is electrically connected to the input terminal of the predetermined input port of the peripheral control MPU 4150a shown in FIG. Be connected.

The circuit composed of the resistors MR35, MR36, and the transistor MTR23 is a switch circuit that is turned on / off by a signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22.

When the logic of the signal output from the 1Q terminal, which is the output terminal of the D type flip-flop MIC22, is LOW, the voltage applied to the base terminal of the transistor MTR23 is lowered to the ground (GND) side, and the transistor MTR23 is turned off. , The switch circuit will also be turned off. On the other hand, when the logic of the signal output from the 1Q terminal, which is the output terminal of the D type flip-flop MIC22, is HI, the voltage applied to the base terminal of the transistor MTR23 is pulled up to the + 5V side, and the transistor MTR23 is turned on. The switch circuit will also be turned on.

When both the condition that the voltage of + 24V is larger than the failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the failure detection voltage V2pf are satisfied, the signal whose logic is HI is the preset of the D type flip-flop MIC22. Since it is input to the PR terminal, which is a terminal, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, has its logic LOW and is input to the base terminal of the transistor MTR23, so that the transistor MTR23 Turn off. As a result, the voltage applied to the collector terminal of the transistor MTR23 is pulled up to the + 12V side by the pull-up resistor in the payout control input circuit of the peripheral control unit 4150 in the peripheral control board 4140 via the wiring (harness), so that the logic is HI. The peripheral power failure warning signal is input to the peripheral control board 4140.

On the other hand, when either of the condition that the voltage of + 24V is smaller than the failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D. Since it is input to the PR terminal which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22 becomes HI and is input to the base terminal of the transistor MTR23. This turns on the transistor MTR23. As a result, the voltage applied to the collector terminal of the transistor MTR23 is lowered to the ground (GND) side in the peripheral control board 4140 via the wiring (harness), so that the peripheral power failure warning signal whose logic is LOW is the peripheral control board. It is input to 4140.

In this way, the main control input circuit 4100b that transmits the signal output from the 1Q terminal that is the output terminal of the D type flip flop MIC 22 to the main control MPU 4100a as a power failure warning signal, and the 1Q terminal that is the output terminal of the D type flip flop MIC 22. There is one transistor in each of the main control output circuit 4100cc without reset function that outputs the signal output from the peripheral control board 4140 as a peripheral power failure warning signal, and the power failure warning signal and peripherals input to the main control MPU 4100a. While the logic is the same as the peripheral power failure warning signal input to the control board 4140, the signal output from the 1Q terminal, which is the output terminal of the D type flip flop MIC 22, is delivered to the payout control board 4110. There is no reset function to output as a power failure warning signal. The main control output circuit 4100cc has two transistors, the front stage and the rear stage, and the logic of the payout power failure warning signal is the logic of the power failure warning signal input to the main control MPU 4100a and its surroundings. The logic is the reverse of the logic of the peripheral power failure warning signal input to the control board 4140, which is different from the logic of the power failure warning signal and the logic of the peripheral power failure warning signal.

Further, the collector terminal of the transistor MTR20 of the main control input circuit 4100b is electrically connected to the other end of the resistor MR29 whose one end is electrically connected to the + 5V power supply line, and the main control MPU4100a is electrically connected via the non-inverting buffer ICMIC23. The collector terminal of the transistor MTR22 in the subsequent stage of the main control output circuit 4100cc without the reset function is electrically connected to the input terminal PA1 of the input port PA of the above, and is a payout control board via a wiring (harness). In the payout control input circuit 4120b of the payout control unit 4120 in 4110, one end is electrically connected to the other end of the pull-up resistor electrically connected to the + 12V power supply line, and the main control output circuit 4100cc without a reset function. The collector terminal of the transistor MTR23 is a pull-up resistor and an electrical one end of which is electrically connected to a + 12V power supply line in the payout control input circuit of the peripheral control unit 4150 in the peripheral control board 4140 via wiring (harness). It is connected to the. This is because the transistor MTR20 of the main control input circuit 4100b and the main control MPU4100a are the main control boards between the collector terminal of the transistor MTR20 of the main control input circuit 4100b and the input terminal PA1 of the input port PA of the main control MPU4100a. Since it is mounted on the 4100, the power failure warning is given by the logic (ON / OFF signal) of the power failure warning signal using + 5V, which is the control reference voltage of the main control MPU 4100a, whereas the main control board 4100 and the payout control board are used. In order to suppress the influence of noise invading the wiring (harness) that electrically connects the boards between the boards of the 4110 and the boards of the main control board 4100 and the peripheral control board 4140, the main control MPU 4100a, A power failure warning is given by the logic (ON / OFF signal) of the power failure warning signal using + 12V, which is a voltage higher than the control reference voltage of + 5V, which is the control reference voltage of the payout control MPU 4120a and the peripheral control MPU 4150a.

[10-6. Various input / output signals to the main control MPU]
Next, various input / output signals to the main control MPU4100a will be described with reference to FIG. 22. In the RXA terminal, which is the serial data input terminal of the serial input port of the main control MPU 4100a, the serial data from the payout control board 4110 shown in FIG. 11 is received as the payer serial data reception signal via the main control input circuit 4100b. .. On the other hand, the TXA terminal and the TXB terminal, which are the serial data output terminals of the serial output port of the main control MPU4100a, use the serial data transmitted from the TXA terminal to the payout control board 4110 as the main payment serial data transmission signal without the reset function. No reset function by transmitting to the circuit 4100cc The main control output circuit 4100cc transmits the main payment serial data transmission signal to the payout control board 4110, and the TXB terminal mainly transmits the serial data to be transmitted to the peripheral control board 4140 shown in FIG. As a peripheral serial data transmission signal, it is transmitted to the main control output circuit 4100cc without a reset function, and the main control output circuit 4100cc without a reset function transmits a main peripheral serial data transmission signal to the peripheral control board 4140.

In addition to the above-mentioned operation signal (RAM clear signal) being input to each input terminal of the predetermined input port of the main control MPU4100a, for example, a payout notifying that the above-mentioned main payment serial data reception signal has been normally received. The payer ACK signal from the control board 4110 is input via the main control input circuit 4100b, and the detection signals from various switches such as the upper start port switch 3022 shown in FIG. 11 are input via the main control input circuit 4100b. It is input and so on.

On the other hand, from each output terminal of the predetermined output port of the main control MPU 4100a, for example, the main payment ACK signal indicating that the normal reception of the above-mentioned payer serial data reception signal is completed is output to the main control output circuit 4100ca with a reset function. Then, the main pay ACK signal is output from the main control output circuit 4100ca with a reset function to the payout control board 4110, or the drive signal is sent to the main control output circuit 4100ca with a reset function for the start port solenoid 2105 shown in FIG. Outputs a drive signal from the main control output circuit 4100ca with a reset function to the start port solenoid 2105 via the main control solenoid drive circuit 4100d, and various indicators such as the upper special symbol display 1185 shown in FIG. On the other hand, the drive signal is output to the main control output circuit 4100ca with a reset function, and the drive signal is output to various indicators from the main control output circuit 4100ca with a reset function.

[10-7. Interface circuit for communication between the main control board and the peripheral control board]
Next, a communication interface circuit between the main control board 4100 and the peripheral control board 4140 will be described with reference to FIG. 24. In the main control board 4100, + 12V from the power supply board 851 shown in FIG. 20 is supplied via the payout control board 4110, and the + 5V creation circuit 4100g creates + 5V, which is the control reference voltage of the main control MPU 4100a, from this + 12V. ing. The main peripheral serial data transmission signal transmitted from the main control board 4100 to the peripheral control board 4140 is affected by noise that invades the wiring (harness) that electrically connects the main control board 4100 and the peripheral control board 4140. In order to suppress the noise, the reliability is enhanced by transmitting using + 12V, which is a voltage higher than the control reference voltage of the main control MPU4100a, which is + 5V.

Specifically, the main control board 4100 makes the main control output circuit 4100 kb without a reset function function as a communication interface circuit, and the communication interface circuit mainly comprises a resistor MR50, a resistor MR51, an MR52, and a transistor MTR50. Has been done. On the other hand, the peripheral control board 4140 has a diode AD10, an electrolytic capacitor AC10 (capacitance: 47 μF in this embodiment), and a photocoupler AIC10 (infrared LED and photoIC) as communication interface circuits. It is mainly composed of.).

+ 12V supplied from the power supply board 851 is applied to the anode terminal of the diode MD50 of the main control board 4100 via the payout control board 4110, and the negative terminal is grounded to the ground (GND) to the cathode terminal of the diode MD50. It is electrically connected to the positive terminal of the electrolytic capacitor MC50 (capacitance: 220 microfarad (μF) in this embodiment). The cathode terminal of the diode MD50 is electrically connected to the positive terminal of the electrolytic capacitor MC50, and is also electrically connected to the anode terminal (terminal 1) of the photocoupler AIC10 of the peripheral control board 4140 via wiring (harness). It is connected to the. As a result, when the power from the power supply board 851 is not supplied to the main control board 4100 via the payout control board 4110 due to, for example, a power failure or a momentary power failure, the charge charged in the electrolytic capacitor MC50 is charged. As + 12V, it can be continuously applied from the main control board 4100 to the anode terminal of the photocoupler AIC10 of the peripheral control board 4140.

As described above, the VDD terminal, which is the power supply terminal of the main control MPU4100a, is charged to the electrolytic capacitor MC2 (capacitance: 470 μF in this embodiment) shown in FIG. 22 when a power failure or a momentary power failure occurs. Since the charged charge is applied as + 5V, the main peripheral serial transmission port 4100ae built in the main control MPU 4100a serially manages at least the command set by the main control CPU core 4100aa in the transmission buffer register 4100aeb. The unit 4100aec can transfer the data to the transmission shift register 41aea and complete the transmission as main peripheral serial data from the transmission shift register 4100aea.

As described above, the main peripheral serial data transmission signal transmitted from the main control board 4100 to the peripheral control board 4140 is connected to the wiring (harness) that electrically connects the boards between the main control board 4100 and the peripheral control board 4140. In order to suppress the influence of invading noise, the reliability is enhanced by transmitting using + 12V, which is a voltage higher than + 5V, which is the control reference voltage of the main control MPU4100a.

Therefore, in the present embodiment, when a power failure or a momentary power failure occurs, the charge charged in the electrolytic capacitor MC50 is applied as + 12V from the main control board 4100 to the anode terminal of the photocoupler AIC10 of the peripheral control board 4140. Therefore, the main peripheral serial transmission port 4100ae built in the main control MPU 4100a transfers the command set by the main control CPU core 4100aa to the transmission buffer register 4100aeb to the transmission shift register 41aea by the serial management unit 4100aec and transmits the command. When transmitted as main-circle serial data from the shift register 4100ea, a main-circle serial data transmission signal whose logic is HI can be transmitted from the collector terminal of the transistor MTR50 by + 12V.

In the present embodiment, the storage capacity of the transmission buffer register 4100aeb of the main peripheral serial transmission port 4100ae built in the main control MPU 4100a has 32 bytes, and one packet is composed of 3 bytes of data. Therefore, data for a maximum of 10 packets is stored in the transmission buffer register 4100aeb. Further, in the present embodiment, the transfer bit rate of the main peripheral serial data transmitted from the main control MPU 4100a is set to 19200 bps.

The cathode terminal (terminal 3) of the photocoupler AIC10 is electrically connected to the collector terminal of the transistor MTR50 of the main control board 4100 via the resistor AR10 and its wiring (harness). The resistor AR10 of the peripheral control board 4140 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler AIC10.

The TXB terminal that outputs the main peripheral serial data transmission signal from the main control MPU4100a shown in FIG. 22 is electrically connected to the other end of the resistance MR50 whose one end is electrically connected to the + 5V power supply line and also to connect the resistance MR51. It is electrically connected to the base terminal of the transistor MTR50 via. In addition to being electrically connected to the resistance MR51, the base terminal of the transistor MTR50 is electrically connected to the other end of the resistance MR52 whose one end is grounded to ground (GND). The emitter terminal of the transistor MTR50 is grounded to ground (GND).

The circuit composed of the resistors MR51, MR52, and the transistor MTR50 is a switch circuit, and when the logic of the main peripheral serial data transmission signal is HI, the voltage applied to the base terminal of the transistor MTR50 is on the ground (GND) side. When it is pulled down, the transistor MTR50 is turned off, and the switch circuit is also turned off. As a result, no forward current flows through the built-in infrared LED of the photocoupler AIC10 of the peripheral control board 4140, so that the photocoupler AIC10 is turned off. On the other hand, when the logic of the main peripheral serial data transmission signal is LOW, the voltage applied to the base terminal of the transistor MTR50 is pulled up to the + 5V side by the resistor MR50, the transistor MTR50 is turned on, and the switch circuit is also turned on. .. As a result, a forward current flows through the built-in infrared LED of the photocoupler AIC10 of the peripheral control board 4140, so that the photocoupler AIC10 is turned on.

+ 5V supplied from the power supply board 851 is applied to the anode terminal of the diode AD10 of the peripheral control board 4140 via the frame peripheral relay terminal board 868, and the cathode terminal of the diode AD10 has the negative terminal as ground (GND). It is electrically connected to the positive terminal of the grounded electrolytic capacitor AC10. The cathode terminal of the diode AD10 is electrically connected to the positive terminal of the electrolytic capacitor AC10, and is also electrically connected to the Vcc terminal (terminal 6) which is the power supply terminal of the photocoupler AIC10. The emitter terminal (terminal 4) of the photocoupler AIC10 is grounded to ground (GND), and the collector terminal (terminal 5) of the photocoupler AIC10 is a pull-up resistor electrically connected to the positive terminal of the electrolytic capacitor AC10. It is pulled up to the + 5V side by AR11 and is electrically connected to the input terminal of the serial I / O port for the main control board of the peripheral control MPU4150a. When the photocoupler AIC10 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler AIC10 changes, and the signal is used as the main peripheral serial data transmission signal to be the serial I / O port for the main control board of the peripheral control MPU4150a. It is input to the input terminal of.

As a result, as described above, when + 5V supplied from the power supply board 851 is not supplied to the peripheral control board 4140 via the frame peripheral relay terminal board 868 due to, for example, a power failure or a momentary power failure. The electric charge charged in the electrolytic capacitor AC10 can be continuously applied to the Vcc terminal of the photocoupler AIC10 as + 5V. When + 5V is applied from the electrolytic capacitor AC10 when an electric power or momentary power failure occurs, the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 is sent to the main control MPU 4100a. The data set in the transmission buffer register 4100aeb of the built-in main peripheral serial transmission port 4100ae can be completed, and the main peripheral serial data transmission signal during transmission, that is, the main peripheral serial data is cut off. The peripheral control board 4140 ensures that the data is received without any omission or omission.

When the logic of the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 is HI, the voltage applied to the base terminal of the transistor MTR50 is pulled down to the ground (GND) side and the transistor. Since the photocoupler AIC10 is turned off when the MTR50 is turned off, the voltage applied to the collector terminal of the photocoupler AIC10 is pulled up to the + 5V side by the pull-up resistor AR11, and the logic becomes HI. The logic of the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 while the serial data transmission signal is input to the input terminal of the serial I / O port for the main control board of the peripheral control MPU 4150a. When is LOW, the voltage applied to the base terminal of the transistor MTR50 is pulled up to the + 5V side by the resistor MR50, and the transistor MTR50 is turned on to turn on the photocoupler AIC10. Therefore, the photocoupler AIC10 is turned on. The main peripheral serial data transmission signal whose logic is LOW when the voltage applied to the collector terminal is lowered to the ground (GND) side is input to the input terminal of the serial I / O port for the main control board of the peripheral control MPU4150a. .. As described above, the logic of the main peripheral serial data transmission signal output from the collector terminal of the photocoupler AIC10 is the same as the logic of the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140. It is the logic of.

As described above, in the present embodiment, the + 5V power supply line to which the control reference voltage of the main control MPU4100a is applied and the + 12V power supply line to which the communication voltage of + 12V applied via the diode MD50 is applied. However, measures are taken when a power failure or momentary power failure occurs and the control reference voltage and communication voltage drop. That is, for the main peripheral serial transmission port 4100ae built in the main control MPU 4100a, a + 5V power supply line, a positive terminal of the electrolytic capacitor MC2 using the electrolytic capacitor MC2 of the main control filter circuit 4100h as the first auxiliary power supply, and Even if the control reference voltage applied from the + 5V power supply line drops due to a power failure or momentary power failure due to the electrical parallel connection, the electrolytic capacitor of the main control filter circuit 4100h, which is the first auxiliary power supply. By applying the control reference voltage from the positive terminal of the MC2, the state in which the control reference voltage is applied can be maintained, and it is composed of the resistors MR50, the resistors MR51, MR52, and the transistor MTR50. For the main control output circuit 4100cc without reset function to function as a communication interface circuit, + 12V applied to the + 12V power supply line is applied to the anode terminal of the diode MD50 as a communication voltage, and the cathode terminal of this diode MD50. And the positive terminal of the electrolytic capacitor MC50, which is the second auxiliary power supply, are electrically connected in parallel, so that a power failure or momentary power failure occurs and the voltage is applied from the + 12V power supply line via the diode MD50. Even if the voltage drops, the communication voltage from the positive terminal of the electrolytic capacitor MC50, which is the second auxiliary power supply, is applied, so that the state in which the communication voltage is applied can be maintained. There is. As a result, it is possible to prevent the command being transmitted from the main control board 4100 to the peripheral control board 4140 to be interrupted and to prevent the command from being omitted, so that the peripheral control board 4140 reliably receives the command being transmitted. can do. Therefore, it is possible to eliminate the omission of a command immediately after the occurrence of a power failure or at the time of a momentary power failure.

Further, a plurality of commands set in the transmission buffer register 4100aeb of the main circuit serial transmission port 4100ae built in the main control MPU4100a are all composed of resistors MR50, resistors MR51, MR52, and transistor MTR50 as main circuit serial data. No reset function to function as a communication interface circuit 470μF is set as the capacitance of the electrolytic capacitor MC2 of the main control filter circuit 4100h so that transmission to the peripheral control board 4140 can be completed via the main control output circuit 4100cc. The capacitance of the electrolytic capacitor MC50 is set to 220 μF. As a result, even if a power failure or momentary power failure occurs during transmission from the main control board 4100 to the peripheral control board 4140, all the commands set in the transmission buffer register 4100aeb are reset to function as an interface circuit as main peripheral serial data. Since transmission to the peripheral control board 4140 can be completed via the functionless main control output circuit 4100cc, the peripheral control board 4140 does not interrupt and omits a plurality of commands set in the transmission buffer register 4100aeb. It can be received reliably without any problems.

[11. Circuit of payout control board]
Next, the circuit and the like of the payout control board 4110 shown in FIG. 12 will be described with reference to FIGS. 25 to 30. 25 is a circuit diagram showing a circuit of a payout control unit and the like, FIG. 26 is a circuit diagram showing a payout control input circuit, FIG. 27 is a circuit diagram showing a continuation of FIG. 26, and FIG. 28 is a payout motor drive. FIG. 29 is a circuit diagram showing a circuit, FIG. 29 is a circuit diagram showing a CR unit input / output circuit, and FIG. 30 is an input / output diagram showing various input / output signals to and from the main control board and various output signals to an external terminal board. Is. First, the payout control filter circuit will be described, and then the circuit of the payout control unit, various input / output signals with the main control board, and various output signals to the external terminal board will be described.

[11-1. Payout control filter circuit]
As shown in FIG. 25, the payout control filter circuit 4110a mainly comprises the payout control 3-terminal filter PIC0. This payout control 3-terminal filter PIC0 is a T-type filter circuit, and is magnetically shielded with ferrite and has excellent attenuation characteristics. + 5V from the power supply board 851 shown in FIG. 20 is applied to the 1st terminal of the payout control 3 terminal filter PIC0, and one end is electrically connected to the other end of the capacitor PC0 grounded to the ground (GND). + 5V from the power supply board 851 is first smoothed by removing ripples (AC components folded by the voltage) by the capacitor PC0. The 2nd terminal of the payout control 3 terminal filter PIC0 is grounded to ground (GND), and the 3rd terminal of the payout control 3 terminal filter PIC0 outputs + 5V from which the noise component is removed.

The third terminal of the payout control three-terminal filter PIC0 is the other end of the capacitor PC1 and the electrolytic capacitor PC2 (capacitance: 180 microfarad (μF) in this embodiment) whose one end is grounded to ground (GND). By being electrically connected to each, ripples are further removed from + 5V output from the 3rd terminal of the payout control 3 terminal filter PIC0 and smoothed. This smoothed + 5V is applied to the power supply terminal of the payout control system reset PIC1, the VCS terminal which is the power supply terminal of the payout control crystal oscillator PX0, the VDD terminal which is the power supply terminal of the payout control MPU4120a, and the like, which will be described later. ..

The VDD terminal of the payout control MPU4120a is electrically connected to the other end of the capacitor PC3 whose one end is grounded to ground (GND), and the + 5V applied to the VDD terminal is further smoothed by removing ripples by the capacitor PC3. ing. The VSS terminal, which is the ground terminal of the payout control MPU4120a, is grounded to the ground (GND).

Further, the VDD terminal of the payout control MPU4120a is electrically connected to the anode terminal of the diode PD0 in addition to being electrically connected to the capacitor PC3. The cathode terminal of the diode PD0 is electrically connected to the VBB terminal, which is the power supply terminal of the RAM (RAM with built-in payout control) built in the payout control MPU4120a, and one end of the capacitor PC4 is grounded to ground (GND). It is electrically connected to the other end of the. The VBB terminal of the RAM with built-in payout control is electrically connected to the cathode terminal of the diode PD0 and the other end of the capacitor PC4, and the plus of the capacitor BC1 of the power supply board 851 shown in FIG. 20 via the resistor PR0. It is electrically connected to the terminal. That is, + 5V smoothed by removing the noise component by the payout control filter circuit 4110a is applied to the VDD terminal of the payout control MPU4120a, and is applied to the VBB terminal of the RAM with built-in payout control and the capacitor BC1 via the diode PD0. It is designed to be applied to the positive terminal of. As a result, as described above, when the + 5V created by the power supply creation circuit 855d of the power supply board 851 shown in FIG. 20 is no longer supplied to the payout control board 4110, the charge charged in the capacitor BC1 is paid VBB. Since the electric charge is supplied to the payout control board 4110, the current is obstructed by the diode PD0 in the VDD terminal of the payout control MPU4120a and the payout control MPU4120a does not operate, but the payout control MPU4120a does not operate. The stored contents are retained by applying the pay VBB.

[11-2. Circuit of payout control unit]
In addition to the payout control MPU 4120a, the payout control input circuit 4120b, the payout control output circuit 4120c, the payout motor drive circuit 4120d, and the CR unit input / output circuit 4120e, the payout control unit 4120 resets as a peripheral circuit as shown in FIG. The payout control system reset PIC1 that outputs a signal and the payout control crystal oscillator PX0 (in this embodiment, 8 megahertz (MHz)) that outputs a clock signal are mainly configured. Here, the payout control system reset will be described first, and then the payout control crystal oscillator, the payout control input circuit, the payout motor drive circuit, the CR unit input / output circuit, and various input / output signals to the payout control MPU will be described.

[11-2-1. Payout control system reset]
As shown in FIG. 25, + 5V smoothed by removing the noise component by the payout control filter circuit 4110a is applied to the power supply terminal of the payout control system reset PIC1. The payout control system reset PIC1 resets the payout control MPU 4120a and the payout control output circuit 4120ca with a reset function, respectively, and has a built-in delay circuit. The delay capacitance terminal of the payout control system reset PIC1 is electrically connected to the other end of the capacitor PC5 whose one end is grounded to ground (GND), and the delay time by the delay circuit is set by the capacitance of this capacitor PC5. You can do it. Specifically, the payout control system reset PIC1 outputs a system reset signal from the output terminal after the delay time elapses when the + 5V input to the power supply terminal reaches the threshold value (for example, 4.25V).

The output terminal of the payout control system reset PIC1 is electrically connected to the SRT0 terminal, which is the reset terminal of the payout control MPU4120a, and the reset terminal of the payout control output circuit 4120ca with a reset function, respectively. The output terminal is an open collector output type, and is a capacitor whose one end is electrically connected to the other end of the pull-up resistor PR1 which is electrically connected to the + 5V power supply line and one end is grounded to ground (GND). It is electrically connected to the other end of the PC 6. This capacitor PC6 plays a role as a low-pass filter. When the voltage input to the power supply terminal is larger than the threshold value, the output terminal is pulled up to the + 5V side by the pull-up resistor PR1 and the logic becomes HI, and this logic becomes the SRT0 terminal of the payout control MPU4120a and the payout control output with a reset function. While each is input to the reset terminal of the circuit 4120ca, when the voltage input to the power supply terminal is smaller than the threshold value, the logic becomes LOW, and this logic becomes the SRT0 terminal of the payout control MPU 4120a and the payout control output circuit 4120ca with a reset function. It is input to each reset terminal. Since the SRT0 terminal of the payout control MPU4120a and the reset terminal of the payout control output circuit 4120ca with a reset function are each negative logic inputs, when the voltage input to the power supply terminal becomes smaller than the threshold value, the payout control MPU4120a and the reset function The payout control output circuit 4120ca is reset. The power supply terminal is electrically connected to the other end of the capacitor PC7 whose one end is grounded to ground (GND), and the + 5V input to the power supply terminal is smoothed by removing ripples. Further, the ground terminal is grounded to the grant (GND), and the NC terminal is not electrically connected to the outside.

[11-2-2. Payout control crystal oscillator]
As shown in FIG. 25, the + 5V smoothed by removing the noise component by the payout control filter circuit 4110a is input to the VCS terminal which is the power supply terminal of the payout control crystal oscillator PX0. This VCS terminal is electrically connected to the other end of the capacitor PC8 whose one end is grounded to ground (GND), and the + 5V input to the VCS terminal is further smoothed by removing ripples. Further, this smoothed + 5V is applied not only to the VCS terminal but also to the OE terminal which is the output enable terminal of the payout control crystal oscillator PX0. The payout control crystal oscillator PX0 outputs a clock signal of 8 MHz from the OUT terminal, which is an output terminal, by applying + 5 V to its OE terminal.

The OUT terminal of the payout control crystal oscillator PX0 is electrically connected to the MCLK terminal, which is the clock terminal of the payout control MPU4120a, and an 8 MHz clock signal is input to the payout control MPU4120a. The GND terminal, which is the ground terminal of the payout control crystal oscillator PX0, is grounded to the grant (GND).

[11-2-3. Payout control input circuit]
The payout control input circuit 4120b is input with a payout power failure warning signal from the power failure monitoring circuit 4100e provided in the door frame opening switch 618, the main body frame opening switch 619, and the main control board 4100 shown in FIG. The circuit, the handle relay terminal plate 192 shown in FIG. 12, the circuit in which the detection signal from the full tank switch 550 is input via the power supply board 851, the circuit in which the operation signal from the operation switch 860a is input, and the like. First, the circuit in which the detection signal from the door frame open switch is input will be described, followed by the circuit in which the detection signal from the main body frame open switch is input, the circuit in which the payout power failure warning signal from the power failure monitoring circuit is input, and the circuit in which the payout power failure warning signal from the power failure monitoring circuit is input. A circuit in which a detection signal from a full tank switch is input and a circuit in which an operation signal from an operation switch is input will be described. Since the output terminals of various detection switches such as the full tank switch 550, the ball-out switch 750, the counting switch 751, and the rotation angle switch 752 shown in FIG. 12 are open collector output types, the various detection switches can be used. Since the circuit configuration in which the detection signal of the above is input is almost the same, a circuit in which the detection signal from the full tank switch is input will be described here.

[11-2-3 (a). Circuit to which the detection signal from the door frame open switch is input]
The door frame opening switch 618 uses a normally closed type (normally closed (NC)), and the switch is turned on (conducting) while the door frame 5 is opened from the main body frame 3 as shown in FIG. 1, and the door frame is turned on. The switch is turned off (disconnected) when 5 is closed to the main body frame 3. The 2nd terminal of the door frame opening switch 618 is grounded to the ground (GND), while the 1st terminal of the door frame opening switch 618 has a pull-up resistor PR20 whose one end is electrically connected to the + 5V power supply line. It is electrically connected to the end and is also electrically connected to the base terminal of the transistor PTR 20 via the resistor PR21. In addition to being electrically connected to the resistor PR21, the base terminal of the transistor PTR20 is electrically connected to the other end of the resistor PR22 whose one end is grounded to ground (GND). Further, the first terminal of the door frame opening switch 618 is electrically connected to the pull-up resistor PR20, and is also electrically connected to the other end of the capacitor PC20 whose one end is grounded to the ground (GND). .. The emitter terminal of the transistor PTR20 is grounded to ground (GND), and the collector terminal of the transistor PTR20 is electrically connected to the other end of the resistor PR23, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Disbursement control via ICPIC20 (non-inverting buffer ICPIC20 includes eight non-inverting buffer circuits, and formats and outputs the logic of the signal waveform input to one of them (PIC20A) without inverting it). It is electrically connected to the input terminal PA0 of the input port PA of the MPU4120a. When the transistor PTR 20 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR 20 changes, and the signal is input to the input terminal PA0 of the input port PA of the payout control MPU4120a as a door opening signal.

Further, the first terminal of the door frame opening switch 618 is pulled up to the + 5V side by the pull-up resistor PR20 and is electrically connected to the base terminal of the transistor PTR20 via the resistor PR21, and is also connected to the + 5V side by the pull-up resistor PR20. It is pulled up to and electrically connected to the base terminal of the transistor PTR21 via the resistor PR24. In addition to being electrically connected to the resistor PR24, the base terminal of the transistor PTR21 is electrically connected to the other end of the resistor PR25 whose one end is grounded to ground (GND). The emitter terminal of the transistor PTR21 is grounded to ground (GND), and the collector terminal of the transistor PTR21 is electrically connected to the external terminal board 784 via wiring (harness). When the collector terminal of the transistor PTR21 is electrically connected to the external terminal board 784 via wiring (harness), one end of the external terminal board 784 is electrically connected to the + 12V power supply line, which is not shown. It is electrically connected to the other end of the up resistor. When the transistor PTR 21 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR 21 changes, and the signal is input to the external terminal board 784 as the outer end frame door opening information output signal.

Further, the first terminal of the door frame opening switch 618 is pulled up to the + 5V side by the pull-up resistor PR20 and is electrically connected to the base terminal of the transistor PTR20 via the resistor PR21, and is also connected to the + 5V side by the pull-up resistor PR20. In addition to being pulled up to the base terminal of the transistor PTR21 via the resistor PR24, it is pulled up to the + 5V side by the pull-up resistor PR20 and electrically connected to the base terminal of the transistor PTR22 via the resistor PR26. ing. In addition to being electrically connected to the resistor PR26, the base terminal of the transistor PTR22 is electrically connected to the other end of the resistor PR27 whose one end is grounded to ground (GND). The emitter terminal of the transistor PTR22 is grounded to ground (GND), and the collector terminal of the transistor PTR22 is electrically connected to the main control board 4100 shown in FIG. 11 via wiring (harness). When the collector terminal of the transistor PTR22 is electrically connected to the main control board 4100 via wiring (harness), one end of the main control input circuit 4100b of the main control board 4100 shown in FIG. 11 is a + 12V power supply. It is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the line. When the transistor PTR22 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR22 changes, and the signal is input to the main control board 4100 as the main frame door opening signal.

The circuit composed of the pull-up resistor PR20 and the capacitor PC20 is a switch signal generation circuit, and when the door frame 5 is opened from the main body frame 3 or when the door frame 5 is closed by the main body frame 3. It is configured as a circuit having a function of absorbing voltage fluctuations from the door frame opening switch 618 due to a fluttering phenomenon in which the contacts constituting the door frame opening switch 618 are repeatedly turned on and off for a short time.

The circuit composed of the resistors PR21, PR22 and the transistor PTR20, the circuit composed of the resistors PR24, PR25 and the transistor PTR21, and the circuit composed of the resistors PR26, PR27 and the transistor PTR22 are door frame open switches. It is a switch circuit that turns ON / OFF by the detection signal from 618.

When the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is turned on, so that the voltage applied to the base terminal of the transistor PTR 20 is lowered to the ground (GND) side, so that the transistor PTR 20 is opened. It will be turned off and the switch circuit will also be turned off. As a result, the voltage applied to the collector terminal of the transistor PTR20 is pulled up to the + 5V side by the pull-up resistor PR23, and the door frame opening signal whose logic is HI is input to the input terminal PA0 of the input port PA of the payout control MPU4120a. To. Further, in the state where the door frame 5 is opened from the main body frame 3, since the door frame opening switch 618 is turned on, the voltage applied to the base terminal of the transistor PTR21 is lowered to the ground (GND) side, so that the transistor is used. The PTR 21 will be turned off and the switch circuit will also be turned off. As a result, the voltage applied to the collector terminal of the transistor PTR21 is pulled up to the + 12V side by the pull-up resistance of the external terminal board 784 via the wiring (harness), and the logic becomes HI. Is input to the external terminal board 784. Further, in the state where the door frame 5 is opened from the main body frame 3, since the door frame opening switch 618 is turned on, the voltage applied to the base terminal of the transistor PTR 22 is lowered to the ground (GND) side, so that the transistor is used. The PTR 22 will be turned off and the switch circuit will also be turned off. As a result, the voltage applied to the collector terminal of the transistor PTR22 is pulled up to the + 12V side by the pull-up resistance of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. The door opening signal is input to the main control board 4100.

On the other hand, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is turned off, so that the voltage applied to the base terminal of the transistor PTR 20 is pulled up to the + 5V side by the pull-up resistor PR20. Then, the transistor PTR20 is turned on, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR 20 is lowered to the ground (GND) side, and the door frame opening signal whose logic is LOW is input to the input terminal PA0 of the input port PA of the payout control MPU4120a. Further, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is turned off, so that the voltage applied to the base terminal of the transistor PTR 21 is raised to the + 5 V side, so that the transistor PTR 21 is turned on. However, the switch circuit will also be turned on. As a result, the voltage applied to the collector terminal of the transistor PTR 21 is lowered to the ground (GND) side, and the outer end frame door opening information output signal whose logic is LOW is input to the external terminal board 784. Further, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is turned off, so that the voltage applied to the base terminal of the transistor PTR 22 is raised to the + 5 V side, so that the transistor PTR 22 is turned on. However, the switch circuit will also be turned on. As a result, the voltage applied to the collector terminal of the transistor PTR 22 is lowered to the ground (GND) side, and the main frame door opening signal whose logic is LOW is input to the main control board 4100.

In this way, when the door frame 5 is opened from the main body frame 3, when the door frame opening switch 618 is turned on, the door frame opening signal whose logic is HI is the input terminal of the input port PA of the payout control MPU4120a. The outer end frame door opening information output signal input to PA0 and whose logic is HI is input to the external terminal board 784, and the main frame door opening signal whose logic is HI is input to the main control board 4100. When the door frame 5 is closed to the main body frame 3, the door frame opening switch 618 is turned off, so that the door frame opening signal whose logic is LOW is input to the input terminal PA0 of the input port PA of the payout control MPU4120a. , The outer end frame door opening information output signal whose logic is LOW is input to the external terminal board 784, and the main frame door opening signal whose logic is LOW is input to the main control board 4100.

[11-2-3 (b). Circuit to which the detection signal from the main body frame open switch is input]
The main body frame opening switch 619 uses a normally closed type (normally closed (NC)), and the switch is turned on (conducting) while the main body frame 3 is opened from the outer frame 2 as shown in FIG. 1, and the main body frame is turned on. The switch is turned off (disconnected) when 3 is closed to the outer frame 2. The 2nd terminal of the main body frame opening switch 619 is grounded to the ground (GND), while the 1st terminal of the main body frame opening switch 619 has a pull-up resistor PR28 whose one end is electrically connected to the + 5V power supply line. It is electrically connected to the end and is also electrically connected to the base terminal of the transistor PTR23 via the resistor PR29. In addition to being electrically connected to the resistor PR29, the base terminal of the transistor PTR23 is electrically connected to the other end of the resistor PR30 whose one end is grounded to ground (GND). Further, the first terminal of the main body frame opening switch 619 is electrically connected to the pull-up resistor PR28, and is also electrically connected to the other end of the capacitor PC21 whose one end is grounded to the ground (GND). .. The emitter terminal of the transistor PTR23 is grounded to ground (GND), and the collector terminal of the transistor PTR23 is electrically connected to the collector terminal of the transistor PTR21 described above, and is connected to the external terminal board 784 via wiring (harness). It is electrically connected. When the collector terminal of the transistor PTR23 is electrically connected to the external terminal board 784 via wiring (harness), one end of the external terminal board 784 is electrically connected to the + 12V power supply line, which is not shown. It is electrically connected to the other end of the up resistor. When the transistor PTR23 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR23 changes, and the signal is input to the external terminal board 784 as the outer end frame door opening information output signal.

Further, the first terminal of the main body frame opening switch 619 is pulled up to the + 5V side by the pull-up resistor PR28 and is electrically connected to the base terminal of the transistor PTR23 via the resistor PR29, and is also connected to the + 5V side by the pull-up resistor PR28. It is pulled up to and electrically connected to the base terminal of the transistor PTR24 via the resistor PR31. In addition to being electrically connected to the resistor PR31, the base terminal of the transistor PTR24 is electrically connected to the other end of the resistor PR32 whose one end is grounded to ground (GND). The emitter terminal of the transistor PTR24 is grounded to ground (GND), and the collector terminal of the transistor PTR24 is electrically connected to the collector terminal of the transistor PTR22 described above, and is shown in FIG. 11 via wiring (harness). It is electrically connected to the main control board 4100. When the collector terminal of the transistor PTR24 is electrically connected to the main control board 4100 via wiring (harness), one end of the main control input circuit 4100b of the main control board 4100 shown in FIG. 11 is a + 12V power supply. It is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the line. When the transistor PTR 24 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR 24 changes, and the signal is input to the main control board 4100 as the main frame door opening signal.

The circuit composed of the pull-up resistor PR28 and the capacitor PC21 is a switch signal generation circuit, and when the main body frame 3 is opened from the outer frame 2 or when the main body frame 3 is closed by the outer frame 2. It is configured as a circuit having a function of absorbing voltage fluctuations from the main body frame opening switch 619 due to a fluttering phenomenon in which the contacts constituting the main body frame opening switch 619 are repeatedly turned on and off for a short time.

The circuit composed of the resistors PR29, PR30 and the transistor PTR23 and the circuit composed of the resistors PR31, PR32 and the transistor PTR24 are switch circuits that are turned ON / OFF by the detection signal from the main body frame opening switch 619.

In the state where the main body frame 3 is opened from the outer frame 2, since the main body frame opening switch 619 is ON, the voltage applied to the base terminal of the transistor PTR23 is lowered to the ground (GND) side, so that the transistor PTR23 is opened. It will be turned off and the switch circuit will also be turned off. As a result, the voltage applied to the collector terminal of the transistor PTR23 is pulled up to the + 12V side by the pull-up resistor of the external terminal board 784 via the wiring (harness), and the logic becomes HI. Is input to the external terminal board 784. Further, in the state where the main body frame 3 is opened from the outer frame 2, since the main body frame opening switch 619 is ON, the voltage applied to the base terminal of the transistor PTR 24 is lowered to the ground (GND) side, so that the transistor is used. The PTR 24 will be turned off and the switch circuit will also be turned off. As a result, the voltage applied to the collector terminal of the transistor PTR24 is pulled up to the + 12V side by the pull-up resistance of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. The door opening signal is input to the main control board 4100.

On the other hand, in the state where the main body frame 3 is closed to the outer frame 2, since the main body frame opening switch 619 is turned off, the voltage applied to the base terminal of the transistor PTR23 is pulled up to the + 5V side by the pull-up resistor PR28. Then, the transistor PTR23 is turned on, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR23 is lowered to the ground (GND) side in the external terminal board 784 via the wiring (harness), and the logic becomes LOW. It is input to the external terminal board 784. Further, in the state where the main body frame 3 is closed to the outer frame 2, since the main body frame opening switch 619 is turned off, the voltage applied to the base terminal of the transistor PTR 24 is pulled up to the + 5V side by the pull-up resistor PR28. Then, the transistor PTR24 is turned on, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR24 is lowered to the ground (GND) side in the main control board 4100 via the wiring (harness), and the main frame door opening signal whose logic is LOW is the main control board. It is input to 4100.

In this way, when the main body frame 3 is released from the outer frame 2, the outer end frame door opening information output signal whose logic is HI is input to the external terminal board 784 by turning on the main body frame opening switch 619. The main frame door opening signal whose logic is HI is input to the main control board 4100, while the main body frame opening switch 619 is turned off in a state where the main body frame 3 is closed to the outer frame 2, thereby making the logic. The outer end frame door opening information output signal whose logic is LOW is input to the external terminal board 784, and the main frame door opening signal whose logic is LOW is input to the main control board 4100.

In the present embodiment, as described above, one or both of the state in which the door frame 5 is closed to the main body frame 3 and the state in which the main body frame 3 is opened from the outer frame 2 are in the present embodiment. Even in the case of, since the main frame door opening signal is input to the main control board 4100, the main control MPU 4100a of the main control board 4100 shown in FIG. 11 is the main frame door opening signal. Although it is not possible to determine whether the door frame 5 is open from the main body frame 3 or the main body frame 3 is open from the outer frame 2, the door frame 5 and / or It is possible for the player to determine that the main body frame 3 is open, which is a state that does not occur during the normal game, and the outer end frame door opening information output signal is sent to the external terminal plate 784. Since it is input, this outer end frame door opening information output signal is transmitted to the hall computer via the external terminal plate 784, and the hall computer uses the outer end frame door opening information output signal to transmit the door frame. Although it is not possible to determine whether 5 is in a state of being released from the main body frame 3 or in a state of being released from the outer frame 2, the door frame 5 and / or the main body frame 3 is opened. It is possible to determine that a state that does not occur during a normal game has occurred.

Further, in the present embodiment, as described above, by adopting a normally closed switch for the door frame opening switch 618 and the main body frame opening switch 619, the door frame opening switch 618 is short-circuited for some reason and the switch is turned on ( Even if the door frame 5 is released from the main body frame 3 and the main body frame opening switch 619 is short-circuited for some reason and the switch is turned on (conducting), the main body frame is turned on. 3 is released from the outer frame 2. In this way, by adopting the normally closed switch for the door frame opening switch 618 and the main body frame opening switch 619, the main frame door opening signal can be output to the main control board 4100 even at the time of a short circuit, and the outer end can be output. The frame door opening information output signal can be transmitted to the hall computer via the external terminal plate 784.

If the door frame opening switch 618 and the main body frame opening switch 619 are changed from the normally closed switch to the normally open type (normally open (NO)) switch (door frame opening switch 618'and main body frame opening switch 619'). In the door frame opening switch 618', the switch is turned on (conducting) when the door frame 5 is closed from the main body frame 3, and the switch is turned off (disconnected) when the door frame 5 is opened to the main body frame 3. .. The main body frame opening switch 619'turns on (conducts) when the main body frame 3 is closed from the outer frame 2, and turns off (disconnects) when the main body frame 3 is opened to the outer frame 2. Then, even if the door frame opening switch 618'is disconnected for some reason and the switch is turned off (disconnected), the door frame 5 will be released from the main body frame 3 and the main body will be released for some reason. Even if the frame opening switch 619'is disconnected and the switch is turned off (disconnected), the main body frame 3 is released from the outer frame 2. In this way, even if the door frame opening switch 618'and the main body frame opening switch 619' are normally open switches, the main frame door opening signal can be output to the main control board 4100 even when the wire is broken. The outer end frame door opening information output signal can be transmitted to the hall computer via the external terminal plate 784.

[11-2-3 (c). A circuit to which a power failure warning signal is input from the power failure monitoring circuit]
The transmission line for transmitting the payout power failure warning signal from the power failure monitoring circuit 4100e provided in the main control board 4100 is electrically connected to and resists the other end of the pull-up resistor PR40 whose one end is electrically connected to the + 12V power supply line. It is electrically connected to the base terminal of the transistor PTR40 via PR41. In addition to being electrically connected to the resistor PR41, the base terminal of the transistor PTR40 is electrically connected to the other end of the resistor PR42, one end of which is grounded to ground (GND). The emitter terminal of the transistor PTR40 is grounded to ground (GND), and the collector terminal of the transistor PTR40 is electrically connected to the other end of the resistor PR43, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Disbursement control via ICPIC40 (non-inverting buffer ICPIC40 includes eight non-inverting buffer circuits, and the logic of the signal waveform input to one of them (PIC40A) is shaped and output without inverting). It is electrically connected to the input terminal PA1 of the input port PA of the MPU4120a. When the transistor PTR 40 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR 40 changes, and the signal is input to the input terminal PA1 of the input port PA of the payout control MPU4120a as a payout power failure warning signal.

The circuit composed of the resistors PR41, PR42, and the transistor PTR40 is a switch circuit that is turned ON / OFF by the payout power failure warning signal from the power failure monitoring circuit 4100e provided in the main control board 4100.

As described above, the power failure monitoring circuit 4100e monitors the signs of power failure or momentary power failure of two types of voltages, + 12V and + 24V, from the power supply board 851, and when the power failure or momentary power failure sign is detected, there is no reset function. The payout power failure notice signal is output to the payout control board 4110 as a power failure notice via the main control output circuit 4100 kb. The power failure monitoring circuit 4100e monitors signs of power failure or momentary power failure of + 12V and + 24V, and as described above, the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf, and the voltage of + 12V is higher than the power failure detection voltage V2pf. When both of the conditions of being large are satisfied, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is lowered to the ground (GND) side in the payout control board 4110 via the wiring (harness), and the logic becomes LOW. While the payout power failure warning signal is input to the payout control board 4110, one of the conditions that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the voltage of + 12V is smaller than the power failure detection voltage V2pf. When the condition is satisfied, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is pulled up to the + 12V side by the pull-up resistor PR40 described above via the wiring (harness), and the logic becomes HI. Is input to the payout control board 4110.

When both the condition that the voltage of + 24V is larger than the failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the failure detection voltage V2pf are satisfied, that is, there is no sign of power failure or momentary power failure of the + 12V and + 24V voltages. Occasionally, a payout power failure warning signal whose logic is LOW is input to the payout control board 4110, so that the voltage applied to the base terminal of the transistor PTR40 is lowered to the ground (GND) side, so that the transistor PTR40 is turned off. The voltage applied to the collector terminal of the transistor PTR40 is pulled up to the + 5V side by the resistor PR43. As a result, the payout power failure warning signal whose logic is HI is input from the collector terminal of the transistor PTR40 to the input terminal PA1 of the input port PA of the payout control MPU4120a.

On the other hand, when either of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, that is, the voltage of + 12V and / or + 24V. When there is a sign of power failure or momentary power failure, the payout power failure warning signal whose logic is HI is input to the payout control board 4110, so that the payout power failure warning signal from the power failure monitoring circuit 4100e is applied to the base terminal of the transistor PTR40. The voltage applied to the collector terminal of the transistor PTR40 is turned on by pulling up the voltage to the + 12V side by the pull-up resistor PR40, and the voltage applied to the collector terminal of the transistor PTR40 is lowered to the ground (GND) side. As a result, the payout power failure warning signal in which the logic of the collector terminal of the transistor PTR40 is LOW is input to the input terminal PA1 of the input port PA of the payout control MPU4120a.

In this way, when there is a sign of a power failure or momentary power failure of the + 12V and / or + 24V voltage, the payout power failure warning signal whose logic is HI is input to the input terminal PA1 of the input port PA of the payout control MPU4120a. When there is no sign of a power failure or momentary power failure of the + 12V and + 24V voltages, the payout power failure warning signal whose logic is LOW is input to the input terminal PA1 of the input port PA of the payout control MPU4120a. As described above, when there is a sign of a power failure or momentary power failure of + 12V and / or + 24V, a power failure warning signal whose logic is HI is input to the input terminal PA1 of the input port PA of the main control MPU4100a. On the other hand, when there is no sign of power failure or momentary power failure of + 12V and + 24V voltage, the power failure warning signal is input to the input terminal PA1 of the input port PA of the main control MPU4100a, so that the power failure monitoring circuit 4100e The logic of the payout power failure warning signal input to the payout control MPU4120a and the logic of the power outage warning signal input to the main control MPU4100a are the same logic.

[11-2-3 (d). Circuit to which the detection signal from the full switch is input]
The detection signal from the full tank switch 550 provided in the foul cover unit 540 shown in FIG. 1 is transmitted to the payout control board 4110 via the handle relay terminal board 192 shown in FIG. 1 and the power supply board 851 shown in FIG. It has been entered. The output terminal of the full tank switch 550 is configured as an open collector output type in which the emitter terminal is grounded to ground (GND), and one end of the payout control board 4110 is electrically connected to the + 12V power supply line. It is electrically connected to the other end of the pull-up resistor PR44a and is also electrically connected to the first terminal of the 3-terminal filter PIC50 for a full tank switch. The 3-terminal filter PIC50 for a full tank switch is a T-type filter circuit, and is magnetically shielded with ferrite and has excellent attenuation characteristics.

The 2nd terminal of the 3-terminal filter PIC50 for a full tank switch is grounded to ground (GND), and the 3rd terminal of the 3-terminal filter PIC50 for a full tank switch is a 3-terminal filter PIC50 for a full tank switch via a resistor PR44b. It is electrically connected to the first terminal of the transistor PTR41 and is also electrically connected to the base terminal of the transistor PTR41 via the resistor PR45. As a result, the detection signal of the full tank switch 550 is input to the base terminal of the transistor PTR 41 after the noise component is removed in the 3-terminal filter PIC50 for the full tank switch. In addition to being electrically connected to the resistor PR45, the base terminal of the transistor PTR41 is electrically connected to the other end of the resistor PR46 whose one end is grounded to ground (GND) and one end to ground (GND). It is electrically connected to the other end of the electrically connected capacitor PC40. The capacitor PC 40 plays a role as a low-pass filter. The emitter terminal of the transistor PTR41 is grounded to ground (GND), and the collector terminal of the transistor PTR41 is electrically connected to the other end of the resistor PR47, one end of which is electrically connected to the + 5V power supply line, and is a non-inverting buffer. Disbursement control via ICPIC40 (non-inverting buffer ICPIC40 includes eight non-inverting buffer circuits, and formats and outputs the logic of the signal waveform input to one of them (PIC40B) without inverting it). It is electrically connected to the input terminal PA2 of the input port PA of the MPU4120a. When the transistor PTR41 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR41 changes, and the signal is input to the input terminal PA2 of the input port PA of the payout control MPU4120a as a full tank signal.

The circuit composed of the resistors PR45, PR46, and the transistor PTR41 is a switch circuit that is turned ON / OFF by a detection signal from the full tank switch 550.

As described above, the full tank switch 550 detects whether or not the accommodation space in the second ball passage of the foul cover unit 540 is full with the stored game ball. In the present embodiment, when the accommodation space is not full in the stored game ball, the voltage applied to the output terminal of the full tank switch 550 is discharged via the handle relay terminal plate 192 and the power supply board 851. When the signal that is pulled up to the + 12V side by the pull-up resistor 44a in the control board 4110 and the logic becomes HI is input to the payout control board 4110, while the accommodation space is full with the stored game ball, The voltage applied to the output terminal of the full switch 550 is pulled down to the ground (GND) side in the payout control board 4110 via the handle relay terminal plate 192 and the power supply board 851, and the signal whose logic is LOW is paid out. It is input to the control board 4110.

When the accommodation space is not full in the stored game ball, the voltage applied to the output terminal of the full tank switch 550 is pulled in the payout control board 4110 via the handle relay terminal board 192 and the power supply board 851. When the signal pulled up to the + 12V side by the up resistor 44a and the logic becomes HI is input to the base terminal of the above-mentioned transistor PTR 41, the transistor PTR 41 is turned on and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR41 is lowered to the ground (GND) side, and the full tank signal whose logic is LOW is input to the input terminal PA2 of the input port PA of the payout control MPU4120a.

On the other hand, when the accommodation space is full with the stored game ball, the voltage applied to the output terminal of the full tank switch 550 is passed through the handle relay terminal plate 192 and the power supply board 851 to the payout control board 4110. When the signal pulled down to the ground (GND) side and the logic becomes LOW is input to the base terminal of the above-mentioned transistor PTR 41, the transistor PTR 41 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR41 is pulled up to the + 5V side by the resistor PR47, and the full tank signal whose logic is HI is input to the input terminal PA2 of the input port PA of the payout control MPU4120a.

In the present embodiment, the detection signal from the full-tan switch 550 is input to the switch circuit composed of the resistor PR45, the resistor PR46, and the transistor PTR41 via the 3-terminal filter PIC50 for the full-tan switch. However, the detection signals from various detection switches such as the ball-out switch 750, the counting switch 751, and the rotation angle switch 752 shown in FIG. 12 are T-type filter circuits such as the 3-terminal filter PIC50 for a full tank switch. It is a circuit configuration that is directly input to each switch circuit without going through. Since the full tank switch 550 is provided in the foul cover unit 540 attached to the door frame 5, the ball out switch 750, the counting switch 751 and the rotation angle switch 752 provided in the prize ball device 740 attached to the main body frame 3 are provided. The path for transmitting the detection signal is extremely long, and it is extremely susceptible to noise.

The full tank switch 550 detects whether or not the accommodation space in the second ball passage of the foul cover unit 540 is full with the stored game ball, and the payout control MPU 4120a is from the full tank switch 550. When it is determined that the game ball in which the accommodation space is stored is full based on the detection signal of, the drive control of the payout motor 744 is forcibly stopped to stop the payout of the game ball by the payout rotating body. It is supposed to do. That is, when noise enters the transmission path (transmission line) that transmits the detection signal from the full tank switch 550, the payout control MPU4120a drives the payout motor 744 even though the game ball has the accommodation space and is not full. In some cases, the control is forcibly stopped to stop the payout of the game ball by the payout rotating body, and even though the game ball in which the accommodation space is stored is full, the payout motor 744 is driven and controlled. When the game ball is filled up to the upstream side of the prize ball passage described above by rotating the payout rotating body and continuing the payout of the game ball, the payout rotating body itself cannot rotate and the payout motor 744 becomes available. The load may be abnormally applied, and the payout motor 744 may become overloaded and generate abnormal heat and fail, or the mechanism for transmitting the rotating shaft of the payout motor 744 to the rotational movement of the payout rotating body may break down. .. Therefore, in the present embodiment, in order to prevent such a problem from occurring, a circuit configuration is adopted so that the detection signal from the full tank switch 550 is first removed by the noise component in the 3-terminal filter PIC 50 for the full tank switch. ..

[11-2-3 (e). Circuit to which the operation signal from the operation switch is input]
The 1st and 2nd terminals, which are the output terminals of the operation switch 860a, are grounded to the ground (GND), and the 3rd and 4th terminals, which are the output terminals of the operation switch 860a, are moved to the + 5V side by the pull-up resistor PR48. It is pulled up and connected to the base terminal of the transistor PTR 42 in the previous stage via a resistor PR49 and electrically. In addition to being electrically connected to the resistor PR49, the base terminal of the transistor PTR42 in the previous stage is electrically connected to the other end of the resistor PR50 whose one end is grounded to ground (GND). In addition to being electrically connected to the pull-up resistor PR48, the fourth terminal, which is the output terminal of the operation switch 860a, is electrically connected to the other end of the capacitor PC41 whose one end is grounded to ground (GND). ing. The emitter terminal of the transistor PTR 42 in the previous stage is grounded to ground (GND), and the collector terminal of the transistor PTR 42 in the previous stage is electrically connected to the other end of the resistor PR51 whose one end is electrically connected to the + 5V power supply line. At the same time, it is electrically connected to the base terminal of the transistor PTR43 in the subsequent stage via the resistor PR52. The base terminal of the transistor PTR43 in the subsequent stage is electrically connected to the resistor PR52, and is also electrically connected to the other end of the resistor PR53 whose one end is grounded to ground (GND). The emitter terminal of the latter transistor PTR43 is grounded to ground (GND), and the collector terminal of the latter transistor PTR43 is electrically connected to the other end of the resistor PR54 whose one end is electrically connected to the + 5V power supply line. The non-inverting buffer ICPIC40 (the non-inverting buffer ICPIC40 includes eight non-inverting buffer circuits, and the logic of the signal waveform input to one of them (PIC40C) is formatted and output without inverting). It is electrically connected to the input terminal PA3 of the input port PA of the payout control MPU4120a via. When the transistors PTR42 and PTR43 in the front and rear stages are turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR43 in the rear stage changes, and the signal is used as the RWMCLR signal and the input terminal PA3 of the input port PA of the payout control MPU4120a. Is entered in.

In addition, the 3rd and 4th terminals, which are the output terminals of the operation switch 860a, are pulled up to the + 5V side by the pull-up resistor PR48 and are electrically connected to the base terminal of the transistor PTR42 in the previous stage via the resistor PR49. It is pulled up to the + 5V side by the pull-up resistor PR48 and is electrically connected to the base terminal of the transistor PTR44 via the resistor PR55. In addition to being electrically connected to the resistor PR55, the base terminal of the transistor PTR44 is electrically connected to the other end of the resistor PR56, one end of which is grounded to ground (GND). The emitter terminal of the transistor PTR44 is grounded to ground (GND), and the collector terminal of the transistor PTR44 is electrically connected to the main control board 4100 via wiring (harness). When the collector terminal of the transistor PTR44 is electrically connected to the main control board 4100 via wiring (harness), one end of the main control input circuit 4100b of the main control board 4100 shown in FIG. 22 is + 12V. It is electrically connected to the other end of the pull-up resistor MR2 that is electrically connected to the power supply line. When the transistor PTR44 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR44 changes, and the signal is input to the input terminal PA0 of the input port PA of the main control MPU4100a as a RAM clear signal.

The circuit composed of the pull-up resistor PR48 and the capacitor PC41 is a switch signal generation circuit, and when the operation switch 860a is pressed, the contacts constituting the operation switch 860a repeatedly turn on and off for a short time. It is configured as a circuit having a function of absorbing the fluctuation of the voltage from the operation switch 860a by the above.

The circuit composed of the resistors PR49, PR50, and the transistor PTR42 is the switch circuit in the front stage, and the circuit composed of the resistors PR52, PR53, and the transistor PTR43 is the switch circuit in the rear stage, and the resistors PR55, PR56, and the transistor PTR44. The circuit composed of is a switch circuit, and is turned on / off by an operation signal from the operation switch 860a.

As described above, the operation switch 860a is used in the RAM (RAM with built-in payout control) built in the payout control MPU 4120a of the payout control board 4110 and the main control MPU 4100a of the main control board 4100 within a predetermined period from the time when the power is turned on. It is operated when clearing the built-in RAM (main control built-in RAM), or when an error is notified after the power is turned on, it is operated to clear the error, and the power is turned on. A function to clear the RAM within a predetermined period from time, and an error cancellation after the power is turned on (after the period during which the function as RAM clear has elapsed, that is, after the predetermined period has elapsed from the time when the power is turned on). It has a function. The operation signal from the operation switch 860a is a RAM clear signal in the function of clearing the RAM within a predetermined period from the time when the power is turned on, while after the power is turned on (after a predetermined period has elapsed from the time when the power is turned on). In the function of canceling the error in), it becomes an error clearing signal.

When the operation switch 860a is not operated, the operation signal whose logic is HI is the transistor in the previous stage because the 3rd and 4th terminals, which are the output terminals of the operation switch 860a, are pulled up to the + 5V side by the pull-up resistor PR48. It is input to the base terminal of the PTR 42 to turn on the transistor PTR 42 in the previous stage, and the switch circuit in the previous stage is also turned on. When the voltage is lowered to the ground (GND) side, the transistor PTR43 in the subsequent stage is turned off, and the switch circuit in the subsequent stage is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR43 in the subsequent stage is pulled up to the + 5V side by the resistor PR54, and the RWMCLR signal whose logic is HI is input to the input terminal PA3 of the input port PA of the payout control MPU4120a. The payout control MPU4120a performs RAM clear to erase the information stored in the payout control built-in RAM when the logic of the RWMCLR signal input to the input terminal PA3 is HI within a predetermined period from the time when the power is turned on. It is judged that it is not an instruction, and after the power is turned on (after a predetermined period has elapsed from the time when the power is turned on), if the logic of the RWMCLR signal input to the input terminal PA3 is HI, the error is cleared. Judge that it is not an instruction.

When the operation switch 860a is not operated, the operation signal whose logic is HI is the transistor PTR44, in which the 3rd and 4th terminals, which are the output terminals of the operation switch 860a, are pulled up to the + 5V side by the pull-up resistor PR48. The transistor PTR44 is turned on by being input to the base terminal of, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR44 is lowered to the ground (GND) side in the main control board 4100 via the wiring (harness), and the RAM clear signal whose logic is LOW is sent to the main control board 4100. Entered. When the RAM clear signal whose logic is LOW is input to the main control MPU 4100a of the main control board 4100 within a predetermined period from the time when the power is turned on, as described above, this logic is LOW. When the RAM clear signal is input to the base terminal of the transistor MTR0, the transistor MTR0 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor MTR0 is pulled up to the + 5V side by the resistor MR5, and the RAM clear signal whose logic is HI is input to the input terminal PA0 of the input port PA of the main control MPU4100a. The main control MPU4100a determines that when the logic of the RAM clear signal input to the input terminal PA0 is HI, it does not instruct to perform RAM clear to erase the information stored in the main control built-in RAM.

On the other hand, when the operation switch 860a is operated, the operation signal whose logic is LOW is the transistor in the previous stage because the 3rd and 4th terminals, which are the output terminals of the operation switch 860a, are pulled down to the ground (GND) side. It is input to the base terminal of the PTR 42 to turn off the transistor PTR 42 in the previous stage, and the switch circuit in the previous stage is also turned off. When the voltage is raised to the + 5V side by the resistor PR51, the transistor PTR43 in the subsequent stage is turned on, and the switch circuit in the subsequent stage is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR43 in the subsequent stage is lowered to the ground (GND) side, and the RWMCLR signal whose logic is LOW is input to the input terminal PA3 of the input port PA of the payout control MPU4120a. The payout control MPU4120a performs RAM clear to erase the information stored in the payout control built-in RAM when the logic of the RWMCLR signal input to the input terminal PA3 is LOW within a predetermined period from the time when the power is turned on. It is determined that the signal is to be instructed, and after the power is turned on (after a predetermined period has elapsed from the time the power is turned on), if the logic of the RWMCLR signal input to the input terminal PA3 is LOW, the error is cleared. Judge that it is an instruction.

Further, when the operation switch 860a is operated, the operation that the output terminal of the operation switch 860a, the 3rd terminal and the 4th terminal, is pulled down to the ground (GND) side by the pull-up resistor PR48, and the logic becomes LOW. A signal is input to the base terminal of the transistor PTR44, the transistor PTR44 is turned off, and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR44 is pulled up to the + 12V side by the pull-up resistor MR2 of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. The clear signal is input to the main control board 4100. When the RAM clear signal whose logic is HI is input to the main control MPU4100a of the main control board 4100 within a predetermined period from the time when the power is turned on, as described above, this logic is HI. When the RAM clear signal is input to the base terminal of the transistor MTR0, the transistor MTR0 is turned on and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor MTR0 is lowered to the ground (GND) side, and the RAM clear signal whose logic is LOW is input to the input terminal PA0 of the input port PA of the main control MPU4100a. The main control MPU4100a determines that when the logic of the RAM clear signal input to the input terminal PA0 is LOW, it is instructed to perform RAM clear that erases the information stored in the main control built-in RAM.

[11-2-4. Payout motor drive circuit]
Next, a payout motor drive circuit 4120d for outputting a drive signal to the payout motor 744 of the prize ball device 740 shown in FIG. 5 will be described. As shown in FIG. 28, the payout motor drive circuit 4120d mainly includes a voltage switching circuit 4120da and a drive ICPIC60. The power input terminals 1 and 2 of the voltage switching circuit 4120da are electrically connected to the + 12V power supply line and the + 5V power supply line, respectively, and +12 and + 5V are applied, respectively. It is grounded. A voltage switching signal is input to the power switching input terminal of the voltage switching circuit 4120da. This voltage switching signal is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120ca with a reset function, and is output from the payout control output circuit 4120ca with a reset function to the power supply switching input terminal of the voltage switching circuit 4120da. It is supposed to be done. The power output terminal of the voltage switching circuit 4120da is electrically connected to the terminal 3 and the terminal 10 which are the cathode terminals of the drive ICPIC60 via the Zener diode PZD60, respectively, and is electrically connected to the power supply terminal of the payout motor 744. Based on the voltage switching signal connected to the voltage switching circuit 4120da and input to the voltage switching input terminal, + 12V or + 5V is used as the motor drive voltage via the Zener diode PZD60, and is the cathode terminal of the drive ICPIC60. It is supplied to the terminal and the 10th terminal, respectively, and is also supplied to the payout motor 744.

The drive ICPIC60 includes four Darlington power transistors. In this embodiment, the 6th and 7th terminals, which are the emitter terminals of the drive ICPIC60, are grounded to ground (GND), respectively, and are the base terminals of the drive ICPIC60. At the 1st terminal, the 5th terminal, the 8th terminal, and the 12th terminal, the payout motor drive signal is input via the resistors PR60 to PR63, respectively. The 2nd terminal, 4th terminal, 9th terminal, and 11th terminal, which are the collector terminals of the drive ICPIC60, are the 1st terminal, the 5th terminal, the 8th terminal, and the 12th terminal, which are the base terminals of the drive ICPIC60, respectively. When the payout motor drive signal is input to the 1st terminal, 5th terminal, 8th terminal, and 12th terminal, which are the base terminals of the drive ICPIC60, via the resistors PR60 to PR63, it is an excitation signal. A certain drive pulse is output to each phase (/ B phase, B phase, A phase, / A phase) corresponding to the payout motor 744. This payout motor drive signal is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120ca with a reset function, and from the payout control output circuit 4120ca with a reset function to the drive ICPIC60 via the resistors PR60 to PR63. It is designed to be output to the 1st terminal, the 5th terminal, the 8th terminal, and the 12th terminal, which are the base terminals, respectively. These drive pulses are performed by switching the exciting current flowing through each phase (/ B phase, B phase, A phase, / A phase) of the payout motor 744 to rotate the payout motor 744. When the drive pulse (excitation signal) of each phase (/ B phase, B phase, A phase, / A phase) is cut off by this switching, a counter electromotive force is generated. If this counter electromotive force exceeds the withstand voltage of the drive ICPIC60, the drive ICPIC60 will be damaged. Therefore, as protection, the Zener diode PZD0 described above is electrically connected to the front stages of the 3rd and 10th terminals which are the cathode terminals of the drive ICPIC60. The circuit configuration is adopted.

[11-2-5. CR unit input / output circuit]
Next, the CR unit input / output circuit 4120e for inputting / outputting various signals with the CR unit 6 shown in FIG. 13 will be described. As described above, the payout control board 4110 includes the BRDY, which is a ball lending request signal, and the BRQ, which is a one-time payout operation start request signal, via the game ball or the like lending device connection terminal board 869 from the CR unit 6. , And the predetermined voltage VL (+ 12V) and ground LG created from AC24V supplied from the power supply board 851 shown in FIG. 13 are supplied, while the payout control board 4110 connects to a rental device such as a game ball. An EXS signal indicating that one payout operation has started or ended, and a PRDY signal indicating that the payout operation for paying out the rental ball is possible or impossible, via the terminal board 869. And is output. As shown in FIG. 29, the input / output circuits for inputting / outputting these various signals and the like are mainly composed of photocouplers PIC70 to PIC74 (infrared LEDs and phototransistors are built-in).

The predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70 via the resistor PR70. The cathode terminal of the photocoupler PIC70 is electrically connected to the ground LG from the CR unit 6. The resistor PR60 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC70. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on, while the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70. Occasionally, the photocoupler PIC 70 is turned off. The emitter terminal of the photocoupler PIC70 is grounded to ground (GND), and the collector terminal of the photocoupler PIC70 is electrically connected to the base terminal of the transistor PTR70 via the resistor PR71 and also to the transistor via the resistor PR72. It is electrically connected to the base terminal of the PTR71. In addition to being electrically connected to the resistor PR71, the collector terminal of the photocoupler PIC70 is electrically connected to the other end of the pull-up resistor PR73, one end of which is electrically connected to the + 5V power supply line.

In addition to being electrically connected to the resistor PR71, the base terminal of the transistor PTR70 is electrically connected to the other end of the resistor PR74 whose one end is grounded to ground (GND). The emitter terminal of the transistor PTR70 is grounded to ground (GND), and the collector terminal of the transistor PTR70 is electrically connected to the other end of the resistor PR75, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. FIG. 25 via the ICPIC80 (the non-inverting buffer ICPIC80 includes eight non-inverting buffer circuits, and the logic of the signal waveform input to one of them (PIC80A) is formatted and output without inverting). It is electrically connected to the input terminal of the predetermined input port of the payout control MPU4120a shown in 1. When the transistor PTR 70 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR 70 changes, and the signal is input as the CR connection signal 1 to the input terminal of the predetermined input port of the payout control MPU4120a.

On the other hand, the base terminal of the transistor PTR71 is electrically connected to the resistor PR72, and is also electrically connected to the other end of the resistor PR76 whose one end is grounded to ground (GND). The emitter terminal of the transistor PTR71 is grounded to ground (GND), and the collector terminal of the transistor PTR71 is electrically connected to the power supply board 851 via wiring (harness). When the collector terminal of the transistor PTR71 is electrically connected to the power supply board 851 via wiring (harness), one end of the power supply board 851 is electrically connected to the + 12V power supply line, which is a pull-up resistor (not shown). It is electrically connected to the other end of the. When the transistor PTR71 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR71 changes, and the signal is input to the power supply board 851 as a CR connection signal.

The circuit composed of the resistors PR71 and PR74 and the transistor PTR70 is a switch circuit that is turned ON / OFF by ON / OFF of the photocoupler PIC70.

When the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned off, and the transistor PTR70 is turned on by being pulled up to the + 5V side by the pull-up resistor PR73, and the switch circuit is also turned on. It will be turned on. As a result, the voltage applied to the collector terminal of the transistor PTR 70 is lowered to the ground (GND) side, and the CR connection signal 1 whose logic is LOW is input to the input terminal of the predetermined input port of the payout control MPU 4120a.

On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on and the voltage applied to the base terminal of the transistor PTR70 is lowered to the ground (GND) side. As a result, the transistor PTR70 is turned off, and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR70 is pulled up to the + 5V side by the pull-up resistor PTR75, and the CR connection signal 1 whose logic is HI is input to the input terminal of the predetermined input port of the payout control MPU4120a. To.

The circuit composed of the resistors PR72, PR76, and the transistor PTR71 is also a switch circuit that is turned ON / OFF by ON / OFF of the photocoupler PIC70.

When the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned off, and the transistor PTR71 is turned on by being pulled up to the + 5V side by the pull-up resistor PR73, and the switch circuit is also turned on. It will be turned on. As a result, the voltage applied to the collector terminal of the transistor PTR71 is lowered to the ground (GND) side in the power supply board 851 via the wiring (harness), and the CR connection signal whose logic is LOW is input to the power supply board 851. Ru.

On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on and the voltage applied to the base terminal of the transistor PTR71 is lowered to the ground (GND) side. As a result, the transistor PTR71 is turned off, and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR71 is pulled up to the + 12V side by the pull-up resistance of the power supply board 851 via the wiring (harness), and the CR connection signal whose logic is HI is input to the power supply board 851. Will be done.

The predetermined voltage VL from the CR unit 6 is applied not only to the anode terminal of the photocoupler PIC70 but also to the anode terminal of the photocoupler PIC71 via the resistor PR77. BRDY from the CR unit 6 is input to the cathode terminal of the photocoupler PIC71. The resistor PR77 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC71. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the logic of BRDY from the CR unit 6 is LOW, the photocoupler PIC71 is turned on while the photo When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the coupler PIC71 and the logic of BRDY from the CR unit 6 is HI, the photocoupler PIC71 is turned off. There is. The emitter terminal of the photocoupler PIC71 is grounded to ground (GND), and the collector terminal of the photocoupler PIC71 is electrically connected to the other end of the pull-up resistor PR78, one end of which is electrically connected to the + 5V power supply line. The non-inverting buffer ICPIC80 (the non-inverting buffer ICPIC80 includes eight non-inverting buffer circuits, and the logic of the signal waveform input to one of them (PIC80B) is formatted and output without inverting). It is electrically connected to the input terminal of the predetermined input port of the payout control MPU4120a via the payout control MPU4120a. When the photocoupler PIC71 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC71 changes, and the signal is input as a BRDY signal to the input terminal of the predetermined input port of the payout control MPU4120a.

When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the logic of BRDY from the CR unit 6 is LOW, the photocoupler PIC71 is turned on and therefore the photo The voltage applied to the collector terminal of the coupler PIC71 is lowered to the ground (GND) side, and the BRDY signal whose logic is LOW is input to the input terminal of the predetermined input port of the payout control MPU4120a. On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the logic of BRDY from the CR unit 6 is HI, the photocoupler PIC71 is turned off. The voltage applied to the collector terminal of the photocoupler PIC71 is pulled up to the + 5V side by the pull-up resistor PR78, and the BRDY signal whose logic is HI is input to the input terminal of the predetermined input port of the payout control MPU4120a. As described above, the logic of the BRDY signal output from the collector terminal of the photocoupler PIC71 is the same as the logic of the BRDY from the CR unit 6.

The predetermined voltage VL from the CR unit 6 is applied not only to the anode terminal of the photocoupler PIC70 and the anode terminal of the photocoupler PIC71, but also to the anode terminal of the photocoupler PIC72 via the resistor PR79. The BRQ from the CR unit 6 is input to the cathode terminal of the photocoupler PIC72. The resistor PR79 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC72. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the logic of the BRQ from the CR unit 6 is LOW, the photocoupler PIC72 is turned on while the photo When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the coupler PIC72 and the logic of the BRQ from the CR unit 6 is HI, the photocoupler PIC72 is turned off. There is. The emitter terminal of the photocoupler PIC72 is grounded to ground (GND), and the collector terminal of the photocoupler PIC72 is electrically connected to the other end of the pull-up resistor PR80, one end of which is electrically connected to the + 5V power supply line. The non-inverting buffer ICPIC80 (the non-inverting buffer ICPIC80 includes eight non-inverting buffer circuits, and the logic of the signal waveform input to one of them (PIC80C) is formatted and output without inverting). It is electrically connected to the input terminal of the predetermined input port of the payout control MPU4120a via the payout control MPU4120a. When the photocoupler PIC72 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC72 changes, and the signal is input as a BRQ signal to the input terminal of the predetermined input port of the payout control MPU4120a.

When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the logic of the BRQ from the CR unit 6 is LOW, the photocoupler PIC72 is turned on and therefore the photo The voltage applied to the collector terminal of the coupler PIC72 is lowered to the ground (GND) side, and the BRQ signal whose logic is LOW is input to the input terminal of the predetermined input port of the payout control MPU4120a. On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the logic of the BRQ from the CR unit 6 is HI, the photocoupler PIC72 is turned off. The voltage applied to the collector terminal of the photocoupler PIC72 is pulled up to the + 5V side by the pull-up resistor PR80, and the BRQ signal whose logic is HI is input to the input terminal of the predetermined input port of the payout control MPU4120a. As described above, the logic of the BRQ signal output from the collector terminal of the photocoupler PIC72 is the same as the logic of the BRQ from the CR unit 6.

The XS signal indicating that one payout operation has started or ended from the output terminal of the predetermined output port of the payout control MPU 4120a is output to the payout control output circuit 4120 kb without a reset function, and the payout control output circuit without a reset function. It is input from 4120 kb to the cathode terminal of the photocoupler PIC73 via the resistor PR81. The anode terminal of the photocoupler PIC73 is electrically connected to the other end of the resistor PR82, one end of which is electrically connected to the + 12V power supply line. The resistor PR82 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC73. When + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, the EXS is output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without a reset function. When the signal logic is LOW, the photocoupler PIC73 is turned on, while + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, and the predetermined output port of the payout control MPU4120a is applied. When the logic of the EXS signal output from the output terminal of the output terminal without the reset function via the payout control output circuit 4120cc is HI, the photocoupler PIC73 is turned off. The emitter terminal of the photocoupler PIC73 is grounded to the ground LG from the CR unit 6, and the collector terminal of the photocoupler PIC73 is inside the CR unit 6 via a pull-up resistor PR83 via a game ball rental device connection terminal plate 869. In, the voltage is raised to a predetermined voltage VL and is electrically connected to the built-in control device. When the photocoupler PIC73 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC73 changes, and the signal is input to the built-in control device of the CR unit 6 as EXS.

When + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, the EXS is output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without a reset function. When the signal logic is LOW, the photocoupler PIC73 is turned on, so the voltage applied to the collector terminal of the photocoupler PIC73 is lowered to the ground (GND) side, and the EXS whose logic is LOW is the CR unit. It is input to the built-in control device of 6. On the other hand, when + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, it is output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without a reset function. When the logic of the EXS signal is HI, the photocoupler PIC73 is turned off, so that the voltage applied to the collector terminal of the photocoupler PIC73 is pulled up to a predetermined voltage VL by the pull-up resistor PR83, and the logic becomes HI. The EXS is input to the built-in control device of the CR unit 6. As described above, the logic of the XS output from the collector terminal of the photocoupler PIC73 is the logic of the XS signal output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without the reset function. It has the same logic.

The PRDY signal indicating that the payout operation for paying out the rental ball from the output terminal of the predetermined output port of the payout control MPU4120a is possible or impossible is transmitted to the cathode terminal of the photocoupler PIC74 via the resistor PR84. Has been entered in. The anode terminal of the photocoupler PIC74 is electrically connected to the other end of the resistor PR85, one end of which is electrically connected to the + 12V power supply line. The resistor PR85 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC74. When + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, the PRDY is output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without a reset function. When the signal logic is LOW, the photocoupler PIC74 is turned on, while + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, and the predetermined output port of the payout control MPU4120a is applied. When the logic of the PRDY signal output from the output terminal of the output terminal without the reset function via the payout control output circuit 4120 kb is HI, the photocoupler PIC74 is turned off. The emitter terminal of the photocoupler PIC74 is grounded to the ground LG from the CR unit 6, and the collector terminal of the photocoupler PIC74 is inside the CR unit 6 via a pull-up resistor PR86 via a terminal board 869 for renting a game ball or the like. In, the voltage is pulled up to a predetermined voltage VL and is electrically connected to the built-in control device. When the photocoupler PIC74 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC74 changes, and the signal is input to the built-in control device of the CR unit 6 as a PRDY.

When + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, the PRDY is output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without a reset function. When the signal logic is LOW, the photocoupler PIC74 is turned on, so the voltage applied to the collector terminal of the photocoupler PIC74 is lowered to the ground (GND) side, and the PRDY whose logic is LOW is the CR unit. It is input to the built-in control device of 6. On the other hand, when + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, it is output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without a reset function. When the logic of the PRDY signal is HI, the photocoupler PIC74 is turned off, so that the voltage applied to the collector terminal of the photocoupler PIC74 is pulled up to a predetermined voltage VL by the pull-up resistor PR86, and the logic becomes HI. The PRDY is input to the built-in control device of the CR unit 6. As described above, the logic of the PRDY output from the collector terminal of the photocoupler PIC74 is the logic of the PRDY signal output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without the reset function. It has the same logic.

[11-2-6. Various input / output signals to the payout control MPU]
Next, various input / output signals input / output from the input / output terminals of the various input / output ports of the payout control MPU4120a will be described.

As shown in FIG. 25, the RXD terminal, which is the serial data input terminal of the serial input port of the payout control MPU 4120a, receives the serial data from the main control board 4100 as the main payout serial data reception signal via the payout control input circuit 4120b. Will be done. On the other hand, from the TXD terminal, which is the serial data output terminal of the serial output port of the payout control MPU4120a, the serial data to be transmitted to the main control board 4100 is transmitted as the payer serial data transmission signal to the payout control output circuit 4120cc without a reset function. No reset function The payer serial data transmission signal is transmitted from the payout control output circuit 4120cc to the main control board 4100.

The RWMCLR signal, the payout failure warning signal, the door open signal, the full tank signal, and various signals from the CR unit 6 (BRQ signal, BRDY signal, CR connection) described above are connected to each input terminal of the predetermined input port of the payout control MPU4120a. In addition to the input of signals 1 and the like), for example, the main payment ACK signal from the main control board 4100 that conveys the completion of normal reception of the above-mentioned payer serial data reception signal is transmitted via the payout control input circuit 4120b. Inputs are made, and detection signals from the ball-out switch 750, the counting switch 751, the rotation angle switch 752, and the like shown in FIG. 12 are input via the payout control input circuit 4120b, respectively.

On the other hand, the above-mentioned EXS signal and PRDY signal are output from each output terminal of the predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120 kb without the reset function, respectively, and the EXS signal and the EXS signal from the payout control output circuit 4120 kb without the reset function. The PRDY signal is output to the CR unit input / output circuit 4120e, or the above-mentioned voltage switching signal is output to the payout control output circuit 4120ca with a reset function, and the voltage switching signal is output from the payout control output circuit 4120ca with a reset function to the voltage switching circuit 4120da. It can be output, or the payout motor drive signal can be output to the payout control output circuit 4120ca with a reset function, and the payout control output circuit 4120ca with a reset function can output the payout motor drive signal to the payout motor 744 via the payout motor drive circuit 4120d. In addition to the above, for example, the payer ACK signal indicating that the normal reception of the main pay serial data reception signal is completed is output to the payout control output circuit 4120ca with a reset function, and the payer is output from the payout control output circuit 4120ca with a reset function. The ACK signal is output to the main control board 4100, or the drive signal of the error LED display 860b shown in FIG. 12 is output to the payout control output circuit 4120ca with a reset function, and the drive signal is output from the payout control output circuit 4120ca with a reset function. Output to the error LED display 860b, etc.

[11-3. Various input / output signals with the main control board and various output signals to the external terminal board]
Next, various input / output signals between the payout control board 4110 and the main control board 4100 and various output signals from the payout control board 4110 to the external terminal board 784 will be described with reference to FIG. 30.

[11-3-1. Various input / output signals with the main control board]
The payout control board 4110 exchanges various input / output signals with the main control board 4100. Specifically, as shown in FIG. 30A, the payout control board 4110 has the payer serial data transmission signal, payer ACK signal, operation signal (RAM clear signal), main frame door open signal, and the like described above. Is output to the main control board 4100. These output signals are pulled up to the + 12V side by the pull-up resistance of the main control input circuit 4100b of the main control board 4100.

On the other hand, in the payout control board 4110, in addition to the above-mentioned main payment serial data reception signal, main payment ACK signal, and operation signal (RAM clear signal), a 15-round jackpot information output signal, a 2-round jackpot information output signal, etc. Game information signals related to games such as jackpot information output signal, probability fluctuation information output signal, special symbol display information output signal, normal symbol display information output signal, time saving medium information output signal, start opening winning information output signal, etc. Signals and the like are input from the main control board 4100. These input signals are pulled up to the + 12V side by the pull-up resistance of the payout control input circuit 4120b of the payout control unit 4120 of the payout control board 4110.

[11-3-2. Various output signals to the external terminal board]
The payout control board 4110 outputs various signals to the external terminal board 784. Specifically, as shown in FIG. 30B, in addition to the above-mentioned outer end frame door opening information output signal, a prize ball number information output signal indicating the number of game balls actually paid out by the payout motor 744 is shown. , In addition to the jackpot information output signal such as the 15-round jackpot information output signal and the 2-round jackpot information output signal from the main control board 4100 via the payout control board 4110, the information output signal during probability fluctuation and the special symbol display information output. A game information signal such as a signal, a normal symbol display information output signal, a time saving medium information output signal, and a start opening winning information output signal is output to the external terminal board 784. These output signals are pulled up to the + 12V side by the pull-up resistance of the external terminal board 784.

The signal output from the external terminal board 784 is transmitted to a hall computer installed in a game hall (hall) (not shown), and the hall computer monitors the player's game or the like. When the 15-round jackpot information output signal or the 2-round jackpot information output signal is output to the hall computer as one jackpot information output signal, the hall computer shall perform the number of jackpots in which the round is twice (two-round jackpot). The number of big hits of the pachinko gaming machine 1 is the sum of the number of big hits in which the number of rounds is 15 (the number of times of big hits in 15 rounds) and the number of big hits. For this reason, the hall computer cannot grasp the number of occurrences of 2 round jackpots and the number of occurrences of 15 land jackpots from the total number of jackpots, so that the number of jackpots actually generated in the pachinko gaming machine 1 is large. However, it is not possible to know whether it is a 2-round jackpot or a 15-round jackpot. Further, a data counter (not shown) is arranged above the pachinko gaming machine 1, and some players can decide whether or not to play the game by referring to the number of occurrences of the jackpot gaming state displayed on the data counter. Some people choose.

However, the number of occurrences of the jackpot game state displayed on the data counter may actually be biased to the number of occurrences of the two-round jackpot, so even if the player starts the game, only the two-round jackpot occurs. It may be difficult to get a big hit for 15 rounds. In this way, the number of occurrences of the jackpot gaming state displayed on the data counter can give the player a sense of expectation, but may arouse the player's gambling spirit more than necessary.

Therefore, in the present embodiment, as the jackpot information output signal, the 15-round jackpot information output signal and the 2-round jackpot information output signal are separately output to the hall computer, so that the hall computer can determine the number of occurrences of the 2-round jackpot and the number of occurrences of the 2-round jackpot. It is possible to accurately grasp the number of big hits in 15 rounds. Therefore, the hall computer can grasp whether the number of big hits actually generated in the pachinko gaming machine 1 is the 2 round big hit or the 15 round big hit, and the data counter has 15 Since the number of round jackpots and the number of 2-round jackpots can be displayed separately or only the number of 15-round jackpots can be displayed as the number of occurrences of the jackpot gaming state, the player's gambling spirit can be stimulated more than necessary. Nor.

In this embodiment, the 2-round jackpot information output signal is in a state of being output to the hall computer during the period from the occurrence of the 2-round jackpot to the end, and the 15-round jackpot information output signal is also the 15-round jackpot. It is in the state of being output to the hall computer during the period from the occurrence to the end. In addition to the method of outputting the 2-round jackpot information output signal and the 15-round jackpot information output signal to the hall computer as in the present embodiment, for example, when a 2-round jackpot occurs, the 2-round jackpot information output signal is output only for a predetermined period. Such a 2-round jackpot information output signal and 15-round jackpot information are output to the hall computer, and when a 15-round jackpot occurs, the 15-round jackpot information output signal is output to the hall computer for a predetermined period. A method of outputting an output signal to a hall computer for the same predetermined period can also be mentioned.

[12. Various commands related to transmission and reception of the main control board]
Next, various commands transmitted from the main control board 4100 to the payout control board 4110 and various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described with reference to FIGS. 31 to 34. FIG. 31 is a table showing an example of various commands transmitted from the main control board to the payout control board, and FIG. 32 is a table showing an example of various commands transmitted from the main control board to the peripheral control board. FIG. 33. Is a table showing the continuation of various commands transmitted from the main control board to the peripheral control board of FIG. 32, and FIG. 34 is a table showing an example of various commands received from the payout control board received by the main control board. First, the prize ball command, which is a command related to payout transmitted from the main control board to the payout control board, is described, and then various commands transmitted from the main control board to the peripheral control board are described, and the main control board receives the command. Various commands from the payout control board will be described.

[12-1. Various commands sent from the main control board to the payout control board]
The main control MPU 4100a of the main control board 4100 has detection signals from various winning switches such as the general winning port switches 3020 and 3020, the upper starting port switch 3022, the lower starting port switch 2109, and the count switch 2110 shown in FIG. When input, a prize ball command for paying out a predetermined number of game balls as a prize ball is transmitted to the payout control board based on these detection signals. This prize ball command is a command having a storage capacity of 1 byte (8 bits). In the present embodiment, the pachinko gaming machine 1 and the CR unit 6 (communication with the pachinko gaming machine 1 and driving the payout motor 744 of the pachinko gaming machine 1 (prize ball device 740) to drive the payout motor 744, which is a storage tray, the upper plate 301 and the like. When the lower plate 302 is electrically connected to a device for paying out a game ball as a rental ball (such a pachinko gaming machine is referred to as a “CR machine”), as shown in FIG. 31 (a). The prize ball commands transmitted from the main control board 4100 to the payout control board 4110 include commands 10H to 1EH (“H” represents a hexadecimal number), and command 10H has one prize ball. Two prize balls are specified in the command 11H, and 15 prize balls are specified in the command 1EH. The payout control board 4110 drives the payout motor 744 to pay out the game balls by the designated number of prize balls.

In addition, a pachinko game machine 1 and a ball lending machine (a device that directly pays out game balls to the upper plate 301 and the lower plate 302 as ball lending plates, which are storage plates) are installed adjacent to the game hall (hall), and pachinko machines are installed. When the gaming machine 1 and the ball lending machine are electrically connected (such a pachinko gaming machine is referred to as a "general machine"), it is paid out from the main control board 4100 as shown in FIG. 31 (b). Command 20H to command 2EH are prepared for the prize ball command to be transmitted to the control board 4110. One prize ball is specified by the command 20H, two prize balls are specified by the command 21H, and so on. In 2EH, 15 prize balls are designated. The payout control board 4110 drives the payout motor 744 to pay out the game balls by the designated number of prize balls.

As a command common to the CR machine and the general machine, a command 30H is prepared as shown in FIG. 31 (c), and a self-check is specified in this command 30H. After the command is transmitted, the transmitting side transmits the command 30H and checks whether or not the ACK signal is input when the ACK signal to be output as confirmation of receipt of the command is not input from the receiving side for a predetermined period. Check the connection status. In the case of the CR machine in the present embodiment, the payout control board 4110 confirms the connection state with the CR unit 6.

[12-2. Various commands sent from the main control board to the peripheral control board]
Next, various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described. The main control MPU 4100a of the main control board 4100 transmits various commands to the peripheral control board 4140 based on the progress of the game. These various commands are commands having a storage capacity of 2 bytes (16 bits), and as shown in FIGS. 32 and 33, a status indicating the type of the command having a storage capacity of 1 byte (8 bits) and a status indicating the type of the command have a storage capacity of 1 byte (8 bits). It is composed of a mode showing a variation of an effect having a storage capacity of 1 byte (8 bits).

As shown in FIGS. 32 and 33, the various commands are related to the special figure 1 tuning effect, the special figure 2 tuning effect, the jackpot related, the power on, the normal electric role effect related, the notification display, and the state. It is divided into display and others.

[12-2-1. Special Figure 1 Entrainment production related]
The special drawing 1 tuning effect-related is based on the detection signal from the upper start port switch 3022 shown in FIG. 11, and the division thereof is as shown in FIG. 32 of the function display board 1191 shown in FIG. It is composed of commands named special figure 1 tuning effect start, special symbol 1 designation, special figure 1 tuning effect end, and change state designation regarding the above special symbol display 1185. These various commands are assigned "A * H" as a status and "** H" as a mode ("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. It is determined in advance by the specifications of the pachinko gaming machine 1).

The special figure 1 tuning effect start command instructs the start of the special figure tuning effect with the effect pattern specified in the mode, and the special symbol 1 designation command specifies the miss, the specific jackpot, and the non-specific jackpot. , The special figure 1 tuning effect end command is instructing the end of the special drawing 1 tuning effect, and the variable time state designation command is instructing the probability and the time saving state.

As the transmission timing of these various commands, the special symbol 1 tuning effect start command is transmitted at the start of the special symbol 1 fluctuation, and the special symbol 1 designation command is transmitted immediately after the start of the special symbol 1 tuning effect. The effect end command is transmitted when the special symbol 1 variation time has elapsed (when the special symbol 1 is confirmed), and the variation state specification command is transmitted immediately after the special symbol winning information is specified. It should be noted that these various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control side timer interrupt process described later.

[12-2-2. Special figure 2 entrainment production related]
The special drawing 2 tuning effect-related is based on the detection signal from the lower start port switch 2109 shown in FIG. 11, and the classification is divided into the function display board 1191 shown in FIG. 11 as shown in FIG. It is composed of commands named special figure 2 tuning effect start, special symbol 2 designation, and special figure 2 tuning effect end for the lower special symbol display 1186. These various commands are assigned "B * H" as the status and "** H" as the mode ("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. It is determined in advance by the specifications of the pachinko gaming machine 1).

The special figure 2 synchronization effect start command instructs the start of the special figure synchronization effect with the effect pattern specified in the mode, and the special symbol 2 designation command specifies the miss, the specific jackpot, and the non-specific jackpot. , The end of the special figure 2 synchronization effect indicates the end of the special figure 2 synchronization effect.

As the transmission timing of these various commands, the special symbol 2 tuning effect start command is transmitted at the start of the special symbol 2 fluctuation, and the special symbol 2 designation command is transmitted immediately after the start of the special symbol 2 tuning effect. The effect end command is transmitted when the special symbol 2 variation time has elapsed (when the special symbol 2 is confirmed). It should be noted that these various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control side timer interrupt process.

[12-2-3. Big hit related]
As shown in FIG. 32, the categories related to big hits include big hit opening, big winning opening 1 open Nth display, big winning opening 1 closed display, big winning opening 1 count display, big hit ending, big hit symbol display, small hit opening. , Small hit open display, small hit count display, and small hit ending commands. These various commands are assigned "C * H" as a status and "** H" as a mode ("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. It is determined in advance by the specifications of the pachinko gaming machine 1).

The jackpot opening command indicates the start of the jackpot opening, and the Nth display command for opening the jackpot 1 is the start during the opening of the jackpot 1 in the 1st to 16th rounds (the attacker unit 2100 shown in FIG. 8). The command for displaying the opening of the Nth round of the large winning opening 2103 (opening or opening) is instructed, and the large winning opening 1 closing display command starts while the large winning opening 1 is closed between rounds (the large winning opening of the attacker unit 2100). (During closing or starting closing) between 2103 rounds is instructed, and the large winning opening 1 count display command has counted 0 to 10 counts (detected by the count switch 2110 shown in FIG. 11). The number of game balls that have entered the jackpot 2103) is transmitted, the jackpot ending command indicates the start of the jackpot ending, and the jackpot symbol display command indicates the jackpot symbol information display. be.

Further, the small hit opening command indicates the start of the small hit opening, and the small hit open display command starts during the small hit opening (during the opening or opening of the large winning opening 2103 of the attacker unit 2100 at the time of the small hit). The small hit count display command indicates (start), and the small hit count display command is used when the small hit medium / large winning opening winning effect (during the small hit, the game ball that has entered the large winning opening 2103 is detected by the count switch 2110). The production) is instructed, and the small hit ending command is instructed to start the small hit ending.

As the transmission timing of these various commands, the jackpot opening command is transmitted at the start of the jackpot opening, and the Nth display command for opening the jackpot 1 is when the jackpot 1 is opened in the 1st to 16th rounds (large attacker unit 2100). It is sent at the time of opening the Nth round of the winning opening 2103), and the big winning opening 1 closing display command is sent at the time of closing the big winning opening 1 (starting closing of the big winning opening 2103 of the attacker unit 2100), and the big winning opening 1 is closed. The mouth 1 count display command is a count switch when the large winning opening 1 is opened and when the count changes to the large winning opening 1 (when the large winning opening 2103 of the attacker unit 2100 is opened, and the game ball that has entered the large winning opening 2103 is a count switch. (When detected by 2110), the jackpot ending command is transmitted at the start of the jackpot ending, and the jackpot symbol display command is transmitted when the jackpot symbol is opened (when the jackpot 2103 of the attacker unit 2100 is opened). To.

Further, the small hit opening command is transmitted at the start of the small hit opening, and the small hit open display command is transmitted at the time of opening the small hit (when the large winning opening 2103 of the attacker unit 2100 is opened at the time of the small hit). The hit count display command is transmitted at the time of winning the small hit medium / large winning opening (when the game ball entered in the large winning opening 2103 is detected by the count switch 2110 during the small hit), and the small hit ending command is Sent at the start of the small hit ending. It should be noted that these various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control side timer interrupt process.

[12-2-4. Power on]
As shown in FIG. 32, the power-on category is composed of various commands named power-on. This power-on command is assigned a status of "D * H" and a mode of "** H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. It is determined in advance by the specifications of the pachinko gaming machine 1).

The power-on command instructs the start of the RAM clear effect and the start of each state effect (for example, the start of the effect when the operation switch 860a of the payout control board 4110 is operated at the time of turning on the power shown in FIG. 12). It is something to instruct).

As the transmission timing of the power-on command, it is transmitted at a time other than RAM clear and RAM clear when the power of the main control board is turned on. Specifically, when the power of the pachinko gaming machine 1 is turned on, when the pachinko gaming machine 1 recovers from a power failure or a momentary power failure, and when the operation switch 860a of the payout control board 4110 is operated, the main control side power-on processing described later is performed. Is executed, and the power-on command is transmitted in the peripheral control board command transmission process in step S92 in the main control side timer interrupt process.

[12-2-5. Fuzu-tuned production-related]
The normal symbol tuning effect-related is based on the detection signal from the gate switch 2352 shown in FIG. 11, and as shown in FIG. 32, the normal symbol display of the function display board 1191 shown in FIG. 11 is classified. It consists of commands related to the device 1189, which are named as the start of the normal map synchronization effect, the designation of the normal symbol, the end of the normal figure synchronization effect, and the specification of the state at the time of fluctuation. These various commands are assigned "E * H" as the status and "** H" as the mode ("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. It is determined in advance by the specifications of the pachinko gaming machine 1).

The normal figure synchronization effect start command is to instruct the start of the normal figure synchronization effect with the effect pattern specified in the mode, and the normal symbol designation command is to specify the miss, the specific big hit, and the non-specific big hit. The figure tuning effect end command is for instructing the end of the normal figure tuning effect, and the variable time state designation command is for instructing the probability and the time saving state.

As the transmission timing of these various commands, the normal symbol synchronization effect start command is transmitted at the start of the normal symbol 1 fluctuation, the normal symbol designation command is transmitted immediately after the start of the normal symbol synchronization effect, and the normal symbol synchronization effect end command is transmitted. , Is transmitted when the normal symbol fluctuation time has elapsed (when the normal symbol is confirmed), and the command for specifying the variable state is sent immediately after the normal symbol winning information is specified. It should be noted that these various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control side timer interrupt process.

[12-2-6. Ordinary electric role production related]
The normal electric service effect is related to the pair of movable pieces 2106 shown in FIG. 8 which are opened and closed by the drive of the start port solenoid 2105 shown in FIG. 11, and the classification is as shown in FIG. 32. It consists of commands named opening per figure, open display of solenoid, and ending per figure. These various commands are assigned "F * H" as the status and "** H" as the mode ("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. It is determined in advance by the specifications of the pachinko gaming machine 1).

The opening command per normal figure indicates the start of the opening per normal figure, and the open power display command starts while the normal power is open (a pair of movable pieces 2106 expands in the left-right direction by driving the starting port solenoid 2105). The ending command per normal figure indicates the start of the ending per normal figure.

As the transmission timing of these various commands, the opening command per drawing is transmitted at the start of the opening per drawing, and the opening display command is sent when the opening is open (a pair of movable pieces 2106 are driven by the starting port solenoid 2105). It is transmitted at the time of expanding in the left-right direction), and the ending command per normal figure is transmitted at the start of the ending per normal figure. It should be noted that these various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control side timer interrupt process.

[12-2-7. Notification display]
As shown in FIG. 33, the notification display category is composed of commands named winning abnormality display, connection abnormality display, disconnection / short circuit abnormality display, magnetic detection switch abnormality display, door opening, and door closing. These various commands are assigned a status of "6 * H" and a mode of "** H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. It is determined in advance by the specifications of the pachinko gaming machine 1).

The prize abnormality display command is issued when a game ball enters the big prize opening 2103 of the attacker unit 2100 even though it is not a big hit (even though it is not a big hit) other than during the big hit (condition device is operating). When the count switch 2110 is detected), the start of the winning abnormality notification is instructed, and the connection abnormality display command is, for example, an electrical connection in the path between the main control board 4100 and the payout control board 4110. When there is an abnormality, it is instructed to start the connection abnormality notification, and the disconnection / short-circuit abnormality display command is, for example, the main control board 4100, the upper start port switch 3022, the lower start port switch 2109, the count switch 2110, and the like. Instructs the start of the disconnection / short-circuit error display when the electrical connection is broken / short-circuited, and the magnetic detection switch error display command causes an error in the magnetic detection switch 3024 shown in FIG. In this case, the magnetic detection switch indicates the start of abnormality notification.

Further, in the door opening command, the door frame 5 is directed to the main body frame 3 based on the detection signal (opening signal) from the door frame opening switch 618 input via the payout control board 4110 shown in FIG. When the door is in the opened state, the door opening notification is instructed, and the door frame closing command causes the door frame 5 to close with respect to the main body frame 3 based on the detection signal from the door frame opening switch 618. This is to instruct the end of the door opening notification when the door is in the closed state. On the other hand, in the main body frame opening command, the main body frame 3 is directed to the outer frame 2 based on the detection signal (opening signal) from the main body frame opening switch 619 input via the payout control board 4110 shown in FIG. In the open state, the main body frame opening notification is instructed, and the main body frame closing command is issued to the main body frame 3 with respect to the outer frame 2 based on the detection signal from the main body frame opening switch 619. This is to instruct the end of the main body frame opening notification when it is in the closed state.

As the transmission timing of these various commands, the winning abnormality display command is transmitted when a prize is won in the big winning opening other than during the big hit (condition device is operating), and the connection abnormality display command is sent from the main control board 4100 to the payout control board 4110. When there is no ACK reply (ACK signal) from the payout control board 4110 when the command is sent to, the disconnection / short circuit error display command is among the upper start port switch 3022, lower start port switch 2109, count switch 2110, etc. , Which is transmitted when the wire is broken or short-circuited, and the magnetic detection switch abnormality display command is transmitted when an abnormality of the magnetic detection switch 3024 is detected. Further, the door opening command is transmitted when the door opening is detected (when the door frame 5 is in the open state with respect to the main body frame 3 based on the detection signal from the door frame opening switch 618), and the door is opened. The frame closing command is transmitted when the door closing is detected (when the door frame 5 is closed with respect to the main body frame 3 based on the detection signal from the door frame opening switch 618). The main body frame opening command is transmitted when the main body frame opening is detected (when the main body frame 3 is in a state of being opened with respect to the outer frame 2 based on the detection signal from the main body frame opening switch 619), and the main body is sent. The frame closing command is transmitted when the main body frame closing is detected (when the main body frame 3 is in a closed state with respect to the outer frame 2 based on the detection signal from the main body frame opening switch 619). It should be noted that these various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control side timer interrupt process.

[12-2-8. Status display]
As shown in FIG. 33, the status display division consists of commands named frame status 1 command (corresponding to an error occurrence command), error cancellation navigation command (corresponding to an error cancellation command), and frame status 2 command. There is. These various commands are assigned a status of "7 * H" and a mode of "** H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. It is determined in advance by the specifications of the pachinko gaming machine 1).

The frame state 1 command, the error release navigation command, and the frame state 2 command are commands having a storage capacity of 1 byte (8 bits) transmitted from the payout control board 4110, respectively, and detailed description thereof will be described later. .. When the main control MPU 4100a of the main control board 4100 receives the frame state 1 command, the error release navigation command, and the frame state 2 command from the payout control board 4110, it outputs "7 * H" as shown in FIG. 33. Set it as a status and set the received command as it is as a mode. That is, when the main control MPU4100a receives the frame state 1 command, the error release navigation command, and the frame state 2 command from the payout control board 4110, the additional information "7 * H" is added to these received commands. Formates the command into a command having a storage capacity of 2 bytes (16 bits).

The formatted frame state 1 command is sent at the time of power recovery, frame state change, and error cancellation navigation, the error cancellation navigation command is sent at the time of error cancellation navigation, and the frame state 2 command is sent at the time of power recovery. , And when the frame state changes. The formatted frame state 1 command, error release navigation command, and frame state 2 command are actually transmitted by the peripheral control board command transmission process in step S92 in the main control side timer interrupt process.

[12-2-9. Test related]
As shown in FIG. 33, the test-related category is composed of various commands named tests. This test command is assigned "8 * H" as the status and "** H" as the mode ("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. It is determined in advance by the specification contents of the pachinko gaming machine 1).

The test command instructs various inspections of the peripheral control board 4140 (for example, the peripheral control unit 4150, the liquid crystal display and the sound control unit 4160, the lamp drive board 4170, the motor drive board 4180, and the frame shown in FIG. 14). It inspects various boards such as the decorative drive amplifier board 194).

As the transmission timing of the test command, it is transmitted at a time other than RAM clear and RAM clear when the main control board power is turned on. Specifically, when the power of the pachinko gaming machine 1 is turned on, when the pachinko gaming machine 1 recovers from a power failure or a momentary power failure, and when the operation switch 860a of the payout control board 4110 is operated, the main control side power-on processing described later is performed. Is executed, and a test command is transmitted in the peripheral control board command transmission process in step S92 in the main control side timer interrupt process.

[12-2-10. others]
In other categories, as shown in FIG. 33, start opening winning, fluctuation shortening operation end designation, high probability end designation, special symbol 1 memory, special symbol 2 memory, normal symbol memory, special symbol 1 memory look-ahead effect, and Special symbol 2 Consists of a command named memory look-ahead effect. These various commands are assigned a status of "9 * H" and a mode of "** H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. It is determined in advance by the specifications of the pachinko gaming machine 1).

The start opening winning command instructs to start the starting opening winning effect, and starts the effect when the game ball enters the upper starting port 2101 based on the detection signal from the upper starting port switch 3022, and lower. Based on the detection signal from the start port switch 2109, it is instructed to start the effect when the game ball enters the lower start port 2102, and the variable shortening operation end designation command is from the variable shortening operation state. The variable shortening non-operation state is instructed, the high-probability end designation command is instructed to change the state from the high-probability state to the low-probability state, and the special symbol 1 storage command is a special symbol. 1 Hold 0 to 4 (The number of balls that have not been used for the variable display of the special symbol on the upper special symbol display 1185 of the function display board 1191 when the game ball enters the upper starting port 2101 shown in FIG. 8 ( (Number of holds))), and the special symbol 2 storage command is a special symbol 2 hold 0 to 4 (the lower special of the function display board 1191 when the game ball enters the lower start opening 2102 shown in FIG. 8). The symbol display 1186 conveys the number of balls (reserved number) that have not yet been used for the variable display of the special symbol, and the normal symbol storage command is the normal symbol 1 hold 0 to 4 (gate shown in FIG. 8). The game ball passes through the unit 2350, and the normal symbol display 1189 of the function display board 1191 conveys the number of balls (holding number) that have not yet been used for the variable display of the normal symbol. The command is pre-read and displayed by the upper special symbol display 1185 based on the special symbol 1 hold before the special symbol 1 hold is used for the variable display of the special symbol on the upper special symbol display 1185 of the function display board 1191. The special symbol 2 storage look-ahead effect command is used to indicate the change of the special symbol on the special symbol display 1186 under the function display board 1191. Before this, the command is instructed to start the look-ahead effect of pre-reading and notifying the notice of the display result by the lower special symbol display 1186 based on the special symbol 2 hold.

As the transmission timing of these various commands, the start port winning command is used when the start port wins (when a game ball enters the upper start port 2101 based on the detection signal from the upper start port switch 3022, or when the game ball enters the upper start port switch, or the lower start port switch. When the game ball enters the lower starting port 2102 based on the detection signal from 2109), the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the door frame shown in FIG. It is transmitted from the speaker 130 provided in No. 5 mainly to notify the effect by voice, and the fluctuation shortening operation end designation command is sent at the end of the stop period after the fluctuation is confirmed after digesting the fluctuation shortening of the specified number of times (elapsed stop period). The high-probability end designation command is sent at the end of the stop period after the fluctuation is confirmed (after the out-of-order stop period has elapsed) after digesting the high-probability number of times in the case of "high probability N times", and the special symbol 1 The storage command is a hold that has not yet been used to display the fluctuation of the special symbol on the upper special symbol display 1185 of the function display board 1191 when the number of balls on hold for operating the special symbol 1 changes (a game ball enters the upper start port 2101). When there is a number, when a game ball enters the upper start port 2101 and the number of holdings increases, or when the number of holdings is used to display the fluctuation of the special symbol on the upper special symbol display 1185, the number of holdings The special symbol 2 storage command is sent when the number of special symbol 2 operation pending balls changes (when the game ball enters the lower start port 2102 and the special symbol 2 storage command is displayed on the lower special symbol display 1186 of the function display board 1191). When there is a hold number that has not yet been used for the variable display of the special symbol, and when the game ball enters the lower start port 2102 and the hold number increases, or from the hold number, the lower special symbol display 1186 It is sent when the number of reserved balls is reduced by using it for variable display of special symbols, and the normal symbol storage command is sent when the number of reserved balls for normal symbol 1 is changed (when the game ball passes through the gate 2350 and the number of reserved balls is changed), the function display board. When the game ball passes through the gate 2350 and the number of holds increases in the state where there is a hold number that has not yet been used for the variable display of the normal symbol on the 1191 normal symbol display 1189, or from the hold number, it is normal. It is transmitted on the symbol display 1189 when it is used for variable display of a normal symbol and the number of reserved balls decreases), and the special symbol 1 storage look-ahead effect command is sent when the number of special symbol 1 operation reserved balls increases (at the upper start port 2101). It is transmitted when the game ball enters and the number of reserved balls increases), and the special symbol 2 storage look-ahead effect command is sent when the number of special symbol 2 operation reserved balls increases (the game ball enters the lower start port 2102). It is sent when the number of pending balls increases). It should be noted that these various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control side timer interrupt process.

By the way, as described above, the starting port winning command is issued at the time of winning the starting opening (when the game ball enters the upper starting opening 2101 based on the detection signal from the upper starting opening switch 3022, or from the lower starting opening switch 2109. When a game ball enters the lower starting port 2102 based on the detection signal of the above), the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 are mainly voiced. Although it is transmitted to notify the effect, how the peripheral control board 4140 shown in FIG. 14 uses the start opening winning command may differ depending on the specifications of the pachinko gaming machine. For example, in the pachinko gaming machine 1 of the present embodiment, in addition to notifying by voice from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the presence or absence of fraudulent activity is monitored. It is a specification that is also used for the purpose. On the other hand, in other pachinko gaming machines, the peripheral control board 4140 simply receives the start opening winning command, and the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5. There is also a specification that does not notify by voice from 130.

[12-3. Various commands from the payout control board received by the main control board]
Next, various commands from the payout control board 4110 received by the main control board 4100 will be described.

As shown in FIG. 34, the classification of various commands from the payout control board 4110 consists of commands named frame state 1, error release navigation, and frame state 2, frame state 1, error release navigation, and The priority is set in the order of the frame state 2.

The frame state 1 command (corresponding to the error occurrence command) includes out-of-ball, full tank, stock of 50 or more, connection error and CR not connected, and bit 0 (B0, "B") when out of ball. Represents a bit.) Is set to a value 1, a value 1 is set to bit 1 (B1) when the tank is full, a value 1 is set to bit 2 (B2) in stock of 50 or more, and a connection error occurs. The value 1 is set in the bit 3 (B3), and the value 1 is set in the bit 4 (B4) when the CR is not connected. Bits 5 (B5) to 7 (B7) of the frame state 1 command are set to have a value of 1 in B5, a value of 0 in B6, and a value of 0 in B7.

The error release navigation command (corresponding to the error release command) has a ball, count switch error, and retry error. For the ball, bit 2 (B2) is set to a value of 1, and for a count switch error. The value 1 is set in the bit 3 (B3), and the value 1 is set in the bit 4 (B4) in the retry error. Here, the "counting switch error" indicates whether or not the counting switch 751 shown in FIG. 12 has a malfunction. The "retry error" indicates that the inconsistent game ball is repeatedly paid out by the retry operation. Bit (B0), bit (B1), and bit 5 (B5) to bit 7 (B7) of the error clear navigation command have a value of 0 for B0, a value of 0 for B1, a value of 0 for B5, and a value of 1 for B6. And the value 0 is set in B7.

The frame state 2 command is prepared during ball removal, and the value 1 is set to bit 0 (B0) during ball removal. Bit 1 (B1) to bit 7 (B7) of the frame state 2 command have a value of 0 for B1, a value of 0 for B2, a value of 0 for B3, a value of 0 for B4, a value of 1 for B5, a value of 1 for B6, and so on. The value 0 is set in B7.

As the transmission timing of these various commands, the frame state 1 command is transmitted at the time of power restoration, the frame state change, and the error release navigation, and the error release navigation command is transmitted at the error release navigation, and the frame state 2 command is transmitted. Is transmitted when the power is restored and when the frame state changes. It should be noted that these various commands are actually transmitted in the command transmission process of step S558 in the payout control section main process of the payout control section power-on process, which will be described later.

[13. Various control processes on the main control board]
Next, various control processes performed by the main control board 4100 shown in FIG. 11 according to the progress of the game of the pachinko gaming machine 1 will be described with reference to FIGS. 35 to 37. FIG. 35 is a flowchart showing an example of the main control side power-on processing, FIG. 36 is a flowchart showing the continuation of the main control-side power-on processing of FIG. 35, and FIG. 37 is an example of the main control side timer interrupt processing. It is a flowchart which shows. First, various random numbers used for game control will be described, and then the operation of the initial value update type counter, the main control side power-on processing, and the main control side timer interrupt processing will be described.

[13-1. Various random numbers]
As various random numbers used for game control, a big hit determination random number to be used for determining whether or not to generate a big hit game state, and a big hit determination initial value determination to be used for determining the initial value of this big hit determination random number. Random numbers for, reach determination random numbers for determining whether to generate reach (reach loss) when the jackpot game state is not generated, and the upper special symbol display 1185 and lower special shown in FIG. A random number for a variable display pattern used to determine a variable display pattern of a special symbol that is variablely displayed on the symbol display 1186, and an upper special symbol display 1185 and a lower special symbol display 1186 when a big hit game state is generated. When generating a random number for the jackpot symbol to be used for determining the jackpot symbol to be derived and displayed, a random number for determining the initial value for the jackpot symbol to be used for determining the initial value of the random number for the jackpot symbol, and a small hit game state. The small hit symbol random number to be used for determining the small hit symbol derived and displayed by the upper special symbol display 1185 and the lower special symbol display 1186, and the small hit to be used to determine the initial value of this small hit symbol random number. Random numbers for determining the initial value for the design are prepared. Further, in addition to these random numbers, a random number for determining a normal symbol hit to be used for determining whether or not to open / close the movable piece 2106 shown in FIG. 8 and an initial value of the random number for determining a normal symbol hit are determined. Random numbers for determining the initial value for determining the normal symbol hit to be used, and random numbers for the normal symbol variation display pattern used for determining the variation display pattern of the normal symbol that is variablely displayed by the normal symbol display 1189 shown in FIG. Is prepared.

For example, the counter that updates the random number for jackpot determination is updated within a predetermined fixed numerical range from the minimum value to the maximum value (in the present embodiment, the minimum value is 0 to the maximum value is 32767). The range from the minimum value to the maximum value is counted up by adding a value of 1 each time a timer interrupt process on the main control side, which will be described later, is performed. This counter counts up from the random number for determining the initial value for jackpot determination toward the maximum value, and then counts up from the minimum value toward the random number for determining the initial value for jackpot determination. When the counter finishes counting up the range from the minimum value to the maximum value of the big hit determination random number, the big hit determination initial value determination random number is updated. Such a counter update method is called an "initial value update type counter". The random number for determining the initial value for jackpot determination can be obtained by executing the initial value lottery process in which one value is drawn from the fixed numerical value range of the counter that updates the random number for jackpot determination. Further, the above-mentioned random number for determining the normal symbol hit and the random number for determining the initial value for determining the normal symbol hit are also the same as the above-mentioned method for updating the random number for determining the big hit.

In the present embodiment, when the counter for updating the big hit judgment random number finishes counting up in the range from the minimum value to the maximum value of the big hit judgment random number, as described above, for determining the initial value for big hit judgment. The random numbers are updated by executing the initial value lottery process, but when the operation switch 860a of the payout control board 4110 shown in FIG. 12 is operated when the power is turned on, or when the main control side is described later. The check sum value (sum value) obtained by calculating the total of the game information stored in the main control built-in RAM of the main control MPU4100a shown in FIG. 11 as a numerical value in the power-on processing is the main control side. When clearing the entire area of the main control built-in RAM, such as when the check sum value (sum value) stored in the power off processing (power off) does not match, the initial value for jackpot judgment is determined. The random numbers for big hits are always the same from the fixed numerical range of the counter that the main control MPU4100a shown in FIG. 11 takes out the ID code from the built-in non-volatile RAM and updates the random number for big hit determination based on the taken out ID code. The initial value derivation process for deriving a fixed value is executed, and the derived fixed value is set. That is, the random number for determining the initial value for jackpot determination is always overwritten and updated with the same fixed value derived based on the ID code by executing the initial value derivation process. In this way, the value set in the random value for determining the initial value for jackpot determination is derived using the ID code, and the ID is stored in the non-volatile RAM built in the main control MPU4100a by the manufacturer of the main control MPU4100a. Based on the ID code by the first security measure that the ID code cannot be rewritten even if the external device is used when the code is stored, and by executing the initial value derivation process when clearing the entire area of the main control built-in RAM. The second security measure of deriving the same fixed value and the two-step security measure are taken to prevent analysis.

Here, an advantage of extracting an ID code from the non-volatile RAM built in the main control MPU4100a and using the extracted ID code as a random number for determining an initial value for jackpot determination will be described. For example, a person who illegally obtains a game ball to be paid out as a prize ball obtains the game board 4 by some method, disassembles it, and inputs an ID code stored in advance in the non-volatile RAM built in the main control MPU 4100a. Even if it is possible to grasp the timing at which the value of the counter that illegally acquires and updates the jackpot judgment random number and the jackpot judgment value match, the ID code is given a unique code for identifying the individual. Therefore, the ID code is completely different from the ID code stored in advance in the non-volatile RAM built in the main control MPU4100a' provided in the other game board 4'. That is, in the other game board 4', the timing at which the value of the counter for updating the big hit determination random number and the big hit determination value match is also completely different from that of the obtained game board 4. In other words, the ID code obtained by disassembling and analyzing the obtained gaming board 4 is completely useless in another gaming board 4', that is, another pachinko gaming machine 1', so it is disassembled and analyzed. Even if you aim for a start-up prize in which a momentary power failure is generated at each predetermined interval obtained and a game ball is inserted into the upper start opening 2101 and the lower start opening 2102 shown in FIG. 8 at each predetermined interval, a big hit is achieved. The gaming state cannot be generated.

[13-2. Initial value update type counter operation]
When the initial value update type counter clears the entire area of the main control built-in RAM (when the RAM is cleared), the main control MPU4100a takes out an ID code from the built-in non-volatile RAM, and based on the taken out ID code. The initial value derivation process for always deriving the same fixed value from the fixed numerical range of the counter that updates the jackpot determination random number is executed, and the derived fixed value is set. The initial value update type counter counts up from this fixed value toward the maximum value, and then counts up from the minimum value toward the fixed value in the first cycle. When the counter finishes counting up the range from the minimum value to the maximum value of the big hit judgment random number, one value is drawn from the fixed numerical range of the counter that updates the big hit judgment random number as the big hit judgment initial value determination random number. The initial value lottery process is executed, and the value obtained in this lottery is set. In the second cycle, the initial value update type counter counts up from the value obtained by lottery toward the maximum value, and then counts up from the minimum value toward the value obtained by lottery. When the counter finishes counting up the range from the minimum value to the maximum value of the big hit judgment random number, the initial value lottery process is executed again, the value obtained in this lottery is set, and the initial value update type counter is used. In the third cycle, the value obtained by lottery will be counted up toward the maximum value. In the present embodiment, the value 32668 to the value 32767 are set as the range of the jackpot determination value (big hit determination range) with a low probability, and are read from the normal time determination table, whereas the value 31768 to the value with a high probability is set. 32767 is set and is read from the probability change determination table. In the present embodiment, the counter that updates the random number for jackpot determination updates a predetermined fixed numerical range ranging from a value of 0 as a minimum value to a value of 32767 as a maximum value. In other words, the range of the jackpot judgment value (big hit judgment range) is the range closer to the maximum value side from the intermediate value (value 16384) between the minimum value and the maximum value in both the low probability and the high probability. It is set.

Here, as the range of the big hit judgment value (big hit judgment range), the case where the value 10 to the value 209 is set in the low probability and the value 10 to the value 339 is set in the high probability is examined. The value range (big hit judgment range) is set to the range closer to the minimum value side from the intermediate value (value 16384) between the minimum value and the maximum value in both the low probability and the high probability. .. In such a case, the period from the timing when the value of the initial value update type counter becomes the value 0 to the time when the first value 10 in the range of the big hit judgment value (big hit judgment range) and this value 10 Comparing the period from the next value 11 to the maximum value (value 32767), the probability that the former period is drawn by the above-mentioned initial value lottery process is extremely lower than that of the latter period. In other words, the range from the timing when the value of the initial value update type counter becomes the value 0 to the last value (value 209 in low probability, value 339 in high probability) in the range of big hit judgment value (big hit judgment range). Comparing the range from the value next to this last value (value 210 for low probability, value 340 for high probability) to the maximum value (value 32767), the former range is the latter. The probability of being drawn by the initial value lottery process is extremely low compared to the range. Then, for example, the game ball is started upward by illegally acquiring the timing when the value of the initial value update type counter becomes the value 0 by some method and irradiating the radio waves toward the upper start port 2101 and the lower start port 2102. When a fraudulent act pretending to have entered the mouth 2101 or the lower starting port 2102 is performed, the value of the initial value update type counter becomes one of the jackpot judgment value ranges (big hit judgment range). It can be said that the probability is high.

On the other hand, as in the present embodiment, the range of the jackpot determination value (big hit determination range) is from the intermediate value (value 16384) between the minimum value and the maximum value in both the low probability and the high probability. If it is set to a range closer to the maximum value side, it is before the first value in the jackpot judgment value range (big hit judgment range) from the timing when the value of the initial value update type counter becomes the value 0. The period from the initial value (value 32668 in low probability, value 31768 in high probability) to the maximum value (value 32767) and the period until the value (value 32667 in low probability, value 31767 in high probability). Compared with the above, the probability that the former period is drawn by the above-mentioned initial value lottery process is extremely higher than that of the latter period. In other words, the value before the first value in the range of the big hit judgment value (big hit judgment range) from the timing when the value of the initial value update type counter becomes the value 0 (value 32667 in low probability, value 31767 in high probability). Comparing the range up to and the range from the first value (value 32668 with high probability, value 31768 with high probability) to the maximum value (value 32767), the former range is compared with the latter range. The probability of being drawn by the initial value lottery process is extremely high. Then, the initial value update type counter has a range from the value 0 to the value before the first value in the range of the big hit judgment value (big hit judgment range) (value 32667 in low probability, value 31767 in high probability). Of these, one of the values becomes the value drawn by the initial value lottery process and is set in the above-mentioned random number for determining the initial value for jackpot determination. Therefore, from the value obtained in this lottery toward the maximum value. It counts up, and then counts up from the minimum value toward the value obtained by lottery. When the counter finishes counting up the range from the minimum value to the maximum value of the big hit judgment random number, the initial value lottery process is executed again, the value obtained in this lottery is set, and the initial value update type counter is used. , The value obtained by lottery will be counted up toward the maximum value.

That is, as in the present embodiment, the range of the jackpot determination value (big hit determination range) is either the low probability or the high probability, and the intermediate value (value 16384) between the minimum value and the maximum value is on the maximum value side. When the value is set to a range closer to, the value before the first value in the range of the big hit judgment value (big hit judgment range) from the timing when the value of the initial value update type counter becomes the value 0 (low). The period until the value becomes 32667 in probability and 31767) in high probability becomes irregular, and is rich in randomness. As a result, for example, the game ball is raised by illegally acquiring the timing at which the value of the initial value update type counter becomes 0 by some method and irradiating the radio waves toward the upper start port 2101 and the lower start port 2102. Even if a fraudulent act pretending to have entered the starting port 2101 or the lower starting port 2102 is performed, the value of the initial value update type counter is one of the range of the jackpot judgment value (big hit judgment range). It can be said that the probability of becoming a value is low.

The initial value update type counter is repeatedly updated in the range from the minimum value to the maximum value. From the minimum value (first value) in the range of the jackpot judgment value (big hit judgment range) from the initial value to the minimum value (first value) of the jackpot judgment value range (big hit judgment range) in the second cycle. The time required is time T0. The time required for the counter to reach the minimum value (first value) of the jackpot judgment value range (big hit determination range) in the third cycle from the time T0 is the time T1, and the time T1 is shorter than the time T0. .. In the 4th cycle from the time T1, the time required for the counter to reach the minimum value (first value) in the range of the big hit judgment value (big hit judgment range) is the time T2, and the time T2 is shorter than the time T1. .. In this way, in the initial value update type counter, the time at which the updated counter becomes the minimum value (first value) of the jackpot judgment value range (big hit judgment range) is allowed to have fluctuation (periodicity). (By eliminating the), it is not detected by the player.

[13-3. Main control side power-on processing]
When the power is turned on to the pachinko gaming machine 1, the above-mentioned main control program performs the main control side power-on processing as shown in FIGS. 35 and 36 under the control of the main control MPU4100a of the main control board 4100. conduct. When the main control side power-on processing is started, the main control program sets the stack pointer under the control of the main control MPU4100a (step S10). The stack pointer indicates, for example, the address stacked on the stack for temporarily storing the contents of the storage element (register) in use, or temporarily returns the return address of this routine when the subroutine is terminated and returned to this routine. It indicates the address stacked on the stack for storage, and the stack pointer advances each time the stack is stacked. In step S10, the main control program sets the initial address on the stack pointer, and from this initial address, the contents of the register, the return address, and the like are pushed onto the stack. Then, the stack pointer returns to the initial address by reading in order from the last stacked stack to the first stacked stack.

Following step S10, the main control program starts outputting a power failure clear signal to the power failure monitoring circuit 4100e shown in FIG. 23 (step S11). The power failure monitoring circuit 4100e is composed of a comparator MIC 21 which is a voltage comparison circuit and a D type flip-flop MIC 22. The comparator MIC21, which is a voltage comparison circuit, outputs the comparison result by comparing the voltage between + 24V and the reference voltage or comparing the voltage between + 12V and the reference voltage. This comparison result becomes HI when no power failure or momentary power failure occurs and is input to the PR terminal which is the preset terminal of the D type flip-flop MIC22, while when a power failure or momentary power failure occurs. The logic becomes LOW and is input to the PR terminal which is a preset terminal of the D type flip-flop MIC22. In step S11, the output of the power failure clear signal is started to the CLR terminal which is the clear terminal of the D type flip-flop MIC22. This power failure clear signal is input from the output terminal of the predetermined output port of the main control MPU 4100a to the CLR terminal which is the clear terminal of the D type flip-flop IC via the main control output circuit 4100ca with a reset function with its logic as LOW. Will be done. As a result, the main control MPU4100a can release the latch state of the D-type flip-flop MIC22, and until the latch state is set, the logic input to the PR terminal which is the preset terminal of the D-type flip-flop MIC22 is input. It can be inverted and output from the 1Q terminal, which is an output terminal, and the signal from the 1Q terminal can be monitored.

Following step S12, the main control program performs wait timer processing 1 (step S12), and determines whether or not a power failure warning signal has been input (step S14). The voltage does not rise immediately from the time the power is turned on until the specified voltage is reached. On the other hand, when a power failure or a momentary power failure (a phenomenon in which the power supply is temporarily stopped) occurs, the voltage drops, and when the voltage becomes smaller than the power failure warning voltage, a power failure warning signal is input from the power failure monitoring circuit 4100e as a power failure warning signal. Similarly, when the voltage becomes smaller than the power failure warning voltage between the time when the power is turned on and the voltage rises to the predetermined voltage, the power failure warning signal is input from the power failure monitoring circuit 4100e. Therefore, the wait timer process 1 in step S12 is a process for waiting until the voltage becomes larger than the power failure warning voltage and stabilizes after the power is turned on. In the present embodiment, the waiting time (wait timer) is 200 milliseconds (waiting timer). ms) is set. In the determination in step S14, it is determined whether or not the power failure warning signal is input. This determination is performed based on the signal output from the 1Q terminal, which is the output terminal of the above-mentioned D type flip-flop MIC 22, as the power failure warning signal.

If there is no power failure warning signal input even after waiting until the voltage becomes higher than the power failure warning voltage and stabilizes after the power is turned on in step S14, the main control program causes a power failure at the CLR terminal, which is the clear terminal of the D-type flip-flop MIC22. The output of the clear signal is stopped (step S15). Here, the power failure clear signal is a CLR terminal which is a clear terminal of the D type flip-flop IC via the main control output circuit 4100ca with a reset function, with its logic as HI from the output terminal of the predetermined output port of the main control MPU4100a. Is entered in. Thereby, the main control MPU4100a can set the D type flip-flop MIC 22 in the latch state. The D-type flip-flop MIC 22 outputs a power failure warning signal from the 1Q terminal, which is an output terminal, when the state in which the logic is input to the PR terminal, which is the preset terminal, is latched as LOW.

Following step S15, the main control program is in a state in which the RAM clear process for initializing the main control built-in RAM (game storage unit) can be executed for a predetermined time from the time when the power is turned on (when the power is turned on on the game side). Operation control means). Specifically, the main control program first determines whether or not the operation switch 860a of the payout control board 4110 shown in FIG. 12 is operated (step S16). In this determination, the main control program inputs an error release navigation command (first error release command) based on the operation signal (detection signal) associated with the operation of the operation switch 860a of the payout control board 4110 to the main control MPU 4100a. It depends on whether or not it is done. Based on the logical value of the operation signal, the main control program determines that it does not instruct to clear the RAM when the logical value of the operation signal from the operation switch 860a is HI, and the operation switch 860a operates. On the other hand, when the logical value of the operation signal from the operation switch 860a is LOW, it is determined that the operation switch 860a is not operated, and it is determined that the operation switch 860a is operated.

In step S16, the main control program sets the value 1 in the RAM clear notification flag RCL-FLG when the operation switch 860a is being operated (step S18). On the other hand, when the operation switch 860a is not operated in step S16, the main control program sets the value 0 in the RAM clear notification flag RCL-FLG (step S20). That is, the main control program can execute a RAM clear process that initializes the RAM (hereinafter, referred to as "main control built-in RAM") built in the main control MPU4100a for a predetermined time from the time when the power is turned on. (Operation control means when the power is turned on on the game control side). The above-mentioned RAM clear notification flag RCL-FLG determines whether or not to erase game information related to games such as probability fluctuations and unpaid prize balls stored in the main control built-in RAM (game storage unit) of the main control MPU4100a. This flag is set to a value of 1 when the game information is deleted and a value of 0 when the game information is not deleted. The value of the RAM clear notification flag RCL-FLG set in steps S18 and S20 is stored in the general-purpose storage element (general-purpose register) of the main control MPU4100a.

Following step S18 or step S20, the main control program performs wait timer processing 2 (step S22). In this wait timer process 2, the system that controls the drawing of the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the plate side by the liquid crystal display of the peripheral control board 4140 and the sound control unit 4160, which is shown in FIG. Wait until boot). In this embodiment, 2 seconds (s) is set as the time until booting (boot timer).

Following step S22, the main control program determines whether or not the RAM clear notification flag RCL-FLG has a value of 0 (step S24). As described above, the RAM clear notification flag RCL-FLG is set to a value of 1 when the game information is erased and a value of 0 when the game information is not erased. When the RAM clear notification flag RCL-FLG has a value of 0 in step S24, that is, when the game information is not erased, the checksum is calculated (step S26). This checksum regards the game information stored in the main control built-in RAM as a numerical value and calculates the total.

Following step S26, in the main control program, the calculated checksum value (sum value) is the checksum value (sum value) stored in the main control side power off time processing (power off) described later. It is determined whether or not they match (step S28). When they match, this main control program determines whether or not the backup flag BK-FLG has a value of 1 (step S30). The backup flag BK-FLG stores game information, checksum value (sum value), backup flag BK-FLG value, and other game backup information in the main control built-in RAM in the main control side power cutoff process described later. It is a flag indicating whether or not the power is turned off, and is set to a value of 1 when the main control side power cutoff process is normally completed and a value of 0 when the main control side power cutoff process is not normally completed.

When the backup flag BK-FLG has a value of 1 in step S30, that is, when the main control side power cutoff process is normally completed, the main control program sets the work area of the main control built-in RAM as the time of power recovery ( Step S32). For this setting, in addition to setting the value 0 to the backup flag BK-FLG, the power recovery information is read from the ROM built in the main control MPU4100a (hereinafter referred to as "main control built-in ROM"), and this power recovery is performed. The time information is set in the work area of the main control built-in RAM. In addition, "recovery" means that the power is turned on from the state where the power is cut off, the state where the power is restored after the power failure or momentary power failure, and the state where high frequency is irradiated is detected and reset. The state of returning after that is also included.

Following step S32, the main control program performs a power-on command creation process (step S34). In this power-on command creation process, the game information is read from the game backup information, and various commands corresponding to the game information are stored in a predetermined storage area of the main control built-in RAM.

On the other hand, when the RAM clear notification flag RCL-FLG is not a value 0 (value 1) in step S24, that is, when the game information is erased, or when the checksum values (sum values) do not match in step S28. Or, when the backup flag BK-FLG is not a value 1 (value 0) in step S30, that is, when the main control side power cutoff process is not normally completed, the main control program is used for all of the main control built-in RAM. Clear the area (step S36). That is, the main control program executes the game control control side RAM clear process triggered by the input of the detection signal accompanying the operation of the operation switch 860a described above (the payout control side power-on operation control means). Specifically, the main control program performs by writing the value 0 to the main control built-in RAM. Instead, the main control program may read a predetermined value from the main control built-in ROM as an initial value and set it. Further, the main control MPU4100a performs processing when the logical value of the operation signal from the operation switch 860a indicates RAM clear and the game information is erased, when the sum values do not match, or when the main control side power is turned off. When it is not completed normally, the unique ID code stored in advance in the non-volatile RAM of the main control MPU4100a is taken out, and the random number for jackpot determination is updated based on the taken out ID code. The initial value derivation process for deriving the same fixed value is performed, and this fixed value is set as the random number for determining the initial value for jackpot determination to be used for determining the initial value of the above-mentioned random number for jackpot determination.

Following step S36, the main control program sets the work area of the main control built-in RAM as an initial setting (step S38). This setting is performed by reading the initial information from the main control built-in ROM and setting this initial information in the work area of the main control built-in RAM.

Following step S38, the main control program performs RAM clear notification and test command creation processing (step S40). In this RAM clear notification and test command creation process, a power-on command classified into power-on as shown in FIG. 32 for notifying that the main control built-in RAM has been cleared and the initial setting has been performed is created, and peripherals are created. Test commands classified in relation to the test shown in FIG. 33 for performing various inspections of the control board 4140 are created and stored as transmission information in the transmission information storage area of the main control built-in RAM.

Following step S34 or step S40, the main control program performs interrupt initial setting (step S42). This setting sets the interrupt cycle when the main control side timer interrupt process, which will be described later, is performed. In this embodiment, it is set to 4 ms.

Following step S42, the main control program sets interrupt enable (step S44). With this setting, the main control side timer interrupt process is repeatedly performed every 4 ms, that is, the interrupt cycle set in step S42.

Following step S44, the main control program receives an error release navigation command associated with the operation of the operation switch 860a (operation switch) when a predetermined time has elapsed from the time when the power is turned on, that is, when the main control side main process is started. Execution of the game control side RAM clear process triggered by receipt is restricted (normal operation control means). As described above, the main control program uses the concept of time sharing to input the detection signal input by operating the operation switch 860a to the error release navigation command for a predetermined time from the time when the power is turned on as described above. The RAM clear process is executed with the input as an opportunity (operation control means when the power is turned on on the game control side), and the execution of the RAM clear process is restricted even if the error release navigation command is input after the predetermined time has elapsed (the execution of the RAM clear process is restricted). (Game control side normal operation control means), it is handled as a release switch for canceling the error notification associated with the generated error. That is, the operation switch 860a (error canceling unit), which was originally supposed to be used to cancel the error generated in the payout operation, is used as a game storage unit instead of the operation switch 860a (error canceling unit) for a predetermined time from the time when the power is turned on. Functions as an operation unit for executing RAM clear processing for starting initialization of the main control built-in RAM (and the payout control built-in RAM as a payout storage unit described later), or after the lapse of the predetermined time, a game It can function as an operation unit for canceling an error that occurs in the ball payout operation.

Next, the main control program sets the value A in the watchdog timer clear register WCL (step S46). The watchdog timer is set to clear by setting the value A, the value B, and the value C in order in the watchdog timer clear register WCL.

Following step S46, the main control program determines whether or not a power failure warning signal has been input (step S48). As described above, when the power of the pachinko gaming machine 1 is cut off, a power failure or a momentary power failure occurs, when the voltage becomes equal to or lower than the power failure warning voltage, a power failure warning signal is input from the power failure monitoring circuit 4100e as a power failure warning. The determination in step S48 is performed based on this power failure warning signal.

When there is no input of the power failure warning signal in step S48, the main control program performs the non-winning random number update process (step S50). In this non-winning random number update process, the above-mentioned random number for reach determination, random number for variable display pattern, random number for determining initial value for big hit symbol, random number for determining initial value for small hit symbol, and the like are updated. In this way, in the non-winning random number update process, random numbers that are not related to the winning determination (big hit determination) are updated. The above-mentioned random number for determining normal symbol hit, random number for determining initial value for determining normal symbol, random number for normal symbol variation display pattern, and the like are also updated by this non-winning random number update process.

Following step S50, the process returns to step S46 again, the main control program sets the value A in the watchdog timer clear register WCL, determines in step S48 whether or not there is a power failure warning signal input, and this power failure warning. If there is no signal input, the non-winning random number update process is performed in step S50, and steps S46 to S50 are repeated. The processing of steps S46 to S50 is referred to as "main control side main processing".

On the other hand, when the power failure warning signal is input in step S48, the main control program sets interrupt prohibition (step S52). With this setting, the timer interrupt process on the main control side, which will be described later, is not performed, writing to the main control built-in RAM is prevented, and rewriting of game information is protected.

Following step S52, the main control program starts outputting a power failure clear signal (step S53). Here, the same processing as the processing for starting the output of the power failure clear signal in step S11 is performed. As a result, the main control program can release the latch state of the D-type flip-flop MIC 22 under the control of the main control MPU4100a.

Following step S53, the main control program includes a start port solenoid 2105, an attacker solenoid 2108, an upper special symbol display 1185, a lower special symbol display 1186, an upper special symbol storage display 1184, and a lower special, as shown in FIG. The drive signal output to the symbol storage display 1187, the normal symbol display 1189, the normal symbol storage display 1188, the game status display 1183, the round display 1190, etc. is stopped (step S54).

Following step S54, the main control program calculates the checksum and stores the calculated value (step S56). This checksum calculates the total of the game information in the work area of the main control built-in RAM, excluding the storage area of the checksum value (sum value) and the backup flag BK-FLG value described above, as numerical values.

Following step S56, the main control program sets the backup flag BK-FLG to a value of 1 (step S58). This completes the storage of the game backup information.

Following step S58, the main control program sets the watchdog timer to clear (step S60). As described above, this clear setting is performed by setting the value A, the value B, and the value C in order in the watchdog timer clear register WCL.

Following step S60, an infinite loop is entered. In this infinite loop, the watchdog timer is not set to clear because the value A, the value B, and the value C are not set in order in the watchdog timer clear register WCL. Therefore, the main control MPU4100a is reset, and then the main control MPU4100a performs the main control side power-on processing again. The process of steps S52 to S60 and the infinite loop are referred to as "main control side power cutoff process".

The pachinko gaming machine 1 (main control MPU4100a) is reset when there is a power failure or when there is a momentary power failure, and when the power is restored thereafter, the processing when the main control side is turned on is performed.

In step S28, it is inspected whether or not the game backup information stored in the main control built-in RAM is normal, and then in step S30, whether or not the main control side power cutoff process is normally completed. Is inspecting. In this way, by double-checking the game backup information stored in the main control built-in RAM, it is inspected whether or not the game backup information is stored by fraudulent activity.

[13-4. Main control side timer interrupt processing]
Next, the timer interrupt processing on the main control side will be described. This main control side timer interrupt process is repeatedly performed every interrupt cycle (4 ms in this embodiment) set in the main control side power-on time process shown in FIGS. 35 and 36.

When the main control side timer interrupt process is started, in the main control board 4100, the main control program sets the value B in the watchdog timer clear register WCL under the control of the main control MPU4100a as shown in FIG. 37. (Step S70). At this time, the value B is set in the watchdog timer clear register WCL following the value A set in step S46 of the main control side power-on processing (main control side main processing).

Following step S70, the main control program clears the interrupt flag (step S72). When this interrupt flag is cleared, the interrupt cycle is initialized, and the next interrupt cycle is clocked from the initial value.

Following step S72, the main control program performs switch input processing (step S74). In this switch input process, various signals input to the input terminals of the various input ports of the main control MPU4100a are read and stored as input information in the input information storage area of the main control built-in RAM. Specifically, this main control program is, for example, a detection signal from the general winning opening switches 3020 and 3020 shown in FIG. 11 for detecting a game ball that has entered the general winning opening 2104, 2201 shown in FIG. The detection signal from the count switch 2110 shown in FIG. 11 for detecting the game ball that has entered the large winning opening 2103 shown in FIG. 8, and the diagram for detecting the game ball that has entered the upper starting opening 2101 shown in FIG. FIG. 8 shows a detection signal from the upper start port switch 3022 shown in FIG. 11, and a detection signal from the lower start port switch 2109 shown in FIG. 11 for detecting a game ball entering the lower start port 2102 shown in FIG. The detection signal from the gate switch 2352 shown in FIG. 11 for detecting the game ball passing through the gate portion 2350 shown, the detection signal from the magnetic detection switch 3024 for detecting fraudulent activity using the magnet shown in FIG. 11, and the detection signal described later. The payer ACK signal from the payout control board 4110 indicating that the payout control board 4110 shown in FIG. 11 has normally received the prize ball command transmitted in the prize ball control process is read, and the input information is stored as input information. Store in the area. Further, the detection signal from the upper start port switch 3022 that detects the game ball that has entered the upper start port 2101 and the detection signal from the lower start port switch 2109 that detects the game ball that has entered the lower start port 2102 are read. And the corresponding start opening winning command shown in FIG. 33, which is classified into other categories, is stored in the above-mentioned transmission information storage area as transmission information. That is, if there is a detection signal from the upper start port switch 3022, the corresponding start port winning command is stored in the transmission information storage area as transmission information, and if there is a detection signal from the lower start port switch 2109, The corresponding start opening winning command is stored in the transmission information storage area as transmission information.

In this embodiment, the detection signals from the general winning opening switches 3020 and 3020 for detecting the game balls entered in the general winning openings 2104 and 2201, and the count switch 2110 for detecting the game balls entered in the large winning openings 2103. Detection signal from, detection signal from the upper start port switch 3022 that detects the game ball that has entered the upper start port 2101, detection signal from the lower start port switch 2109 that detects the game ball that has entered the lower start port 2102. , And the detection signal from the gate switch 2352 that detects the game ball that has passed through the gate portion 2350 is first read as the first time when this switch input process is started, and after a predetermined time (for example, 10 μs) has elapsed. The second time, each is read again. Then, the result read for the second time and the result read for the first time are compared. It is determined whether or not any of the comparison results has the same result. If the result is not the same, it is read again as the third time, and the result read in the third time is compared with the result read in the second time. It is determined again whether or not any of the comparison results has the same result. If the result is not the same, it is read again as the fourth time, and the result read in the fourth time is compared with the result read in the third time. It is determined again whether or not any of the comparison results has the same result. If the result is the same, it is treated as if there is no game ball.

As described above, in the switch input process, the main control program first detects the detection signals from the general winning port switches 3020 and 3020, the count switch 2110, the upper starting port switch 3022, the lower starting port switch 2109, and the gate switch 2352. False detection due to the effects of chattering, noise, etc. by performing a total of two readings, a double reading for comparison over the third time and a double reading for comparison over the second to fourth times. The reliability of the detection signals from the general winning port switches 3020 and 3020, the count switch 2110, the upper start port switch 3022, the lower start port switch 2109, and the gate switch 2352 is improved. be able to.

Following step S74, the main control program performs timer subtraction processing (step S76). In this timer subtraction process, for example, the time during which the upper special symbol display 1185 and the lower special symbol display 1186 are lit according to the fluctuation display pattern determined by the special symbol and the special electric accessory control process described later, the normal symbol described later, and the normal symbol In addition to the time when the normal symbol display 1189 lights up according to the normal symbol variation display pattern determined by the normal electric accessory control process, the payout control board 4110 is normal for various commands transmitted by the main control board 4100 (main control MPU4100a). When determining whether or not a payer ACK signal for notifying that the signal has been received is input, time management such as the ACK signal input determination time set as the determination condition is performed. Specifically, when the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is 5 seconds, the timer interrupt cycle is set to 4 ms, so that the fluctuation time is subtracted by 4 ms each time the timer subtraction process is performed. Then, when the subtraction result becomes a value of 0, the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is accurately measured.

In this embodiment, the ACK signal input determination time is set to 100 ms. Each time this timer subtraction process is performed, the ACK signal input determination time is subtracted by 4 ms, and the subtraction result becomes a value of 0, so that the ACK signal input determination time is accurately measured. These various times and the ACK signal input determination time are stored in the time management information storage area of the main control built-in RAM as time management information.

Following step S76, the main control program performs a winning random number update process (step S78). In this winning random number update process, the above-mentioned big hit determination random number, big hit symbol random number, and small hit symbol random number are updated. Further, in addition to these random numbers, a random number for determining an initial value for a jackpot symbol, which is updated by the non-winning random number update process in step S50 in the main control side power-on processing (main control side main process) shown in FIG. And the random number for determining the initial value for the small hit symbol is also updated. These random numbers for determining the initial value for the big hit symbol and the random numbers for determining the initial value for the small hit symbol are updated in the main control side main process and the main control side timer interrupt process, respectively, to further enhance the randomness. .. On the other hand, since the big hit judgment random number, the big hit symbol random number, and the small hit symbol random number are random numbers related to the winning judgment (big hit judgment), the respective counters are used only each time the winning random number update process is performed. Counts up.

For example, as described above, the counter that updates the random number for jackpot determination is an initial value update type counter, and has a predetermined fixed numerical range from the minimum value to the maximum value (in the present embodiment, the value is set as the minimum value). It is updated within the value 32767) from 0 to the maximum value, and the range from the minimum value to the maximum value is counted up by adding a value of 1 each time the main control side timer interrupt process is performed. The random number for determining the initial value for jackpot determination is counted up toward the maximum value (value 32767), and then the random number for determining the initial value for jackpot determination is counted up from the minimum value (value 0). When the counter for updating the big hit determination random number finishes counting up in the range from the minimum value to the maximum value of the big hit determination random number, the big hit determination initial value determination random number is updated by this winning random number update process. The random number for determining the initial value for jackpot determination can be obtained by executing the initial value lottery process in which one value is drawn from the fixed numerical value range of the counter that updates the random number for jackpot determination. The above-mentioned random number for determining the normal symbol hit and the random number for determining the initial value for determining the normal symbol hit are also updated by this winning random number update process. The normal symbol hit determination random number and the like are the same as the above-mentioned method for updating the big hit determination random number, and the description thereof will be omitted.

In the present embodiment, the random number for determining the initial value for jackpot determination, the random number for determining the initial value for the jackpot symbol, and the random number for determining the initial value for the small hit symbol are processed at power-on on the main control side shown in FIG. 36 (main control). The non-winning random number update process in step S50 in the side main process) and the hit random number update process in step S78 in the main control side timer interrupt process, which is this routine, are updated respectively, but this routine is performed every time an interrupt timer occurs. When the number of executions of the non-winning random number update process in step S50 becomes random by repeatedly executing the main control side main process within the remaining time until the next interrupt timer occurs due to unevenness in the process time of , The random number for determining the initial value for big hit determination, the random number for determining the initial value for the big hit symbol, and the random number for determining the initial value for the small hit symbol may be updated only in the non-winning random number update process in step S50.

Following step S78, the main control program performs prize ball control processing (step S80). In this prize ball control process, the prize ball command shown in FIG. 31 for reading the input information from the above-mentioned input information storage area and paying out the game ball based on the input information can be created, or with the main control board 4100. The self-check command shown in FIG. 31 for confirming the connection state between the payout control board 4110 and the board is created. Then, the created prize ball command and self-check command are transmitted to the payout control board 4110 as the main payment serial data. For example, when one game ball enters the large winning opening 2103 shown in FIG. 8, a prize ball command for paying out 15 balls as a prize ball is created and transmitted to the payout control board 4110, or this prize ball command is used. Create a self-check command to check the connection status between the main control board 4100 and the payout control board 4110 when the payer ACK signal indicating that the payout control board 4110 has normally received is not input within the specified time. And send it to the payout control board 4110.

Following step S80, the main control program performs frame command reception processing (step S82). In the payout control board 4110, the payout control program has various 1-byte (8-bit) commands (for example, a frame state 1 command, an error release navigation command, and a frame state 2 command) classified into the status display shown in FIG. 34. To send. On the other hand, as will be described later, the payout control program outputs an error occurrence command when an error occurs in the payout operation, or outputs an error release navigation command based on the detection signal of the operation switch 860a. In the above-mentioned frame command reception process, when the main control program normally receives these various commands as payer serial data, the information to convey that fact to the payout control board 4110 is stored as output information in the main control built-in RAM. Store in the area. In addition, the main control program formats the command normally received as the payer serial data into a 2-byte (16-bit) command (various commands classified into the status display in FIG. 33 (frame status 1 command, error cancellation). The navigation command and the frame state 2 command)) are stored in the transmission information storage area described above as transmission information. The frame state 1 command referred to here corresponds to the first error occurrence command, and the error release navigation command corresponds to the first error release command.

Following step S82, the main control program performs fraud detection processing (step S84). In this fraud detection process, an abnormal state related to the prize ball is confirmed. For example, when the input information is read from the above-mentioned input information storage area and the detection signal from the count switch 2110 is input when the game is not in the big hit game state (when the game ball enters the big winning opening 2103). , A winning abnormality display command classified into the notification display shown in FIG. 33 as an abnormal state is created, and is stored in the above-mentioned transmission information storage area as transmission information.

Following step S84, the main control program performs special symbol and special electric accessory control processing (step S86). In this special symbol and special electric accessory control process, the value of the counter that updates the above-mentioned random number for jackpot determination is taken out, and it is determined whether or not it matches the jackpot determination value stored in advance in the main control built-in ROM (big hit). It is determined whether or not to generate a game state (referred to as "special lottery"), and the value of the counter that updates the random number for the jackpot symbol is taken out and used as the probability variation hit determination value stored in advance in the main control built-in ROM. It is determined whether or not they match (determination of whether or not a probability fluctuation is generated). Here, the "probability fluctuation" means that the probability of a big hit changes to a high probability (probability change time) set higher than that in the normal time (low probability). In the present embodiment, the value 32668 to the value 32767 are set as the above-mentioned jackpot determination value range (big hit determination range) with a low probability, and are read from the normal time determination table, whereas the value 31768 with a high probability. A value of 32767 is set, and the value is read from the probability change determination table. As described above, in the special symbol and special electric accessory control process in step S86, whether or not the value of the counter for updating the random number for jackpot determination and the jackpot determination value stored in advance in the main control built-in ROM match. When determining whether or not, the value of the counter that updates the random number for jackpot determination is included in the jackpot determination range.

When these determination results are based on the upper start port switch 3022, various commands related to the special drawing 1 tuning effect shown in FIG. 32 are created, while the lottery results are based on the lower start port switch 2109. In, various commands related to the special figure 2 synchronization effect shown in FIG. 32 are created and stored in the transmission information storage area as transmission information, and the upper special symbol display 1185 or the upper special symbol display 1185 or according to the determined variation display pattern of the special symbol is created. The output of the lighting signal to the upper special symbol display 1185 or the lower special symbol display 1186 is set so as to light the lower special symbol display 1186, and is stored as the output information in the above-mentioned output information storage area. Further, depending on the game state to be generated, for example, when the big hit game state is reached, various commands classified as related to the big hit shown in FIG. 32 (big hit opening command, big winning opening 1 opening Nth display command, big winning opening 1). A closing display command, a big winning opening 1 count display command, a big hit ending command, and a big hit symbol display command) are created and stored in the transmission information storage area as transmission information, or the opening / closing member 2107 shown in FIG. 8 is opened / closed. When the output of the drive signal to the attacker solenoid 2108 is set and stored as output information in the output information storage area, or when the number of times (round) the large winning opening 2103 is changed from the closed state to the open state is 2, the figure. The output of the lighting signal to the 2-round indicator lamp 1190a is set so as to turn on the 2-round indicator lamp 1190a of the round indicator 1190 shown in 10. The output information is stored in the output information storage area, or the round is performed 15 times. At one time, the output of the lighting signal to the 15-round indicator lamp 1190b is set so as to turn on the 15-round indicator lamp 1190b of the round indicator 1190 shown in 89, and the lighting signal is stored in the output information storage area as output information or the probability fluctuates. The output of the lighting signal to the game status display 1183 is set so that the presence or absence of the occurrence of the above is lit in a predetermined color, and the information is stored in the output information storage area as output information.

Following step S86, the main control program performs a normal symbol and a normal electric accessory control process (step S88). In this ordinary symbol and ordinary electric accessory control process, input information is read from the above-mentioned input information storage area, and gate winning processing is performed based on this input information. In this gate winning process, it is determined from the input information whether or not the detection signal from the gate switch 2352 has been input to the input terminal. Based on this determination result, when the detection signal is input to the input terminal, the value of the counter that updates the above-mentioned normal symbol hit determination random number is extracted and used as gate information in the gate information storage area of the main control built-in RAM. Remember in.

The gate information storage area is provided with a 0th section to a 3rd section (4 sections), and gate information is stored in the order of the 0th section, the 1st section, the 2nd section, and the 3rd section. It has become like. For example, when the gate information is stored in the 0th to 2nd sections of the gate information storage, the gate information is stored in the 3rd section of the gate information storage when the detection signal from the gate switch 2352 is input to the input terminal. do.

The gate information stored in the 0th section of the gate information storage is set in the work area of the main control built-in RAM. When this gate information is set, the gate information of the first section of the gate information storage is in the 0th section of the gate information storage, and the gate information of the second section of the gate information storage is in the first section of the gate information storage. The gate information of the third section of the information storage is shifted to the second section of the gate information storage, and the third section of the gate information storage becomes an empty area. For example, when the gate information is stored in the first to second sections of the gate information storage, the gate information of the first section of the gate information storage is stored in the 0th section of the gate information storage, and the gate information is stored in the 0th section. The gate information of the two sections is shifted to the first section of the gate information storage, and the second section of the gate information storage and the third section of the gate information storage become empty areas. Here, when the gate information is stored in the first to third sections of the gate information storage, the above-mentioned gate information is set so that the normal symbol storage display 1188 is turned on with the total number of the stored gate information as the holding ball. The output of the lighting signal of the normal symbol storage display 1188 is set based on the above, and is stored in the output information storage area described above as output information.

Following the gate winning process, the gate information set in the work area of the main control built-in RAM is read, and the value of the random number for normal symbol hit determination is taken out from the read gate information and stored in advance in the main control built-in ROM. It is judged whether or not it matches the judgment value per normal symbol (referred to as "normal lottery"). Whether or not to open / close the movable piece 2106 is determined based on this determination result (lottery result by ordinary lottery). When the opening / closing operation is performed by this determination, the pair of movable pieces 2106 is in a state of being expanded in the left-right direction, so that the game ball can be accepted into the lower starting port 2102, which is advantageous for the player. It becomes a game state. The variation display pattern of the normal symbol corresponding to this determination is determined based on the above-mentioned random number for the normal symbol variation display pattern, and various commands classified to be related to the normal symbol tuning effect shown in FIG. 32 are created and used as transmission information. In addition to storing in the transmission information storage area described above, the output of the lighting signal to the normal symbol display 1189 is set so as to light the normal symbol display 1189 according to the determined variation display pattern of the normal symbol, and the output information is described above. It is stored in the output information storage area. Further, for example, when the value of the extracted normal symbol hit determination random number matches the normal symbol hit determination value stored in advance in the main control built-in ROM, various commands related to the normal electric service effect shown in FIG. 32 are used. Is stored in the transmission information storage area as transmission information, and the output of the drive signal to the start port solenoid 2105 is set so as to open and close the movable piece 2106, and is stored in the output information storage area described above as output information. On the other hand, when the value of the extracted normal symbol hit judgment random number does not match the normal symbol hit judgment value stored in advance in the main control built-in ROM, the normal symbol is based on the above-mentioned normal symbol variation display pattern random number. A variation display pattern is determined, various commands classified in relation to the normal symbol synchronization effect shown in FIG. 32 are created, stored as transmission information in the transmission information storage area described above, and according to the determined normal symbol variation display pattern. The output of the lighting signal to the normal symbol display 1189 is set so as to light the normal symbol display 1189, and is stored as the output information in the above-mentioned output information storage area.

Following step S88, the main control program performs port output processing (step S90). In this port output process, output information is read from the output information storage area described above from the output terminals of various output ports of the main control MPU4100a, and various signals are output based on this output information. This main control program, for example, outputs a main payment ACK signal when various commands from the payout control board 4110 are normally received from the output terminal of the predetermined output port of the main control MPU 4100a based on the output information. A drive signal is output to the attacker solenoid 2108 that opens and closes the opening and closing member 2107 of the big winning opening 2103, and a drive signal is output to the starting opening solenoid 2105 that opens and closes the movable piece 2106 when it is in the big hit game state. In addition to outputting, 15 round jackpot information output signal, 2 round jackpot information output signal, probability fluctuation information output signal, special symbol display information output signal, normal symbol display information output signal, time saving medium information output information, start Various information (game information) signals related to the game such as the winning information output signal are output to the payout control board 4110.

Following step S90, the main control program performs peripheral control board command transmission processing (step S92). In this peripheral control board command transmission process, the main control program reads transmission information from the transmission information storage area described above and transmits this transmission information to the peripheral control board 4140 as main peripheral serial data. This transmission information includes various commands classified in the special figure 1 synchronization effect-related and various categories in the special figure 2 synchronization effect-related, as shown in FIG. 32, created by the main control side timer interrupt process of this routine. A big prize is won based on the detection signal from the count switch 2110 (see FIG. 11) when a game ball that has entered the big prize opening 2103 (see FIG. 8) is detected. Large winning mouth 1 count display command equivalent to the mouth count command), various commands classified as power-on, various commands classified as related to normal electric power production, various commands classified as related to ordinary electric power production, FIG. 33. Various commands classified into notification display (door open command, door frame close command, main body frame open command, main body frame close command, etc.) and various commands classified into status display (frame state 1 command, error cancellation) shown in Navi commands and frame status 2 commands), various commands classified as test-related, and various commands classified as others are stored. One packet of the main peripheral serial data is composed of 3 bytes. Specifically, the main peripheral serial data has a status indicating the type of a command having a storage capacity of 1 byte (8 bits), a mode indicating a variation of an effect having a storage capacity of 1 byte (8 bits), and a status. And the sum value calculated by regarding the mode as a numerical value and the sum, and this sum value is created at the time of transmission.

In this peripheral control board command transmission process, when the main control program receives the frame state 1 command (first error generation command) from the payout control board 4110 by the receiving port of the RXA terminal, the peripheral control board 4140 (effect control unit). ) Is sent a frame state 1 command (second error occurrence command) (error command sending means). In this case, the main control program transfers the frame state 1 command in the form shown in FIG. 34 received from the payout control board 4110 to the peripheral control board 4140 as the frame state 1 command in the form shown in FIG. 33.

On the other hand, in this peripheral control board command transmission process, when the main control program receives an error release navigation command (first error release command) from the payout control board 4110 via the receiving port of the RXA terminal, the peripheral control board 4140 An error release navigation command (second error release command) is transmitted to (error command transmission means). In this case, the main control program transfers the error release navigation command in the form shown in FIG. 34 received from the payout control board 4110 to the peripheral control board 4140 as the error release navigation command in the form shown in FIG. 33.

Furthermore, in this peripheral control board command transmission process, when the main control program receives the main body frame opening command (first main body frame opening command) from the payout control board 4110 by the receiving port of the RXA terminal, the peripheral control board 4140 A main body frame opening command (second main body frame opening command) is transmitted to (effect control unit) (main body frame command sending means, second main body frame sending means). In this case, the main control program transfers the main body frame opening command in the form shown in FIG. 34 received from the payout control board 4110 to the peripheral control board 4140 as the main body frame opening command in the form shown in FIG. 33. On the other hand, in this peripheral control board command transmission process, when the main control program receives the main body frame closing command (first main body frame closing command) from the payout control board 4110 by the receiving port of the RXA terminal, the peripheral control board 4140 ( A main body frame closing command (second main body frame closing command) is transmitted to the effect control unit) (main body frame command sending means, second main body frame command sending means). In this case, the main control program transfers the main body frame closing command in the form shown in FIG. 34 received from the payout control board 4110 to the peripheral control board 4140 as the main body frame closing command in the form shown in FIG. 33.

Further, in this peripheral control board command transmission process, when the main control program receives a door opening command (first door opening command) from the payout control board 4110 by the receiving port of the RXA terminal, the peripheral control board 4140 (effect control). A door opening command (second door frame opening command) is transmitted to (part) (door frame command sending means, second door frame command sending means). In this case, the main control program transfers the door frame closing command in the form shown in FIG. 34 received from the payout control board 4110 to the peripheral control board 4140 as the door closing command in the form shown in FIG. 33. On the other hand, in this peripheral control board command transmission process, when the main control program receives a door closing command (first door closing command) from the payout control board 4110 by the receiving port of the RXA terminal, the peripheral control board 4140 (effect control). A door closing command (second door closing command) is transmitted to (part) (door frame command sending means, second door frame command sending means). In this case, the main control program transfers the door closing command in the form shown in FIG. 34 received from the payout control board 4110 to the peripheral control board 4140 as the door closing command in the form shown in FIG. 33.

Following step S92, the main control program sets the value C in the watchdog timer clear register WCL (step S94). By setting the value C in the watchdog timer clear register WCL in step S94, the value C is set in the watchdog timer clear register WCL following the value B set in step S70. As a result, the value A, the value B, and the value C are set in order in the watchdog timer clear register WCL, and the watchdog timer is set to clear.

Following step S94, the main control program switches (returns) registers (step S96) and ends this routine. Here, when the main control side timer interrupt process, which is this routine, is started, the main control MPU4100a stacks the contents of the general-purpose register on the stack and saves them. This prevents the contents of the general-purpose register used in the main processing on the main control side from being destroyed. In step S96, the contents stacked on the stack and saved are read and written to the original register. The main control MPU4100a sets interrupt enable after returning by step S96.

[14. Various control processes for payout control boards]
Next, various control processes performed by the payout control board 4110 shown in FIG. 12 will be described with reference to FIGS. 38 to 54. FIG. 38 is a flowchart showing an example of the power-on processing of the payout control unit, FIG. 39 is a flowchart showing the continuation of the power-on processing of the payout control unit, and FIG. 40 shows the payout control unit following FIG. FIG. 41 is a flowchart showing the continuation of the power-on processing, FIG. 41 is a flowchart showing an example of the payout control unit timer interrupt processing, FIG. 42 is a flowchart showing an example of the rotation angle switch history creation processing, and FIG. 43 is a sprocket. FIG. 44 is a flowchart showing an example of a fixed position determination skip process, FIG. 44 is a flowchart showing an example of a ball scuff determination process, and FIG. 45 is a flowchart showing an example of a prize ball stock number addition process for a prize ball. 46 is a flowchart showing an example of the prize ball stock number addition process for lending, FIG. 47 is a flowchart showing an example of the stock monitoring process, and FIG. 48 is a flowchart showing an example of the payout ball motion determination setting process. FIG. 49 is a flowchart showing an example of the payout setting process, FIG. 50 is a flowchart showing an example of the ball-shaped motion setting process, and FIG. 51 is a flowchart showing an example of the retry operation monitoring process. FIG. 52. Is a flowchart showing an example of inconsistency counter reset determination processing, FIG. 53 is a flowchart showing an example of error cancellation operation determination processing, and FIG. 54 is a signal processing (a) at the time of payout operation by ball lending, from the CR unit. It is a timing chart which shows the input signal confirmation processing (a) of.

First, the payout control unit power-on processing will be described, followed by the payout control unit timer interrupt processing, ball removal switch operation determination processing, rotation angle switch history creation processing, sprocket fixed position determination skip processing, ball bending determination processing, and prize. Ball prize ball stock number addition process, ball rental prize ball stock number addition process, stock monitoring process, payout ball motion judgment setting process, payout setting process, ball beam motion setting process, retry motion monitoring process, inconsistency The counter reset determination process and the error release operation determination process will be described. In addition, ball removal switch operation judgment processing, rotation angle switch history creation processing, sprocket fixed position judgment skip processing, ball shaving judgment processing, prize ball stock number addition processing for prize ball stock number addition processing, stock The monitoring process, the payout ball motion determination setting process, the retry operation monitoring process, the inconsistency counter reset determination process, and the error cancellation operation determination process are one of the main operation setting processes of step S562 in the payout control unit power-on time process described later. It is performed as processing, rotation angle switch history creation processing, sprocket fixed position judgment skip processing, ball scuff judgment processing, retry operation monitoring processing, inconsistency counter reset judgment processing, error cancellation operation judgment processing, prize ball stock number for prize balls The priority is set in the order of addition processing, prize ball stock number addition processing for lending, stock monitoring processing, and payout ball operation determination setting processing.

[14-1. Dispensing control unit power-on processing]
When the power is turned on to the pachinko gaming machine 1, in the payout control unit 4120 on the payout control board 4110, the payout control program controls the payout control MPU 4120a, as shown in FIGS. 38 to 40, the payout control unit power supply. Performs on-time processing. When the payout control unit power-on processing is started, the payout control program sets the interrupt mode for the payout control MPU4120a (step S500). This interrupt mode sets the priority of the interrupt of the payout control MPU4120a. In the present embodiment, the payout control unit timer interrupt process, which will be described later, is set to have the highest priority, and when an interrupt of the payout control unit timer interrupt process occurs, the process is preferentially performed.

Following step S500, the payout control program performs input / output settings (I / O input / output settings) (step S502). In this I / O input / output setting, various input ports and various output ports of the payout control MPU4120a are set.

Following step S502, the payout control program performs wait timer processing 1 (step S506) and determines whether or not a power failure warning signal has been input (step S508). The voltage does not rise immediately from the time the power is turned on until the specified voltage is reached. On the other hand, when a power failure or a momentary power failure (a phenomenon in which the power supply is temporarily stopped) occurs, the voltage drops, and when the voltage becomes smaller than the power failure warning voltage, the power failure monitoring circuit 4100e of the main control board 4100 shown in FIG. A warning signal (payout power failure warning signal) is input. Similarly, when the voltage becomes smaller than the power failure warning voltage between the time when the power is turned on and the voltage rises to a predetermined voltage, a power failure warning signal (payout power failure warning signal) is input from the power failure monitoring circuit 4100e of the main control board 4100. Therefore, the wait timer process 1 in step S506 is a process for waiting until the voltage becomes larger than the power failure warning voltage and stabilizes after the power is turned on. In the present embodiment, the waiting time (wait timer) is 200 milliseconds (waiting timer). ms) is set. The determination in step S508 is performed based on the power failure warning signal (payout power failure warning signal) from the power failure monitoring circuit 4100e of the main control board 4100.

Following step S508, the payout control program determines whether or not the operation switch 860a is operated (step S512). This determination is based on the logical value of the operation signal from the operation switch 860a, and it is determined that the operation switch does not indicate that the RAM is cleared when the logical value of the operation signal from the operation switch 860a is HI. While it is determined that the 860a is not operated, it is determined that when the logical value of the operation signal from the operation switch 860a is LOW, it is determined that the RAM is cleared and the operation switch 860a is operated. judge.

When the operation switch 860a is operated in step S512, the payout control program sets the payout RAM clear notification flag HRCL-FLG to a value of 1 (step S514). That is, the payout control program can execute a RAM clear process that initializes the RAM (hereinafter, referred to as “payout control built-in RAM”) built in the payout control MPU4120a for a predetermined time from the time when the power is turned on. (Delivery control side power-on operation control means). On the other hand, when the operation switch 860a is not operated in step S512, the payout control program sets the payout RAM clear notification flag HRCL-FLG to a value 0 (step S516). The payout RAM clear notification flag HRCL-FLG is stored in the payout control built-in RAM (payout storage unit) of the payout control MPU4120a, for example, various flags, various information stored in various information storage areas (for example, various information). The number of prize ball stocks stored in the prize ball information storage area, PBS, actual ball count PB, drive command number DRV, mismatch counter INCC, etc., and the logic of the PRDY signal stored in the CR communication information storage area. It is a flag indicating whether or not to delete the payout information related to the payout of the PRDY signal output setting information whose status is set), and is set to a value of 1 when the payout information is erased and a value of 0 when the payout information is not erased. Will be done. The payout RAM clear notification flag HRCL-FLG set in steps S514 and S516 is stored in the general-purpose storage element (general-purpose register) of the payout control MPU4120a.

Following step S514 or step S516, the payout control program sets to allow access to the payout control built-in RAM (step S518). With this setting, the RAM with built-in payout control can be accessed, and for example, payout information can be written (stored) or read out.

Following step S518, the payout control program sets the stack pointer (step S520). The stack pointer indicates, for example, the address stacked on the stack for temporarily storing the contents of the storage element (register) in use, or temporarily returns the return address of this routine when the subroutine is terminated and returned to this routine. It indicates the address stacked on the stack for storage, and the stack pointer advances each time the stack is stacked. In step S520, the initial address is set in the stack pointer, and the contents of the register, the return address, and the like are pushed onto the stack from this initial address. Then, the stack pointer returns to the initial address by reading in order from the last stacked stack to the first stacked stack.

Following step S520, the payout control program determines whether or not the payout RAM clear notification flag HRCL-FLG has a value of 0 (step S522). As described above, the payout RAM clear notification flag HRCL-FLG is set to a value 1 when the payout information is erased and a value 0 when the payout information is not erased.

When the payout RAM clear notification flag HRCL-FLG has a value of 0 in step S522, that is, when the payout information is not erased, the payout control program calculates the checksum (step S524). This checksum regards the payout information stored in the payout control built-in RAM as a numerical value and calculates the total.

Following step S524, the payout control program determines whether or not the calculated checksum value matches the checksum value stored in the payout control unit power cutoff process (when the power is turned off), which will be described later. (Step S526). When they match, the payout control program determines whether or not the payout backup flag HBK-FLG has a value of 1 (step S528). The payout backup flag HBK-FLG is a flag indicating whether or not the payout backup information such as the payout information and the checksum value is stored and held in the payout control built-in RAM in the payout control unit power cutoff process described later, and is paid out. The value is set to 1 when the power cutoff process of the control unit is normally completed, and to 0 when the power cutoff process of the payout control unit is not normally completed.

When the payout backup flag HBK-FLG has a value of 1 in step S528, that is, when the payout control unit power cutoff process is normally completed, the payout control program sets the work area of the payout control built-in RAM as the time of power recovery. (Step S530). In this setting, in addition to setting the value 0 to the payout backup flag HBK-FLG, the power recovery information is read from the ROM built in the payout control MPU4120a (hereinafter, referred to as “payout control built-in ROM”). Then, this power recovery information is set in the work area of the payout control built-in RAM. As a result, various flags, various information stored in various information storage areas, etc. (for example, prizes stored in the prize ball information storage area), which are the above-mentioned payout backup information stored in the payout control built-in RAM. Ball stock number PBS, actual ball count PB, drive command number DRV, inconsistency counter INCC, etc., PRDY signal output setting information in which the logical state of the PRDY signal is set, stored in the CR communication information storage area, Information used for various processes is set based on the payout information related to the payout of the inconsistency counter reset determination time stored in the time management information storage area. The term "recovery" includes not only the state in which the power is turned on from the state in which the power is cut off, but also the state in which the power is restored after the power failure or momentary power failure.

On the other hand, when the payout RAM clear notification flag HRCL-FLG is not a value 0 (value 1) in step S522, that is, when the payout information is erased, or when the checksum values do not match in step S526, or step. When the payout backup flag HBK-FLG is not a value 1 (value 0) in S528, that is, when the payout control unit power cutoff process is not normally completed, the payout control program covers the entire area of the payout control built-in RAM. Clear (step S532). That is, the payout control program executes the payout control side RAM clear process triggered by the detection of the operation signal of the operation switch 860a (payout control side power-on operation control means). As a result, the payout backup information stored in the payout control built-in RAM is cleared.

Following step S532, the payout control program sets the work area of the payout control built-in RAM as an initial setting (step S534). This setting reads the initial information from the payout control built-in ROM and sets this initial information in the work area of the payout control built-in RAM.

Following step S530 or step S534, the payout control program performs interrupt initial setting (step S536). This setting sets the interrupt cycle when the payout control unit timer interrupt process, which will be described later, is performed. In this embodiment, it is set to 2 ms.

Following step S536, the payout control program sets interrupt enable (step S538). With this setting, the payout control unit timer interrupt process is repeatedly performed every 2 ms, that is, the interrupt cycle set in step S536.

Following step S538, the payout control program sets the value A in the watchdog timer clear register HWCL (step S539). The watchdog timer is set to clear by setting the value A, the value B, and the value C in order in the watchdog timer clear register HWCL.

Following step S539, the payout control program determines whether or not a power failure warning signal (payout power failure warning signal) has been input (step S540). As described above, when the power of the pachinko gaming machine 1 is cut off, a power failure or a momentary power failure occurs, when the voltage becomes equal to or lower than the power failure warning voltage, a power failure warning signal (payout power failure warning signal) is used as the main control board. It is input from the power failure monitoring circuit 4100e of the 4100. The determination in step S540 is performed based on this power failure warning signal.

When there is no input of the power failure warning signal in step S540, the payout control program determines whether or not the 2 ms elapsed flag HT-FLG has a value of 1 (step S542). This 2 ms elapsed flag HT-FLG is a flag for timing 2 ms by the timer interrupt process of the payout control unit, which is processed every 2 ms, which will be described later. Set.

When the value of the 2 ms elapsed flag HT-FLG is 0 in step S542, that is, when 2 ms has not elapsed, the process returns to step S540, and the payout control program determines whether or not a power failure warning signal (payout power failure warning signal) has been input. To judge.

On the other hand, when the 2 ms elapsed flag HT-FLG has a value of 1 in step S542, that is, when 2 ms has elapsed, the payout control program sets the value 0 to the 2 ms elapsed flag HT-FLG (step S544).

Following step S544, the payout control program sets the value B in the watchdog timer clear register HWCL (step S546). At this time, the value B is set in the watchdog timer clear register HWCL following the value A set in step S539.

Following step S546, the payout control program performs port output processing (step S548). In this port output process, various information is read from the output information storage area of the payout control built-in RAM, and various signals are output from the output terminals of the various output ports of the payout control MPU4120a based on the various information. In the output information storage area, for example, payer ACK information indicating that various commands related to payout from the main control board 4100 (prize ball command and self-check command shown in FIG. 31) have been normally received, payout motor 744. Various information such as drive information for driving control to, prize ball number information for the number of balls actually paid out by the payout motor 744, and LED display information displayed on the error LED display 860b is stored. When various commands related to payout from the main control board 4100 are normally received from the output terminal of the predetermined output port of the payout control MPU 4120a based on the output information, the payer ACK signal is output to the main control board 4100 or the payout motor. A drive signal may be output to the 744, or the number of balls actually paid out by the payout motor 744 may be output to the external terminal plate 784 as a prize ball number information signal (in the present embodiment, the payout motor 744 is actually 10). Each time each game ball is paid out, a prize ball number information signal is output to the external terminal plate 784), and a display signal is output to the error LED display 860b.

Following step S548, the payout control program performs port input processing (step S550). In this port input process, various signals input to the input terminals of the various input ports of the payout control MPU4120a are read and stored as input information in the input information storage area of the payout control built-in RAM. For example, an operation signal of the operation switch 860a, a detection signal from the rotation angle switch 752, a detection signal from the counting switch 751, a detection signal from the full tank switch 550, a BRQ signal from the CR unit 6, a BRDY signal, and a CR connection signal. The main payment ACK signal and the like from the main control board 4100 that conveys that the main control board 4100 has normally received various commands transmitted in the command transmission process described later are read and stored in the input information storage area as input information.

Following step S550, the payout control program performs a timer update process (step S552). In this timer update process, the ball squeeze determination set as the determination condition when determining whether or not the sphere is squeezed by the payout rotating body to which the rotation of the rotation axis of the payout motor 744 is transmitted is determined. The time, the skip determination time set when the fixed position determination of the payout rotating body is not performed, and the skip determination time set when discharging the game balls stored in the prize ball tank 720 and the tank rail 731 shown in FIG. The full tank determination time is set as the determination condition when determining whether or not the game ball in which the accommodation space of the foul cover unit 540 shown in FIG. 1 is full is full. It is set as a judgment condition when it is judged whether or not the number of balls of the game ball taken into the supply passage of the prize ball device 740 is equal to or more than a predetermined number by the detection signal from the time and the ball out switch 750. In addition to managing the time such as the ball out judgment time, the number of game balls received and paid out in the recess of the payout rotating body and the number of balls actually detected by the counting switch 751 do not match. Inconsistency counter reset determination set as the determination condition when determining whether to reset the inconsistency counter INCC for monitoring whether or not the inconsistent game ball is repeatedly paid out. Manage time. For example, when the ball squeeze determination time is set to 5005 ms, the timer interrupt cycle is set to 2 ms. Therefore, the sphere squeeze determination time is subtracted by 2 ms each time the timer update process is performed, and the subtraction result is obtained. When the value becomes 0, the ball squeeze judgment time is accurately measured.

In the present embodiment, the skip determination time is set to 22.75 ms, the ball removal determination time is set to 60060 ms, the full tank determination time is set to 504 ms, the ball out determination time is set to 119 ms, and the inconsistency counter reset determination time is set to 7000 s (about 2 hours). Each time this timer update process is performed, the ball removal determination time, the full tank determination time, the ball out determination time, and the inconsistency counter reset determination time are subtracted by 2 ms, and the subtraction result becomes a value of 0. The withdrawal judgment time, the full tank judgment time, the ball out judgment time, and the inconsistency counter reset judgment time are accurately measured. These various determination times are stored in the time management information storage area of the payout control built-in RAM as time management information.

Following step S552, the payout control program performs CR communication processing (step S554). In this CR communication process, whether or not various signals (BRQ signal, BRDY signal and CR connection signal) from the CR unit 6 are input based on the input information read from the above-mentioned input information storage area. Is determined. The payout control MPU4120a exchanges various signals with the CR unit 6 based on various signals from the CR unit 6. In the process of setting the work area of the payout control built-in RAM in step S530, as described above, various flags and various information stored in the payout control built-in RAM, which are payout backup information stored in the payout control built-in RAM. Etc. (For example, prize ball stock number PBS, actual ball count PB, drive command number DRV, mismatch counter INCC, etc. stored in the prize ball information storage area, PRDY stored in the CR communication information storage area, etc. Information used for various processes is set based on the payout information related to the payout (PRDY signal output setting information, etc. in which the logical state of the signal is set).

By this processing, for example, even if there is a momentary power failure or a power failure, the values of the prize ball stock number PBS, the actual ball count PB, the drive command number DRV, the mismatch counter INCC, etc. at the time of power recovery are stored as payout backup information. It can be restored to the values of the prize ball stock number PBS, the actual ball count PB, the drive command number DRV, the mismatch counter INCC, etc. immediately before the momentary power failure or power failure. As a result, even if the payout operation of the game ball by the prize ball device 740 cannot be continued due to a momentary power failure or a power failure, the payout operation is continued at the time of power recovery. Therefore, the game ball can be paid out to the upper plate 301 and the lower plate 302 without excess or deficiency. In other words, the payout control MPU4120a momentarily stops or loses power when the game ball is paid out to the upper plate 301 or the lower plate 302 while exchanging various signals with the CR unit 6 in the CR communication process. Even if the exchange of various signals with the unit 6 is cut off and the payout of the game ball cannot be continued, the prize ball stock number PBS, the actual ball count PB, the drive command number DRV, and the mismatch counter INCC at the time of power recovery. By restoring the values such as, etc. to the values of the prize ball stock number PBS, the actual ball count PB, the drive command number DRV, the mismatch counter INCC, etc., which are stored as the payout backup information immediately before the momentary power failure or the power failure. , The exchange of various signals between the pachinko gaming machine 1 (pain control MPU4120a) and the CR unit 6 immediately before a momentary power failure or a power failure can be continued from the time of power recovery, and the gaming balls can be continuously paid out. You can do it.

In this way, the exchange of various signals between the pachinko gaming machine 1 (pain control MPU4120a) and the CR unit 6 is restored to the state immediately before the momentary power failure or stop even if the power is restored. The various signals by the pachinko gaming machine 1 (payout control MPU4120a) and the CR unit 6 do not change due to the influence of the momentary power failure or stoppage. Therefore, it is possible to improve the reliability of the exchange of various signals between the pachinko gaming machine 1 (payout control MPU4120a) and the CR unit 6.

Further, various information stored in the CR communication information storage area is included in the payout backup information as described above. In the CR communication process, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM set in the process of setting the work area of the payout control built-in RAM in step S530 at the time of power recovery. When the read PRDY signal output setting information is set to the logical state of the PRDY signal that conveys, for example, that the payout operation for paying out the rental ball is impossible, the PRDY signal is paid out. Output to the CR unit 6 from the output terminal of the predetermined output port of the MPU 4120a. Then, in the retry operation monitoring process performed as one of the main operation setting processes, for example, the value of the mismatch counter INCC of the prize ball information storage area stored in the payout control built-in RAM included in the payout backup information. Based on, it is determined whether or not the value of the inconsistency counter INCC is smaller than the inconsistency threshold value INCTH, and when the value of the inconsistency counter INCC is not smaller than the inconsistency threshold value INCTH, the retry operation is abnormal operation. In other words, it is determined that the payout operation of the game ball by the prize ball device 740 is in an abnormal state, a value 1 is set in the retry error flag RTERR-FLG, and the payout ball operation determination setting process is performed. In the setting of the output of the error state to the CR unit 6, for example, the logical state (LOW) of the PRDY signal telling that the payout operation for paying out the rental ball is impossible when the communication with the CR unit 6 is not in progress. Is set in the PRDY signal output setting information and stored in the CR communication information storage area.

As a result, in the CR communication processing, the logical state of this PRDY signal is read from the CR communication information storage area by the next timer interrupt from the time of power recovery, and the PRDY signal is output from the output terminal of the predetermined output port of the MPU4120a. Is output to the CR unit 6. In this way, for example, if the payout operation of the game ball by the prize ball device 740 is in an abnormal state immediately before the momentary power failure, that state is restored when the power is restored, so that it is extremely after the power is restored. At an early stage, a PRDY signal indicating that the payout operation for paying out the rental ball is impossible can be output to the CR unit 6 from the output terminal of the predetermined output port of the payout control MPU4120a, and the CR unit 6 can be output. It is possible to convey that the payout operation of the game ball by the prize ball device 740 is in an abnormal state. As a result, it is possible to prevent BRDY, which is a useless ball lending request signal, from being output from the CR unit 6 at an extremely early stage after the power is restored.

Further, in the CR communication process, in the port input process of step S550, a CR connection signal is read from the input information storage area of the payout control built-in RAM, and based on this CR connection signal, the logic is HI, that is, a patch panel game. When the power of the machine 1 is turned on and the payout control board 4110 and the CR unit 6 are electrically connected via the game ball or the like rental device connection terminal board 869, the payout ball is to be paid out. When the logic state of the PRDY signal is set to HI and is output from the output terminal of the predetermined output port of the payout control MPU4120a to the CR unit 6 in order to convey that the payout operation is possible, the logic is LOW. That is, when the pachinko game machine 1 is turned on and the payout control board 4110 and the CR unit 6 are not electrically connected via the game ball or the like rental device connection terminal board 869, the ball rental is performed. In order to convey that the payout operation for paying out is impossible, the logical state of the PRDY signal is set to LOW and output to the CR unit 6 from the output terminal of the predetermined output port of the payout control MPU4120a. The logical state of the EXS signal for notifying that one payout operation has started or ended is stored in the CR communication information storage area of the payout control built-in RAM as EXS signal output setting information, and is stored with the payout control board 4110. The CR connection signal that conveys whether or not the CR unit 6 is electrically connected is stored in the state information storage area as CR connection information.

Following step S554, the payout control program performs a full tank and out-of-ball check process (step S556). In this full tank and out of ball check process, the input information is read from the above-mentioned input information storage area, and based on this input information, the accommodation space of the above-mentioned foul cover unit 540 is stored by the detection signal from the full tank switch 550. It is determined whether or not the game ball is full, and the number of game balls taken into the supply passage of the above-mentioned prize ball device 740 by the detection signal from the ball out switch 750 becomes a predetermined number or more. It is judged whether or not it is. For example, to determine whether or not the accommodation space of the foul cover unit 540 is full with the stored game ball, the full tank switch is used in the current full tank and out of ball check process using the timer interrupt cycle of 2 ms. When the detection signal from the 550 is ON and the detection signal from the full tank switch 550 is OFF in the previous (2 ms before) full tank and ball out check process, that is, the detection signal from the full tank switch 550 is ON from OFF. When the transition to, the time counting of the full tank determination time (504 ms) described above is started in the timer update process of step S552. Then, when the full tank determination time becomes 0 in the timer update process, that is, when the full tank determination time is reached, whether or not the detection signal from the full tank switch 550 is ON in this full tank and out-of-ball check process. Is determined. In this determination, when the detection signal from the full tank switch 550 is ON, the state information storage described above indicates that the game ball in which the accommodation space of the foul cover unit 540 is stored is full. Store in the area. On the other hand, when the detection signal from the full tank switch 550 is OFF, the full tank information indicating that the game ball in which the accommodation space of the foul cover unit 540 is stored is not full is stored in the state information storage area. ..

Whether or not the number of game balls taken into the supply passage of the prize ball device 740 is equal to or more than a predetermined number is also determined by using the timer interrupt cycle of 2 ms in the current full tank and out-of-ball check process. When the detection signal from the cut-off switch is ON, and the detection signal from the ball-out switch is OFF in the previous (2 ms before) full tank and ball-out check processing, that is, the detection signal from the ball-out switch 750 is from OFF to ON. When the transition to, the timer update process in step S552 starts counting the ball-out determination time (119 ms) described above. Then, when the ball-out determination time becomes 0 in the timer update process, that is, when the ball-out determination time is reached, whether or not the detection signal from the ball-out switch 750 is ON in this full tank and ball-out check process. Is determined. In this determination, when the detection signal from the ball-out switch 750 is ON, the ball-out information indicating that the number of game balls taken into the supply passage of the prize ball device 740 is equal to or more than a predetermined number is displayed. While storing in the information storage area, when the detection signal from the ball out switch 750 is OFF, it is assumed that the number of game balls taken into the supply passage of the prize ball device 740 is not equal to or more than a predetermined number, and the ball is out. Information is stored in the state information storage area.

Following step S556, the payout control program performs command reception processing (step S558). In this command reception process, various commands related to payout from the main control board 4100 (prize ball command and self-check command shown in FIG. 31) are received. When these various commands are normally received, the payer ACK information to that effect is stored in the above-mentioned output information storage area. On the other hand, when various commands cannot be received normally, a connection abnormality is transmitted to indicate that an abnormality has occurred in the connection between the main control board 4100 and the payout control board 4110 (an abnormality has occurred in various command signals). Information is stored in the state information storage area described above.

Following step S558, the payout control program performs command analysis processing (step S560). In this command analysis process, the command received in step S558 is analyzed, and the analyzed command is stored in the received command information storage area of the payout control built-in RAM as received command information.

Following step S560, the payout control program performs the main operation setting process (step S562). In this main motion setting process, motion settings such as prize balls, lending balls, ball pulling, and ball scooping are performed, retry motions are determined, and the number of unpaid balls (prize ball stock number) is monitored. do.

Following step S562, the payout control program performs LED display data creation processing (step S564). In this LED display data creation process, various information is read from the state information storage area described above, display data to be displayed on the error LED display 860b of the payout control board 4110 is created, and the output information storage area described above is used as the LED display information. Remember. For example, when the above-mentioned ball-out information is read from the state information storage area and the number of game balls taken into the supply passage of the prize ball device 740 is not equal to or more than a predetermined number based on the ball-out information, the corresponding display data is obtained. (In this embodiment, the display value 1 (number "1")) is created and the LED display information is stored in the output information storage area.

Following step S564, the payout control program performs a command transmission process (step S566). In this command transmission process, various information is read from the above-mentioned state information storage area, and various commands (door open command, door frame close command, main body frame open) classified into the state display shown in FIG. 34 based on the various information. Create a command, main unit frame closing command, frame state 1 command (corresponding to the first error occurrence command), error cancellation navigation command (corresponding to the first error canceling command), and frame state 2 command) to the main control board 4100. Send to. For example, when the ball out information is read out from the state information storage area, the frame state 1 command is issued when the number of balls of the game ball taken into the supply passage of the prize ball device 740 is not equal to or more than a predetermined number based on the ball outage information. It is created and transmitted to the main control board 4100. Further, in this command transmission process, when there is a change in the frame state such as an error related to the payout operation of the game ball, the payout control program provides information on the part where the error occurs regarding the payout operation (hereinafter referred to as A frame state 1 command (first error release command) including "error occurrence position information") is generated (error occurrence command generation means). On the other hand, in this command transmission process, when the payout control program has a payout RAM clear notification flag HRCL-FLG of value 1, that is, when an operation signal corresponding to the operation of the operation switch 860a is detected, the above-mentioned error Output the release navigation command (first error release command) (command sending means). Further, this payout control program transmits a main body frame opening command (first main body frame opening command) when a main body frame opening detection signal is input from the main body frame opening switch 619 (main body frame command sending means, first. 1 main body frame command sending means). B. Ayumu, this payout control program transmits a main body frame closing command (first main body frame closing command) when a main body frame closing detection signal is input from the main body frame opening switch 619 (main body frame command sending means). , First main body frame command sending means). Further, this payout control program transmits a door frame opening command (first door frame opening command) when a door frame opening detection signal from the door frame opening switch 618 is input (door frame command sending means, first. 1 door frame command sending means). On the other hand, this payout control program transmits a door frame closing command (first door frame closing command) when a door frame closing detection signal from the door frame opening switch 618 is input (door frame command sending means, first. 1 door frame command sending means). Further, in the above-mentioned command transmission process (step S566), this payout control program reads error information including error contents from the above-mentioned state information storage area, and has unit number information for distinguishing itself from other pachinko machines. The error information signal based on the error information is output to the hall computer via the external terminal plate 784. Upon receiving this error information signal, the hall computer provides the above-mentioned unit number information and error information to the wireless device possessed by the hall clerk, and the hall clerk provides the unit number pachinko machine based on this unit number information. In, it is possible to recognize that the error content included in the error information has occurred.

Following step S566, the payout control program sets the value C in the watchdog timer clear register HWCL (step S568). By setting the value C in the watchdog timer clear register HWCL in step S568, the value C is set in the watchdog timer clear register HWCL following the value B set in step S546. As a result, the value A, the value B, and the value C are set in order in the watchdog timer clear register HWCL, and the watchdog timer is set to clear.

Following step S568, the process returns to step S539 again, the payout control program sets the value A in the watch dock timer clear register HWCL, and determines whether or not a power failure warning signal (payout power failure warning signal) has been input in step S540. If the determination is made and there is no input of this power failure warning signal (payout power failure warning signal), it is determined in step S542 whether or not the 2ms elapsed flag HT-FLG has a value of 1, and the 2ms elapsed flag HT-FLG has a value of 1. In other words, when 2 ms has elapsed, the value 0 is set in the 2 ms elapsed flag HT-FLG in step S544, the value B is set in the watch dock timer clear register HWCL in step S546, and port output processing is performed in step S548. , Port input processing is performed in step S550, timer update processing is performed in step S552, CR communication processing is performed in step S554, full tank and ball out check processing is performed in step S556, and command reception processing is performed in step S558. Command analysis processing is performed in step S560, main operation setting processing is performed in step S562, LED display data creation processing is performed in step S564, command transmission processing is performed in step S566, and a value is set in the watch dock timer clear register HWCL in step S568. C is set, and steps S539 to S568 are repeated. The processing of steps S539 to S568 is referred to as "payout control unit main processing".

The processing content of the payout control unit main processing differs depending on the progress of the game by the main control board 4100. Therefore, the time required for processing the payout control MPU4120a varies. Therefore, in the port output process of step S548, the payout control MPU 4120a preferentially outputs a payer ACK signal indicating that various commands related to payout from the main control board 4100 have been normally received to the main control board 4100. There is. As a result, the payout control MPU4120a secures the processing time so that other variable processing can be sufficiently performed.

On the other hand, when the power failure warning signal (payout power failure warning signal) is input in step S540, the interrupt prohibition setting is set (step S570). By this setting, the timer interrupt process of the payout control unit, which will be described later, is not performed, the writing to the payout control built-in RAM is prevented, and the above-mentioned rewriting of the payout information is protected.

Following step S570, the payout control program stops the output of the drive signal to the payout motor 744 (step S574). As a result, the payout of the game ball is stopped.

Following step S574, the payout control program sets the watchdog timer to clear (step S60). As described above, this clear setting is performed by setting the value A, the value B, and the value C in order in the watchdog timer clear register HWCL.

Following step S576, the payout control program calculates the checksum and stores the calculated value (step S578). For this checksum, the payout information of the work area of the payout control built-in RAM excluding the storage area of the checksum value calculated in step S524 and the value of the payout backup flag HBK-FLG is regarded as a numerical value, and the total is calculated.

Following step S578, the payout control program sets the payout backup flag HBK-FLG to a value of 1 (step S580). This completes the storage of the payout backup information.

Following step S580, the payout control program sets the prohibition of access to the payout control built-in RAM (step S582). By this setting, access to the payout control built-in RAM is prohibited, writing and reading become impossible, and the payout backup information stored in the payout control built-in RAM is protected.

Following step S582, the payout control program enters an infinite loop. In this infinite loop, the watchdog timer is not set to clear because the value A, the value B, and the value C are not set in order in the watchdog timer clear register HWCL. Therefore, the payout control MPU4120a is reset, and then the payout control program performs the payout control unit power-on processing again under the control of the payout control MPU4120a. The process of steps S570 to S582 and the infinite loop are referred to as "payout control unit power cutoff process".

The pachinko gaming machine 1 (pain control MPU4120a) is reset when there is a power failure or when there is a momentary power failure, and when the power is restored thereafter, the payout control unit power-on processing is performed.

In step S526, it is inspected whether or not the payout backup information stored in the payout control built-in RAM is normal, and then in step S528, whether or not the payout control unit power cutoff process is normally completed. Is inspecting. In this way, by double-checking the payout backup information stored in the payout control built-in RAM, it is inspected whether or not the payout backup information is stored by fraudulent activity.

[14-2. Payout control unit timer interrupt processing]
Next, the payout control unit timer interrupt processing will be described. This payout control unit timer interrupt process is repeatedly performed every interrupt cycle (2 ms in this embodiment) set in the payout control unit power-on time process shown in FIGS. 38 to 40.

When the payout control unit timer interrupt process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program sets the timer interrupt to be disabled as shown in FIG. 41 under the control of the payout control MPU4120a. To switch (save) the register (step S590). Here, the general-purpose storage element (general-purpose register) used in the above-mentioned payout control unit main processing is switched to the auxiliary register. By using this auxiliary register in the payout control unit timer interrupt processing, the value of the general-purpose register is not overwritten. This prevents the contents of the general-purpose register used in the main processing of the payout control unit from being destroyed.

Following step S590, the payout control program sets the 2ms elapsed flag HT-FLG to a value of 1 (step S592). This 2 ms elapsed flag HT-FLG is a flag that clocks 2 ms every time the payout control unit timer interrupt process is performed, that is, every 2 ms, and becomes a value of 1 when 2 ms has elapsed and a value of 0 when 2 ms has not elapsed. Each is set.

Following step S592, the payout control program switches (returns) registers (step S594). This return switches from the auxiliary register used in the payout control unit timer interrupt processing to the general-purpose storage element (general-purpose register). By using this general-purpose register in the payout control unit main processing, the value of the auxiliary register is not overwritten. This prevents the contents of the auxiliary register used in the payout control unit timer interrupt processing from being destroyed.

Following step S594, the payout control program sets interrupt enable (step S596) and ends this routine.

[14-3. Rotation angle switch history creation process]
Next, the rotation angle switch history creation process will be described. In this rotation angle switch history creation process, the history of the detection signal from the rotation angle switch 752 shown in FIG. 12 is created.

When the rotation angle switch history creation process is started, in the payout control unit 4120 on the payout control board 4110, the payout control program controls the rotation angle from the payout control built-in RAM as shown in FIG. 42 under the control of the payout control MPU4120a. The switch detection history information RSW-HIST is read (step S610). This rotation angle switch detection history information RSW-HIST is 1 byte (8 bits: most significant bit B7, B6, B5, B4, B3, B2, B1, least significant bit B0, "B" represents a bit). It has a storage capacity, and the history of the detection signal from the rotation angle switch 752 is stored in the rotation angle switch history information storage area of the payout control built-in RAM as the rotation angle switch detection history information LSB-HIST. In step S610, the rotation angle switch detection history information RSW-HIST is read from the rotation angle switch history information storage area.

Following step S610, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 (step S612). This determination is performed based on the detection signal from the rotation angle switch 752 in the port input process of step S550 in the power-on process of the payout control unit (main process of the payout control unit) shown in FIG. 40. Specifically, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S612, the input information is read from the input information storage area, and it is determined whether or not there is a detection signal from the rotation angle switch 752. When there is a detection signal from the rotation angle switch 752 in the input information, the payout control program has a detection slit for grasping the rotation position of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. It is determined that the axis is in a state of transition from a cutoff state to a non-cutoff state. On the other hand, when there is no detection signal from the rotation angle switch 752 in the input information, the payout control program determines that the detection slit has transitioned the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state.

When the detection slit has transitioned the optical axis of the rotation angle switch 752 from the cutoff state to the non-blocking state in step S612, the payout control program shifts the rotation angle switch detection history information (step S614). In this shift process of the rotation angle switch detection history information, the rotation angle switch detection history information RSW-HIST read in step S610 is converted to the most significant bit B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2. , B2 ← B1, B1 ← least significant bit B0, and so on, shifting from the least significant bit B0 toward the most significant bit B7 one bit at a time.

Following step S614, the payout control program sets the least significant bit B0 of the rotation angle switch detection history information RSW-HIST to a value 1 (step S616), and ends this routine.

On the other hand, when the detection slit has transitioned the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state in step S612, the payout control program shifts the rotation angle switch detection history information (step S618). .. In the shift processing of the rotation angle switch detection history information, the payout control program performs the same processing as the shift processing of the rotation angle switch detection history information in step S614, and the rotation angle switch detection history information LSB-HIST read in step S610. From the least significant bit B0 to the most significant bit B7, such as the most significant bit B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2, B2 ← B1, B1 ← least significant bit B0. Shifts one bit at a time.

Following step S618, the payout control program sets the least significant bit B0 of the rotation angle switch detection history information RSW-HIST to a value 0 (step S620), and ends this routine.

In this way, each time the rotation angle switch history creation process is performed, the rotation angle switch detection history information RSW-HIST is shifted by one bit from the least significant bit B0 toward the most significant bit B7, and then the detection slit rotates. The value 1 or the lowermost bit B0 is set according to the state in which the optical axis of the angle switch 752 is transitioned from the cutoff state to the non-blocking state or the detection slit is in the state in which the optical axis of the rotation angle switch 752 is transitioned from the non-blocking state to the blocking state. Since the value 0 is set, the history of the detection signal from the rotation angle switch 752 can be created.

[14-4. Sprocket fixed position judgment skip processing]
Next, the sprocket fixed position determination skip process will be described. This sprocket fixed position determination skip process skips the determination of whether or not the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted is in the fixed position when a predetermined condition is satisfied. It should be noted that the fixed position determination of the payout rotating body is also performed when the payout of the game ball by the prize ball device 740 is completed. As a result, the rotation of the rotation shaft of the payout motor 744 can be reliably started in a state where the ball is not squeezed.

When the sprocket fixed position determination skip process is started, in the payout control unit 4120 in the payout control board 4110, the payout control program controls the payout control MPU4120a, and as shown in FIG. 43, the fixed position determination skip flag SKP- It is determined whether or not the FLG has a value of 0 (step S630). This fixed position determination skip flag SKP-FLG is a flag indicating whether or not the fixed position determination of the payout rotating body is performed, and when the fixed position determination of the payout rotating body is not performed (when skipping), the value is 1, and the payout rotation The value is set to 0 when the fixed position of the body is determined (when not skipped).

When the fixed position determination skip flag SKP-FLG has a value of 0 (not skipped) in step S630, that is, when the fixed position determination of the payout rotating body is performed, the payout control program has the rotation angle switch history information of the payout control built-in RAM. The rotation angle switch detection history information RSW-HIST is read from the storage area (step S632), and it is determined whether or not the rotation angle switch detection history information matches the fixed position determination value (step S634). This fixed position determination value is stored in the payout built-in ROM, and in the present embodiment, it is "000011111B (" B "represents a bit)", and the upper 4 bits B7 to B4 have a value of 0 and a lower 4 bits. Bits B3 to B0 have a value of 1. In the determination in step S634, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

Here, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST have a value of 1, the detection slit described above is the optical axis of the rotation angle switch 752, continuing in four timer interrupt cycles. It means that the state has changed from the blocked state to the non-blocked state. In the generation of the four timer interrupt cycles, the payout motor 744 shown in FIG. 12 is rotated by four steps. The rotation of the payout motor 744 is the rotation of the payout rotating body of the rotation detection panel via the first gear, the second gear, and the third gear. Since the first gear, the second gear, and the third gear have play (backlash), the payout rotating body rotates clockwise or counterclockwise, but the payout rotating body due to this backlash Since the rotation is designed to correspond to the rotation of about two steps of the payout motor 744, in the present embodiment, when the fixed position determination of the payout rotating body is performed, the rotation angle switch 752 is used. The rotation angle switch detection history information RSW-HIST is created by the rotation angle switch history creation process shown in the history of the detection signal and FIG. 42, and the lower 4 bits B3 to B0 of the created rotation angle switch detection history information RSW-HIST, that is, This is performed based on the detection signal from the rotation angle switch 752 due to the occurrence of the latest four timer interrupt cycles. As a result, in the four timer interrupt cycles, the payout motor 744 rotates four steps, so that it rotates more than the rotation of the payout rotating body due to backlash, and absorbs the rotation of the payout rotating body due to backlash. Can be done. Therefore, since it is possible to prevent erroneous detection of the fixed position of the payout rotating body due to backlash, the rotation position of the payout rotating body can be correctly managed by the rotation position of the payout motor 744. In this embodiment, the four timer interrupt cycles are 8 ms (= 2 ms × 4 times), and are set as the backlash absorption time.

In step S634, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S632 and the lower 4 bits B3 to B0 of the fixed position determination value match, the payout control program determines. The value 1 is set in the fixed position determination skip flag SKP-FLG (step S636). As a result, it is possible to set not to perform (skip) the fixed position determination of the payout rotating body. The payout control MPU4120a sets the rotation position of the payout rotating body in step S636 to a fixed position of the payout rotating body.

Following step S636, the payout control program effectively sets the skip determination time (step S638) and ends this routine. Here, the number of detection slits is three, which is the same as the number of recesses of the payout rotating body, and is formed in equal parts (every 120 degrees) on the outer periphery of the rotation detecting board. Further, as described above, the rotation of the payout motor 744 is the rotation of the payout rotating body of the rotation detection panel via the first gear, the second gear, and the third gear. In the present embodiment, the rotation between the detection slits (120 degrees) of the rotation detection board (delivery rotating body) is designed to correspond to the rotation of 18 steps of the payout motor 744.

The payout control program manages the rotation position of the payout rotating body based on the number of steps of the payout motor 744 under the control of the payout control MPU4120a. Specifically, (1) a transient state (referred to as "edge detection state") in which the detection slit transitions the optical axis of the rotation angle switch 752 from a cutoff state to a non-blocking state, and (2) the detection slit has a rotation angle. The state in which the optical axis of the switch 752 is transitioned from the cutoff state to the non-blocking state (referred to as "fixed position determination state"), and (3) the detection slit shifts the optical axis of the rotation angle switch 752 from the non-blocking state to the non-blocking state. It is managed in three states: the state in which it is set (“fixed position determination skip state”). The edge detection state of (1) corresponds to the rotation of one step of the payout motor 744, the fixed position determination state of (2) corresponds to the rotation of four steps of the payout motor 744, and the fixed position determination skip state of (3). It corresponds to the rotation of 13 steps of the payout motor 744, and manages the rotation position between each detection slit (120 degrees) of the rotation detection board, that is, the rotation position of the payout rotating body by the rotation of 18 steps in total.

In the fixed position determination skip state of (3), since the detection slit is in a state in which the optical axis of the rotation angle switch 752 has transitioned from the non-blocking state to the blocking state, the skip determination time is the time for 13 steps of rotation of the payout motor 744. Is set. As described above, since the timer interrupt cycle is set to 2 ms, the skip determination time is 26 ms (= 2 ms × 13 steps).

When the skip determination time becomes valid in step S638, the skip determination time is subtracted in the timer update process of step S552 in the payout control unit power-on time process (payout control unit main process) shown in FIG. 40. The payout control MPU4120a subtracts the skip determination time, and when the subtraction result becomes the value 0, the fixed position determination skip flag SKP-FLG is set to the initial value 0.

On the other hand, when the fixed position determination skip flag SKP-FLG is not a value 0 (value 1) (when skipping) in step S630, that is, when the fixed position determination of the payout rotating body is not performed, or in step S634, step S632. When the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step 1 and the lower 4 bits B3 to B0 of the fixed position determination value do not match, the payout control program ends this routine as it is. .. The fixed position determination skip flag SKP-FLG set in step S636 is stored in the general-purpose storage element (general-purpose register) of the payout control MPU4120a.

The game balls supplied from the pachinko island facility are stored in the prize ball tank 720 and the tank rail 731, taken into the supply passage of the prize ball device 740, and guided to the prize ball device 740. When the game balls rub against each other and become charged, they electrostatically discharge and generate noise. Therefore, the prize ball device 740 is susceptible to noise and is in an environment. The rotation angle switch board 753 of the prize ball device 740 shown in FIG. 3 is provided with a rotation angle switch 752, and the detection signal from the rotation angle switch 752 is affected by noise due to electrostatic discharge of the game ball. Cheap. Further, the wiring (harness) connecting the payout control board 4110 and the board 754 in the prize ball case in the prize ball device 740 shown in FIG. 3 is also affected by noise due to electrostatic discharge of the game ball. Cheap.

Therefore, in the present embodiment, in order to suppress erroneous detection due to the influence of noise, the above-mentioned fixed position determination skip state (3), that is, the detection slit changes the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state. In the transitional state, the fixed position determination of the payout rotating body is not performed. This enhances the accuracy of the fixed position determination of the payout rotating body. As described above, the period and period required to detect the fixed position of the payout rotating body can be obtained by calculation in advance, so that the skip determination time can be easily set and adjusted.

[14-5. Ball shaving judgment processing]
Next, the ball shaving determination process will be described. This ball squeeze determination process determines whether or not a sphere squeeze state is generated by the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted.

When the ball squeeze determination process is started, the payout control MPU4120a of the payout control unit 4120 on the payout control board 4110 has a rotation angle from the rotation angle switch history information storage area of the above-mentioned payout control built-in RAM, as shown in FIG. The switch detection history information RSW-HIST is read (step S640).

Following step S640, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 described above (step S642). This determination determines whether or not the rotation angle switch detection history information RSW-HIST read in step S640 matches the fixed position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in the present embodiment, it is "00001111B (" B "represents a bit)", and the upper 4 bits B7 to B4 are. The value 0 and the lower 4 bits B3 to B0 are the values 1. In the determination in step S642, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

In step S642, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S640 and the lower 4 bits B3 to B0 of the fixed position determination value match, the payout control program determines. This routine is terminated as it is, assuming that the detection slit has transitioned the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state, that is, the payout rotating body is rotating and the ball is not squeezed. do.

On the other hand, in step S642, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S640 and the lower 4 bits B3 to B0 of the fixed position determination value do not match, the ball is squeezed. The value 1 is set in the middle flag PBE-FLG (step S644). This ball-sliding flag PBE-FLG is a flag indicating whether or not a ball-squashing state is generated by the payout rotating body, and has a value of 1 when the payout motor 744 is performing a ball-squashing operation. The value is set to 0 when no operation is performed.

Following step S644, the payout control program effectively sets the ball squeeze determination time (step S646) and ends this routine. When this ball blistering determination time becomes valid, the ball blistering determination time is subtracted in the timer update process of step S552 in the payout control unit power-on processing (payout control unit main process) shown in FIG. 40. ..

[14-6. Various prize ball stock number addition processing]
Next, various prize ball stock number addition processes will be described. The various prize ball stock number addition processes include a prize ball stock number addition process for prize balls and a prize ball stock number addition process for rental balls, and the prize ball stock number addition process for prize balls is performed from the main control board 4100. It is a process of adding the number of balls to be paid out based on the prize ball command described later, and the process of adding the number of prize balls stock for lending is a process of adding the number of balls to be paid out based on the ball lending request signal from the CR unit 6. be. First, the prize ball stock number addition process for prize balls will be described, and then the prize ball stock number addition process for rental balls will be described. In this embodiment, the prize ball stock number addition process is set to be preferentially performed, and the prize ball stock number added in the prize ball stock number addition process is set according to the prize ball stock number. After the game ball is paid out by the prize ball device 740, it is set to perform the prize ball stock number addition processing for rental ball rental.

[14-6-1. Prize ball stock number addition processing for prize balls]
When the prize ball stock number addition process for the prize ball is started, in the payout control unit 4120 in the payout control board 4110, the payout control program issues a prize ball command as shown in FIG. 45 under the control of the payout control MPU4120a. It is determined whether or not there is (step S650). This determination is performed based on the command analyzed in the command analysis process of step S560 in the power-on process of the payout control unit (main process of the payout control unit) shown in FIG. 40. Specifically, the analyzed command is stored in the receive command information storage area of the payout control built-in RAM as receive command information. In step S650, the payout control program reads the received command information from the received command information storage area and determines whether or not it is a prize ball command.

When the received command information is not a prize ball command in step S650, the payout control program terminates this routine as it is, while when the received command information is a prize ball command in step S650, the payout control program is assigned to this prize ball command. The corresponding prize ball number PBV is read out from the prize ball number information table (step S652). The prize ball number information table, which will be described in detail later, is an information table stored in advance in the payout built-in ROM in which the prize ball command and the prize ball number PBV are associated with each other.

Following step S652, the payout control program reads the prize ball stock number PBS from the payout control built-in RAM (step S654). This prize ball stock number PBS represents the number of game balls that have not yet been paid out by the prize ball device 740, that is, the number of unpaid balls, and in the present embodiment, it has a storage capacity of 2 bytes (16 bits). ing. As a result, the prize ball stock number PBS can store the number of unpaid balls from the value 0 to the value 32767. The prize ball stock number PBS is stored in the prize ball information storage area of the RAM with built-in payout control. In step S652, the prize ball stock number PBS is read out from this prize ball information storage area.

The payout control program adds the prize ball number PBV read out in step S652 to the prize ball stock number PBS read out in step S654 (step S656), and ends this routine. After adding in step S656, the prize ball command read in step S650 is deleted from the received command information storage area.

[14-6-2. Prize ball stock number addition processing for rental ball]
Next, the process of adding the number of prize ball stocks for lending will be described. When the process of adding the number of prize balls for ball rental is started, in the payout control unit 4120 in the payout control board 4110, the payout control program requests the ball rental as shown in FIG. 46 under the control of the payout control MPU4120a. It is determined whether or not there is a signal (step S660). This determination is performed based on the ball lending request signal from the CR unit 6 in the port input process of step S550 in the payout control unit power-on time process (payout control unit main process) shown in FIG. 40. Specifically, the ball rental request signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S660, the payout control program reads the input information from the input information storage area and determines whether or not there is a ball lending request signal.

When there is no ball lending request signal in step S660, the payout control program ends this routine as it is, while when there is a ball lending request signal in step S660, the payout control program uses the above-mentioned prize ball information of the payout control built-in RAM. The prize ball stock number PBS is read from the storage area (step S662), the number of rented balls RBV is added to the prize ball stock number PBS (step S664), and this routine is terminated. The number of rented balls RBV is a fixed value and is stored in advance in the payout built-in ROM. In this embodiment, a value of 25 is set as the number of rented balls RBV. After the addition in step S664, the payout control program erases the ball lending request signal read in step S660 from the input information storage area. Further, in the present embodiment, since the prize ball is prioritized (the prize ball and the ball lending are managed separately), the ball lending request signal is held even when there is a ball lending request signal. , The loan ball will be paid out when the payout of the prize ball is completed. Therefore, in the present embodiment, the ball loan is paid out after the prize ball stock number PBS reaches a value of 0.

[14-7. Stock monitoring process]
Next, the stock monitoring process will be described. In this stock monitoring process, the player monitors whether or not the player continues the game in a state where the accommodation space of the foul cover unit 540 shown in FIG. 1 is filled with the stored game balls (stocked state) during the game. It is a process to do.

When the stock monitoring process is started, in the payout control unit 4120 in the payout control board 4110, the payout control program controls the payout control MPU4120a, and as shown in FIG. 47, the prize ball information of the above-mentioned payout control built-in RAM. The prize ball stock number PBS is read from the storage area (step S670), and it is determined whether or not the read prize ball stock number PBS is equal to or higher than the caution threshold TH (step S672). The caution threshold TH is a fixed value and is stored in advance in the payout built-in ROM. In this embodiment, the value 50 is set as the caution threshold TH.

When the prize ball stock number PBS is equal to or higher than the caution threshold TH in step S672, the payout control program sets the caution flag CA-FLG to a value of 1 (step S674) and ends this routine. With this caution flag CA-FLG, the player starts stocking the game balls in the accommodation space of the foul cover unit 540, and the number of unpaid game balls (the number of prize balls stock described above) becomes the caution threshold TH or higher. It is a flag indicating that the value has been reached, and is set to a value 1 when the caution threshold value TH or higher is reached and a value 0 when the caution threshold value TH or higher is not reached.

On the other hand, when the prize ball stock number PBS is less than the caution threshold TH in step S672, the payout control program sets the caution flag CA-FLG to a value 0 (step S676) and ends this routine.

When the game state becomes a big hit and the player relaxes and watches the production unfolded by the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the plate side as shown in FIG. 14, the player carelessly During one round, the game ball paid out as a prize ball may not be pulled out by operating the lower plate ball removal button 354 from the lower plate 302 shown in FIG. 7. If the game is continued in this state, the lower plate 302 is filled with the game balls, and the game balls start to accumulate in the accommodation space of the foul cover unit 540. When the accommodation space of the foul cover unit 540 is filled with game balls, as described above, the value of the prize ball stock number PBS increases and becomes the caution threshold TH or higher, and the door frame 5 is provided as a caution effect. Multiple LEDs on various decorative boards flash. By this blinking, for example, it is possible to inform the clerk of the hall to pay attention to the player's game. As a result, the clerk in the hall can inform the player that the game ball is to be pulled out from the lower plate 302, and the player can fill the lower plate 302 (the accommodation space of the foul cover unit 540) with the game ball. It is possible to prevent the game from continuing.

In the present embodiment, the caution threshold TH is set to a value 50 corresponding to about one-fifth of the upper limit value 255 that can be represented by 1 byte (8 bits). This makes it possible to inform the clerk of the hall to call attention to the player's game at the earliest possible stage.

[14-8. Payout ball movement judgment setting process]
Next, the payout ball motion determination setting process will be described. In the payout ball movement determination setting process, the payout motor 744 pays out the game ball to the upper plate 301 or the lower plate 302 shown in FIG. 7, performs a ball-brushing operation, or such a payout. It is a process to set either or not to discharge.

When the payout ball operation determination setting process is started, in the payout control unit 4120 on the payout control board 4110, the payout control program has a built-in payout control as shown in FIG. 48 under the control of the payout control MPU4120a. The rotation angle switch detection history information RSW-HIST is read from the rotation angle switch history information storage area of the RAM (step S680).

Following step S680, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 shown in FIG. 12 (step S682). This determination determines whether or not the rotation angle switch detection history information RSW-HIST read in step S680 matches the fixed position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in the present embodiment, it is "00001111B (" B "represents a bit)", and the upper 4 bits B7 to B4 are. The value 0 and the lower 4 bits B3 to B0 are the values 1. In the determination in step S682, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

In step S682, when the payout control program matches the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S680 and the lower 4 bits B3 to B0 of the fixed position determination value, It is determined whether or not the retry error flag RTERR-FLG has a value of 1 (step S684). This retry error flag RTERR-FLG is a flag indicating whether or not the retry operation described later is abnormally operating, and has a value of 1 when the retry operation is abnormally operating and when the retrying operation is not abnormally operating (retry). When the operation is normal), the value is set to 0, respectively.

When the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S682 and the lower 4 bits B3 to B0 of the fixed position determination value do not match in step S682, or in step S684. , When the retry error flag RTERR-FLG is not a value 1 (value is 0), that is, when the retry operation is not abnormally operating, the payout control program determines whether or not the ball-filled flag PBE-FLG has a value of 1. (Step S686). This ball-filling flag PBE-FLG is a flag indicating whether or not a ball-swelling state is generated by the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, and the payout motor 744 is a ball-squeeze flag. The value is set to 1 when the motion is performed, and the value is set to 0 when the ball is not performing the motion.

When the ball-sucking flag PEB-FLG is not a value 1 (value is 0) in step S686, that is, when the ball-sucking operation is not performed, the payout control program stores the prize ball information of the above-mentioned payout control built-in RAM. The prize ball stock number PBS is read from the region (step S688), and it is determined whether or not the read prize ball stock number PBS is larger than the value 0 (step S690). In this determination, it is determined whether or not there is an unpaid number of balls in the payout of the game balls by the payout motor 744.

When the prize ball stock number PBS is larger than the value 0 in step S690, that is, when there is an unpaid number of balls, the payout control program determines whether or not the accommodation space of the foul cover unit 540 is full with the stored game balls. (Step S692). This determination is performed based on the full tank information stored in the full tank and out-of-ball check processing in step S556 in the power-on processing of the payout control unit (main process of the payout control unit) shown in FIG. 40. Specifically, the full tank information is stored in the state information storage area of the above-mentioned payout control built-in RAM. In step S692, the full tank information is read from this state information storage area, and it is determined whether or not the game ball in which the accommodation space of the foul cover unit 540 is stored is full.

When the accommodation space of the foul cover unit 540 is not full in the game ball stored in step S692, the payout control program performs the payout setting process described later (step S694), and ends this routine. In this payout setting process, a payout operation is performed in which the game ball is paid out to the upper plate 301 and the lower plate 302.

On the other hand, when the accommodation space of the foul cover unit 540 is full with the stored game ball in step S692, the payout control program ends this routine as it is. In the pachinko gaming machine 1 of the present embodiment, when the accommodation space of the foul cover unit 540 is filled with the stored game balls, the payout motor 744 is forcibly stopped. When a prize ball is generated while the payout motor 744 is forcibly stopped, the number of unpaid balls by the payout motor 744 increases, and the prize ball stock number PBS is added by the prize ball stock number addition process for prize balls shown in FIG. Will increase.

On the other hand, when the prize ball stock number PBS is not larger than the value 0 (value 0) in step S690, that is, when there is no unpaid number of balls, the payout control program ends this routine as it is. As a result, the game ball is not paid out.

On the other hand, when the ball-grinding flag PBE-FLG has a value of 1, that is, the ball-grinding operation is performed in step S686, the payout control program performs the ball-grinding operation setting process described later (step S700), and this routine To finish. In this ball-grinding motion setting process, a ball-grinding motion is performed to eliminate the ball-grinding state by the payout rotating body of the prize ball device 740.

On the other hand, in step S684, when the retry error flag RTERR-FLG has a value of 1, that is, when the retry operation is abnormally operating, the payout control program sets the output stop (stop) of the drive signal to the payout motor 744. (Step S702). In this setting, the drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the above-mentioned payout control built-in RAM.

Following step S702, the payout control program sets the output of the error state to the CR unit 6 (step S704) and ends this routine. In step S704, when the payout control program is not communicating with the CR unit 6 under the control of the payout control MPU4120a in order to inform the CR unit 6 that the ball lending is currently not possible (CR unit 6). When the logic of BRDY from is LOW, that is, when it is held down), the logic of the PRDY signal is kept in the LOW, that is, the down state, and the logic state of the PRDY signal is set in the PRDY signal output setting information. And store it in the CR communication information storage area. As a result, in the CR communication process of step S554 in the payout control section main process of the payout control section power-on process of FIG. 40, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW, is CRed from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120 via the game ball rental device connection terminal board 869. Output to unit 6. On the other hand, when communicating with the CR unit 6 (when the logic of BRDY from the CR unit 6 is HI, that is, when it stands up and is held), the logic state of the EXS signal is maintained, and the logic state of the EXS signal is maintained. Is set in the EXS signal output setting information and stored in the CR communication information storage area. As a result, the EXS signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control section main process of the payout control section power-on process of FIG. 40. The read out EXS signal output setting information, that is, the EXS signal whose logic is maintained is output from the output terminal of the predetermined output port of the payout control MPU4120a to the CR unit 6 via the game ball rental device connection terminal board 869. .. In addition, "maintaining the logic state of the EXS signal" means that when the logic of the EXS signal is LOW (the EXS signal is held down), the logic LOW is maintained, and the logic of the EXS signal is HI. At some point (the EXS signal is up and held), the logic HI is maintained.

[14-8-1. Payout setting process]
Next, the payout setting process will be described. In this payout setting process, the payout motor 744 is driven to set the payout of the game ball.

When the payout setting process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program outputs the drive command number DRV from the payout control built-in RAM as shown in FIG. 49 under the control of the payout control MPU4120a. Read (step S710). This drive command number DRV commands the number of game balls to be paid out by the payout motor 744, and is equivalent to the prize ball stock number PBS. The drive command number DRV is stored in the prize ball information storage area of the payout control built-in RAM. In step S710, the drive command number DRV is read from the prize ball information storage area.

Following step S710, the payout control program determines whether or not the drive command number DRV has a value of 0 (step S712). This determination is determined based on the drive command number DRV whether or not the number of game balls to be paid out by the payout motor 744 remains.

When the drive command number DRV is 0 in step S712, that is, when the number of game balls to be paid out by the payout motor 744 is zero, the payout control program stops (stops) the output of the drive signal to the payout motor 744. ) Is set (step S714). In this setting, the drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the above-mentioned payout control built-in RAM.

Following step S714, the payout control program reads out the prize ball stock number PBS from the prize ball information storage area of the payout control built-in RAM (step S716), and reads out the actual ball count PB (step S718). This actual ball count PB is a count of the number of game balls actually paid out by the payout motor 744. Although a detailed description thereof will be described later, this count is from the counting switch 751 shown in FIG. 12 in the port input processing of step S550 in the power-on processing of the payout control unit (main processing of the payout control unit) shown in FIG. 40. Perform based on the detection signal. The actual ball count PB is stored in the prize ball information storage area of the RAM with built-in payout control. In step S718, the actual ball count PB is read from the prize ball information storage area.

Following step S718, the payout control program sets the value obtained by subtracting the actual ball count PB read in step S718 from the prize ball stock number PBS read in step S716 to the prize ball stock number PBS and the drive command number DRV. (Step S720), the value 0 is set in the actual ball count PB (step S722), and this routine is terminated. When the drive command number DRV and the actual ball count PB are values 0, in step S722, the value of the prize ball stock number PBS read in step S716 is set to the drive command number DRV as it is.

On the other hand, when the drive command number DRV is not 0 in step S712, that is, when there is a number of game balls to be paid out by the payout motor 744, the payout control program sets the output of the drive signal to the payout motor 744. (Step S724). In this setting, the drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

Following step S724, the payout control program subtracts a value of 1 from the drive command number DRV (decrements and steps S726), and determines whether or not there is a detection signal from the counting switch 751 (step S728). This determination is performed based on the detection signal from the counting switch 751 in the port input processing of step S550 in the power-on processing of the payout control unit (main processing of the payout control unit) shown in FIG. 40. Specifically, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S728, the payout control program reads the input information from the input information storage area and determines whether or not there is a detection signal from the counting switch 751.

When there is a detection signal from the counting switch 751 in step S728, the payout control program adds a value of 1 to the actual ball counting PB (increments, step S730), and ends this routine. By incrementing the actual ball count PB in step S730, the actual ball count PB is counted up.

On the other hand, when there is no detection signal from the counting switch 751 in step S728, the payout control program ends this routine as it is. As described above, the payout control program is in the case of decrementing the drive command number DRV in step S726 under the control of the payout control MPU4120a, and when there is no detection signal from the counting switch 751 in the determination of step S728, that is, in fact. If it is not incremented to the ball count PB, it is said that one ball could not be paid out because the game ball was not received in the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. to decide. Therefore, the payout control program sets the value obtained by subtracting the actual ball count PB from the prize ball stock number PBS in the above-mentioned step S720 to the drive command number DRV in order to pay out the one ball to be paid out again. As a result, when there is no detection signal from the counting switch 751 in the determination of step S728, that is, when the actual ball counting PB is not incremented, the value 1 which is one ball to be paid out can be included in the prize ball stock number PBS. In other words, since the value 1 which is one ball to be paid out can be rounded into the prize ball stock number PBS, the retry operation to pay out the one ball to be paid out can be performed again. By performing this retry operation, it is possible to extremely reduce the possibility that the game ball is not paid out to the player, and it is possible to prevent the player from being disadvantaged due to the unpaid game ball.

[14-8-2. Ball motion setting process]
Next, the ball-shaped motion setting process will be described. In this ball squeeze operation setting process, it is a process of setting to eliminate the ball squeeze state by the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 of the prize ball device 740 is transmitted.

When the ball shaving operation setting process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program elapses the ball squeeze determination time as shown in FIG. 50 under the control of the payout control MPU 4120a. It is determined whether or not the program has been performed (step S750). This determination is performed based on the ball squeeze determination time subtracted in the timer update process of step S552 in the payout control unit power-on time process (payout control unit main process) shown in FIG. 40. Specifically, the ball scooping determination time is stored in the time management information storage area of the above-mentioned payout control built-in RAM as time management information. In step S750, the time management information is read from the time management information storage area, and it is determined whether or not the ball squeeze determination time has elapsed.

When the ball squeeze determination time has not elapsed in step S750, the payout control program reads the rotation angle switch detection history information RSW-HIST from the rotation angle switch history information storage area of the above-mentioned payout control built-in RAM (step S752). ..

Following step S752, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 described above (step S754). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S752 matches the fixed position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in the present embodiment, it is "00001111B (" B "represents a bit)", and the upper 4 bits B7 to B4 are. The value 0 and the lower 4 bits B3 to B0 are the values 1. In the determination in step S754, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

In step S754, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S752 and the lower 4 bits B3 to B0 of the fixed position determination value do not match, the payout control program determines. The output of the drive signal to the payout motor 744 is set so that the ball is operated (step S756), and this routine is terminated. In this setting, the drive information for outputting the drive signal is set in the payout motor 744 and stored in the output information storage area of the above-mentioned payout control built-in RAM.

On the other hand, in step S754, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S752 and the lower 4 bits B3 to B0 of the fixed position determination value match, the payout control program Sets the stop of the drive signal to the payout motor 744 (step S758). In this setting, the drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

Following step S758, the payout control program sets the value 0 in the ball-grinding flag PBE-FLG as the end of the ball-grinding operation (step S760), and ends this routine. This ball-sliding flag PBE-FLG is a flag indicating whether or not a ball-squashing state is generated by the payout rotating body, and has a value of 1 when the payout motor 744 is performing a ball-squashing operation. When no operation is performed (end of ball-sliding operation), the values are set to 0, respectively.

On the other hand, when the ball squeeze determination time has elapsed in step S750, the payout control program sets the stop of the drive signal to the payout motor 744 (step S762). In this setting, the drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

Following step S762, the payout control program sets the output of the error state to the CR unit 6 (step S764). Here, in order to inform the CR unit 6 that the ball lending is not possible at present, the payout control MPU4120a is not communicating with the CR unit 6 (the logic of BRDY from the CR unit 6 is LOW, that is, (When it is down and held), the logic of the PRDY signal is LOW, that is, the down state is held, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area. do. As a result, in the CR communication process of step S554 in the payout control section main process of the payout control section power-on process of FIG. 40, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW, is CRed from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120 via the game ball rental device connection terminal board 869. Output to unit 6. On the other hand, when communicating with the CR unit 6 (when the logic of BRDY from the CR unit 6 is HI, that is, when it stands up and is held), the logic state of the EXS signal is maintained, and the logic state of the EXS signal is maintained. Is set in the EXS signal output setting information and stored in the CR communication information storage area. As a result, the EXS signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control section main process of the payout control section power-on process of FIG. 40. The read out EXS signal output setting information, that is, the EXS signal whose logic is maintained is output from the output terminal of the predetermined output port of the payout control MPU4120a to the CR unit 6 via the game ball rental device connection terminal board 869. .. As described above, "maintaining the logic state of the EXS signal" means that when the logic of the EXS signal is LOW (the EXS signal is held down), the logic LOW is maintained and the EXS signal is maintained. When the logic of is HI (the EXS signal is raised and held), the logic HI is maintained.

Following step S764, the payout control program sets the value 0 in the ball-grinding flag PBE-FLG as the end of the ball-grinding operation (step S766), and ends this routine.

[14-9. Retry operation monitoring process]
Next, the retry operation monitoring process will be described. This retry operation monitoring process is a process of monitoring whether or not the retry operation of paying out the game ball to be paid out again is normally performed.

When the retry operation monitoring process is started, in the payout control unit 4120 on the payout control board 4110, the payout control program controls the payout control MPU4120a, and as shown in FIG. 51, the rotation angle of the above-mentioned payout control built-in RAM. The rotation angle switch detection history information RSW-HIST is read from the switch history information storage area (step S770).

Following step S770, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 described above (step S772). This determination determines whether or not the rotation angle switch detection history information RSW-HIST read in step S770 matches the fixed position determination value. As described above, this fixed position determination value is stored in the payout control built-in ROM, and in the present embodiment, it is "00001111B (" B "represents a bit)", and the upper 4 bits B7 to B4. Has a value of 0, and B3 to B0 of the lower 4 bits have a value of 1. In the determination in step S772, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

In step S772, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S770 and the lower 4 bits B3 to B0 of the fixed position determination value match, the payout control program determines. Add the value 1 to the mismatch counter INCC (increment, step S774). This mismatch counter INCC includes the number of game balls received and discharged in the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, the number of balls detected by the counting switch 751 and the number of balls. It is a counter for calculating the difference between , The value is 0. Since the payout control program performs a retry operation in the payout installation process shown in FIG. 49, the number of game balls received and paid out in the concave portion of the payout rotating body by this retry operation and the actual counting switch. The inconsistency counter INCC monitors and determines whether or not the number of balls detected by the 751 and the inconsistent payout of the game balls due to the inconsistency are repeatedly performed. The inconsistency counter INCC is stored in the prize ball information storage area of the payout control built-in RAM. In step S774, the payout control program increments the mismatch counter INCC stored in the prize ball information storage area.

Following step S774 or in step S772, the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S770 and the lower 4 bits B3 to B0 of the fixed position determination value do not match. Occasionally, the payout control program determines if there is a detection signal from the counting switch 751 (step S776). This determination is performed based on the detection signal from the counting switch 751 in the port input processing of step S550 in the power-on processing of the payout control unit (main processing of the payout control unit) shown in FIG. 40. Specifically, as described above, the detection signal is stored in the input information storage area of the above-mentioned payout control built-in RAM as input information. In step S776, the payout control program reads the input information from the input information storage area and determines whether or not there is a detection signal from the counting switch 751.

When there is a detection signal from the counting switch 751 in step S776, the payout control program subtracts a value of 1 from the mismatch counter INCC stored in the prize ball information storage area of the payout control built-in RAM (decrement, step S778). ..

Following step S778, or when there is no detection signal from the counting switch 751 in step S776, the payout control program determines if the value of the mismatch counter INCC is less than the mismatch threshold INCTH (step S780). ). In the pachinko gaming machine 1, it has been experimentally obtained that the probability that one inconsistent gaming ball is paid out due to the retry operation is about 1 in millions, and in the present embodiment, the inconsistency threshold value is obtained. A value of 5 is set as INCTH.

As described above, in the process of setting the work area of the payout control built-in RAM in step S530 in the payout control unit power-on process of FIG. 40, the payout backup information is stored in the payout control built-in RAM at the time of power recovery. , Information used for this retry operation monitoring process is set based on the mismatch counter INCC stored in the prize ball information storage area. By this processing, for example, even if there is a momentary power failure or a power failure, the value of the inconsistency counter INCC or the like at the time of power recovery is restored to the value of the mismatch counter INCC or the like stored as the payout backup information immediately before the momentary power failure or the power failure. You can do it. As a result, in the determination of step S780, the monitoring of the payout operation (retry operation) of the game ball by the prize ball device 740, which was performed until just before the momentary power failure or the power failure, can be continued from the time of power recovery. ing. Therefore, for example, when the value of the inconsistency counter INCC is smaller than the inconsistency threshold value INCTH in the determination of step S780 immediately before the momentary power failure or power failure, it is determined that the retry operation is operating normally, that is, the prize ball. It can be determined that the payout operation of the game ball by the device 740 is in the normal state, and even at the time of power recovery, it can be determined that the payout operation of the game ball by the prize ball device 740 is in the normal state by the determination in step S780. On the other hand, when the value of the inconsistency counter INCC is not smaller than the inconsistency threshold value INCTH in the determination in step S780, it is determined that the retry operation is abnormal, that is, the game ball payout operation by the prize ball device 740 is abnormal. It can be determined that the state is in the state, and even at the time of power recovery, it can be determined in the determination in step S780 that the payout operation of the game ball by the prize ball device 740 is in an abnormal state.

When the value of the inconsistency counter INCC is smaller than the inconsistency threshold value INCTH in step S780, this routine is terminated as it is. On the other hand, when the value of the inconsistency counter INCH is not smaller than the inconsistency threshold value INCTH in step S780, that is, when the value of the inconsistency counter INCTH is equal to or more than the inconsistency threshold value INCTH, the payout control program determines the "retry error". The above-mentioned payout control built-in RAM is set with retry error information for displaying the number "5" on the error LED display 860b, which is a segment display mounted on the payout control board 4110, in order to notify that the value is "5". It is set (stored) in the state information storage area of (step S782). On the other hand, in the case of notifying that "the prize ball is in stock", the payout control program sets the information in the prize ball stock that displays the number "9" on the error LED display 860b and has the above-mentioned built-in payout control. It is set (stored) in the state information storage area of the RAM (step S782).

Following step S782, the payout control program sets a value 0 (initial value 0) in the mismatch counter INCC stored in the prize ball information storage area of the payout control built-in RAM (step S784). In step S784, the inconsistent counter INCC is determined in step S780 when the value of the inconsistent counter INCC is not smaller than the inconsistent threshold value INCTH, that is, when the value of the inconsistent counter INCC is equal to or greater than the inconsistent threshold value INCTH. It is initialized when this internal factor occurs. The inconsistency counter INCC is initialized when the operation switch 860a is operated to clear the RAM when the power is turned on, triggered by the occurrence of this external factor. When the operation switch 860a is operated when the power is turned on, as described above, the operation signal corresponding to the operation is input to the main control MPU 4100a of the main control board 4100 shown in FIG. 11 as a RAM clear signal. As described above, the main control program described above erases all the various information stored in the main control built-in RAM under the control of the main control MPU4100a, and issues a RAM clear notification command to the peripheral control board shown in FIG. Output to 4140. As a result, the RAM clear notification sound flows from the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the speaker 130 provided in the door frame 5 shown in FIG.

Following step S784, the retry error flag RTERR-FLG is set to the value 1 (step S786), and this routine is terminated. This retry error flag RTERR-FLG is a flag indicating whether or not the retry operation is abnormally operating, and has a value of 1 when the retry operation is abnormally operating and when the retrying operation is not abnormally operating (retrying operation is). It is set to 0 when it is operating normally).

Note that the payout control program shows retry error information (or information in prize ball stock) set (stored) in the output information storage area of the payout control built-in RAM in step S782 under the control of the payout control MPU4120a. In the command transmission process of step S566 in the power-on processing of the payout control unit (main process of the payout control unit), a retry error status command is created and transmitted to the main control board 4100, and the LED display data of step S564 in the same process is created. In the process, display data to be displayed on the error LED display 860b is created and stored in the output information storage area as LED display information, and in the LED display information stored in the output information storage area in the port output process of step S548 in the same process. Based on this, a drive signal is output to the error LED display 860b, and the number "5" is displayed on the error LED display 860b. In the main control board 4100 that has received the status command, the main control program transmits the peripheral control board command transmission process in step S92 in the main control side timer interrupt process shown in FIG. 37 to the peripheral control board 4140. The peripheral control board 4140 emits a plurality of LEDs of various decorative boards provided on the door frame 5 in a predetermined color (red in the present embodiment), and outputs a lighting signal to output a lighting signal. FIG. It is output to the frame decoration drive amplifier board 194 shown in the above, and a plurality of LEDs are made to emit light in a predetermined color. As described above, the clerk in the hall who noticed the light emission of the plurality of LEDs put the number "on the error LED display 860b mounted on the payout control board 4110 by opening the main body frame 3 with respect to the outer frame 2. By visually observing that "5" is displayed, it can be confirmed that the "retry error" has occurred. As a result, the clerk in the hall, etc., in order to investigate the cause of the occurrence, confirms the malfunction of the counting switch 751, the disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, and the contact failure of various connectors. This can be performed extremely quickly as compared with the case where the light emission of a plurality of LEDs and the display content of the error LED display 860b are not notified.

Further, as described above, it is difficult to detect the game ball that is received and discharged by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted by intentionally deactivating the counter switch 751. Even if a retry operation is forcibly generated and a fraudulent act of illegally acquiring the game ball paid out by this retry operation is performed, the value of the inconsistency counter INCC described above becomes equal to or higher than the inconsistency threshold INCTH. Since a plurality of LEDs of various decorative boards provided on the door frame 5 emit light, a clerk in the hall or the like rushes to check the state of the pachinko gaming machine 1. Then, the player who commits the fraudulent act has no choice but to interrupt the act so that the act is not discovered, and cannot continuously acquire the fraudulent game ball due to the fraudulent act. Even if the value of the inconsistency counter INCC matches the inconsistency threshold value INCTH, the number of game balls that can be acquired by the cheating player is the same as the inconsistency threshold value INCTH, that is, with 5 balls. Therefore, the damage to the hall due to the act of intentionally deactivating the counting switch 751 can be suppressed to an extremely small value.

Further, as described above, the inconsistent counter INCC is set when the value of the inconsistent counter INCC is not smaller than the inconsistent threshold value INCTH in step S780, that is, the value of the inconsistent counter INCC is equal to or higher than the inconsistent threshold value INCTH. It is being initialized when an internal factor such as the fact that it has become is generated. As a result, the inconsistency counter INCC is not initialized when an external factor such as the operation of the operation switch 860a is operated to clear the error occurs. Therefore, even if the operation switch 860a or the like is illegally modified so that the operation signal is input to the payout control MPU4120a, the mismatch counter INCC may be forcibly initialized by such an illegal act. do not have.

[14-10. Inconsistency counter reset judgment process]
Next, the inconsistency counter reset process will be described. In this mismatch counter reset process, the number of game balls received and discharged in the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, and the number of balls detected by the counting switch 751. This is a process of determining whether or not to reset the inconsistency counter INCC that calculates the difference between.

When the inconsistency counter reset determination process is started, in the payout control unit 4120 in the payout control board 4110, the payout control program controls the payout control MPU 4120a, and as shown in FIG. 52, the inconsistency counter reset determination time. It is determined whether or not the elapse has passed (step S790). This determination is performed based on the inconsistency counter reset determination time updated in the timer update process of step S552 in the payout control unit power-on time process (payout control unit main process) shown in FIG. 40. Specifically, the inconsistency counter reset determination time is stored in the time management information storage area of the above-mentioned payout control built-in RAM as time management information. In step S790, the time management information is read from the time management information storage area, and it is determined whether or not the inconsistency counter reset determination time has elapsed.

When the inconsistency counter reset determination time has not elapsed in step S790, the payout control program ends this routine as it is. On the other hand, when the inconsistency counter reset determination time has elapsed in step S790, the payout control program initializes the inconsistency counter reset determination time (step S792). By this initialization, the inconsistency counter reset determination time is set to the initial value of 7000s (about 2 hours).

Following step S792, the payout control program sets a value 0 (initial value 0) in the mismatch counter INCC stored in the prize ball information storage area of the above-mentioned payout control built-in RAM (step S794), and this routine To finish. As described above, the mismatch counter INCC was detected by the counting switch 751 and the number of game balls received and discharged in the concave portion of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. It is a counter for calculating the difference between the number of balls and the number of balls of the game ball, which is usually received and paid out in the concave portion of the payout rotating body, and the number of balls detected by the counting switch 751 is one. The value is 0 because it is done. Since the payout control program performs a retry operation in the payout installation process shown in FIG. 49 under the control of the payout control MPU4120a, the ball of the game ball received and paid out in the recess of the payout rotating body by this retry operation. The inconsistency counter INCC monitors and determines whether or not the number and the number of balls actually detected by the counting switch 751 are inconsistent with each other and the game balls are paid out repeatedly. In the pachinko gaming machine 1 of the present invention, it has been experimentally obtained that the probability that one inconsistent gaming ball is paid out due to a retry operation is about 1 in millions.

Here, as described above, the pachinko gaming machine 1 is composed of a gaming board 4 and a frame such as a main body frame 3 on which the gaming board 4 is mounted, and by exchanging the gaming board 4 (replacement of a new machine). Since the game specifications can be changed, the payout control board 4110 for controlling the prize ball device 740, the power supply board 851 for generating the drive power supply for the prize ball device 740 and the control power supply for the payout control board 4110 are common. It is equipped on the frame side as a function. In the payout control unit 4120 of the payout control board 4110, it is abnormal whether or not the payout control program repeatedly performs the retry operation by monitoring the mismatch counter INCC as described above under the control of the payout control MPU4120a. The operation can be determined, and in the payout control unit power-off process in the payout control unit power-on process shown in FIG. 40, the inconsistency counter INCC immediately before the power-off is stored when the power is turned off, while the figure is shown. In the process of step S530 (setting at the time of power recovery of the RAM work area) in the process at the time of turning on the power of the payout control unit shown in 39, the process is restarted from the inconsistent counter INCC stored at the time of turning on the power.

Then, when the power is cut off and the game board 4 mounted on the pachinko gaming machine 1 is replaced with a game board 4'of another game specification different from the game board 4, the payout control is performed. The payout control MPU4120a of the payout control unit 4120 on the board 4110 starts processing again from the mismatch counter INCC stored when the gaming board 4 is mounted on the pachinko gaming machine 1. That is, when the player plays the pachinko gaming machine 1 equipped with the gaming board 4', the inconsistency counter INCC in the pachinko gaming machine 1 equipped with the gaming board 4 before replacement is inherited as it is. For this reason, the player plays the pachinko game machine 1 equipped with the game board 4', and there is a probability of 1 in millions that the number of inconsistent game balls is generated, and the mismatch counter INCC. When the inconsistency counter INCC becomes equal to or higher than the above-mentioned inconsistency value INCTH, the game board 4 is replaced with the game board 4', and the payout control MPU4120a determines that the retry operation is abnormal. There is a risk of That is, in a period shortly after the game board 4 is replaced with the game board 4', a malfunction of the counting switch 751, disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, poor contact of various connectors, etc. There is a possibility that it is suddenly determined as an abnormal operation of the retry operation even though the above has not occurred.

In this way, when the game board 4 is replaced with the game board 4'and judged as an abnormal operation of the retry operation in a short period of time, the replaced game board 4'has the impression that it is easy to break down even though it is new. It may be given to the player. The probability that one inconsistent game ball will be paid out due to the retry operation is 1 in millions when the pachinko game machine 1 is installed in the hall and continuously operated for one week during the opening hours of the hall. , Since it is the same as the probability that one inconsistent game ball due to the retry operation is paid out, the probability of one millionth from the mismatch counter INCC in the process of step S778 in the retry operation monitoring process shown in FIG. In the state where only the value 1 is not subtracted. Then, in one week, the value 1 is incremented to the inconsistency counter INCC and the inconsistency counter INCC becomes the value 1, and in two weeks, the value 1 is further incremented to the inconsistency counter INCC and the inconsistency counter INCC becomes the value 2. In the week, the value 1 is further incremented to the inconsistency counter INCC to the value 3, the inconsistency counter INCC becomes the value 3, and in the 4th week, the value 1 is further incremented to the inconsistency counter INCC to the inconsistency counter INCC to the value 4. The value 1 is further incremented by the inconsistency counter INCC, and the inconsistency counter INCC becomes a value of 5, which coincides with the above-mentioned inconsistency threshold INCTH. That is, after 5 weeks have passed, since the inconsistency counter INCC matches the inconsistency threshold value INCTH, the payout control program is controlled by the payout control MPU4120a in step S776 in the retry operation monitoring process shown in FIG. In the judgment, it is judged that there is no detection signal from the counting switch 751, and a malfunction of the counting switch 751, disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, poor contact of various connectors, etc. occur. It is a segment display mounted on the payout control board 4110 in order to notify that a "retry error" has occurred in the process of step S782 in the retry operation monitoring process shown in FIG. Retry error information for displaying the number "5" is set in the error LED display 860b and set (stored) in the state information storage area of the payout control built-in RAM.

Therefore, when the payout control MPU4120a determines that the inconsistency counter reset determination time has elapsed in the determination in step S790 in this inconsistency counter reset determination process, that is, every 7000s (about 2 hours), the inconsistency counter reset is repeated. By forcibly setting the value 0 to the inconsistency counter INCC in the process of step S794 in the determination process, that is, forcibly resetting it, the increment of the inconsistency counter INCC that occurs with a probability of 1 / million of the above-mentioned is increased. It has been disabled. As a result, an error has occurred in the retry operation even though there is no malfunction of the counting switch 751, disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, poor contact of various connectors, and the like. It is possible to prevent the retry error information that conveys the above from being set (stored) in the state information storage area of the payout control built-in RAM.

It should be noted that by intentionally deactivating the counting switch 751, it is difficult to detect the game ball that is received and paid out by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. Even if a retry operation is forcibly generated and a fraudulent act of illegally acquiring the game ball paid out by this retry operation is performed, the counting switch 751 is intentionally repeatedly deactivated for a short time as described above. As described above, when the value of the inconsistency counter INCC becomes equal to or higher than the inconsistency threshold INCTH, a plurality of LEDs of various decorative boards provided on the door frame 5 emit light, so that the clerk in the hall or the like can check the state of the pachinko gaming machine 1. I will rush to confirm. Then, the player who commits the fraudulent act has no choice but to interrupt the act so that the act is not discovered, and cannot continuously acquire the fraudulent game ball due to the fraudulent act. On the other hand, when the counting switch 751 is intentionally repeatedly inactive for a long time so that the value of the inconsistency counter INCC does not exceed the inconsistency threshold value INCTH, the inconsistency counter INCC is set every 7000s (about 2 hours). Although reset, the number of game balls that can be acquired by the cheating player during this period is, as described above, the inconsistency counter INCC up to the inconsistency threshold value INCTH, and the counting switch 751 is intentionally set. Even if the player is repeatedly inactive for a long period of time, the number of game balls that can be acquired by a player who commits a fraudulent act can be extremely reduced.

[14-11. Error cancellation operation judgment processing]
Next, the error cancellation operation determination process will be described. In this error release operation determination process, it is determined whether or not the operation switch 860a shown in FIG. 12 is operated.

When the error canceling operation determination process is started, in the payout control unit 4120 on the payout control board 4110, the payout control program controls the payout control MPU4120a, and as shown in FIG. 53, the operation switch 860a cancels the error. It is determined whether or not the operation is performed (step S800). This determination is performed based on the operation signal from the operation switch 860a in the port input process of step S550 in the power-on processing of the payout control unit (main process of the payout control unit) shown in FIG. 40. Specifically, the operation signal is stored as input information in the input information storage area of the above-mentioned payout control built-in RAM. In step S800, it is determined that the payout control program does not read the input information from the input information storage area and instruct to cancel the error when the logical value of the operation signal from the operation switch 860a is HI. While it is determined that the operation switch 860a is not operated, it is determined that when the logical value of the operation signal from the operation switch 860a is LOW, it is determined that the error is canceled and the operation switch 860a is operated. It is determined that it is.

When the operation switch 860a is not operated in step S800, the payout control program terminates this routine as it is, while when the operation switch 860a is operated in step S800, the payout control program performs an error flag status confirmation process. (Step S802). In this error flag state determination process, the state of the error flag corresponding to various error information related to the prize ball device 740 is confirmed. For example, the state of the retry error flag RTERR-FLG indicating whether or not the retry operation is abnormal is confirmed. As described above, the retry error flag RTERR-FLG has a value of 1 when the retry operation is abnormally operating and a value of 0 when the retry operation is not abnormally operating (the retry operation is operating normally). Since it is set, the payout control program confirms whether the value of the retry error flag RTERR-FLG is a value 0 or a value 1 under the control of the payout control MPU4120a.

Following step S802, the payout control program performs the state information setting process (step S804). In this state information setting process, if the state of the error flag indicates that an error has occurred based on the error flag confirmed in step S802, the state information corresponding to the error flag is described above. Set (store) in the status information storage area of the payout control built-in RAM. As a result, various information (state information) is read from the state information storage area in the command transmission process of step S566 in the power-on processing of the payout control unit (main process of the payout control unit) shown in FIG. 40, and the read state is read. A state command is created based on the information and sent to the main control board 4100. For example, when the retry error flag RTERR-FLG indicating whether or not the above-mentioned retry operation is abnormally operating has a value of 1, that is, when the retrying operation is abnormally operating, an error has occurred in the retrying operation. When the retry error information to be transmitted is set (stored) in the state information storage area of the payout control built-in RAM, the command transmission process in step S566 in the payout control unit power-on process (payout control unit main process) shown in FIG. 40 A retry error status command is created and sent to the main control board 4100.

In the main control board 4100 that has received the retry error information, the main control program transmits the peripheral control board 4140 to the peripheral control board 4140 in the peripheral control board command transmission process of step S92 in the main control side timer interrupt process shown in FIG. 37. On the control board 4140, the sub-control program performs a retry operation error notification process for notifying that an error has occurred in the retry operation. In this retry operation error notification process, the error notification announcement of the retry operation of "Please check the prize ball unit" and "Check the harness of the payout control board" is made a predetermined number of times (in this embodiment). 2 times.) Repeatedly, the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the speaker 130 provided in the door frame 5 shown in FIG. It is designed to do. The clerk in the hall who heard the error notification announcement of this retry operation had a malfunction of the counting switch 751 shown in FIG. 12, disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, poor contact of various connectors, etc. Can be confirmed extremely quickly as compared with the case where the error notification announcement of the retry operation does not flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. Further, in the retry operation error notification process, a plurality of LEDs of various decorative boards provided on the door frame 5 are made to emit light in a predetermined color (red in this embodiment).

Following step S804, the payout control program performs the release setting process (step S806). In this release setting process, if the state of the error flag indicates that an error has occurred based on the error flag corresponding to the various error information confirmed in step S802, the error flag corresponds to the error flag. The CR unit 6 indicates that the content displayed by the error LED display 860b, which is a segment display already mounted on the payout control board 4110, is forcibly stopped or the ball can be rented. In order to convey the above-mentioned PRDY signal logic to HI, that is, the state in which it is started is maintained, and the game ball or the like lending device connection terminal board 869 is connected from the output terminal of the predetermined output port of the payout control MPU4120a of the payout control unit 4120. It is output to the CR unit 6 via. For example, when the retry error flag RTERR-FLG indicating whether or not the above-mentioned retry operation is abnormally operating has a value of 1, that is, when the retrying operation is abnormally operating, the error LED indicator 860b has already displayed it. The retry error information stored in the state information storage area of the above-mentioned payout control built-in RAM is "normal" in order to forcibly stop the number "5" notifying that the "retry error" is present. Forcibly overwrite the information on which the figure "-" that informs the effect is displayed. Further, in order to inform the CR unit 6 that the ball can be rented, the logic of the PRDY signal is kept in the HI, that is, the raised state, and the game ball is played from the output terminal of the predetermined output port of the payout control MPU4120a. It is output to the CR unit 6 via the equal rental device connection terminal board 869.

Following step S806, the payout control program performs error flag initialization processing (step S808), and ends this routine. In this error flag initialization process, if the state of the error flag indicates that an error has occurred based on the error flag corresponding to the various error information confirmed in step S802, the error flag is set. initialize. For example, when the retry error flag RTERR-FLG indicating whether or not the above-mentioned retry operation is abnormally operating has a value of 1, that is, when the retry operation is abnormally operating, a value 0 is set to the retry error flag RTERR-FLG. Set and initialize. At this time, the logic of the PRDY signal described above is held in the HI, that is, the rising state, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area. As a result, in the CR communication process of step S554 in the payout control section main process of the payout control section power-on process of FIG. 40, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW is output from the output terminal of the predetermined output port of the payout control MPU4120a to the CR unit 6 via the game ball rental device connection terminal board 869. ..

As described above, the retry error flag RTERR-FLG is an internal factor when the value of the inconsistency counter INCC is equal to or greater than the inconsistency threshold value INCTH in the determination of step S780 in the retry operation monitoring process shown in FIG. The value 1 is set in the retry error flag RTERR-FLG in the process of step S786 of the same process, and when the operation switch 860a is operated, this is the trigger, that is, this external factor is caused. When the occurrence occurs, the retry error flag RTERR-FLG is set to a value of 0 and initialized. When the operation switch 860a is operated to clear the RAM when the power is turned on, the retry error flag RTERR-FLG is operated to clear the RAM in order to clear the RAM, that is, the operation switch 860a is operated to clear the RAM. Similar to the case where the switch 860a is operated, it is initialized when this external factor occurs.

As described above, in the pachinko gaming machine 1, the main control side main process executes the operation switch 860a (operation switch) that was originally supposed to be used to cancel the error that occurred in the payout operation from the time when the power is turned on. An operation for demonstrating the RAM clear function for starting the initialization of the main control built-in RAM (game storage unit) and the payout control built-in RAM (payout storage unit) for a predetermined time until the operation is performed. It is functioning as a department. Further, the pachinko gaming machine 1 causes the operation switch 860a to function as an operation unit for canceling an error generated in the payout operation of the game ball after the lapse of the predetermined time. Here, even if the hall clerk is not accustomed to operating the pachinko machine, as long as he / she remembers the position of the operation switch 860a on the back of the gaming machine, it depends on the timing of operating the operation switch 860a. If a predetermined time has passed from the time when the power is turned on, the function of canceling the error generated in the payout operation of the game ball is exerted, while the predetermined time is determined from the time when the power is turned on according to the timing when the operation switch 860a is operated. Within the time, the function of initializing the storage unit can be exerted. Therefore, even if an error occurs in such a gaming machine, the hall clerk can improve the efficiency of the switch operation when dealing with the error and can appropriately deal with the switch operation without hesitation, so that the game is interrupted. The game can be restarted before the player who has been played is discouraged from playing the game.

[14-12. Exchange of various signals with CR unit]
Next, the CR communication process in step S554 in the payout control section main process of the payout control section power-on process of FIG. 40 will be described using a timing chart. In this CR communication process, various signals shown in FIG. 13 are exchanged between the payout control board 4110 and the CR unit 6. First, the signal processing at the time of payout operation by ball lending will be described, and then the input signal confirmation processing from the CR unit 6 will be described. Here, the number of balls for 200 yen as the amount of money (in this embodiment, 50 balls, and the payout operation of 25 balls for 100 yen as the amount of money is performed twice) is used as the number of balls to be rented. A case of paying out to the upper plate 301 and the lower plate 302 shown in FIG. 7 will be described. The BRQ signal, BRDY signal, and CR connection signal from the CR unit 6 read input information from the input information storage area of the payout control built-in RAM and are stored in the read input information, and are stored in the CR communication process. Checks the logical state of the BRQ signal, BRDY signal, and CR connection signal from the input information every 2 ms, which is the interrupt timer cycle.

[14-12-1. Signal processing during payout operation by ball lending]
The payout control MPU4120a of the payout control unit 4120 in the payout control board 4110 reads out the PRDY signal output setting information from the CR communication information storage area of the payout control built-in RAM, and the read out PRDY signal output setting information pays out the rental ball. When the logic state of the PRDY signal that conveys that the payout operation is possible is set, the payout operation for paying out the rental ball is possible as shown in FIG. 54 (d). The logic of the PRDY signal is HI, that is, it is started up and held, and is output from the output terminal of the predetermined output port of the payout control MPU4120a of the payout control unit 4120. It is output to the CR unit 6 via the plate 869 (timing H0). In this state, for example, when the player presses the ball lending button 361 of the ball lending unit 360 shown in FIG. 2, the ball lending switch 365b is switched on (turned on), and this ball lending is turned on. The operation signal is input to the CR unit 6 from the frequency display board 365 as the TDS shown in FIG. 13 via the game ball rental device connection terminal board 869. The CR unit 6 into which the TDS is input pays out the number of game balls worth 200 yen as the number of balls to be rented to the upper plate 301 and the lower plate 302, so that the CR unit 6 can be rented as shown in FIG. 54 (a). BRDY, which is a ball request signal, is output from the CR unit 6 to the payout control board 4110 (payout control MPU4120a) via the game ball rental device connection terminal board 869, and the signal is started up and held (timing H1). .. This BRDY is input as a BRDY signal to the input terminal of a predetermined input port of the payout control MPU4120a.

In the payout control MPU4120a to which the BRDY signal is input, as shown in FIG. 54 (b), the payout control program has a lending request monitoring time HA (in this embodiment, 20 milliseconds (ms) to 58 ms) from the timing H1. By the time the set number has elapsed, a predetermined number of balls can be rented from the CR unit 6 via the game ball renting device connection terminal board 869 (25 balls in the present embodiment) in one payout operation. , Equivalent to 100 yen as the amount of money.) Monitors whether or not the BRQ, which is a single payout operation start request signal for paying out, is started.

Of the number of game balls worth 200 yen, the CR unit 6 first pays out the number of game balls worth 100 yen to the upper plate 301 and the lower plate 302 as the number of rented balls, so FIG. 54 (b) ), The BRQ is output from the CR unit 6 to the CR unit 6 via the game ball rental device connection terminal plate 869 from the timing H1 until the rental request monitoring time HA elapses, and the signal is output. Start up and hold (timing H2). This BRQ is input as a BRQ signal to the input terminal of a predetermined input port of the payout control MPU4120a.

As shown in FIG. 54 (c), when the BRQ signal rises from the timing H1 until the lending request monitoring time HA elapses, the payout control MPU4120a has the BRQ request approval ACK monitoring time HB from the timing H2 (in the present embodiment). It is set to 20 ms ± 1 ms.) In order to convey that one payout operation has started, the logic of the EXS signal is set as HI, that is, the payout control MPU4120a is held in the activated state. It is output from the output terminal of the predetermined output port of the above, and is output to the CR unit 6 as an EXS via the game ball or the like rental device connection terminal board 869 (timing H3).

As shown in FIG. 54 (b), the CR unit 6 to which this EXS is input has a lending instruction monitoring time HC (set to 20 ms to 58 ms in this embodiment) from timing H3 to elapse. The BRQ that has been started up and held from the timing H2 is output from the CR unit 6 to the payout control board 4110 via the game ball rental device connection terminal board 869, and the signal is lowered and held (timing H4).

As shown in FIG. 54 (c), the payout control MPU4120a performs one payout operation until the payout monitoring time HD (in this embodiment, the ball payout time is set) elapses from the timing H4. Go and pay out the predetermined number of balls to be rented, that is, the number of game balls for 100 yen to the upper plate 301 and the lower plate 302 as the number of rented balls. Then, when the payout monitoring time HD elapses, the EXS signal started up and held from the timing H3 is held as LOW, that is, held in the down state, and output from the output terminal of the predetermined output port of the payout control MPU4120a. , EXS is output to the CR unit 6 via the game ball or the like rental device connection terminal board 869 (timing H5).

Since the CR unit 6 pays out the remaining 100 yen worth of game balls to the upper plate 301 and the lower plate 302 as the number of rented balls out of the number of game balls worth 200 yen as the amount of money, FIG. 54 (b). ), The BRQ is transferred from the CR unit 6 to the terminal board for connecting the rental device such as a game ball by the time when the next request confirmation timing HE (in this embodiment, the maximum is set to 268 ms) elapses from the timing H5. It is output to the payout control board 4110 (payout control MPU4120a) via the 869, and the signal is started up and held (timing H6).

Similarly, when the payout control MPU4120a pays out the remaining 100 yen worth of game balls to the upper plate 301 and the lower plate 302 as the number of rented balls, as shown in FIG. 54 (c). The EXS signal that has been started up and held is output from the output terminal of the predetermined output port of the payout control MPU4120a by holding the logic as LOW, that is, in the down state, and as EXS, the game ball rental device connection terminal. It is output to the CR unit 6 via the plate 869 (timing H7).

As shown in FIG. 54 (a), the CR unit 6 stands up from the timing H1 until the CR unit lending completion monitoring time HF (in this embodiment, the maximum is set to 268 ms) elapses from the timing H7. The raised and held BRDY is output from the CR unit 6 to the payout control board 4110 (payout control MPU4120a) via the game ball or the like lending device connection terminal board 869, and the signal is lowered and held (timing H8).

The above-mentioned lending request monitoring time HA, BRQ request approval ACK monitoring time HB, lending instruction monitoring time HC, payout monitoring time HD, next request confirmation timing HE, and CR unit lending completion monitoring time HF are the payout control shown in FIG. 40. The time is measured by the timer update process in step S552 in the process when the power is turned on (main process of the payout control unit).

The payout control MPU4120a is not communicating with the CR unit 6 when the ball is out, the ball is squeezed, a counting switch error, a retry error, a full tank, or the like occurs (the logic of BRDY from the CR unit 6). (When is LOW, that is, when it is held down), as shown in FIG. 54 (d), the PRDY signal which is started up and held from the timing H1 is changed to the LOW state, that is, the state where the logic is lowered. It is held and output from the output terminal of the predetermined output port of the payout control MPU4120a, and is output as PRDY to the CR unit 6 via the game ball or the like rental device connection terminal board 869 (timing H9). On the other hand, when communicating with the CR unit 6 (when the logic of BRDY from the CR unit 6 is HI, that is, when it stands up and is held), although not shown, the logic state of the EXS signal is maintained and dispensed. It outputs from the output terminal of the predetermined output port of the control MPU 4120a, and outputs as EXS to the CR unit 6 via the game ball or the like rental device connection terminal board 869. "Maintaining the logic state of the EXS signal" means that when the logic of the EXS signal is LOW (the EXS signal is held down), the logic LOW is maintained, and the logic of the EXS signal is HI (maintaining the logic state of the EXS signal). The logic HI is to be maintained when the EXS signal is up and held).

In this way, the CR unit 6 exchanges various signals with the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110, and the payout control MPU 4120a uses the number of game balls for 200 yen as the amount of money and 100 as the amount of money. By performing the payout operation of 25 balls for a yen twice, the game balls having a loan number of 50 balls are paid out to the upper plate 301 and the lower plate 302. A clerk in the hall or the like operates a setting unit (not shown) provided on the front side of the CR unit 6, and for example, the number of game balls for 100 yen as the amount of money is used as the number of rented balls such as the upper plate 301. When it is set to pay out to the lower plate 302, the payout control MPU4120a performs a payout operation of 25 balls for 100 yen as the amount of money once, and the number of game balls for 500 yen as the amount of money is used as the number of loaned balls. When it is set to pay out to the upper plate 301 or the lower plate 302, the payout control MPU4120a performs the payout operation of 25 balls for 100 yen as the amount of money five times, and the number of game balls for 1000 yen as the amount of money is calculated. When the number of rented balls is set to be paid out to the upper plate 301 or the lower plate 302, the payout control MPU4120a will perform the payout operation of 25 balls for 100 yen as the amount of money 10 times.

[14-12-2. Input signal confirmation processing from CR unit]
In the payout control MPU4120a of the payout control unit 4120 in the payout control board 4110, the CR unit 6 passes through the BRQ and the CR unit 6 via the game ball or the like lending device connection terminal board 869 even after the above-mentioned lending request monitoring time HA has elapsed. Even if the signal is output to the payout control board 4110 and the signal is not started, or even if the above-mentioned rental instruction monitoring time HC has elapsed, the CR unit 6 connects the BRDY to the game ball rental device from the CR unit 6. Even if the signal is output to the payout control board 4110 via the terminal board 869 and the signal is not shut down, or even if the above-mentioned next request confirmation timing HE has elapsed, the CR unit 6 plays the BRQ from the CR unit 6. Even if the signal is output to the payout control board 4110 via the ball rental device connection terminal board 869 and the signal is not started, or even if the above-mentioned CR unit rental completion monitoring time HF has elapsed, the CR unit 6 is BRDY. Is output from the CR unit 6 to the payout control board 4110 via the game ball rental device connection terminal board 869, and when the signal is not shut down, the BRQ and the BRQ and the XS are used as described above. Check whether BRDY is normal or not. Specifically, as shown in FIGS. 54 (e) and 54 (f), when the payout control MPU4120a determines that the BRQ and BRDY are not normal (timing J0), the timing J0 is followed by a predetermined period JA (in the present embodiment). , 200 ms ± 1 ms), the logic of the PRDY signal is set to LOW, that is, it is kept in the down state and output from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120. Then, as PRDY, it is output to the CR unit 6 via the game ball rental device connection terminal board 869, and the logic of the EXS signal is set as LOW, that is, the predetermined output port of the payout control MPU4120a while holding the down state. It is output from the output terminal of the above, and is output to the CR unit 6 as EXS via the game ball or the like rental device connection terminal board 869 (timing J1).

Subsequently, the payout control MPU4120a uses the logic of the PRDY signal, which is held down from the timing J1 after the lapse of JB (set to 200 ms ± 1 ms in this embodiment) from the timing J1 for a predetermined period, as HI. That is, it is held in the started-up state and output from the output terminal of the predetermined output port of the payout control MPU4120a, and is output as PRDY to the CR unit 6 via the game ball rental device connection terminal board 869 (timing J2). ).

Subsequently, the payout control MPU4120a uses the PRDY signal that is started up and held from the timing J2 after the lapse of JC (set to 100 ms ± 1 ms in this embodiment) for a predetermined period from the timing J2, and its logic is LOW. That is, it is held in the down state and output from the output terminal of the predetermined output port of the payout control MPU4120a, and is output as PRDY to the CR unit 6 via the game ball rental device connection terminal board 869 (timing J3). ).

Subsequently, the payout control MPU4120a uses the logic of the PRDY signal, which is held down from the timing J3 after the lapse of JD (set to 100 ms ± 1 ms in this embodiment) for a predetermined period from the timing J3, as HI. That is, it is held in the started-up state and output from the output terminal of the predetermined output port of the payout control MPU4120a, and is output as PRDY to the CR unit 6 via the game ball rental device connection terminal board 869 (timing J4). ).

Subsequently, the payout control MPU4120a uses the PRDY signal that is started up and held from the timing J4 after the lapse of JE (set to 100 ms ± 1 ms in this embodiment) for a predetermined period from the timing J4, and its logic is LOW. That is, it is held in the down state and output from the output terminal of the predetermined output port of the payout control MPU4120a, and is output as PRDY to the CR unit 6 via the game ball rental device connection terminal board 869 (timing J5). ).

Subsequently, the payout control MPU4120a uses the logic of the PRDY signal, which is held down from the timing J5 after the lapse of JF (set to 10000 ms ± 1 ms in this embodiment) for a predetermined period from the timing J5, as HI. That is, it is held in the started-up state and output from the output terminal of the predetermined output port of the payout control MPU4120a, and is output as PRDY to the CR unit 6 via the game ball rental device connection terminal board 869 (timing J6). ).

The predetermined period JA to the predetermined period JF described above are timed by the timer update process of step S552 in the payout control unit power-on time process (payout control unit main process) shown in FIG. 40.

[15. Various control processes for peripheral control boards]
Next, various processes of the peripheral control board 4140 for receiving various commands from the main control board 4100 (main control MPU 4100a) shown in FIG. 11 will be described with reference to FIGS. 55 to 59. FIG. 55 is a flowchart showing an example of peripheral control unit power-on processing, FIG. 56 is a flowchart showing an example of peripheral control unit V blank interrupt processing, and FIG. 57 shows an example of peripheral control unit 1ms timer interrupt processing. FIG. 58 is a flowchart showing an example of peripheral control unit command reception interrupt processing, and FIG. 59 is a flowchart showing an example of peripheral control unit power failure warning signal interrupt processing.

As shown in FIG. 14, the peripheral control board 4140 is composed of a peripheral control unit 4150, a liquid crystal display, and a sound control unit 4160, and here, various control processes of the peripheral control unit 4150 will be described. First, the peripheral control unit power-on processing will be described, and then the peripheral control unit V blank interrupt processing, the peripheral control unit 1ms timer interrupt processing, the peripheral control unit command reception interrupt processing, and the peripheral control unit power failure warning signal interrupt processing will be described. .. In the present embodiment, the peripheral control unit power failure warning signal interrupt processing is set to the highest priority as the interrupt processing, followed by the peripheral control unit 1ms timer interrupt processing, the peripheral control unit command reception interrupt processing, and the peripheral control unit. It is set in the order of V blank interrupt processing.

[15-1. Various control processes of the peripheral control unit]
[15-1-1. Peripheral control unit power-on processing]
First, the peripheral control unit power-on processing will be described with reference to FIG. 55. When the power is turned on to the pachinko gaming machine 1, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 14 performs a power-on processing of the peripheral control unit as shown in FIG. 55. When the peripheral control unit power-on processing is started, the effect control program performs initial setting processing under the control of the peripheral control MPU4150a (step S1000). In this initial setting process, the effect control program performs a process of initializing the peripheral control MPU4150a itself, a process of determining hot start / cold start, a process of setting a wait timer after reset, and the like. The peripheral control MPU4150a first performs a process of initializing itself, and the time required for the process of initializing the peripheral control MPU4150a is on the order of microseconds (μs), and the peripheral control MPU4150a is initialized in an extremely short time. be able to. As a result, the peripheral control MPU 4150a is output from the main control board 4100 in, for example, the peripheral control unit command reception interrupt processing described later by setting the interrupt enable, as shown in FIGS. 32 and 33. , It becomes possible to receive various commands such as a command related to the control of the game effect and a command related to the state of the pachinko gaming machine 1.

In the hot start / cold start determination process, the peripheral control RAM 4150c shown in FIG. 15 is backed up by Bank1 (1fr) and Bank2 (1fr) in the backup first area 4150cc. ), And the effect backup information (1 ms), which is the content backed up in Bank 1 (1 ms) and Bank 2 (1 ms), are compared, and Bank 3 (1 fr) and Bank 4 (1 fr) in the backup second area 4150 cc. The production backup information (1fr), which is the content backed up in, is compared, and the production backup information (1ms), which is the content backed up in Bank3 (1ms) and Bank4 (1ms), are compared. When they match, the effect backup information (1fr), which is the content stored in Bank1 (1fr) with respect to Bank0 (1fr), which is the normally used storage area of the peripheral control RAM 4150c shown in FIG. When the production backup information (1 ms), which is the content stored in Bank 1 (1 ms) for Bank 0 (1 ms), is copied back and used as a hot start, but the compared contents do not match (that is,). , When there is a mismatch), the value 0 is forcibly written to each of the normally used storage areas of the peripheral control RAM 4150c, Bank0 (1fr) and Bank0 (1ms), to make a cold start.

Further, in the hot start / cold start determination process, the peripheral control SRAM 4150d shown in FIG. 15 is also backed up by Bank1 (SRAM) and Bank2 (SRAM) in the backup first area 4150db. (SRAM) are compared, and the effect backup information (SRAM), which is the content backed up in Bank 3 (SRAM) and Bank 4 (SRAM), in the backup second area 4150 dc is compared. When the compared contents match, the effect backup information (SRAM) which is the contents stored in the Bank0 (SRAM) with respect to the normally used storage area of the peripheral control SRAM 4150d shown in FIG. 15 (SRAM). ) Is copied back to make a hot start, while when the compared contents do not match (that is, when they do not match), the value is set with respect to Bank0 (SRAM), which is a normally used storage area of the peripheral control SRAM 4150d. Forcibly write 0 to make it a cold start. Following such a hot start or cold start, the value 0 is forcibly written to the backup unmanaged work area 4150cf of the peripheral control RAM 4150c shown in FIG. 15 to clear zero. After performing this initialization setting process, the peripheral control MPU4150a outputs a clear signal to the peripheral control built-in WDT4150af shown in FIG. 15 and the peripheral control external WDT4150e shown in FIG. 14, and resets to the peripheral control MPU4150a. I try not to take it.

Following step S1000, the effect control program performs the current time information acquisition process (step S1002). In this current time information acquisition process, the calendar information for specifying the date and the time information for specifying the hour, minute, and second are acquired from the RTC built-in RAM4165aa of the RTC41654a of the RTC control unit 4165 shown in FIG. In the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in the above, the current calendar information is set in the calendar information storage unit, and the current time information is set in the time information storage unit. Further, in the current time information acquisition process, the brightness setting process of the liquid crystal display device is also performed. In the brightness setting process of this liquid crystal display device, the peripheral control MPU4150a acquires the brightness setting information from the RTC built-in RAM4165aa of the RTC control unit 4165 so that the brightness of the LED is included in the acquired brightness setting information. The processing of adjusting the brightness of the backlight of the side liquid crystal display device 1900 to turn it on is performed. As described above, the brightness setting information includes brightness adjustment information for adjusting the range in which the brightness of the LED, which is the backlight of the liquid crystal display device 1900 on the game board side, ranges from 100% to 70% in 5% increments. The brightness of the LED, which is the backlight of the liquid crystal display device 1900 on the game board side, which is set, is included.

In the brightness setting process of the liquid crystal display device, specifically, the brightness of the LED included in the brightness setting information stored in the RTC built-in RAM4165aa of the RTC control unit 4165 is 75%, and the backlight of the liquid crystal display device 1900 on the game board side. Is turned on by adjusting the brightness of the backlight of the liquid crystal display device 1900 on the game board side based on the brightness adjustment information included in the brightness setting information, and the brightness stored in the RTC built-in RAM4165aa of the RTC control unit 4165. When the brightness of the LED included in the setting information is 80% and the backlight of the liquid crystal display device 1900 on the game board side is turned on, the backlight of the liquid crystal display device 1900 on the game board side is based on the brightness adjustment information included in the brightness setting information. It lights up by adjusting the brightness. In the brightness setting process of this liquid crystal display device, the same correction as the brightness correction program for correcting the brightness of the liquid crystal display device 1900 on the game board side according to the usage time of the liquid crystal display device 1900 on the game board side is performed. It is not done at all. This is because a correction program similar to the brightness correction program is incorporated in the brightness setting process of the liquid crystal display device, so that the brightness of the LED is corrected toward 100% each time the brightness setting process of the liquid crystal display device is executed. This is to prevent it from being done.

In the present embodiment, the peripheral control MPU4150a acquires the calendar information and the time information from the RTC built-in RAM4165aa of the RTC4165a only once when the power is turned on. Further, the peripheral control MPU4150a outputs a clear signal to the peripheral control built-in WDT4150af and the peripheral control external WDT4150e after the current time information acquisition process is performed so that the peripheral control MPU4150a is not reset.

Following step S1002, the effect control program sets the value 0 in the V blank signal detection flag VB-FLG (step S1006). This V blank signal detection flag VB-FLG is a flag for determining whether or not to execute the peripheral control unit steady processing described later, and has a value of 1 when the peripheral control unit steady processing is executed, and the peripheral control unit steady processing. Is set to a value of 0 when is not executed. The V-blank signal detection flag VB-FLG is executed when a V-blank signal indicating that screen data from the peripheral control MPU4150a can be accepted is input from the sound source built-in VDP4160a, which will be described later. The value 1 is set in the part V blank signal interrupt processing. In this step S1006, the V blank signal detection flag VB-FLG is initialized once by setting the value 0 to the V blank signal detection flag VB-FLG. Further, the peripheral control MPU4150a outputs a clear signal to the peripheral control built-in WDT4150af and the peripheral control external WDT4150e after setting the value 0 to the V blank signal detection flag VB-FLG so that the peripheral control MPU4150a is not reset. There is.

Following step S1006, the effect control program determines whether or not the V blank signal detection flag VB-FLG has a value of 1 (step S1008). When the V blank signal detection flag VB-FLG is not a value 1 (value is 0), the process returns to step S1008 again to repeatedly determine whether or not the V blank signal detection flag VB-FLG has a value 1. By repeating such a determination, it becomes a state of waiting until the peripheral control unit steady processing is executed. Further, the peripheral control MPU4150a outputs a clear signal to the peripheral control built-in WDT4150af and the peripheral control external WDT4150e after determining whether or not the V blank signal detection flag VB-FLG has a value of 1, and resets to the peripheral control MPU4150a. I try not to take it.

When the V blank signal detection flag VB-FLG has a value of 1 in step S1008, that is, when the peripheral control unit steady processing is executed, the value 1 is first set in the steady processing flag SP-FLG (step S1009). The steady-state processing flag SP-FLG is set to a value of 1 when the peripheral control unit steady-state processing is being executed, and to a value of 0 when the peripheral control unit steady-state processing is completed.

Following step S1009, the effect control program performs 1 ms interrupt timer activation processing (step S1010). In this 1 ms interrupt timer activation process, the 1 ms interrupt timer for executing the peripheral control unit 1 ms timer interrupt process, which will be described later, is activated, and the number of times the 1 ms interrupt timer is activated and the peripheral control unit 1 ms timer interrupt process is executed. The 1ms timer interrupt execution count STN for counting is set to a value of 1, and the 1ms timer interrupt execution count STN is also initialized. The 1ms timer interrupt execution count STN is updated by the peripheral control unit 1ms timer interrupt processing.

Following step S1010, the effect control program performs lamp data output processing (step S1012). In this lamp data output process, the effect control program performs DMA serial continuous transmission to the lamp drive board 4170 shown in FIG. Here, the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. 15 is used to continuously transmit the serial I / O port for the lamp drive board. When the continuous transmission of the serial I / O port for the lamp drive board is started, it is shown in FIG. 8 in the lamp drive board side transmission data storage area 4150caa of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. The game board side light emission data SL-DAT for outputting lighting signals, blinking signals, or gradation lighting signals to a plurality of LEDs of various decorative boards provided on the game board 4 is created by the lamp data creation process described later. It is in the set state.

The peripheral control CPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 15 specifies the transmission of the serial I / O port for the lamp drive board as the requirement factor of the peripheral control DMA controller 4150ac, and the transmission data storage area 4150caa on the lamp drive board side. The first byte of the game board side light emission data SL-DAT stored in the start address is sent to the serial I / O port for the lamp drive board via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer to and write to the transmit buffer register of. As a result, the serial I / O port for the lamp drive board transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the game board side emission clock signal SL-CLK to synchronize with 1 byte of the transmission shift register. Data is started to be transmitted bit by bit.

The peripheral control DMA controller 4150ac triggers each time a transmission interrupt request for the serial I / O port for the lamp drive board is generated (in the present embodiment, the transmission buffer register for the serial I / O port for the lamp drive board is used). The written 1-byte data is transferred to the transmission shift register, and the transmission buffer register runs out of 1-byte data and becomes empty.) The peripheral control CPU core 4150aa is using the bus. If not, the remaining game board side light emission data SL-DAT stored in the lamp drive board side transmission data storage area 4150caa is sent byte by byte via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. By transferring and writing to the transmission buffer register of the serial I / O port for the lamp drive board, the serial I / O port for the lamp drive board transfers the data of the written transmission buffer register to the transmission shift register and plays a game. In synchronization with the board-side emission clock signal SL-CLK, 1-byte data of the transmission shift register is started to be transmitted bit by bit, and continuous transmission is performed by the serial I / O port for the lamp drive board.

Further, in the lamp data output processing, the effect control program performs the DMA serial continuous transmission processing to the frame decoration drive amplifier board 194 shown in FIG. Here, too, the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a is used to continuously transmit the serial I / O port for the frame decoration drive amplifier board LED. When the continuous transmission of the serial I / O port for the frame decoration drive amplifier board LED is started, the transmission data storage area for the frame decoration drive amplifier board side LED of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. Door-side light emission data STL-DAT for outputting lighting signals, blinking signals or gradation lighting signals to a plurality of LEDs of various decorative boards provided on the door frame 5 is created on the 4150cab by the lamp data creation process described later. It is in the set state.

The peripheral control CPU core 4150aa of the peripheral control MPU 4150a specifies the transmission of the serial I / O port for the frame decoration drive amplifier board LED as the requirement factor of the peripheral control DMA controller 4150ac, and the transmission data storage area for the frame decoration drive amplifier board side LED. The first byte of the door-side emission data STL-DAT stored at the start address of the 4150cab is serialized for the frame decoration drive amplifier board LED via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer to the transmit buffer register of the I / O port and write. As a result, the serial I / O port for the frame decoration drive amplifier board LED transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the door-side emission clock signal STL-CLK of the transmission shift register. Transmission of 1 byte of data is started bit by bit.

The peripheral control DMA controller 4150ac triggers each time a transmission interrupt request for the serial I / O port for the frame decoration drive amplifier board LED is generated (in this embodiment, the serial I / O for the frame decoration drive amplifier board LED). The 1-byte data written in the transmit buffer register of the port is transferred to the transmit shift register, and the 1-byte data is exhausted in the transmit buffer register and becomes empty.), Peripheral control CPU core 4150aa When the bus is not used, the remaining door-side emission data STL-DAT stored in the transmission data storage area 4150cab for the frame decoration drive amplifier board side LED is stored in 1 byte each, external bus 4150h, peripheral control bus controller 4150ad. The serial I / O port for the frame decoration drive amplifier board LED is written by transferring the data to the transmission buffer register of the frame decoration drive amplifier board LED serial I / O port via the peripheral bus 4150ai. The data of the transmission buffer register is transferred to the transmission shift register, and the 1-byte data of the transmission shift register is started to be transmitted bit by bit in synchronization with the door-side emission clock signal STL-CLK, for the frame decoration drive amplifier board LED. Continuous transmission is performed by the serial I / O port.

Following step S1012, the effect control program performs the operation unit monitoring process (step S1014). In this operation unit monitoring process, in the operation unit information acquisition process in the peripheral control unit 1 ms timer interrupt process described later, the dial operation unit 401 is based on the detection signals from various detection switches provided in the operation unit 400 shown in FIG. Rotation (rotation direction) of the dial operation unit 401 created based on various information (for example, detection signals from various detection switches provided in the operation unit 400) acquired such as rotation (rotation direction) and operation of the pressing operation unit 405. ) History information, operation history information of the pressing operation unit 405, etc.) Based on the operation unit information acquisition storage area 4150kai of the peripheral control RAM 4150c shown in FIG. 15, the rotation direction and pressing operation of the dial operation unit 401. The presence or absence of operation of the unit 405 is monitored, and it is appropriately determined whether or not the rotation direction of the dial operation unit 401 and the operation state of the pressing operation unit 405 are reflected in the game effect.

Following step S1014, the effect control program performs display data output processing (step S1016). In this display data output process, the drawing data for one screen (one frame) generated on the built-in VRAM of the sound source built-in VDP4160a in the display data creation process described later is transferred from the channels CH1 and 2 shown in FIG. 16 by the sound source built-in VDP4160a. It is output to the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the precision plate side. As a result, various screens are drawn on the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the upper plate side. In the display data output processing, when drawing exceeding the drawing capacity of the VDP4160a with a built-in sound source is performed, the generated drawing data for one screen (one frame) is displayed on the liquid crystal display device 1900 on the game board side and the liquid crystal display on the precision plate side. The output to the display device 470 is canceled. As a result, it is possible to prevent a delay in the processing time, but although so-called frame dropping occurs, the various decorative boards provided on the game board 4 shown in FIG. 8 by the lamp data output processing in step S1012. A speaker housed in a speaker box 820 provided in the main body frame 3 shown in FIG. 5 by a plurality of LEDs and a plurality of LEDs of various decorative boards provided on the door frame 5 and a sound data output process described later. From the speaker 130 provided on the door frame 5 shown in FIG. 2, it is possible to prioritize the synchronization with the production by music, sound effects, etc. according to various productions.

Following step S1016, the effect control program performs sound data output processing (step S1018). In this sound data output process, the effect control program outputs sound data such as music and sound effects set in the sound source built-in VDP4160a in the sound data creation process described later to the audio data transmission IC 4160c as serialized audio data. In addition to music and sound effects, sound data of notification sounds and notification sounds are output to the audio data transmission IC 4160c as serialized audio data. When the serialized audio data from the sound source built-in VDP4160a is input to the audio data transmission IC 4160c, the right side audio data is converted into a positive signal and a negative signal as differential serial data toward the frame decoration drive amplifier board 194. At the same time as transmitting, the left side audio data is transmitted toward the frame decoration drive amplifier board 194 as differential serial data having a positive signal and a negative signal. As a result, music, sound effects, and the like that match various effects are reproduced in stereo from the speakers housed in the speaker box 820 provided in the main body frame 3 and the speakers 130 provided in the door frame 5, as well as notification sounds and notification sounds. Is also played back in stereo.

Following step S1018, the effect control program performs a scheduler update process (step S1020). In this scheduler update process, the effect control program updates various schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. For example, in the scheduler update process, among the screen data arranged in time series constituting the screen generation schedule data set in the schedule data storage area 4150 cage, the screen data from the first screen data is transferred to the sound source built-in VDP4160a. Update the pointer to indicate whether to output.

Further, in the scheduler update process, among the light emission data arranged in the time series constituting the light emission mode generation schedule data set in the schedule data storage area 4150 cage, the light emission data of which number from the first light emission data is emitted from various LEDs. Update the pointer to indicate whether it is an aspect.

Further, in the scheduler update process, sound data such as music and sound effects, and sound data of notification sound and notification sound arranged in a time series constituting the schedule data for sound generation set in the schedule data storage area 4150 cage are instructed. The pointer is updated in order to indicate which sound command data is output to the sound source built-in VDP4160a from the first sound command data among the sound command data.

Further, in the scheduler update process, from the first drive data among the drive data of the electric drive sources such as motors and solenoids arranged in time series constituting the electric drive source schedule data set in the schedule data storage area 4150 cage. Update the pointer to indicate which drive data is to be output. Electrical drive source The drive data of an electric drive source such as a motor or solenoid that constitutes the schedule data is the peripheral control unit 1ms timer interrupt that is repeatedly executed every time a 1ms timer interrupt occurs, which will be described later. Updated with motor and solenoid drive processing in the processing. In the motor and solenoid drive processing that is repeatedly executed each time this 1 ms timer interrupt occurs, the electric drive source such as the motor or solenoid is driven according to the drive data indicated by the pointer, and the next drive specified in time series is performed. It updates the pointer to the data and updates the pointer each time it executes its own processing. That is, since the drive data instructed by the pointer updated in the motor and solenoid drive processing is forcibly updated in the scheduler update processing, the pointer is originally instructed in the motor and solenoid drive processing for some reason. Even if another drive data is instructed from the drive data that should be used, the drive data that should be originally instructed is forcibly updated in the scheduler update process.

Following step S1020, the effect control program performs reception command analysis processing (step S1022). In this reception command analysis process, the effect control program uses various data transmitted from the touch panel control board 450 shown in FIG. 17 (for example, the sensing position of the touch panel 480 is set to the contact state detection value at the sensing position in the entire area of the touch panel 480). (Sensing data to which (X coordinate, Y coordinate) are linked) is received in the touch panel processing described later, and various received data are analyzed, and various commands transmitted from the main control board 4100 are transmitted to the peripherals described later. Control unit Command reception Analyzes various commands received in command processing (command receiving means) (command analysis means). The effect control program peripherally controls screen generation schedule data, light emission mode generation schedule data, sound generation schedule data, electrical drive source schedule data, etc., based on various data transmitted from the touch panel control board 450. It is extracted from the peripheral control ROM 4150b of the unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and set in the schedule data storage area of the peripheral control RAM 4150c at 4150 ce. Further, in the effect control program, the command from the main control board 4100 received in the peripheral control unit command interrupt process is, for example, a start port winning command for instructing the start of the start port winning effect, and the number of reserved symbols. Normal symbol memory command for identifying (0 to 4), symbol synchronization effect start command for instructing the start of symbol synchronization effect, symbol memory command output when the number of start hold changes, large winning opening 2103 The large winning opening 1 count display command (large winning opening count command) output each time the game ball is accepted, or the frame state 1 command (second error occurrence command,) indicating the content of full tank shown in FIG. It analyzes whether or not it is a full tank error occurrence command (command analysis means), and recognizes which game state it is currently in. Further, in this effect control program, after a predetermined time has elapsed from the time when the power is turned on, the commands received by the peripheral control unit command reception interrupt processing are the main body frame open command, the main body frame close command, the door open command, or the door frame close. Analyze whether it is a command or not. Various commands from the main control board 4100 are received by the peripheral control unit command reception interrupt processing and stored in the reception command storage area 4150cc of the peripheral control RAM 4150c shown in FIG. 15, and are stored in the reception command storage area 4150cc in the reception command analysis processing. , The effect control program analyzes various commands stored in the received command storage area 4150cc. The various commands are classified into the various commands shown in FIG. 32, which are classified as related to the special drawing 1 tuning effect, the various commands classified as related to the special drawing 2 tuning effect, the various commands classified as related to the jackpot, and the power-on. Various commands to be executed, various commands classified to be related to the normal electric function production, various commands classified to be related to the normal electric service production, various commands classified to the notification display shown in FIG. 33, and the above-mentioned door frame opening command. , Door frame closing command, main body frame opening command, main body frame closing command, error cancellation navigation command (corresponding to the second error canceling command), frame status 1 command (corresponding to the second error occurrence command), etc. There are various commands that are classified, various commands that are classified as test-related, and various commands that are classified as others.

Here, in the effect control program, the command analyzed in the received command analysis process (step S1022) is a frame state 1 command (second error occurrence command) or the large winning opening 1 count display command (large winning opening count command). ), A suggestion display for urging the pressing operation unit 405 (operation unit) to be pressed as shown in FIG. 60 by using the upper plate side liquid crystal display device 470 (second display device). As an object, based on the suggestion display object image data, for example, the display of an arrow-shaped icon in a display mode in which the words "press a button to call a clerk" is superimposed is performed (operation arousing means). Subsequently, the effect control program, as a call control function, starts displaying this arrow-shaped icon, and then controls a call operation different from the latest effect operation to the outside (call), triggered by the operation of the pressing operation unit 405. Control means), the mode is such that it is easy to attract the attention of the hall clerk.

In this way, the player who tried to call the hall clerk does not have to stretch his arm or body to reach the data counter, which was often located above the pachinko machine 1. Since it is sufficient to press the pressing operation unit 405 provided on the door frame 5, which is located closer to the player, it is possible to suppress the physical inconvenience and physical burden of calling the hall clerk. Therefore, even if the pachinko machine 1 is played for a long time, it is less likely to receive unnecessary stress. Therefore, such a configuration can contribute to the improvement of the operating rate.

By the way, the work by the hall clerk who appeared at the player in response to the above-mentioned call should be completed as soon as possible, considering the psychological state of the player who wants to restart the game as soon as possible. You should have a desire to cooperate with the hall clerk as much as possible. On the other hand, in this pachinko machine 1, the effect control program analyzes the error content based on the frame state 1 command (second error generation command) received from the main control board 4100 (error content analysis means). Further, the production control program is based on an error content management table (not shown) that manages whether or not the player should leave the seat according to each error content, and the hall clerk performs complicated coping work (for example) according to the error content. When it is determined that opening and closing of the main body frame 3 or the door frame 5 is necessary, as described above, only the standard message "Please press the button to call the clerk" is superimposed on the above arrow-shaped icon. On the other hand, if it is determined that complicated handling work by the hall clerk is not necessary according to the error content, in addition to the above standard message, an additional message "Please leave your seat" is added to the above arrow icon. The display mode is superimposed. In this way, the player who encounters such an error will act immediately without wondering whether to leave the seat and wait for the hall clerk due to the presence of the additional message mentioned above. It is possible to determine if it should be done, and if necessary, give the hall clerk ample work space to complete subsequent work.

Further, when the effect control program detects the operation signal output in response to the operation of the pressing operation unit 405, it determines whether or not the arrow-shaped icon is displayed, and when the arrow-shaped icon is displayed, the effect control program determines whether or not the arrow-shaped icon is displayed. Considers that the operation signal is operated by the pressing operation unit 405 in response to the appearance of the arrow-shaped icon. On the other hand, when this effect control program detects the operation signal, if the arrow-shaped icon is not displayed, the operation signal is not the appearance of the arrow-shaped icon but other factors (operation is prompted for the effect). It is considered that the pressing operation unit 405 has been operated in response to the above.

Here, when it is determined that the effect control program has shifted from the normal gaming state to the jackpot gaming state (special gaming state) based on the command received from the main control board 4100, the suggestion read from the liquid crystal display and the sound control ROM 4160b thereafter. Based on the display image data, the arrow-shaped icon on the liquid crystal display device 470 (second display device) on the upper plate side, for example, "Please press the pressing operation unit to call the clerk when the dollar box is about to overflow." It may be a display mode superimposed on the above. In this way, when the player is about to overflow the game ball discharged through the lower plate 302 after being paid out in the jackpot game state, the player is likely to overflow from the storage box (corresponding to the above dollar box). Since it is not necessary to extend the arm or body to operate the so-called data counter call button by hand, it is possible to concentrate more on the game and suppress the decrease in the operating rate.

By the way, in order to call the hall clerk in search of a new storage box in the big hit game state, the display mode of the liquid crystal display device 470 on the upper plate side urges the player to operate the pressing operation unit 405. At first glance, the control program seems to be difficult to distinguish the operation signal from the case where the player is actually urged to operate the pressing operation unit 405 in the big hit game state itself. That is, in the effect control program, when the operation signal is detected, the player operates the pressing operation unit 405 in search of a new storage box, or the player operates the pressing operation in response to the effect in the jackpot gaming state. It seems that it is not possible to distinguish whether the unit 405 was operated.

However, the effect control program uses the concept of time sharing to actually urge the player to operate the pressing operation unit 405 in the big hit game state (special game state) and execute the call operation by the call control function. The participation operationable time zone in which is restricted and the clerk callable time zone in which the hall clerk can be called by the operation of the pressing operation unit 405 and the call operation by the call control function is allowed to be executed are distinguished. (Time sharing control means). Specifically, the effect control program was found to be a frame state 1 command (second error occurrence command) indicating that the command analyzed in the received command analysis process (step S1022) is full. In this case, it is regarded as the above-mentioned clerk callable time zone, while the other time zone is the above-mentioned participation operation possible time zone. This effect control program is shown in FIG. 61 by using the upper plate side liquid crystal display device 470 (second display device) that displays that the jackpot is in progress when it is considered that the store clerk is in the callable time zone. In addition to controlling the display of the phrase "please pull out the ball" at the top of the screen, control the display of the arrow-shaped icon in the display mode in which the phrase "please press the button to call the clerk" is superimposed. ing. In this way, when the effect control program detects the operation signal in the jackpot game state, and the detection timing is within the participation operation possible time zone, the pressing operation unit responds to the effect of the jackpot game state. While it is determined that the 405 has been operated, if the detection timing is within the above-mentioned clerk callable time zone, it is determined that the pressing operation unit 405 has been operated to call the hall clerk, and the distinction is made. In the above-mentioned effect control program, a touch panel is mounted on the surface of the upper plate side liquid crystal display device 470 to prompt the operation of the button displayed on the upper plate side liquid crystal display device 470 instead of the pressing operation unit 405. good. By the way, the effect control program indicates that the command analyzed in the received command analysis process (step S1022) is the large winning opening 1 count display command (large winning opening count command) and is full. When it is found that the command is the frame state 1 command (second error occurrence command), the game ball is likely to not fit in the storage box at the time of a big hit, and the above-mentioned is used as an opportunity for the player to call the hall clerk. The screen shown in FIG. 61 is displayed.

By the way, in this effect control program, when it is found that the command analyzed in the received command analysis process (step S1022) is a door opening command or a main body frame opening command (that is, the door frame 5 is relative to the main body frame 3). When the main body frame 3 is opened with respect to the outer frame 2), the upper plate side liquid crystal display device 470 (second display device) is made to display in the following display mode. That is, the effect control program gives an instruction to display the service mode screen (see FIG. 62) for work by the hall clerk on the upper plate side liquid crystal display device 470, and then the dial operation unit 401 (see FIG. 62) by the player. When it is detected that "meal break setting" is selected by the pressing operation of the pressing operation unit 405 (operation unit) after the rotation operation of the operation unit), the operation for setting the operation stop time that does not allow the above-mentioned operation is performed. An instruction is given to display the break timer setting screen (see FIG. 63) corresponding to the setting screen (operation setting screen display control means). By using the door opening command or the main body frame opening command, which can be generated only by the operation of the hall clerk, as an opportunity, it is difficult for the player to display such a break timer setting screen. Can be done.

Further, the effect control program inputs the time information (for example, 60 minutes) input to the break timer setting screen (operation setting screen) according to the operation of the hall clerk using the dial operation unit 401 (operation unit) and the pressure operation unit 405. Set as the operation stop time (operation stop time setting means). Further, the effect control program takes the opportunity of setting the operation stop time on the break timer setting screen (operation setting screen) to set the operation stop time on the upper plate side liquid crystal display device 470 (second display device). The remaining time of is displayed as shown in FIG. 64 (remaining time display control means). At the same time, the effect control program may set at least a part of the effect operations by the peripheral control board 4140 into a stopped state or a suppressed state (remaining time display control means). It should be noted that this effect control program at least suppresses the display operation of the liquid crystal display device 1900 (first display device) on the game board side by the peripheral control board 4140 over the set operation stop time, for example, a blackout display mode. (First display control suppressing means). By doing so, it is possible to suppress the power consumption of the liquid crystal display device 1900 on the game board side during the operation stop time during which the player does not play the game.

Further, in the effect control program, when the remaining time of the operation stop time becomes a specified state, for example, the count becomes zero, or the command analyzed in the above-mentioned received command analysis process (step S1022) is a door closing command or a main body. When it is found that the command is a frame closing command, the display control of the remaining time of the operation stop time shown in FIG. 64 is terminated, and the stopped state or the suppressed state of some of the above-mentioned effect operations is released (stop state release means). By doing so, by using the door closing command or the main body frame closing command that can be generated only by the operation of the hall clerk as a trigger, it is difficult for the player to perform such a release. Can be done.

By the way, in this effect control program, the remaining time of this operation stop time becomes a count of zero (specified state), and the command analyzed in the above-mentioned received command analysis process (step S1022) is a door closing command or a main body frame. If it is not a close command, for example, the liquid crystal display device 1900 on the game board side is controlled in a specific mode different from the latest effect operation, and a notification operation indicating that the remaining operation stop time has ended is executed (notification operation). Getting started). By doing so, it is possible to immediately and easily inform not only the hall clerk but also the player who is waiting for the pachinko machine 1 to be opened to a third party that the allowable break time has expired. can. Further, when the effect control program finds that the command analyzed in the above-mentioned received command analysis process (step S1022) is a door closing command or a main body frame closing command after the start of such a notification operation (that is, the door). When the frame 5 is closed with respect to the main body frame 3 or when the main body frame 3 is closed with respect to the outer frame 2), the above-mentioned notification operation is stopped (notification operation stop means). By doing so, it is possible to shorten the time during which the pachinko machine 1 cannot be operated based on the player's intention such as a break as much as possible.

In this way, it is necessary to open and close the main body frame 3 or the door frame 5 in order to suspend or restart the operation of the pachinko machine 1, so only the hall clerk who possesses the key necessary for opening and closing such pachinko machines. It is possible to suspend and restart the operation of the machine 1. Moreover, a hall clerk puts the operation of the pachinko machine 1 on hold for a while because he is taking a break, and then receives calls from many players to pay sufficient attention to each pachinko machine 1 and each player. Even if this is not possible, as soon as the downtime of the pachinko machine 1 that has been suspended from operation has elapsed, it becomes publicly easily recognizable by a third party that the low operation time has elapsed. .. For this reason, even if the player does not easily return from the break, the hall clerk can quickly put the pachinko machine 1 into a state in which other players can play, so that the hall can play this pachinko machine. The operating rate of the machine 1 can be increased as much as possible, and the operating rate of each pachinko machine 1 installed in each island facility can be increased as a whole.

By the way, the effect control program is based on the calendar information and the time information stored in the RTC built-in RAM4165aa of the RTC control unit 4165 mounted on the peripheral control board 4140, according to the time zone in which the player takes a break. The unit time that can be changed per operation (hereinafter referred to as "variable unit time") when setting the operation stop time is changed from 5 minutes to the desired unit time (for example, 15 minutes) as shown in FIG. 63. May be. If such a change is possible, the operation stop time can be flexibly set according to the time zone such as the day or the day of the day, so that the weekday night time zone (or weekend) where a high utilization rate is desired can be ensured. ) Keeps the operating rate as high as possible by shortening the variable unit time, and improves the feelings for hall service as a longer variable unit time during the time zone (weekday daytime) when it is originally difficult to expect a high operating rate. As a result, it is possible to prevent the player's motivation to play the game again in the hole from being impaired next time.

On the other hand, in this effect control program, when the command analyzed in the received command analysis process (step S1022) is the error release navigation command (second error occurrence command) as described above, this error release navigation command is used. The error occurrence position information included in is extracted and acquired (error occurrence location identification means).

Following step S1022, the effect control program performs warning processing (step S1024). In this warning process, further, when the command analyzed by the effect control program in the received command analysis process in step S1022 includes various commands classified into the notification display shown in FIG. 33, various commands are included. Peripheral control unit 4150 sets the screen generation schedule data, the light emission mode generation schedule data, the sound generation schedule data, the electrical drive source schedule data, etc., which are set in the abnormality display mode for executing the abnormality notification, to the peripheral control unit 4150. It is extracted from various control data copy areas 4150ce of the peripheral control ROM 4150b or the peripheral control RAM 4150c and set in the schedule data storage area of the peripheral control RAM 4150c in 4150cae. In the warning process, when multiple abnormalities occur at the same time, the abnormality notification is performed from the order of the highest priority registered in advance, and the abnormality is automatically resolved and the remaining abnormality notification is automatically transferred. It is designed to do. This allows multiple anomalies to be monitored simultaneously without losing information that another anomaly has occurred and that one anomaly has occurred after one anomaly has occurred but before the anomaly has been resolved. Can be done.

Further, in this warning process, after a predetermined time has elapsed from the time when the power is turned on, the command analyzed by the effect control program in the received command analysis process (step S1022) described above is classified into the state display shown in FIG. 33. In the case of various commands such as an error cancellation navigation command (second error cancellation command), for example, a liquid crystal display can be obtained by controlling the liquid crystal and the sound control unit 4160 in a mode different from the normal effect mode associated with the effect operation. The device 1900 (effect device), the upper plate side liquid crystal display device 470 (effect device), and the lamp (effect device) are used to visually warn the outside, and the pair of side speakers 130 (effect device) is used to audibly warn the outside. To warn the outside (error notification means). In this way, when a malicious player attempts to input an error release navigation command to the main control board 4100 by operating the operation switch 860a of the payout control board 4110 even though the player is in the gaming state. Since the pachinko machine 1 is configured to give a warning to the outside, fraudulent acts on the main control board 4100 that may affect the progress of the game are suppressed.

When notified to the outside as described above, the effect control program reads the image data on the back surface of the main body frame from the liquid crystal and the sound control ROM 4160b (data storage unit), and the read image on the back surface of the main body frame. Based on the data, the rear image of the main body frame designated by the upper plate side liquid crystal display device 470 (second display device) based on the error occurrence position information included in the frame state 1 command (second error occurrence command). A maintenance screen with the above specific area as a specified display mode is displayed as shown in FIG. 60 (error occurrence position suggestion means).

In the maintenance screen shown in FIG. 60, the error number and the error content are displayed in a horizontally elongated shape at the upper part thereof, and in addition to the arrow-shaped icon described above, for example, "Insufficient payout" is displayed on the left side of the center. The details of the error content are displayed. Furthermore, on this maintenance screen, the back image of the main body frame is displayed in the right half. This image of the back of the main body frame is a schematic view of the pachinko machine 1 as viewed from the back, that is, the arrangement of each part on the back side of the main body frame 3 on which the game board 4 is mounted. The above-mentioned effect control program corresponds to a specific area (corresponding to the area 740Z) on the rear image of the main body frame based on the error occurrence position information included in the frame state 1 command (second error generation command) received from the main control board 4100. ) Is specified, and the specific area 740Z is blinked on the back image of the main body frame (specified display mode).

In this way, the hall clerk who arrives at the player in response to the call of the player opens the main body frame 3 with respect to the outer frame 2 and is attached to the main body frame 3 as in the conventional case. The upper plate side liquid crystal display device 470 (second display device) provided in a part of the door frame 5 without confirming the error content of the error LED display 860c provided on the payout control board 4110 of the board 4. By confirming the area 740Z on the image of the back surface of the main body frame on the maintenance screen, it is possible to immediately grasp which part of the pachinko machine 1 the error has occurred by visually recognizing the blinking mode of the area 740Z. Therefore, according to the configuration of the present embodiment, even in a situation where the pachinko machine 1 is complicated as in recent years, it is possible to prevent the time required for error handling from becoming long, and the pachinko machine 1 having a complicated configuration is suppressed. In this case as well, the hall clerk can complete the error handling as soon as possible, and the player's impatience and dissatisfaction during the error handling can be less likely to occur.

Here, in addition to extinguishing the error occurrence position suggestion image from the upper plate side liquid crystal display device 470 when the effect control program receives the error release navigation command (second error release command), instead. If the main body frame closing command is received before this error release navigation command, this main body frame closing command is regarded as an error cancellation navigation command, and the upper plate side liquid crystal display device is triggered by receiving this main body frame closing command. The main body frame maintenance image is erased from 470 (second display device) (screen return means). By doing so, even if the hall clerk who has completed the error handling forgets to operate the operation switch 860a, the main body frame closing command is regarded as a substitute for the error cancellation navigation command, and not only the error notification is canceled but also the upper plate side. The display on the maintenance screen of the liquid crystal display device 470 can be turned off. By doing so, even if the hall clerk forgets to turn off the maintenance screen of the upper plate side liquid crystal display device 470 after dealing with the error, it is automatically turned off by closing the main body frame 3 with respect to the outer frame 2, and then the player feels uncomfortable. You can continue the game without feeling.

Next, following step S1024 described above, the effect control program performs RCT acquisition information update processing (step S1026). In this RTC acquisition information update process, the effect control program acquires the current time information in the current time information acquisition process in step S1002 and stores it in the calendar information storage unit set in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. The stored calendar information and the time information stored in the time information storage unit are updated. By this RCT acquisition information update process, the hour, minute, and second, which is the time information stored in the time information storage unit, is updated, and the year and month, which is the calendar information stored in the calendar information storage unit based on the updated time information. The day is updated.

Following step S1026, the effect control program performs lamp data creation processing (step S1028). In this lamp data creation process, the effect control program updates the pointer in the scheduler update process of step S1020, and the pointer indicates among the light emission data arranged in time series constituting the schedule data for generating the light emission mode. Based on the light emission data to be output, the game board side light emission data SL- for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs of various decorative boards provided in the game board 4 shown in FIG. The DAT is created by extracting from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c, and is set in the lamp drive board side transmission data storage area 4150caa of the peripheral control RAM 4150c shown in FIG. At the same time, the door side light emission data STL-DAT for outputting lighting signals, blinking signals or gradation lighting signals to a plurality of LEDs of various decorative boards provided on the door frame 5 is provided to the peripheral control ROM 4150b of the peripheral control unit 4150. Alternatively, it is created by extracting from various control data copy areas 4150ce of the peripheral control RAM 4150c, and set in the frame decoration drive amplifier board side LED transmission data storage area 4150cab of the peripheral control RAM 4150c shown in FIG.

Following step S1028, the effect control program performs display data creation processing (step S1030). In this display data creation process, the effect control program updates the pointer in the scheduler update process of step S1020, and among the screen data arranged in time series constituting the screen generation schedule data, the screen data indicated by the pointer. Is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP4160a. When screen data is input from the peripheral control MPU4150a, the sound source built-in VDP4160a extracts character data from the liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data, and creates a sprite data on the game board side liquid crystal display device. Drawing data for one screen (one frame) to be displayed on the 1900 and the liquid crystal display device 470 on the precision plate side is generated on the built-in VRAM.

Following step S1030, the effect control program performs touch panel processing (step S1031). In this touch panel processing, the effect control program controls the contact state of the capacitive touch panel 480 provided so as to cover the display area of the upper plate side liquid crystal display device 470 shown in FIG. 2, the touch panel control board 450. It is a process of exchanging (sending and receiving) control commands and various information (various data) with. For example, as control commands, there are a detection control start command for starting the detection control of the contact state of the touch panel 480, a power saving mode transition command for shifting to the power saving mode, and the like. The effect control program uses the touch panel 480 sensing position (X coordinate, Y coordinate) as the contact state detection value at the sensing position in the entire area of the touch panel 480 shown in FIG. 17, which is one of various data from the touch panel control board 450. ) Is linked, the coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger is acquired, and the position represented by this coordinate value is specified as a detection point (detection). Point acquisition means).

Specifically, the effect control program includes the coordinate values of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger acquired in the previous touch panel process (that is, 16 ms before) and the touch panel process this time. It is determined whether or not the acquired coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger matches, and if they match, the coordinate value is represented by the matching coordinate value. Identify the location as a detection point. In this way, the coordinate values of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger 16 ms before, and the touch panel 480 indicating the center of the contact portion touched by the finger acquired in this touch panel processing. By constantly comparing with the coordinate value of the contact surface, the reliability of acquiring the coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger is improved. Even if the finger touching the touch panel 480 is being moved, if the finger is moved in an extremely short period of 16 ms, for example, 50 mm in 1 s, the 16 ms is 0.8 mm (0.05 mm). Since the moving distance is extremely short (/ ms × 16 ms), as described above, in this embodiment, the touch panel 480 is a type with 4.3 inches and a resolution of 10 × 20, and the resolution is low, and the finger touches 16 ms before. The coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion with the finger matches the coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger acquired in this touch panel processing. It will be.

Further, the coordinate values of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger 16 ms before, and the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger acquired in this touch panel processing. The process of constantly comparing with the coordinate value of is functioning as a so-called software-based low-pass filter for acquiring the coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger. The coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger obtained in the touch panel processing is from the coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger 16 ms before. If the human finger indicates a position that cannot be moved within this 16 ms period, it is considered that the finger is affected by the momentary noise caused by the electrostatic discharge of the game ball, and this comparison shows a disagreement. It is not specified as a detection point. The coordinate values of the contact surface of the touch panel 480, which indicates the center of the contact portion touched by the finger, acquired in this touch panel process are momentarily affected by noise, and will be acquired in the next touch panel process. The coordinate values of the contact surface of the touch panel 480, which indicates the center of the contact portion touched by the finger, are normal without being affected by noise. As a result, the next coordinate value and the next coordinate value for this time affected by noise (that is, the coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger acquired 16 ms after this time). And the coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger, which was acquired after 32 ms this time). In addition, this effect control program may acquire not only such a coordinate value but also a range of the contact surface (hereinafter referred to as a contact range), and in this case, the finger touches 16 ms before. The contact range of the touch panel 480 and the contact range of the touch panel 480 touched by the finger may be compared and acquired in the touch panel processing this time.

Following step S1031, the effect control program performs sound data creation processing (step S1032). In this sound data creation process, the effect control program updates the pointer in the scheduler update process of step S1020, and the pointer indicates among the sound command data arranged in time series constituting the sound generation schedule data. Sound command data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP4160a. When sound command data is input from the peripheral control MPU4150a, the sound source built-in VDP4160a extracts sound data such as music and sound effects stored in the liquid crystal and sound control ROM 4160b to control the built-in sound source to control the sound command. Sound data such as music and sound effects are incorporated according to the track number specified in the data, and the output channel to be used is set according to the output channel number.

In the sound data creation process, each time this sound data creation process is performed (that is, each time the peripheral control unit steady process is performed), the peripheral control A / D converter 4150ak shown in FIG. 15 is started and the volume adjustment volume is adjusted. The voltage divided by the resistance value at the rotation position of the knob portion of 4140a is converted into a value of 1024 steps from the value 0 to the value 1023. In this embodiment, the value of 1024 steps is divided into seven and managed as the board volume 0 to 6, the board volume 0 is set to mute, the board volume 6 is set to the maximum volume, and the board volume 0 to the board. The volume is set to increase toward the volume 6. The sound source built-in VDP4160a of the liquid crystal and the sound control unit 4160 is controlled so that the volume is set to the board volumes 0 to 6, and the sound data is serialized in the sound data output process of step S1018 described above. By outputting to the transmission IC 4160c, music and sound effects can be played from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5.

In addition, the notification sound and notification sound flow without depending on the volume adjustment based on the rotation operation of the knob, and the volume from mute to maximum volume is programmed to be the sound source of the liquid crystal display and the sound control unit 4160. The built-in VDP4160a can be controlled and adjusted. The volume adjusted by this program is different from the substrate volume divided into the above-mentioned seven stages, and can smoothly change from mute to maximum volume. For example, even when a clerk in the hall or the like rotates the knob portion of the volume adjustment volume 4140a to set the volume low, the speaker and the door frame 5 housed in the speaker box 820 provided in the main body frame 3 can be used. Although the production sounds such as music and sound effects flowing from the provided speaker 130 are reduced, the volume is loud when the pachinko gaming machine 1 has a problem or when the player is cheating (in this embodiment, the volume is high). The notification sound set to (maximum volume) can be played. Therefore, even if the volume of the effect sound is reduced, it is possible to prevent the hall clerk and the like from becoming less likely to notice the occurrence of a problem or the player's fraudulent activity due to the notification sound. In addition, based on the current board volume set by adjusting the volume based on the rotation operation of the knob, the volume at which the advertising sound is played is reduced so that it does not interfere with music or sound effects, while the advertising sound is played. In addition to music and sound effects by increasing the volume of the sound, the screen unfolded by the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the precision plate side can be produced as more powerful, which is advantageous for the player. It is also possible to announce that there is a high possibility of shifting to the gaming state.

Following step S1032, the effect control program performs backup processing (step S1034). In this backup process, the effect control program converts the contents stored in the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. 15 into the backup first area 4150 cc and the backup second area 4150 cc. In addition to copying and backing up each, the contents stored in the peripheral control MPU 4150a and the external peripheral control SRAM 4150d are copied and backed up in the backup first area 4150db and the backup second area 4150dc, respectively.

Specifically, in the backup process, the peripheral control RAM 4150c is backed up for each frame (1 frame) in the backup target work area 4150ca shown in FIG. 15, that is, every time the peripheral control unit routine process is executed. The lamp drive board side transmission data storage area 4150caa, the frame decoration drive amplifier board side LED transmission data storage area 4150cab, the reception command storage area 4150cac, the RTC information acquisition storage area 4150cad, and Peripheral control DMA controller 4150ac is set in Bank1 (1fr) and Bank2 (1fr) of the backup first area 4150cc as the effect information (1fr) stored in the schedule data storage area 4150cae as the effect backup information (1fr). Copy at high speed, and the peripheral control DMA controller 4150ac copies at high speed to Bank3 (1fr) and Bank4 (1fr) in the backup second area 4150cc.

Briefly explaining the high-speed copy of the contents stored in Bank0 (1fr) by the peripheral control DMA controller 4150ac, the peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 15 is a requirement factor of the peripheral control DMA controller 4150ac. Specify a copy of the contents stored in Bank0 (1fr) to Bank1 (1fr) of the backup first area 4150cc, and change the contents stored in the start address of Bank0 (1fr) to the end address of Bank0 (1fr). All the stored contents are continuously copied in order from the start address of Bank1 (1fr) of the backup first area 4150cc by a predetermined byte (for example, 1 byte), and the peripheral control MPU core 4150aa is the peripheral control DMA controller. Specify the copy of the contents stored in Bank0 (1fr) as the request factor of 4150ac to Bank2 (1fr) of the backup first area 4150cc, and specify the copy from the contents stored in the start address of Bank0 (1fr) to Bank0 (1fr). ), The contents stored in the terminal address of) are continuously copied by predetermined bytes (for example, 1 byte) in order from the start address of Bank2 (1fr) in the backup first area 4150 kb.

Subsequently, the peripheral control MPU core 4150aa specifies a copy of the contents stored in Bank0 (1fr) as a requirement factor of the peripheral control DMA controller 4150ac to Bank3 (1fr) of the backup second area 4150cc, and specifies Bank0 (1fr). ), The contents stored in the end address of Bank0 (1fr) are continuously backed up by predetermined bytes (for example, 1 byte). The start address of Bank3 (1fr) in the second area 4150cc. Copy everything in order from, and specify the copy of the contents stored in Bank0 (1fr) as the requirement factor of the peripheral control DMA controller 4150ac to Bank4 (1fr) of the backup second area 4150cc. Then, the contents stored in the start address of Bank0 (1fr) to the contents stored in the end address of Bank0 (1fr) are continuously backed up by predetermined bytes (for example, 1 byte) in Bank4 of the second area 4150cc (Bunk4). Copy everything in order from the start address of 1fr).

Further, in the backup process, the peripheral control SRAM 4150d is backed up for each frame (1 frame) in the backup target work area 4150da shown in FIG. 15, that is, every time the peripheral control unit routine process is executed. Peripheral control DMA controller 4150ac is high-speed in Bank1 (SRAM) and Bank2 (SRAM) of the backup first area 4150db using the effect information (RAM) stored in Bank0 (SRAM) as the effect backup information (SRAM). And the peripheral control DMA controller 4150ac copies to Bank3 (SRAM) and Bank4 (SRAM) in the backup second area 4150dc at high speed.

Briefly explaining the high-speed copy of the contents stored in Bank0 (SRAM) by the peripheral control DMA controller 4150ac, the peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 15 is a requirement factor of the peripheral control DMA controller 4150ac. Specify a copy of the contents stored in Bank0 (SRAM) to Bank1 (SRAM) of the backup first area 4150db, and change the contents stored in the start address of Bank0 (RAM) to the end address of Bank0 (SRAM). All the stored contents are continuously copied in order from the start address of Bank1 (SRAM) in the backup first area 4150db by a predetermined byte (for example, 1 byte), and the peripheral control MPU core 4150aa is the peripheral control DMA controller. Specify the copy of the contents stored in Bank0 (SRAM) as the request factor of 4150ac to Bank2 (SRAM) of the backup first area 4150db, and specify the copy from the contents stored in the start address of Bank0 (SRAM) to Bank0 (SRAM). ), The contents stored in the terminal address of) are continuously copied in order from the start address of Bank2 (SRAM) in the backup first area 4150db by a predetermined byte (for example, 1 byte).

Subsequently, the peripheral control MPU core 4150aa specifies a copy of the contents stored in the Bank0 (SRAM) as a requirement factor of the peripheral control DMA controller 4150ac to the Bank3 (SRAM) of the backup second area 4150dc, and specifies the copy to the Bank0 (SRAM). ), The contents stored in the end address of Bank0 (RAM) are continuously backed up by predetermined bytes (for example, 1 byte). The start address of Bank3 (SRAM) in the second area 4150dc. All are copied in order from, and the peripheral control MPU core 4150aa specifies the copy of the contents stored in Bank0 (SRAM) as the requirement factor of the peripheral control DMA controller 4150ac to Bank4 (SRAM) of the backup second area 4150dc. Then, the contents stored in the start address of Bank0 (RAM) to the contents stored in the end address of Bank0 (RAM) are continuously backed up by predetermined bytes (for example, 1 byte) in Bank4 of the second area 4150dc (Bunk4). All copies are made in order from the start address of SRAM).

Following step S1034, the WDT clear process is performed (step S1036). In this WDT clear processing, a clear signal is output to the peripheral control built-in WDT4150af and the peripheral control external WDT4150e so that the peripheral control MPU4150a is not reset.

Following step S1036, the effect control program sets the value 0 in the steady processing flag SP-FLG as the execution of the peripheral control unit steady processing is completed (step S1038), returns to step S1006 again, and returns to the V blank signal detection flag VB. -The value 0 is set in FLG and initialized, and the determination in step S1008 is repeated until the value 1 is set in the V blank signal detection flag VB-FLG in the peripheral control unit V blank signal interrupt processing described later. That is, in step S1008, the process waits until the value 1 is set in the V blank signal detection flag VB-FLG, and when it is determined in step S1008 that the V blank signal detection flag VB-FLG has a value 1, steps S1009 to step S1009. The process of S1038 is performed, and the process returns to step S1006 again. As described above, when it is determined in step S1008 that the V blank signal detection flag VB-FLG has a value of 1, the processes of steps S1009 to S1038 are performed. The processing of steps S1009 to S1038 is referred to as "peripheral control unit steady processing".

This peripheral control unit steady processing starts from setting the value 1 in the steady processing flag SP-FLG assuming that the peripheral control unit steady processing is being executed in step S1009, and 1 ms in step S1010. The interrupt timer start processing is performed, each processing of step S1012, step S1014, ..., And step S1036 is performed, and finally, in step S1038, the value 0 is set to the steady processing flag SP-FLG as the execution of the peripheral control unit steady processing is completed. If you set, it will be completed. Peripheral control unit steady processing is executed when the V blank signal detection flag VB-FLG has a value of 1 in step S1008. As described above, this V blank signal detection flag VB-FLG is executed when a V blank signal indicating that the screen data from the peripheral control MPU4150a can be accepted is input from the sound source built-in VDP4160a. The value 1 is set in the peripheral control unit V blank signal interrupt processing described later. In the present embodiment, as described above, the frame frequency (number of screen updates per second) of the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the upper plate side is set to approximately 30 fps per second. The interval at which the blank signal is input is about 33.3 ms (= 1000 ms ÷ 30 fps). That is, the peripheral control unit steady processing is repeatedly executed approximately every 33.3 ms.

[15-1-2. Peripheral control unit V blank signal interrupt processing]
Next, a V blank signal indicating that the screen data from the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 14 can be accepted is input from the liquid crystal display and the sound source built-in VDP 4160a of the sound control unit 4160. Peripheral control unit V blank signal interrupt processing to be executed with this as an opportunity will be described. When the peripheral control unit V blank signal interrupt processing is started, the peripheral control MPU4150a of the peripheral control unit 4150 determines whether the steady-state processing flag SP-FLG has a value of 0, as shown in FIG. 56 (step). S1045). As described above, the steady processing flag SP-FLG has a value of 1 when the peripheral control unit steady processing in steps S1009 to S1038 in the peripheral control unit power-on processing in FIG. 55 is being executed, and the peripheral control unit steady state. The value is set to 0 when the processing is completed.

When the steady processing flag SP-FLG is not a value 0 (value 1) in step S1045, that is, when the peripheral control unit steady processing is being executed, this routine is terminated as it is. On the other hand, when the steady processing flag SP-FLG has a value of 0 in step S1045, that is, when the execution of the peripheral control unit steady processing is completed, the value 1 is set in the V blank signal detection flag VB-FLG (step S1050). End this routine. As described above, this V blank signal detection flag VB-FLG is a flag for determining whether or not to execute the peripheral control unit steady processing, and has a value of 1 when the peripheral control unit steady processing is executed. The value is set to 0 when the steady processing is not executed.

In the present embodiment, in step S1045, it is determined whether or not the constant processing flag SP-FLG has a value of 0, that is, whether or not the peripheral control unit steady processing has been executed, and the peripheral control unit steady processing has been executed. Occasionally, in step S1050, the value 1 is set to the V blank signal detection flag VB-FLG, but this is because the V blank signal is input and the V blank is input while the peripheral control unit steady processing is being executed. When the value 1 is set in the signal detection flag VB-FLG, the peripheral control unit steady processing currently being executed is executed as the peripheral control unit steady processing is executed in the determination of step S1008 in the peripheral control unit power-on processing in FIG. 55. Since it is forcibly canceled in the middle and the peripheral control unit steady processing is started from the beginning, in order to prevent this, the peripheral control unit power-on processing (peripheral control unit steady processing) in FIG. 55 is steady in step S1009. By setting the value 1 to the processing flag SP-FLG, it is notified to the peripheral control unit V blank signal interrupt processing, which is this routine, that the peripheral control unit steady processing is being executed, and the peripheral control unit power supply in FIG. 55. Peripheral control unit V blank, which is this routine, indicates that the execution of peripheral control unit steady processing is completed by setting the value 0 to the flag SP-FLG during steady processing in step S1038 in the on-time processing (peripheral control unit steady processing). By transmitting to the signal interrupt processing, whether or not the constant processing flag SP-FLG has a value of 0 in the determination of step S1045 in the peripheral control unit V blank signal interrupt processing, which is this routine, that is, the peripheral control unit steady processing is executed. It is designed to determine whether it is completed or not. In other words, it is a measure when the peripheral control unit steady processing cannot be completed by the time the V blank signal is input and the next V blank signal is input, so that the processing fails.

As a result, in the peripheral control unit steady processing this time, if the processing cannot be completed in about 33.3 ms and the processing fails, the next time the determination in step S1008 in the peripheral control unit power-on processing in FIG. 55 is performed. It will be in a state of waiting until the V blank signal of is input. That is, the time for executing the current peripheral control unit steady processing that has failed the processing is about 66.6 ms. Normally, the peripheral control unit 1ms timer interrupt processing, which will be described later, is repeatedly executed every time the 1ms interrupt timer is activated by starting the 1ms interrupt timer in step S1010 in the peripheral control unit power-on processing (peripheral control unit steady processing) of FIG. Is executed only 32 times for one peripheral control unit steady processing, but if the peripheral control unit steady processing of this time that the above-mentioned processing failed exists, the peripheral control unit 1ms timer interrupt processing is 64 times. It is designed to be executed only 32 times. That is, even if the peripheral control unit steady processing fails, the consistency between the progress state of the effect by the peripheral control unit steady processing and the progress state of the effect by the peripheral control unit 1ms timer interrupt processing, which is the timer interrupt control, is consistent. It is designed not to collapse. Therefore, even if the peripheral control unit steady processing fails, the progress state of the effect can be reliably matched.

[15-1-3. Peripheral control unit 1ms timer interrupt processing]
Next, the peripheral control unit 1ms timer interrupt processing that is repeatedly executed every time the 1ms interrupt timer is generated by the activation of the 1ms interrupt timer in step S1010 in the peripheral control unit steady processing of the peripheral control unit power-on processing of FIG. 55 will be described. .. When the peripheral control unit 1ms timer interrupt processing is started, the peripheral control MPU4150a of the peripheral control unit 4150 shown in FIG. 14 has whether or not the 1ms timer interrupt execution count STN is smaller than 33 times, as shown in FIG. 57. Is determined (step S1100). As described above, the 1ms timer interrupt execution count STN is determined by the 1ms interrupt timer activation processing in step S1010 in the peripheral control unit steady processing of the peripheral control unit power-on processing in FIG. 55, in which the 1ms interrupt timer is activated in this routine. It is a counter that counts the number of times that a certain peripheral control unit 1ms timer interrupt processing is executed. In the present embodiment, as described above, the frame frequency (number of screen updates per second) of the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the upper plate side is set to approximately 30 fps per second. The interval at which the blank signal is input is about 33.3 ms (= 1000 ms ÷ 30 fps). That is, since the peripheral control unit steady processing is repeatedly executed approximately every 33.3 ms, after the 1 ms interrupt timer is started in step S1010 in the peripheral control unit steady processing, the next peripheral control unit steady processing is performed. Is executed, the peripheral control unit 1 ms timer interrupt process is executed only 32 times. Specifically, when the 1 ms timer interrupt is activated in step S1010 in the peripheral control unit steady processing, the first 1 ms timer interrupt is generated first, the second, ..., And the 32nd 1 ms timer interrupt is sequentially performed. It will occur.

When the 1ms timer interrupt execution count STN is not smaller than 33 times in step S1100, that is, when the 33rd 1ms timer interrupt occurs and the peripheral control unit 1ms timer interrupt processing is started, this routine is terminated as it is. When the occurrence of the 33rd 1ms timer interrupt happens to precede the generation of the next V blank signal, in the present embodiment, the peripheral control unit 1ms timer interrupt processing is the peripheral control unit V as the priority of the interrupt processing. Although it is set higher than the blank interrupt processing, the start of the peripheral control unit 1ms timer interrupt processing by the 33rd 1ms timer interrupt is forcibly canceled. In other words, in the present embodiment, since the V blank signal is the signal that controls the entire system of the peripheral control board 4140, when the occurrence of the 33rd 1 ms timer interrupt happens to precede the generation of the next V blank signal. , The start of the peripheral control unit 1ms timer interrupt processing by the 33rd 1ms timer interrupt is forcibly canceled in order to execute the peripheral control unit V blank interrupt processing. Then, after the 1ms interrupt timer is restarted in step S1010 in the peripheral control unit steady processing due to the generation of the V blank signal, the peripheral control unit 1ms timer interrupt processing due to the generation of the first 1ms timer interrupt is newly started. ing.

On the other hand, when the 1 ms timer interrupt execution count STN is smaller than 33 in step S1100, the value 1 is added to the 1 ms timer interrupt execution count STN (increment, step S1102). By adding the value 1 to the 1ms timer interrupt execution count STN, the 1ms interrupt timer is activated by the 1ms interrupt timer activation processing in step S1010 in the peripheral control unit steady processing of the peripheral control unit power-on processing in FIG. 55. The number of times the peripheral control unit 1ms timer interrupt processing, which is this routine, is executed is increased by one time.

Following step S1102, motor and solenoid drive processing is performed (step S1104). In this motor and solenoid drive process, the electrical drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. 15 are arranged in a time series constituting the schedule data. Of the drive data of the electric drive sources such as motors and solenoids, the electric drive sources such as motors and solenoids of the frame decoration drive amplifier board 194 and the motor drive board 4180 shown in FIG. 14 according to the drive data indicated by the pointer. The pointer is updated to the next drive data specified in the time series, and the pointer is updated every time the motor and solenoid drive process is executed.

Specifically, in the motor and solenoid drive processing, the DMA serial continuous transmission processing to the frame decoration drive amplifier board 194 is performed. Here, the serial I / O port for the frame decoration drive amplifier board motor is continuously transmitted by using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. When continuous transmission of the serial I / O port for the frame-decorated drive amplifier board motor is started, first, the electrical drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the external peripheral control RAM 4150c is input. Of the drive data of electric drive sources such as motors and solenoids arranged in a time series, the drive signal to the dial drive motor 414 of the operation unit 400 shown in FIG. 7 is based on the drive data indicated by the pointer. The door-side motor drive data STM-DAT for outputting is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c, and is created, and the peripheral control RAM 4150c shown in FIG. The frame is set in the transmission data storage area 4150 caf for the motor on the board side of the decorative drive amplifier. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a specifies the transmission of the serial I / O port for the frame decoration drive amplifier board motor as a requirement factor of the peripheral control DMA controller 4150ac, and stores the transmission data for the frame decoration drive amplifier board side motor. The first byte of the door-side motor drive data STM-DAT stored at the start address of the region 4150 caf is sent to the frame decoration drive amplifier board motor via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer to the transmission buffer register of the serial I / O port for writing. As a result, the serial I / O port for the frame decoration drive amplifier board motor transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the door side motor drive clock signal STM-CLK to transmit the transmission shift register. 1 byte of data is started to be transmitted bit by bit.

The peripheral control DMA controller 4150ac triggers each time a transmission interrupt request for the serial I / O port for the frame decoration drive amplifier board motor is generated (in this embodiment, the serial I / O for the frame decoration drive amplifier board motor). The 1-byte data written in the transmit buffer register of the port is transferred to the transmit shift register, and the 1-byte data disappears in the transmit buffer register and becomes empty.), Peripheral control CPU core 4150aa When the bus is not used, the remaining door-side motor drive data STM-DAT stored in the transmission data storage area 4150 caf for the frame decoration drive amplifier board side motor is stored in 1 byte each, external bus 4150h, peripheral control bus controller. The serial I / O port for the frame decoration drive amplifier board motor is written by transferring to the transmission buffer register of the serial I / O port for the frame decoration drive amplifier board motor via the 4150ad and the peripheral bus 4150ai. The data of the transmitted buffer register is transferred to the transmission shift register, and the 1-byte data of the transmission shift register is started to be transmitted bit by bit in synchronization with the door-side motor drive clock signal STM-CLK, and the frame decoration drive amplifier board is used. Continuous transmission is performed by the serial I / O port for the motor.

Further, in the motor and solenoid drive processing, the DMA serial continuous transmission process to the motor drive board 4180 is performed. Here, too, the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. 15 is used to continuously transmit the serial I / O port for the motor drive board. When the continuous transmission of the serial I / O port for the motor drive board is started, first, when the peripheral control MPU 4150a and the electrical drive source schedule data set in the schedule data storage area 4150cae of the external peripheral control RAM 4150c are configured. Of the drive data of electric drive sources such as motors and solenoids arranged in a series, a motor for moving various movable bodies provided on the game board 4 shown in FIG. 8 based on the drive data indicated by the pointer. The game board side motor drive data SM-DAT for outputting the drive signal to the or solenoid is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c, and is also shown in the figure. It is set in the transmission data storage area 4150 cag on the motor drive board side of the peripheral control RAM 4150 c shown in 15. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a specifies the transmission of the serial I / O port for the motor drive board as the requirement factor of the peripheral control DMA controller 4150ac, and stores it in the start address of the transmission data storage area 4150ca on the motor drive board side. The first byte of the game board side motor drive data SM-DAT is transmitted to the transmission buffer of the serial I / O port for the motor drive board via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer to a register and write. As a result, the serial I / O port for the motor drive board transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the game board side motor drive clock signal SM-CLK to be one of the transmission shift registers. Transmission of byte data is started bit by bit.

The peripheral control DMA controller 4150ac triggers each time a transmission interrupt request for the serial I / O port for the motor drive board is generated (in the present embodiment, the transmission buffer register for the serial I / O port for the motor drive board is used). The written 1-byte data is transferred to the transmission shift register, and the transmission buffer register runs out of 1-byte data and becomes empty.) The peripheral control CPU core 4150aa is using the bus. If not, the remaining game board side motor drive data SM-DAT stored in the motor drive board side transmission data storage area 4150 cag is sent byte by byte via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. By transferring and writing to the transmission buffer register of the serial I / O port for the motor drive board, the serial I / O port for the motor drive board transfers the data of the written transmission buffer register to the transmission shift register. In synchronization with the game board side motor drive clock signal SM-CLK, 1-byte data of the transmission shift register is started to be transmitted bit by bit, and continuous transmission is performed by the serial I / O port for the motor drive board.

Following step S1104, the movable body information acquisition process is performed (step S1106). In this movable body information acquisition process, history information of detection signals from various detection switches (for example, in-situ history information) is determined by determining whether or not detection signals from various detection switches provided on the game board 4 are input. , Movable position history information, etc.) is created and set in the movable body information acquisition storage area 4150cah of the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. From the history information of the detection signals from the various detection switches set in the movable body information acquisition storage area 4150cah, it is possible to acquire the original position, the movable position, and the like of the various movable bodies provided in the game board 4.

Following step S1106, the operation unit information acquisition process is performed (step S1108). In this operation unit information acquisition process, history information of detection signals from various detection switches (for example, a dial operation unit) is determined by determining whether or not detection signals from various detection switches provided in the operation unit 400 are input. The rotation (rotation direction) history information of 401, the operation history information of the pressing operation unit 405, etc.) are created, and the operation unit information acquisition storage area of the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. Set to 4150 kai. It is possible to acquire the rotation direction of the dial operation unit 401 and the presence / absence of operation of the pressing operation unit 405 from the history information of the detection signals from various detection switches set in the operation unit information acquisition storage area 4150 kai.

Following step S1108, a backup process is performed (step S1110), and this routine is terminated. In this backup process, the contents stored in the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. 15 are copied to the backup first area 4150 cc and the backup second area 4150 cc, respectively, and backed up. At the same time, the contents stored in the peripheral control MPU 4150a and the external peripheral control SRAM 4150d are copied to the backup first area 4150db and the backup second area 4150dc, respectively, and backed up.

Specifically, in the backup process, for the peripheral control RAM 4150c, the peripheral control unit 1 ms timer interrupt process, which is the present routine, is executed every time the 1 ms interrupt timer is generated in the backup target work area 4150ca shown in FIG. Each time it is backed up, the frame decoration drive amplifier board side motor transmission data storage area 4150 caf, motor drive board side transmission data storage area 4150 cag, and movable body information acquisition storage area 4150 cah included in the backup target Bank0 (1 ms). , And the effect information (1 ms) stored in the operation unit information acquisition storage area 4150 kai is used as the effect backup information (1 ms), and peripheral control is performed on Bank 1 (1 ms) and Bank 2 (1 ms) of the backup first area 4150 cc. The DMA controller 4150ac copies at high speed, and the peripheral control DMA controller 4150ac copies at high speed to Bank 3 (1 ms) and Bank 4 (1 ms) in the backup second area 4150 cc.

Briefly explaining the high-speed copy of the contents stored in Bank 0 (1 ms) by the peripheral control DMA controller 4150ac, the peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 15 is a requirement factor of the peripheral control DMA controller 4150ac. Specify a copy of the contents stored in Bank0 (1ms) to Bank1 (1ms) of the backup first area 4150cc, and change the contents stored in the start address of Bank0 (1ms) to the end address of Bank0 (1ms). All the stored contents are continuously copied in order from the start address of Bank1 (1 ms) of the backup first area 4150 kb by a predetermined byte (for example, 1 byte), and the peripheral control MPU core 4150aa is the peripheral control DMA controller. Specify a copy of the contents stored in Bank0 (1ms) as the request factor of 4150ac to Bank2 (1ms) of the backup first area 4150cc, and use Bank0 (1ms) from the contents stored in the start address of Bank0 (1ms). ), The contents stored in the terminal address of) are continuously copied by predetermined bytes (for example, 1 byte) in order from the start address of Bank 2 (1 ms) in the backup first area 4150 kb.

Subsequently, the peripheral control MPU core 4150aa specifies a copy of the content stored in Bank0 (1ms) as a requirement factor of the peripheral control DMA controller 4150ac to Bank3 (1ms) of the backup second area 4150cc, and specifies Bank0 (1ms). ), The contents stored in the end address of Bank0 (1 ms) are continuously backed up by predetermined bytes (for example, 1 byte). The start address of Bank3 (1 ms) in the second area 4150 cc. Copy everything in order from, and specify the copy of the contents stored in Bank0 (1ms) as the requirement factor of the peripheral control DMA controller 4150ac to Bank4 (1ms) of the backup second area 4150cc. Then, the contents stored in the start address of Bank0 (1 ms) to the contents stored in the end address of Bank0 (1 ms) are continuously backed up by predetermined bytes (for example, 1 byte) in Bank4 of the second area 4150 cc (Bunk4). Copy everything in order from the start address of 1ms).

As described above, in the peripheral control unit 1 ms timer interrupt process, various processes related to the effect of steps S1104 to S1108 described above are executed as the progress of the effect within the period of 1 ms. On the other hand, in the peripheral control unit steady processing in the peripheral control unit power-on processing of FIG. 55, various processes related to the above-mentioned effects of steps S1012 to S1032 are executed as the progress of the effects within a period of about 33.3 ms. is doing. In the peripheral control unit 1ms timer interrupt processing, when the 1ms timer interrupt execution count STN is not smaller than the value 33 in step S1100, that is, when the 33rd 1ms timer interrupt occurs and the peripheral control unit 1ms timer interrupt processing is started. Since this routine is terminated as it is, even if the occurrence of the 33rd 1ms timer interrupt happens to precede the generation of the next V blank signal, the peripheral control unit due to this 33rd 1ms timer interrupt Peripheral control by forcibly canceling the start of the 1ms timer interrupt process, restarting the 1ms interrupt timer in step S1010 in the peripheral control unit steady processing due to the generation of the V blank signal, and then newly generating the 1ms timer interrupt. Part 1ms Timer interrupt processing is started. That is, the consistency between the progress state of the effect by the peripheral control unit steady processing and the progress state of the effect by the peripheral control unit 1 ms timer interrupt process, which is the timer interrupt control, is not broken. Therefore, it is possible to surely match the progress state of the production.

Further, as described above, the interval at which the V blank signal is output varies slightly depending on the liquid crystal size of the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the precision plate side, and the peripheral control MPU 4150a and the sound source built-in VDP 4160a Even in the production lot of the mounted peripheral control board 4140, the interval at which the V blank signal is output may change slightly. In the present embodiment, since the V blank signal is a signal that controls the entire system of the peripheral control board 4140, if the occurrence of the 33rd 1 ms timer interrupt happens to precede the generation of the next V blank signal, peripheral control is performed. The start of the peripheral control unit 1ms timer interrupt processing by the 33rd 1ms timer interrupt is forcibly canceled in order to execute the unit V blank interrupt processing. That is, in the present embodiment, even if the interval at which the V blank signal is output changes slightly, the start of the peripheral control unit 1ms timer interrupt processing by the 33rd 1ms timer interrupt is forcibly canceled. It is possible to absorb the time lag due to a slight change in the interval at which the V-blank signal is output.

[15-1--4. Peripheral control unit command reception interrupt processing]
Next, peripheral control unit command reception interrupt processing for receiving various commands from the main control board 4100 will be described. When the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 14 starts transmitting various commands from the main control board 4100 as serial data, the main control that incorporates the main peripheral serial data into the peripheral control MPU 4150a is triggered by this. 1 byte (8 bits) of information is fetched into the receive buffer by the serial I / O port for the board, and when this fetch is completed, an interrupt is generated with this as a trigger, and peripheral control unit command reception interrupt processing is performed. In the main peripheral serial data, one packet is composed of 3 bytes, the status is assigned as the 1st byte, the mode is assigned as the 2nd byte, and the status and mode are regarded as numerical values as the 3rd byte, and the total thereof. Is assigned the calculated sum value.

When the peripheral control unit command reception interrupt process is started, the peripheral control MPU4150a of the peripheral control unit 4150 determines whether or not the 1-byte reception period timer has timed out, as shown in FIG. 58 (step S1200). This 1-byte reception period timer sets a period during which 1-byte (8-bit) information of the main peripheral serial data transmitted from the main control board 4100 can be received.

When the 1-byte reception period timer has not timed out in step S1200, that is, within the period during which 1-byte (8-bit) information of the main peripheral serial data transmitted from the main control board 4100 can be received, the peripheral area is used. 1 byte of information received from the receive buffer of the serial I / O port for the main control board built in the control MPU4150a is taken in (step S1202), and a value 1 is added to the reception counter SRXC (increment, step S1204). This reception counter SRXC is a counter indicating the number of times the data is fetched from the receive buffer, and when the status which is the first byte of the main cycle serial data is fetched from the receive buffer, the value is 1, and the mode which is the second byte of the main cycle serial data is set. When it is taken out from the receive buffer, it becomes a value 2, and when the sum value which is the third byte of the main peripheral serial data is taken out from the receive buffer, it becomes a value 3. The initial value 0 of the reception counter SRXC is set when the power is turned on or the like.

Following step S1204, it is determined whether or not the reception counter SRXC has a value of 3, that is, whether or not the sum value, which is the third byte of the main peripheral serial data, has been fetched from the receive buffer (step S1206). In this determination, following the status that is the first byte of the main cycle serial data, the mode that is the second byte of the main cycle serial data, and the sum value that is the third byte of the main cycle serial data are sequentially input from the receive buffer. It is determined whether or not it has been taken out.

When the reception counter SRXC is not a value 3 in step S1206, that is, a mode in which the status is the first byte of the main cycle serial data, the mode is still the second byte of the main cycle serial data, and the third byte of the main cycle serial data. When the sum values are not sequentially fetched from the receive buffer, the 1-byte reception period timer is set (step S1208), and this routine is terminated. By setting the 1-byte reception period timer in step S1208, the mode in which the second byte of the main cycle serial data or the sum value which is the third byte of the main cycle serial data can be received is set.

On the other hand, when the reception counter SRXC has a value of 3 in step S1206, that is, the mode which is the second byte of the main cycle serial data following the status which is the first byte of the main cycle serial data, and 3 of the main cycle serial data. When the sum value, which is the byte th, is sequentially taken out from the receive buffer, the initial value 0 is set in the reception counter SRXC (step S1210), and the sum value is calculated (step S1212). In this calculation, the status which is the first byte of the main peripheral serial data and the mode which is the second byte of the main peripheral serial data already taken out from the receive buffer in step S1202 are regarded as numerical values and the total (sum value). ) Is calculated.

Following step S1212, it is determined whether or not the sum value, which is the third byte of the main peripheral serial data already fetched from the receive buffer in step S1202, and the sum value calculated in step S1212 match (step). S1214). The thumb value, which is the third byte of the main peripheral serial data already taken out from the receive buffer in step S1202, is the sum value allocated as the third byte of the main peripheral serial data among the main peripheral serial data from the main control board 4100. Therefore, it should match the sum value calculated in step S1212. However, in the pachinko gaming machine 1, game balls are supplied from the pachinko island facility, and when the gaming balls rub against each other and become charged, they are electrostatically discharged and generate noise. Therefore, the pachinko gaming machine 1 is affected by noise. It is in a vulnerable environment. Therefore, in the present embodiment, the status allocated as the first byte of the received main peripheral serial data and the mode allocated as the second byte of the main peripheral serial data on the peripheral control unit 4150 side are regarded as numerical values. The total (sum value) is calculated, and whether the calculated sum value matches the sum value allocated as the third byte of the main circumference serial data in the main circumference serial data from the main control board 4100. It is judged whether or not. As a result, the peripheral control MPU 4150a determines whether or not the main peripheral serial data has changed to the main peripheral serial data different from the normal one due to the influence of noise between the substrates of the main control board 4100 and the peripheral control board 4140. be able to.

In step S1214, when the sum value which is the third byte of the main peripheral serial data already fetched from the receive buffer in step S1202 and the sum value calculated in step S1212 match, the received main peripheral serial data is received. The status allocated as the first byte of the peripheral control MPU 4150a and the mode allocated as the second byte of the main peripheral serial data are shown in FIG. (Step S1216), and the routine is terminated. This reception command storage area 4150cc is used as a ring buffer, and the status allocated as the first byte of the main peripheral serial data and the mode allocated as the second byte of the main circumference serial data are the reception command storage area. It is stored in the peripheral control unit reception ring buffer of 4150cc. This "peripheral control unit receive ring buffer" is a buffer that is used so that the end and the beginning of the buffer are connected. Data is stored sequentially from the beginning of the buffer, and when the end of the buffer is reached, it returns to the beginning. Remember. The peripheral control MPU4150a is allocated as the status allocated as the first byte of the main peripheral serial data received when stored in the peripheral control unit reception ring buffer in step S1216, and as the second byte of the main peripheral serial data. The mode is stored in association with the specified mode, and the sum value allocated as the third byte is discarded.

On the other hand, when the 1-byte reception period timer has not timed out in step S1200, that is, the period during which 1 byte (8 bits) of the main peripheral serial data transmitted from the main control board 4100 can be received has been exceeded. Occasionally, or in step S1214, if the sum value, which is the third byte of the main peripheral serial data already fetched from the receive buffer in step S1202, and the sum value calculated in step S1212 do not match, this routine is used as it is. finish.

[15-1-5. Peripheral control unit power failure warning signal interrupt processing]
Next, the peripheral control unit power failure warning signal executed when the power failure warning signal (peripheral power failure warning signal) from the power failure monitoring circuit 4100e of the main control board 4100, which is shown in FIG. 20, is input from the main control board 4100. Interrupt processing will be described. When the peripheral control unit power failure warning signal interrupt process is started, the peripheral control MPU4150a of the peripheral control unit 4150 shown in FIG. 14 first activates a 2-microsecond timer (step S1300), and then a power failure warning signal (peripheral power failure warning). It is determined whether or not the signal) is input (step S1302). If a power failure warning signal (peripheral power failure warning signal) is not input in this determination, this routine is terminated as it is.

On the other hand, when the power failure warning signal is input in step S1302, it is determined whether or not 2 microseconds have elapsed (step S1304). In this determination, it is determined whether or not the timer started in step S1300 has elapsed 2 microseconds. When 2 macroseconds have not elapsed in step S1304, the process returns to step S1302 to determine whether or not a power failure warning signal has been input. When the signal is input, it is determined again in step S1304 whether or not 2 microseconds have elapsed. That is, in the determination in step S1304, it is determined whether or not the power failure warning signal is continuously input for 2 microseconds after the peripheral control unit power failure warning signal interrupt processing, which is the routine, is started.

When the peripheral control unit power failure warning signal interrupt process, which is the routine, is started in step S1304 and the power failure warning signal is continuously input for 2 microseconds, power saving processing is performed (step S1306). In this power saving process, the backlights of the liquid crystal display device 1900 on the game board side and the liquid crystal display device 470 on the precision plate side are turned off, the motors and solenoids provided in the game board 4 are turned off, and various LEDs are turned off in sequence. By suppressing the power consumption of the entire system of the pachinko game machine 1, stable operation is ensured for a period of 20 milliseconds, which is the time during which the peripheral control MPU4150a can operate even if the power of the pachinko game machine 1 is cut off. ..

Following step S1306, command reception standby processing is performed (step S1308). In this command reception standby process, assuming that there are various commands being transmitted by the main control board 4100, the peripheral control MPU4150a can receive the commands being transmitted for a period of at least 17 milliseconds. It is supposed to wait. When the command is received, the above-mentioned peripheral control unit command reception interrupt processing is started, and the reception command storage area 4150cc (peripheral control unit reception ring buffer) of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. 15 is started. ) Stores the received command.

Following step S1308, command backup processing is performed (step S1310). In the backup process of this command, the contents stored in the reception command storage area 4150cac included in the Bank0 (1fr) in the backup target work area 4150ca shown in FIG. The peripheral control DMA controller 4150ac copies to Bank2 (1fr) at high speed, and the peripheral control DMA controller 4150ac copies to Bank3 (1fr) and Bank4 (1fr) of the backup second area 4150cc at high speed.

Briefly explaining the high-speed copy of the contents stored in the received command storage area 4150cc included in Bank0 (1fr) by the peripheral control DMA controller 4150ac, the peripheral control MPU core 4150aa of the peripheral control MPU4150a shown in FIG. 15 is peripheral. Specify the copy of the contents stored in the receive command storage area 4150cc included in Bank0 (1fr) to the receive command storage area included in Bank1 (1fr) of the backup first area 4150cc as the request factor of the control DMA controller 4150ac. Then, from the content stored in the start address of the received command storage area 4150cc included in Bank0 (1fr) to the content stored in the terminal address of the received command storage area 4150cc included in Bank0 (1fr), a predetermined byte (for example). 1 byte) in succession, all copies are made in order from the start address of the received command storage area included in Bank1 (1fr) of the first area 4150cc, and the peripheral control MPU core 4150aa is a requirement factor of the peripheral control DMA controller 4150ac. Specify a copy of the contents stored in the receive command storage area 4150cc included in Bank0 (1fr) to the receive command storage area included in Bank2 (1fr) of the backup first area 4150cc, and set it to Bank0 (1fr). From the content stored in the start address of the received command storage area 4150cc included to the content stored in the end address of the received command storage area 4150cc included in Bank0 (1fr), a predetermined byte (for example, 1 byte) is continuous. Then, all copies are made in order from the start address of the received command storage area included in Bank2 (1fr) of the backup first area 4150cc.

Subsequently, the peripheral control MPU core 4150aa includes the content stored in the reception command storage area 4150cc included in the Bank0 (1fr) as a requirement factor of the peripheral control DMA controller 4150ac in the Bank3 (1fr) of the backup second area 4150cc. The copy to the received command storage area is specified, and the contents stored in the start address of the received command storage area 4150cc included in Bank0 (1fr) are stored in the terminal address of the receiving command storage area 4150cc included in Bank0 (1fr). All the contents are copied in order from the start address of the received command storage area included in Bank3 (1fr) of the second area 4150cc, which is continuously backed up by a predetermined byte (for example, 1 byte), and the peripheral control MPU core. The content stored in the receive command storage area 4150cc included in Bank 0 (1fr) as a requirement factor of the peripheral control DMA controller 4150ac is transferred to the reception command storage area included in Bank 4 (1fr) of the backup second area 4150cc. Specify a copy, and specify the contents from the contents stored in the start address of the receive command storage area 4150cc included in Bank0 (1fr) to the contents stored in the end address of the receive command storage area 4150cc included in Bank0 (1fr). All copies are made in order from the start address of the received command storage area included in Bank 4 (1fr) of the backup second area 4150 cc in succession of bytes (for example, 1 byte).

Following step S1310, it is determined whether or not a power failure warning signal (peripheral power failure warning signal) has been input (step S1312). When the power failure warning signal is input in this determination, the WDT clear process is performed (step S1314). In this WDT clear process, the peripheral control MPU4150a outputs a clear signal to the peripheral control built-in WDT4150af shown in FIG. 15 and the peripheral control external WDT4150e shown in FIG. 14 to prevent the peripheral control MPU4150a from being reset. ..

On the other hand, when the power failure warning signal is not input in step S1312, or after step S1314, the process returns to step S1312 again to determine whether or not the power failure warning signal is input. That is, it is infinitely determined whether or not the power failure warning signal (peripheral power failure warning signal) is input. By continuing the determination indefinitely in this way, when the power failure warning signal (peripheral power failure warning signal) is not input in step S1312, the peripheral control MPU4150a is a clear signal to the peripheral control built-in WDT4150af and the peripheral control external WDT4150e. Is not output, and the peripheral control MPU4150a is reset. On the other hand, when the power failure warning signal is input in step S1312, the WDT clear process is performed in step S1314, and the peripheral control MPU4150a is not reset. When the peripheral control MPU4150a is reset, the peripheral control unit power-on processing shown in FIG. 55 is restarted.

In this way, when the input of the power failure warning signal (peripheral power failure warning signal) continues in the infinite loop according to the determination in step S1312, the WDT clear processing is executed in step S1314 to perform peripheral control immediately before the power failure state occurs. The MPU4150a is not reset. On the other hand, if the input of the power failure warning signal is not continued and is canceled in the infinite loop by the determination in step S1312, the WDT clear process is not executed. The output of the clear signal is interrupted. As a result, even if the peripheral control unit power failure warning signal interrupt process, which is the routine, is erroneously started due to noise or the like, and the noise occurs for more than a period of 2 microseconds, the determination in step S1302 is passed. If the input of the power failure warning signal (peripheral power failure warning signal) is not continued and canceled in the infinite loop by the determination by S1312, the peripheral control MPU4150a is reset because the WDT clear processing in step S1314 is not executed. Therefore, it is possible to deal with such noise by automatically resetting and returning.

According to the above embodiment, the pachinko gaming machine 1 includes the main control board 4100 of FIG. 11 and the payout control board 4110 of FIG. FIG. 8 shows that the main control board 4100 is a starting area in which a game ball launched by the hit ball launching device 650 of FIG. 5 is provided in the game area 1100 toward the game area 1100 partitioned on the game board 4 of FIG. The main control MPU 4100a of FIG. 11, which is a game control microprocessor that controls the progress of the game based on the intrusion into the upper start port 2101 and the lower start port 2102, is mounted. The payout control board 4110 is a payout control micro that controls the payout of the game ball by the prize ball device 740 of FIG. 5 based on the prize ball command of FIGS. 31 (a) and 31 (b) which is a payout command from the main control board 4100. The payout control MPU4120a of FIG. 12, which is a processor, is implemented.

The main control MPU 4100a, which is a game control microprocessor, includes at least a RAM (main control built-in RAM) built in the main control MPU 4100a. The main control built-in RAM can store information about the game even after the power is cut off.

The payout control MPU4120a, which is a payout control microprocessor, includes at least a RAM (a payout control built-in RAM) built in the payout control MPU4120a. The payout control built-in RAM can store information about payout even after the power is cut off.

The pachinko gaming machine 1 of the present embodiment further includes the operation switch 860a of FIG. When the operation switch 860a is operated within the period from the time when the power is turned on to the time when the determination process of step S16 in the main control side power on side process of FIG. 35 is performed, the information about the game stored in the main control built-in RAM is erased. The RAM clear signal of FIG. 22 is output to the main control MPU4100a which is a game control microprocessor, and the operation is performed within the period from the time when the power is turned on to the time when the determination process of step S512 in the process when the payout control unit is turned on in FIG. 38 is performed. Then, the RAM clear function for outputting the RWMCLR signal of FIG. 27 to the payout control microprocessor MPU4120a as the RAM clear signal for erasing the payout information stored in the payout control built-in RAM, and the power-on From time to time, the period during which the determination process of step S16 in the main control side power-on process of FIG. 35 is performed (or the period during which the determination process of step S512 in the payout control unit power-on process of FIG. 38 is performed from the time of power-on). When operated after the lapse of time, the RWMCLR signal of FIG. 27 is not output to the main control MPU4100a, which is a game control microprocessor, as an error release signal for canceling the error generated in the prize ball device 740, and the payout control microprocessor is used. It also has an error canceling function to output to the payout control MPU4120a.

As described above, when the operation switch 860a is operated within the period from the time when the power is turned on to the time when the determination process of step S16 in the process when the main control side power is turned on in FIG. 35 is performed, the game stored in the main control built-in RAM is stored. The RAM clear signal of FIG. 22 for erasing the information related to the above is output to the main control MPU4100a which is a game control microprocessor, and the determination process of step S512 in the process of power-on of the payout control unit of FIG. When operated within the specified period, the RWMCLR signal of FIG. 27 is output to the payout control microprocessor MPU4120a as a RAM clear signal for erasing the payout information stored in the payout control built-in RAM. Function and the period during which the determination process of step S16 in the main control side power-on process of FIG. 35 is performed from the time of power-on (or the determination process of step S512 in the payout control unit power-on process of FIG. 38 from the time of power-on). The RWMCLR signal of FIG. 27 is not output to the main control MPU4100a, which is a game control microprocessor, as an error release signal for canceling the error generated in the prize ball device 740. Since it also has an error canceling function that outputs to the payout control MPU4120a, which is a payout control microprocessor, two different functions, a RAM clear function and an error clearing function, can be pachinko by operating with one operation switch 860a. It can be provided in the game machine 1. Therefore, it is possible to provide a RAM clear function and an error clear function while contributing to cost reduction.

By the way, as described above, in the pachinko machine 1, a touch panel 480 is provided on the door frame 5 that can be opened and closed with respect to the main body frame 3 so that the operation surface overlaps the display area of the liquid crystal display device 470 on the upper plate side. The effect control program uses the sound source built-in VDP4160a controlled by the peripheral control MPU4140a to display the selected display item image data and the operation menu background image data stored in advance in the liquid crystal display and the sound control ROM 4160b. The operation menu screen is displayed on the upper plate side liquid crystal display device 470 (second display device) in a display mode in which at least one selection display object is superimposed on the operation menu background image as shown in FIG. 65 (selection). Display object display control means). Specifically, on this operation menu screen, for example, a volume light amount selection display for resetting the volume and light amount, an extra selection display that imitates a violent person wearing sunglasses and calling himself "Bomb King", and a bonus selection display. Along with the word "first pachinko" that catches the eyes of unfamiliar pachinko beginners, the selection display items for beginners that imitate a game ball are arranged and displayed at almost equal intervals along the horizontal direction, and they are placed almost in the center. The selected display item is displayed in a slightly larger size than the other selected display items.

As shown in FIG. 66, the operator touches the contact surface of the touch panel 480 with the finger F at the position of the selection display object for beginners displayed on the slightly right side of the display area of the liquid crystal display device 470 on the upper plate side, from right to left. When slid toward, the effect control program reduces the size of the bonus selection display based on the contact state of the contact surface of the touch panel 480, and expands the selection display for beginners, for example, as a candidate to be selected next. And display so that each selected display object is moved to the left as shown in FIG. 67.

Subsequently, when this operator touches the pachinko selection display object KHB for the first time with the finger F as shown in FIG. 68 (hereinafter, referred to as “tap”), the effect control program is shown in the figure as described above. The detection point is specified based on the contact portion according to the contact state of the contact surface of the touch panel 480 by the sensing data from the touch panel control board 450 shown in 17. (Detection point acquisition means). Further, the effect control program is the first time based on the annular image data read from the liquid crystal and the sound control ROM 4160b (effect control storage unit) at the corresponding detection point in the display area of the upper plate side liquid crystal display device 470. A small initial liquid crystal display KHB is displayed at the position of the pachinko selection display object (initial display control means).

Next, as shown in FIG. 70, the effect control program enlarges and displays the above-mentioned wording “first pachinko” and makes the player visually recognize that the first pachinko selection display object has been selected. As shown in FIG. 71, this effect control program reduces the density while leaving an afterimage of the annular display in the middle of the display mode in which the initial annular display is continuously enlarged with the passage of time at the detection point. While continuously enlarging the display to display the final annular display, while eliminating the first pachinko selection display corresponding to the detection point, the next transition destination screen associated with the first pachinko selection display is displayed. Display (afterimage display control means).

In this way, the operator of the touch panel 480 can visually recognize the annular display object KHB displayed in the display area of the upper plate side liquid crystal display device 470 through the contact surface in response to his / her own operation. .. Here, in today's world where precise production display has become possible, it seems that the player does not respond to his / her own operation at first glance, as the response of the touch panel generally remains even slightly. It seems that the psychology of actively participating in the player-participation-type production will be difficult to work, erroneously recognizing that it may be. However, according to the present embodiment, even if a precise effect display is possible, an afterimage of the annular display object KHB remains according to the operation of the operator, so that the operator operates even if the response to the operation is slightly delayed. It can be visually recognized that the response to is surely made.

By the way, instead of constantly displaying the afterimage as described above in the upper plate side liquid crystal display device 470, the effect control program causes an error release navigation command (second error) associated with the operation of the payout control board 4110 operation switch 860a. When the release command) is received from the main control board 4100, the test mode may be temporarily switched to the test mode for confirming the operation of the upper plate side liquid crystal display device 470 and executed. That is, although the effect control program normally does not execute the afterimage display using the upper plate side liquid crystal display device 470, when the operation switch 860a is operated, it switches to the test mode and executes the afterimage display. You may do so. In this case, the effect control program controls to switch from the test mode to the normal mode when the operation switch 860a is operated again. By doing so, the display operation of the upper plate side liquid crystal display device 470 can be temporarily tested (for example, at the time of shipment of the pachinko machine 1) in the test mode, or the upper plate side liquid crystal display device 470 can be temporarily tested according to the convenience of the operator. Afterimages can be displayed constantly as part of the production using.

On the other hand, on the operation menu screen as shown in FIG. 72, the operator touches the touch panel 480 corresponding to the volume adjustment selection display object displayed in the display area of the upper plate side liquid crystal display device 470 as shown in FIG. 73. When the surface is tapped and selected, the effect control program displays a small initial liquid crystal display KHB as shown in FIG. 74 based on the contact portion based on the contact state. This effect control program displays the final annular display KHB as shown in FIG. 75 via the annular display KHB in the middle of the display mode in which the initial annular display KHB is continuously enlarged (final display). Control means). That is, the effect control program expands the annular display object KHB steplessly, for example, from the initial annular display object KHB to the final annular display object KHB, or, for example, divides the annular display object KHB into 10 stages and displays the annular display stepwise. The object KHB may be expanded.

In this way, as described above, the operator of the touch panel 480 visually recognizes the annular display object displayed in the display area of the upper plate side liquid crystal display device 470 through the contact surface in response to his / her operation. be able to. Here, if the reaction remains sluggish in today's world where precise production display is becoming possible, when it becomes possible to realize more precise production display in the future, such a detailed production display will be used. At first glance, it is possible that the player may feel a relative discomfort. However, according to the present embodiment, due to the appearance (display) of the annular display object displayed in the display area of the liquid crystal display device 470 on the upper plate side when the contact surface of the touch panel 480 is touched, the accuracy using vision is used. Since the response inspection becomes possible, even if it becomes possible to realize a more detailed effect display in the future, it is possible to make it difficult for the operator to feel a sense of discomfort by the direct response to the operation.

On the other hand, similarly, the operator touches the touch panel corresponding to the volume adjustment selection display object displayed in the display area of the upper plate side liquid crystal display device 470 as shown in FIG. 73 on the operation menu screen as shown in FIG. 72. When the contact surface of 480 is tapped and selected, the effect control program determines that the contact area of the contact portion based on the contact state is larger than the predetermined contact area (that is, when the pressing force is strong). After displaying or without displaying the small initial annular display KHB as shown in FIG. 75, at least a part of the annular display KHB in the middle is omitted, and the final annular display KHB is displayed as shown in FIG. It may be displayed. When the pressing force is strong in this way, the initial annular display KHB in the display area that is visually recognized through the contact surface of the touch panel 480 by the operator's finger, or the annular display in the middle of the above part. Although the KHB is also hidden, the effect control program reduces the unnecessary display that the player cannot see and reduces the processing load by omitting the display control of some of the annular display objects KHB in this way. can do.

After the final annular display KHB is displayed as described above, the effect control program has a volume of 1 to 6 as shown in FIG. 76 based on the tone adjustment background image data read from the liquid crystal and the sound control ROM 4160b. A volume adjustment icon OCI with a note mark based on the volume setting icon image data also read from the liquid crystal and sound control ROM 4160b is slidably superimposed on the volume adjustment background image including the scale VSCL. Display the volume adjustment screen of the mode.

When the operator taps the volume adjustment icon OCI on the volume adjustment screen with the finger F and slides it to the left as shown in FIG. 76, the effect control program controls the touch panel shown in FIG. 17 as described above. The detection point is specified based on the contact portion based on the contact state from the sensing data from the substrate 450 (detection point acquisition means), and the corresponding detection is performed in the display area of the upper plate side liquid crystal display device 470 (second display device). At the point, first, a small initial annular display object KHB is displayed based on the annular image data read from the liquid crystal display and the sound control ROM 4160b (initial display control means).

Further, when the operator slides the volume adjustment icon OCI along the volume scale VSC with the finger F as shown in FIG. 77, the effect control program senses from the touch panel control board 450 as shown in FIG. From the data, the movement locus of the position where the contact portion based on the contact state is present (hereinafter referred to as the initial position) is detected for each movement detection point (movement locus acquisition means). Next, as shown in FIG. 77, the effect control program independently and continuously expands the initial annular display KHB at each movement detection point along the detected movement locus with the passage of time. The final annular display KHB is displayed via the annular display KHB in the middle of the display mode (movement locus display control means). At this time, as shown in FIG. 78, the effect control program moves and displays the volume adjustment icon OCI so as to slide along the volume scale according to the slide of the finger F to which the volume adjustment icon OCI is tapped, and finally. Similarly, as shown in FIG. 79, the volume adjustment icon OCI is moved to the position of the finger F where the slide is completed via the display of the annular display object in the middle of the display mode. When the operator releases the finger F from the contact surface of the touch panel 480, the effect control program has lost any of the contact objects due to the sensing data from the touch panel control board 450, and thus the final contact as shown in FIG. 80. A further enlarged final annular display is displayed in the vicinity of the surface.

In this way, as described above, the operator of the touch panel 480 visually recognizes the annular display object KHB displayed in the display area of the upper plate side liquid crystal display device 470 through the contact surface in response to his / her own operation. can do. Therefore, at each movement detection point along the movement locus of the contact portion on the contact surface by the operation of the operator, the final ring-shaped display object KHB is displayed via the ring-shaped display object KHB in the middle, which is represented like an afterimage of the initial ring-shaped display object KHB. Since the annular display object KHB is displayed, the operator does not need to memorize the latest operation history along the movement locus one by one, and the operator is less likely to feel stress during operation.

By the way, even if the above-mentioned effect control program is controlled to increase the size of the final annular display object KHB in proportion to the maximum area of the contour area of the contact portion based on the contact state of the above-mentioned touch panel 480, for example. Good (final display control means, afterimage display control means, movement trajectory display means). Specifically, this effect control program relatively increases the size of the final annular display KHB when the contour area is relatively large, while it is final when the contour area is relatively small. The size of the annular display KHB is made relatively small. By doing so, since the size of the final annular display KHB is proportional to the pressing force of the contact surface by the operator, it is possible to determine after the fact how much this pressing force was from the operator's point of view. Can be recognized.

Instead or in combination, the effect control program controls, for example, the expansion mode of the final annular display KHB in proportion to the change in the contour area per unit time in the contact portion based on the contact state of the touch panel 480 described above. (Final display control means, afterimage display control means, movement locus display means). Specifically, when the change in the contour area per unit time is large, the size of the annular display KHB on the way is changed in a relatively short time, while the contour area per unit time. When the change is small, the size of the annular display KHB on the way is changed in a relatively long time. In this way, when the operator touches the contact surface in a relatively short time, the annular display KHB expands relatively quickly, while when the operator touches the contact surface in a relatively long time, the annular display is displayed. The object KHB expands relatively slowly, and not only can the reaction of the touch panel 480 according to the operation mode of the operator be inspected more accurately, but also the player operates the object in the real world. You will be able to get a feeling of operation that is closer to the feeling of operation at the time.

According to the pachinko gaming machine 1 of the present embodiment described above, it is possible to control the prize ball device 740 of FIG. 3 to dispense the gaming ball to the plate unit 300 (specifically, the upper plate 301) of FIG. can. The plate unit 300 (specifically, the upper plate 301) is arranged on the front side of the pachinko gaming machine 1. The upper plate side liquid crystal display device 470 of FIG. 7 to which the capacitance type touch panel 480 of FIG. 7 is attached is attached to the plate unit 300.

The pachinko gaming machine 1 further includes a peripheral control board 4140 of FIG. 16 and a touch panel control board 450 of FIG. The peripheral control board 4140 can control the display of the upper plate side liquid crystal display device 470. The touch panel control board 450 can detect the contact state of the touch panel 480. The peripheral control board 4140 is detected from the touch panel control board 450 every time 16 ms, which is a predetermined period, elapses in the touch panel process of step S1031 of the peripheral control unit steady process in the peripheral control unit power-on processing of FIG. 55. Based on the signal, the contact state of the touch panel 480 is set to be valid from the first detected contact portion to the N (N is an integer of 2 or more) th detected contact portion, and each contact portion is set to the touch panel 480. Coordinate values can be repeatedly acquired as the contact surface of. The peripheral control board 4140 has the coordinate values acquired when 16 ms, which is the previous predetermined period, has elapsed in the touch panel processing of step S1031 of the peripheral control unit steady processing in the peripheral control unit power-on processing of FIG. 55. It is possible to determine whether or not the coordinate values acquired when 16 ms, which is the predetermined period of this time, have elapsed, match the coordinate values. The peripheral control board 4140 is determined in advance by the touch panel process of step S1031 in the scheduler update process of step S1020 and the display data creation process of step S1030 in the peripheral control unit steady processing in the peripheral control unit power-on processing of FIG. 55. When the coordinate value acquired when the specified period of 16 ms has elapsed and the coordinate value acquired when the predetermined period of 16 ms has elapsed, the acquired coordinate value is used. Based on this, it is possible to impart a change due to contact with the touch panel 480 to the image displayed in the display area of the upper plate side liquid crystal display device 470.

Specifically, the controller 450ba of the touch panel controller IC450b of FIG. 17 issues, for example, a detection control start command for starting the detection control of the contact state of the touch panel 480 from the peripheral control board 4140 to the serial interface for the peripheral control board of FIG. When transmitted via 450b, a detection control program for detecting the contact state of the touch panel 480 is read out from the ROM 450bc of FIG. When various stored programs are copied, they are read from this RAM), and this read detection control program is started. When this detection control program is started, the controller 450ba transmits serial data for instructing the sensing position of the touch panel 480 from the sensing IC serial interface 450bg of FIG. 17 to the sensing IC 450d. The sensing IC 450d receives serial data at the serial interface 450da of FIG. 17, outputs the serial data to the decoder 450db of FIG. 17, and restores the sensing position data at the decoder 450db. The analog multiplexer 450dc of FIG. 17 opens and closes an electrical connection to the sensing position in the entire area of the touch panel 480 according to the sensing position data from the decoder 450db, and uses the value of the capacitance of the touch panel 480 at the sensing position as an analog signal. It is output to the sensing unit 450df of FIG. The controller 450ba of the touch panel controller IC450b outputs a synchronization signal from the synchronization signal output circuit 450bf of FIG. 17 to the sensing IC 450d, and when this synchronization signal is input to the synchronization signal input circuit 450de of the sensing IC 450d and transmitted to the sensing unit 450df, this is transmitted. With this as an opportunity, the sensing unit 450df opens and closes the electrical connection to the sensing position in the entire area of the touch panel 480 according to the sensing position data from the decoder 450db by the analog signal from the analog multiplexer 450dc, and the touch panel 480 at the sensing position. It is determined that it is the value of the electrostatic capacity and is output to the amplifier circuit 450e of FIG. The analog signal amplified via the amplifier circuit 450e is converted into a digital signal by the ADC 450bb of the touch panel controller IC450b of FIG. 17 and input to the controller 450ba.

The controller 450ba obtains a contact state detection value at the sensing position in the entire area of the touch panel 480 from the digital signal converted by the ADC 450bb, and associates the contact state detection value with the sensing position (X coordinate, Y coordinate) of the touch panel 480. By (that is, adding a sensing position), sensing data is created, and the created sensing data is serialized and transmitted from the peripheral control board serial interface 450bh to the peripheral control board 4140. The controller 450ba transmits serial data indicating the sensing position of the touch panel 480 from the serial interface 450bg for the sensing IC to the sensing IC 450d, outputs the synchronization signal from the synchronization signal output circuit 450bf to the sensing IC 450d, and is digitally converted by the ADC 450bb. Obtaining the contact state detection value at the sensing position in the entire area of the touch panel 480 from the signal, and linking the sensing position (X coordinate, Y coordinate) of the touch panel 480 to this contact state detection value (that is, adding the sensing position). By repeating the control of creating sensing data and serializing the created sensing data and transmitting it from the peripheral control board serial interface 450bh to the peripheral control board 4140, the entire area of the touch panel 480 is sensed and sensed. Data is transmitted to the peripheral control board 4140.

The peripheral control board 4140 that receives the sensing data in which the sensing position (X coordinate, Y coordinate) of the touch panel 480 is linked to the contact state detection value at the sensing position in the entire area of the touch panel 480 is the peripheral control unit shown in FIG. The peripheral control MPU4150a of the 4150 acquires the coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger based on the contact state detection value and the sensing position (X coordinate, Y coordinate). The position represented by the coordinate value is specified as a detection point. Specifically, the peripheral control MPU4150a of the peripheral control unit 4150 of the peripheral control board 4140 of FIG. 14 is the touch panel process of the previous time (that is, in step S1031 of the peripheral control unit steady processing in the peripheral control unit power-on processing of FIG. 55). , 16 ms ago) The coordinate values of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger obtained in the touch panel process and the center of the contact portion touched by the finger obtained in the touch panel process this time. It is determined whether or not the coordinate values of the contact surface of the touch panel 480 shown match with each other, and if they match, the position represented by the matching coordinate values is specified as a detection point. Even if the finger touching the touch panel 480 is being moved, if the finger is moved in an extremely short period of 16 ms, for example, 50 mm in 1 s, the 16 ms is 0.8 mm (0.05 mm). Since the moving distance is extremely short (/ ms × 16 ms), as described above, in this embodiment, the touch panel 480 is a type with 4.3 inches and a resolution of 10 × 20, and the resolution is low, and the finger touches 16 ms before. The coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion with the finger matches the coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger acquired in this touch panel processing. It will be.

For example, when the peripheral control MPU4150a determines, for example, that the touch panel 480 is touching only the index finger of the left hand (that is, touching one point), as shown in FIG. 18A, based on the sensing data, FIG. As shown in (b), P0 (x0, y0), which is a contact position of one point, is acquired as a coordinate value, and the position represented by this coordinate value is specified as a detection point, while FIG. 18 (c) shows. As shown in FIG. 18, for example, when it is determined that the index finger and the middle finger of the left hand are touching (that is, touching two points) on the touch panel 480, as shown in FIG. A certain P0 (x0, y0) and P1 (x1, y1) are acquired as coordinate values, and the position represented by these coordinate values is specified as a detection point.

The peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 of FIG. 14 is transmitted from the touch panel control board 450 in the reception command processing of step 1022 of the peripheral control unit steady processing in the peripheral control unit power-on processing of FIG. 55. Various data (for example, sensing data in which the sensing position (X coordinate, Y coordinate) of the touch panel 480 is linked to the contact state detection value at the sensing position in the entire area of the touch panel 480) is received in the touch panel process of step S1031. The various data received are analyzed, and based on the various data transmitted from the touch panel control board 450, the screen generation schedule data, the light emission mode generation schedule data, the sound generation schedule data, and the electrical drive source schedule are analyzed. Data or the like is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and set in the schedule data storage area of the peripheral control RAM 4150c in 4150cae. When screen data is input from the peripheral control MPU4150a, the sound source built-in VDP4160a has one screen (one frame) displayed on the upper plate side liquid crystal display device 470 in the built-in VRAM based on the input screen data. The drawing data is generated, and the image data for the upper plate side liquid crystal display device 470 is output from the channel CH2 to the upper plate side liquid crystal display device 470.

As a result, for example, as shown in FIG. 77, when the volume adjustment icon OCI displayed in the display area of the liquid crystal display device 470 on the upper plate side is slid along the volume scale VSC with the finger F on the contact surface of the touch panel 480. , The annular display object KHB is displayed in the display area of the upper plate side liquid crystal display device 470 along the movement locus of the contact portion based on the contact state of the finger F. That is, it is possible to impart a change due to contact with the touch panel 480 to the image displayed in the display area of the upper plate side liquid crystal display device 470 based on the contact state of the finger F.

As described above, the peripheral control MPU4150a of the peripheral control unit 4150 of the peripheral control board 4140 is effective from the first detected contact portion to the second detected contact portion every 16 ms which is a predetermined period elapses. And, the coordinate values are repeatedly acquired with each contact part as the contact surface of the touch panel 480, and the coordinate values acquired when 16 ms, which is the previous predetermined period, has elapsed, and the predetermined period this time. Since it is possible to determine whether or not the coordinate values acquired when a certain 16 ms have elapsed match, the coordinate values acquired when the previous predetermined period of 16 ms has elapsed and this time. When the coordinate values acquired when the predetermined period of 16 ms has elapsed and the coordinate values match, the reliability of the coordinate values can be improved. Thereby, based on the highly reliable coordinate values, it is possible to impart a change due to contact with the touch panel 480 to the image displayed in the display area of the liquid crystal display device 470 on the upper plate side. Therefore, the pachinko gaming machine 1 of the present invention can provide a player with a novel effect.

Further, the pachinko gaming machine 1 can invalidate three or more contact positions detected by the sensing IC 450d on the touch panel control board 450 of FIG. Specifically, when the peripheral control MPU4150a determines that three or more points are touching the touch panel 480, the contact surface determined as the first point and the second point in the sensing order by a predetermined algorithm are used. The determined contact surface is valid, whereas the contact surface determined as the third point, the contact surface determined as the fourth point, ..., The contact surface determined after the third point is invalidated. The contact positions of the first and second points (P0 (x0, y0) and P1 (x1, y1)) are acquired as coordinate values, and the position represented by these coordinate values is specified as a detection point. It has become. For example, as shown in FIG. 19E, when the touch panel 480 is touched in the order of the index finger, the middle finger, and the ring finger of the left hand, the peripheral control MPU4150a touches the touch panel 480 with the index finger, the middle finger, and the ring finger of the left hand. When it is determined that the finger is (that is, touching three points), the position of the contact surface determined as the first point in the sensing order (that is, that is, as shown in FIG. 19 (f)) is determined by a predetermined algorithm. The contact position P0 (x0, y0) of the index finger of the left hand and the position of the contact surface determined as the second point (that is, the contact position P1 (x1, y2) of the middle finger of the left hand) are valid (that is, the left hand). The contact position P0 (x0, y0) of the index finger of the left hand and the contact position P1 (x1, y2) of the middle finger of the left hand are each enabled points. ), The position of the contact surface determined as the third point (that is, the contact position P2 (x2, y2) of the ring finger of the left hand) is invalidated (that is, the contact position P2 (x2, y2) of the ring finger of the left hand is invalid. The contact positions of the first and second points (P0 (x0, y0) and P1 (x1, y1))) are acquired as coordinate values, respectively. The position represented by the coordinate value of is specified as a detection point.

In this way, even if the peripheral control MPU4150a detects three or more contact positions in the entire area of the touch panel 480, the first detected contact position and the second detected contact position are obtained by a predetermined algorithm. Since only the contact positions of two points of and can be acquired as coordinate values, the contact positions of three or more points can be invalidated. As a result, the number of fingers required by the player to operate the touch panel 480 can be limited to a maximum of two, so that the operation of the touch panel 480 does not impose a burden on the player.

[16. Another example]
It goes without saying that the present invention is not limited to the above-described embodiment, and can be carried out in various embodiments as long as it belongs to the technical scope of the present invention.

For example, in the above-described embodiment, the peripheral control MPU4150a of the peripheral control unit 4150 of the peripheral control board 4140 has two points, a contact position detected first and a contact position detected second by a predetermined algorithm. It was configured so that only the contact position of can be acquired as a coordinate value, but the contact positions of three points from the first detected contact position to the third detected contact position are acquired as the maximum coordinate values. It may be configured so that the contact positions of four points from the first detected contact position to the fourth detected contact position can be acquired as coordinate values at the maximum. May be good. In this way, the peripheral control MPU4150a acquires the coordinates from the first detected contact position to the N (N is an integer of 2 or more, 3 or 4) th detected contact position as coordinate values, respectively, in advance of the previous time. When the coordinate value acquired when the predetermined period of 16 ms has elapsed and the coordinate value acquired when the predetermined period of 16 ms has elapsed match, the reliability of the coordinate value is determined. Can be enhanced. Thereby, based on the highly reliable coordinate values, it is possible to impart a change due to contact with the touch panel 480 to the image displayed in the display area of the liquid crystal display device 470 on the upper plate side. Therefore, the gaming machine of the present invention can provide a player with a novel effect. Then, by changing the number of fingers for detecting the contact position from two to three or four, the degree of freedom of the player's operation of the touch panel 480 can be further increased, and the effect corresponding to these operations can be achieved. By providing it to the player, it is possible to give more variation to the production, so it is difficult to give the player a feeling of boredom.

Further, in the above-described embodiment, the pachinko gaming machine 1 has been described as an example, but the gaming machine to which the present invention can be applied is not limited to the pachinko gaming machine, and a gaming machine other than the pachinko gaming machine, for example, a slot machine or It can also be applied to a fusion game machine (a machine that plays a slot game using a game ball), which is a fusion of a pachinko game machine and a slot machine.

1 ... Pachinko game machine (game machine), 2 ... Outer frame, 3 ... Main body frame, 4 ... Game board, 5 ... Door frame, 192 ... Handle relay terminal board, 300 ... Dish unit (dish unit), 450 ... Touch panel control Board (contact state detecting means), 470 ... LCD display device on the upper plate side (display device), 480 ... Touch panel (touch panel), 650 ... Ball launcher, 740 ... Prize ball device, 784 ... External terminal board, 851 ... Power supply board , 860a ... Operation switch, 860b ... Error LED display, 1100 ... Game area, 1900 ... Game board side liquid crystal display device, 4100 ... Main control board, 4100a ... Main control MPU, 4110 ... Payout control board, 4120 ... Payout control unit 4,120a ... Disbursement control MPU, 4140 ... Peripheral control board (display control means), 4150 ... Peripheral control unit, 4160 ... Liquid crystal and sound control unit, 4165 ... RTC control unit, 4170 ... Lamp drive board, 4180 ... Motor drive board.

Claims (1)

It is a gaming machine equipped with a gaming area where gaming balls can flow down.
The front component that constitutes the front side of the gaming machine,
A main control means for controlling the progress of the game based on the entry of the ball into the starting port provided in the game area, and
Production control means to control the production related to the game,
A specific operation unit provided below the game area of the front component and operated by the player, and a specific operation unit.
A calling operation executing means for executing a calling operation capable of calling a staff member of the game hall by operating the specific operation unit by the player, and a calling operation executing means.
A call notification display execution means for displaying a call notification to inform the player that it is possible to call a staff member of the game hall by operating the specific operation unit.
Equipped with
By displaying the call notification, it is possible to make the player recognize that it is possible to call the staff of the game hall by the operation of the specific operation unit provided in the game machine instead of the external device.
The gaming machine characterized in that the call notification display executing means is controlled by the effect control means instead of the main control means.

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