JP2022019771A - Detection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a detection device with higher detecting performance.

SOLUTION: The detection device includes a substrate, an organic material layer provided to the substrate and forming an optical sensor, a plurality of detection electrodes provided between the substrate and the organic material layer, a first switching element provided between the respective detection electrodes, a second switching element different from the first switching element, a gate line connected to the first switching element and the second switching element and extending in a first direction, a signal line connected to the first switching element and extending in a second direction intersecting with the first direction, a reference signal line connected to the second switching element and supplying a reference signal that is a fixed potential to the detection electrode, and a driving circuit that supplies a gate driving signal to the gate line. The first switching element is a TFT with a first conductivity type, and the second switching element is a TFT with a second conductivity type.

SELECTED DRAWING: Figure 1

COPYRIGHT: (C)2022,JPO&INPIT

Description

The present invention relates to a detection device.

In recent years, a detection device in which a plurality of sensors using an organic material are provided on a flexible substrate has been known (see, for example, Patent Document 1). In such a sensor, for example, the signal output from the detection electrode changes according to a predetermined physical quantity such as the amount of light emitted from the organic material and the temperature.

Japanese Patent Publication No. 2008-525962

In a sensor using an organic material, the change in the output signal with respect to the input light, heat, etc. may be weak. In this case, it is necessary to increase the area of each sensor, which makes it difficult to achieve high definition. Further, when the change in the output signal is weak, it may be difficult to separate the output signal between the plurality of sensors.

An object of the present invention is to provide a detection device capable of improving detection performance.

The detection device according to one aspect of the present invention includes a substrate, an organic material layer provided on the upper side of the substrate and at least at a position overlapping the detection region, and the substrate and the organic material layer in a direction perpendicular to the substrate. A plurality of detection electrodes provided between the two, a first switching element provided in each of the plurality of detection electrodes, and a plurality of gate wires connected to the first switching element and extending in the first direction. , A plurality of signal lines connected to the first switching element and extending in the second direction intersecting the first direction, and a gate drive signal whose potential is determined for each of the plurality of gate lines based on a predetermined code. Is provided with a drive circuit for supplying the first switching element to the first switching element via the gate wire.

FIG. 1 is a plan view showing a detection device according to the first embodiment. FIG. 2 is a block diagram showing a configuration example of the detection device according to the first embodiment. FIG. 3 is a plan view schematically showing the backplane of the detection device. FIG. 4 is a plan view schematically showing the organic sensor layer included in the detection device. FIG. 5 is a cross-sectional view taken along the line VV'of FIGS. 3 and 4. FIG. 6 is a cross-sectional view taken along the line VI-VI'of FIGS. 3 and 4. FIG. 7 is a circuit diagram showing a drive circuit for one detection electrode. FIG. 8 is a circuit diagram showing AFE. FIG. 9 is a timing waveform diagram showing an example of AFE operation. FIG. 10 is a circuit diagram showing an arrangement of detection electrodes. FIG. 11 is an explanatory diagram for explaining an operation example of code division selection drive by the gate line drive circuit. FIG. 12 is an explanatory diagram for explaining an operation example of the code division selection drive by the signal line selection circuit. FIG. 13 is a table showing an example of the detection operation by the gate line drive circuit and the signal line selection circuit in the first to third periods. FIG. 14 is a table showing an example of the detection operation by the gate line drive circuit and the signal line selection circuit in the 4th to 7th periods. FIG. 15 is a block diagram showing a configuration example of a sensor unit, a gate line drive circuit, and a signal line selection circuit. FIG. 16 is a block diagram of a gate line drive circuit. FIG. 17 is a timing waveform diagram showing various control signals output from the control signal generation circuit. FIG. 18 is a circuit diagram showing an example of the first code generation circuit. FIG. 19 is a table showing the relationship between the first control signal and the first partial selection signal. FIG. 20 is a circuit diagram showing an example of the second code generation circuit. FIG. 21 is a table showing the relationship between the second control signal and the inversion control signal and the second partial selection signal. FIG. 22 is a circuit diagram showing an example of a third code generation circuit. FIG. 23 is a diagram showing an example of a pattern code generated by the third code generation circuit when the inversion control signal has a high level voltage. FIG. 24 is a diagram showing an example of a pattern code generated by the third code generation circuit when the inversion control signal has a low level voltage. FIG. 25 is a table showing the relationship between the first control signal, the second control signal, and the inversion control signal. FIG. 26 is a circuit diagram showing a signal line selection circuit. FIG. 27 is a plan view showing the relationship between the detection electrode, the first switching element, and the second switching element. FIG. 28 is a cross-sectional view showing a schematic cross-sectional configuration of the first switching element. FIG. 29 is a plan view showing the detection device according to the second embodiment. FIG. 30 is a block diagram showing a configuration example of the sensor unit, the gate line drive circuit, and the signal line selection circuit according to the second embodiment. FIG. 31 is a timing waveform diagram showing an operation example of the detection device according to the second embodiment. FIG. 32 is a circuit diagram showing the AFE and the inverting circuit according to the third embodiment. FIG. 33 is a plan view showing the detection device according to the fourth embodiment. FIG. 34 is a circuit diagram showing a drive circuit for one detection region. FIG. 35 is a circuit diagram showing a reset circuit. FIG. 36 is a cross-sectional view showing a schematic cross-sectional configuration of the detection device according to the fifth embodiment. FIG. 37 is a plan view schematically showing the detection device according to the fifth embodiment. FIG. 38 is a plan view showing the relationship between the detection electrode, the drive electrode, the eighth switching element, and the ninth switching element. FIG. 39 is an enlarged plan view showing the region C4 of FIG. 38.

An embodiment (embodiment) for carrying out the invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiments. In addition, the components described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the components described below can be combined as appropriate. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention, which are naturally included in the scope of the present invention. Further, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is just an example, and the interpretation of the present invention is used. It is not limited. Further, in the present specification and each figure, the same elements as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and detailed description thereof may be omitted as appropriate.

(First Embodiment)
FIG. 1 is a plan view showing a detection device according to the first embodiment. FIG. 2 is a block diagram showing a configuration example of the detection device according to the first embodiment. As shown in FIGS. 1 and 2, the detection device 1 includes a sensor unit 10, a gate line drive circuit 15, and a signal line selection circuit 16.

As shown in FIG. 1, the control board 101 is electrically connected to the sensor unit 10 via the flexible printed board 71. The flexible printed circuit board 71 is provided with an analog front end circuit (hereinafter referred to as AFE (Analog Front End) 48. The control board 101 is provided with a control circuit 102 and a power supply circuit 103. The control circuit 102 is provided with a control circuit 102. For example, it is an FPGA (Field Programmable Gate Array). The control circuit 102 supplies a control signal to the sensor unit 10, the gate line drive circuit 15, and the signal line selection circuit 16 to control the detection operation. The power supply circuit 103 controls the detection operation. A voltage signal such as a power supply voltage VDD is supplied to the sensor unit 10 and the gate line drive circuit 15.

As shown in FIG. 2, the detection device 1 further includes a detection control unit 11 and a detection unit 40. A part or all of the functions of the detection control unit 11 are included in the control circuit 102. Further, in the detection unit 40, a part or all of the functions other than the AFE48 are included in the control circuit 102.

The sensor unit 10 is an optical sensor having an organic material layer 31 (see FIG. 5). The characteristics (for example, voltage-current characteristics and resistance value) of the organic material layer 31 included in the sensor unit 10 change according to the emitted light. The sensor unit 10 outputs a signal corresponding to the amount of emitted light to the signal line selection circuit 16. Further, the sensor unit 10 detects according to the first gate drive signal VGH and the second gate drive signal VGL supplied from the gate line drive circuit 15 by code division multiplexing drive (hereinafter referred to as CDM (Code Division Multiplexing) drive). I do. That is, a plurality of detection electrodes 24 (see FIG. 5) are simultaneously selected by the operation of the gate wire drive circuit 15.

The detection control unit 11 is a circuit that supplies control signals to the gate line drive circuit 15, the signal line selection circuit 16, and the detection unit 40, respectively, and controls their operations. The detection control unit 11 includes a drive unit 11a and a clock signal output unit 11b. The drive unit 11a supplies the power supply voltage VDD to the gate line drive circuit 15. The detection control unit 11 supplies various control signals Vctrl to the gate line drive circuit 15 based on the clock signal of the clock signal output unit 11b.

The gate line drive circuit 15 is a circuit that simultaneously selects a plurality of gate line GCLs (see FIG. 7) based on various control signals Vctrl. The gate line drive circuit 15 supplies the first gate drive signal VGH or the second gate drive signal VGL to the plurality of selected gate line GCLs. As a result, the gate line drive circuit 15 selects a plurality of detection electrodes 24 connected to the gate line GCL. The sensor unit 10 can realize CDM drive by differentiating the selection state of the detection electrode 24 by the gate wire drive circuit 15.

The signal line selection circuit 16 is a switch circuit that simultaneously selects a plurality of signal line SGLs (see FIG. 7). The signal line selection circuit 16 drives the CDM based on the signal line selection signal Vhsel supplied from the detection control unit 11. As a result, the signal line selection circuit 16 selects a plurality of detection electrodes 24 connected to the signal line SGL. The signal line selection circuit 16 outputs the first output signal Svh (1) and the second output signal Svh (2) to the detection unit 40. The first output signal Svh (1) and the second output signal Svh (2) are signals in which the detection signals of the plurality of selected detection electrodes 24 are integrated.

The detection unit 40 is a circuit that detects a predetermined physical quantity based on the control signal supplied from the detection control unit 11 and the first output signal Svh (1) and the second output signal Svh (2) in the CDM drive. be. The detection unit 40 includes an AFE 48, a signal processing unit 44, a coordinate extraction unit 45, a storage unit 46, and a detection timing control unit 47. The detection timing control unit 47 controls the AFE 48, the signal processing unit 44, and the coordinate extraction unit 45 to operate in synchronization with each other based on the control signal supplied from the detection control unit 11. When it is not necessary to distinguish between the first output signal Svh (1) and the second output signal Svh (2) in the following description, it is simply referred to as an output signal Svh.

The AFE 48 is a signal processing circuit having at least the functions of the detection signal amplification unit 42 and the A / D conversion unit 43. The detection signal amplification unit 42 amplifies the output signal Svh. The A / D conversion unit 43 converts the analog signal output from the detection signal amplification unit 42 into a digital signal.

The signal processing unit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the AFE 48. The signal processing unit 44 receives the first output signal Svh (1) and the second output signal Svh (2) via the signal line selection circuit 16, and calculates the third output signal Svh (3). The signal processing unit 44 receives the calculated third output signal Svh (3) and performs decoding processing based on a predetermined code. The signal processing unit 44 can also perform a process of extracting a signal (absolute value | ΔV |) of the difference between the decoded signals. The signal processing unit 44 can compare the absolute value | ΔV | with a predetermined threshold voltage and detect the amount of light emitted to the sensor unit 10.

The storage unit 46 temporarily stores the calculated third output signal Svh (3). The storage unit 46 may be, for example, a RAM (Random Access Memory), a register circuit, or the like.

The coordinate extraction unit 45 calculates the sensor coordinates based on the difference signal of the decoding signal, and outputs the obtained sensor coordinates as the sensor output Vo. The coordinate extraction unit 45 may output the decoding signal as the sensor output Vo without calculating the sensor coordinates.

Next, the detailed configuration of the detection device 1 will be described. FIG. 3 is a plan view schematically showing the backplane of the detection device. FIG. 4 is a plan view schematically showing the organic sensor layer included in the detection device. FIG. 5 is a cross-sectional view taken along the line VV'of FIGS. 3 and 4. FIG. 6 is a cross-sectional view taken along the line VI-VI'of FIGS. 3 and 4.

As shown in FIG. 5, the detection device 1 includes a backplane 2 and an organic sensor layer 3. The organic sensor layer 3 is arranged so as to face the surface of the backplane 2 in a direction perpendicular to the surface. The backplane 2 is a drive circuit board that drives a sensor for each predetermined detection region.

The backplane 2 includes a substrate 21, a TFT layer 22, an insulating layer 23, and a detection electrode 24. The substrate 21 is a glass substrate having a translucency capable of transmitting visible light. Alternatively, the substrate 21 may be a translucent resin substrate or a resin film made of a resin such as polyimide. The TFT layer 22 is provided on the substrate 21. The TFT layer 22 is provided with circuits such as a gate line drive circuit 15 and a signal line selection circuit 16. Further, in the TFT layer 22, various wirings such as a first switching element Tr such as a TFT (Thin Film Transistor) and a second switching element xTr (see FIG. 10), a gate line GCL, and a signal line SGL (see FIG. 10) are provided. Is provided.

The detection electrodes 24 are arranged in a matrix on the upper side of the substrate 21. The detection electrode 24 is provided between the substrate 21 and the organic material layer 31 of the organic sensor layer 3. For the detection electrode 24, for example, a conductive material having translucency such as ITO (Indium Tin Oxide) is used. An insulating layer 23 is provided between the detection electrode 24 and the TFT layer 22. The insulating layer 23 is an inorganic insulating layer. As the insulating layer 23, for example, an oxide such as silicon oxide (SiO ₂ ) or a nitride such as silicon nitride (SiN) is used. The flexible printed circuit board 71 is connected to the frame region GA of the board 21. The detection electrode 24 is electrically connected to the flexible printed circuit board 71 via the signal line SGL and the signal line selection circuit 16.

In the description of the detection device 1, the direction from the substrate 21 toward the organic sensor layer 3 in the direction perpendicular to the surface of the substrate 21 is referred to as “upper side”. The direction from the organic sensor layer 3 to the substrate 21 is defined as the “lower side”. Further, the “planar view” indicates a case where the substrate 21 is viewed from a direction perpendicular to the surface of the substrate 21.

The organic sensor layer 3 includes an organic material layer 31, a driving electrode 32, and a protective layer 33. The organic material layer 31 is provided on the plurality of detection electrodes 24. As the organic material layer 31, an organic material whose characteristics (for example, voltage-current characteristics and resistance value) change according to the irradiated light is used. Examples of the organic material layer 31 include C ₆₀ (fullerene), PCBM (phenyl C61-butyric acid methyl ester), CuPc (copper phthalocyanine), and F ₁₆ CuPc (phenyl C61-butyric acid methyl ester), which are low molecular weight organic materials. Fluorinated copper phthalocyanine), rubrene (rubrene: 5,6,11,12-tetraphenyltetracene), PDI (a derivative of Perylene) and the like can be used. The organic material layer 31 can be formed by a thin film deposition (Dry Process) using these small molecule organic materials. In this case, the organic material layer 31 may be, for example, a laminated film of CuPc and F ₁₆ CuPc, or a laminated film of rubrene and C ₆₀ . The organic material layer 31 can also be formed by a coating type (Wet Process). In this case, as the organic material layer 31, a material that is a combination of the above-mentioned low molecular weight organic material and high molecular weight organic material is used. As the polymer organic material, for example, P3HT (poly (3-hexylthiophene)), F8BT (F8-alt-benzothiadiazole) and the like can be used. The organic material layer 31 can be a film in which P3HT and PCBM are mixed, or a film in which F8BT and PDI are mixed.

The drive electrode 32 is provided so as to face the plurality of detection electrodes 24 with the organic material layer 31 interposed therebetween in a direction perpendicular to the surface of the substrate 21. An organic material layer 31 is provided between the drive electrode 32 and the detection electrode 24. The drive electrode 32 is in contact with the upper surface of the organic material layer 31, and the detection electrode 24 is in contact with the lower surface of the organic material layer 31. For the drive electrode 32, for example, a metal material such as silver (Ag) or aluminum (Al) is used. Alternatively, the drive electrode 32 may be an alloy material containing at least one of these metal materials. The protective layer 33 is provided so as to cover the drive electrode 32. The protective layer 33 is a passivation film and is provided to protect the drive electrode 32 and the organic material layer 31.

As shown in FIG. 3, the plurality of detection electrodes 24 are provided in a matrix in the detection region AA of the substrate 21. In other words, the plurality of detection electrodes 24 are arranged in the first direction Dx and in the second direction Dy. Here, the detection area AA is an area for detecting the detection device 1. The frame area GA is an area outside the detection area AA.

The first direction Dx is one direction in a plane parallel to the substrate 21, for example, a direction parallel to the gate line GCL (see FIG. 10). Further, the second direction Dy is one direction in a plane parallel to the substrate 21 and is a direction orthogonal to the first direction Dx. The second direction Dy may intersect with the first direction Dx without being orthogonal to each other.

Various circuits such as the gate line drive circuit 15 and the signal line selection circuit 16 are provided in the frame region GA of the substrate 21. The gate line drive circuit 15 is provided on the side of the frame region GA along the second direction Dy. Further, the signal line selection circuit 16 is provided on the side of the frame region GA along the first direction Dx. The signal line selection circuit 16 is provided between the detection area AA and the flexible printed circuit board 71.

Further, the frame region GA of the substrate 21 is provided with a plurality of terminals 25 and drive electrode connection terminals 29. The flexible printed board 71 is connected to a plurality of terminals 25. The drive electrode connection terminal 29 is a terminal for supplying the drive signal VDD_ORG (see FIG. 15) to the drive electrode 32. The drive electrode connection terminal 29 is connected to the flexible printed substrate 71. As a result, the drive signal VDD_ORG is supplied to the drive electrode connection terminal 29 from the control board 101 (see FIG. 1).

As shown in FIG. 4, the organic material layer 31, the driving electrode 32, and the protective layer 33 are provided up to the outer periphery of the frame region GA and are provided so as to overlap each other. In other words, the organic material layer 31 and the driving electrode 32 are provided at least in a region overlapping the detection region AA shown in FIG. As a result, the organic material layer 31 and the drive electrode 32 are provided over the plurality of detection electrodes 24, and have a portion that overlaps the plurality of detection electrodes 24 and a portion that does not overlap the plurality of detection electrodes 24. The organic material layer 31 is formed by coating, for example, by inkjet printing or the like. In the present embodiment, the organic material layer 31 is a high resistance material, and the distance between the adjacent detection electrodes 24 is sufficiently large with respect to the thickness of the organic material layer 31. Therefore, in each of the detection electrodes 24, a current flows in the vertical direction between the detection electrodes 24 and the drive electrodes 32, and the current flowing between the adjacent detection electrodes 24 is suppressed. As a result, the plurality of detection electrodes 24 each function as individual sensors.

A recess 3a recessed inward is provided on the outer periphery of the organic material layer 31, the drive electrode 32, and the protective layer 33. The recess 3a is provided at a position where it overlaps with the plurality of terminals 25. As a result, the plurality of terminals 25 are exposed from the organic material layer 31, the drive electrode 32, and the protective layer 33, and are connected to the flexible printed substrate 71.

Further, the organic material layer 31 is provided with an opening 31a at a position overlapping with the drive electrode connection terminal 29. As shown in FIG. 6, the drive electrode connection terminal 29 is provided on the substrate 21 via the insulating layer 25A. The drive electrode connection terminal 29 is provided in the same layer as the signal line SGL. A hard coat layer 25B and an insulating layer 23 are provided on the insulating layer 25A. The hard coat layer 25B and the insulating layer 23 are provided with openings 25Ba and 23a at positions overlapping with the drive electrode connection terminal 29. The opening 31a of the organic material layer 31 is provided at a position overlapping the openings 25Ba and 23a.

The connection electrode 34 is provided at a position overlapping the opening 31a of the organic material layer 31. As a result, the connection electrode 34 comes into contact with the drive electrode connection terminal 29. Further, the drive electrode 32 and the protective layer 33 are also provided at positions overlapping with the opening 31a. With such a configuration, the drive electrode 32 is electrically connected to the drive electrode connection terminal 29 via the opening 31a. A drive signal VDD_ORG is supplied to the drive electrode 32 from the control substrate 101 (see FIG. 1) via the flexible printed substrate 71 and the drive electrode connection terminal 29.

Next, the detection operation of the detection device 1 will be described. FIG. 7 is a circuit diagram showing a drive circuit for one detection electrode. FIG. 8 is a circuit diagram showing AFE. FIG. 9 is a timing waveform diagram showing an example of AFE operation.

As shown in FIG. 7, the backplane 2 (see FIG. 5) has wirings such as a detection electrode 24, a first switching element Tr, a second switching element xTr, a signal line SGL, a gate line GCL, and a reference signal line COM. It is formed. The first switching element Tr and the second switching element xTr are provided corresponding to each of the detection electrodes 24. The signal line SGL is a wiring that outputs the detection signal of each detection electrode 24 to the AFE 48 via the signal line selection circuit 16 (see FIG. 3). The gate line GCL is a wiring for supplying the first gate drive signal VGH and the second gate drive signal VGL that drive the first switching element Tr and the second switching element xTr. The reference signal line COM is a wiring for supplying the reference signal Vcom (see FIG. 15) to the detection electrode 24.

The first switching element Tr is composed of a thin film transistor, and in this example, it is composed of an n-channel MOS (Metal Oxide Semiconductor) type TFT. In this example, the second switching element xTr is composed of a p-channel MOS type TFT. That is, when the same first gate drive signal VGH is supplied, the first switching element Tr is turned on and the second switching element xTr is turned off. Further, when the same second gate drive signal VGL is supplied, the first switching element Tr is turned off and the second switching element xTr is turned on. The first gate drive signal VGH is a voltage signal having a higher potential than the second gate drive signal VGL.

In one detection electrode 24, the source of the first switching element Tr is connected to the signal line SGL, the gate is connected to the gate line GCL, and the drain is connected to the detection electrode 24. The drain of the second switching element xTr is connected to the reference signal line COM, the gate is connected to the gate line GCL, and the source is connected to the detection electrode 24. As shown in FIG. 7, the organic material layer 31 is represented equivalent to a diode element. Further, in the present embodiment, the detection electrode 24 is the anode and the drive electrode 32 is the cathode.

When the gate line drive circuit 15 supplies the first gate drive signal VGH to the gate line GCL, the first switching element Tr is turned on. The first switching element Tr connects the detection electrode 24 and the signal line SGL. As a result, the detection electrode 24 is selected as the detection target. When the drive signal VDD_ORG is supplied to the drive electrode 32, a predetermined current Ifh flows through the organic material layer 31. The current Ifh changes based on the characteristic change of the organic material layer 31 according to the irradiated light. The plurality of detection electrodes 24 output the current Ifh from the organic material layer 31 to the signal line SGL as an output signal Svh. On the other hand, the second switching element xTr is turned off by the first gate drive signal VGH. Therefore, the current Idh flowing from the detection electrode 24 to the reference signal line COM is suppressed. In this way, the sensor unit 10 changes the signal (current Ifh) output from the detection electrode 24 according to the amount of light emitted to the organic material layer 31. As a result, the detection device 1 can detect the light.

When the gate line drive circuit 15 supplies the second gate drive signal VGL to the gate line GCL, the first switching element Tr is turned off. As a result, the current Idl flowing from the detection electrode 24 to the signal line SGL is suppressed, and the detection electrode 24 becomes a non-detection target. On the other hand, the second switching element xTr is turned on. The second switching element xTr connects the detection electrode 24 and the reference signal line COM. Therefore, a current Ifl flows from the detection electrode 24 to the reference signal line COM. A reference signal Vcom is supplied to the reference signal line COM from the control board 101. The reference signal Vcom is a voltage signal having a fixed potential. The reference signal Vcom can be, for example, a ground potential. As a result, fluctuations in the potential of the detection electrode 24 to be non-detected are suppressed.

Polysilicon or oxide semiconductors are used as the material of the semiconductor layer of the first switching element Tr and the second switching element xTr. For the semiconductor layer, for example, Low Temperature Polycrystalline Silicon (LTPS) is used. The first switching element Tr and the second switching element xTr using low-temperature polysilicon can be manufactured at a process temperature of 600 ° C. or lower. Therefore, circuits such as the gate line drive circuit 15 and the signal line selection circuit 16 can be formed simultaneously on the same substrate as the first switching element Tr and the second switching element xTr. The detection device 1 has a first switching element Tr and a second switching element xTr. Therefore, when one of the first switching element Tr and the second switching element xTr is turned on, the other is turned off, and the leak current can be suppressed.

As shown in FIG. 8, the AFE 48 has an amplifier 481, a capacitance Cf, a first switch SW1 and a second switch SW2. In FIG. 8, the second switching element xTr and the reference signal line COM are omitted. The first switch SW1 is a switch that controls the detection timing based on the control signal from the detection control unit 11 (see FIG. 2). The second switch SW2 is a switch that resets the AFE48 based on the control signal from the detection control unit 11 (see FIG. 2).

As shown in FIG. 8, a current Ifh flows from the detection electrode 24 to the signal line SGL. AFE48 converts fluctuations in current Ifh into fluctuations in voltage. Then, the obtained voltage value is integrated and output as a sensor output Vo. The signal processing unit 44 (see FIG. 2) can compare the amplitude (| ΔV |) of the output signal Svh with a predetermined threshold voltage and detect the amount of light emitted to the sensor unit 10.

As shown in FIG. 9, during the non-detection period to off, the first switch SW1 is turned off and the AFE48 is cut off from the signal line SGL. Further, in the non-detection period to off, the second switch SW2 is turned on. As a result, AFE48 is reset and the output signal Svh becomes a potential equal to the ground potential GND.

During the detection period ton, the first switch SW1 is turned on and the AFE48 is connected to the signal line SGL. Further, in the detection period ton, the second switch SW2 is turned off. As a result, the electric charge moves to the capacitance Cf, and the amplitude (| ΔV |) of the sensor output Vo becomes large. By repeating the non-detection period ton and the detection period ton at a predetermined frequency, the detection device 1 can detect the light.

Next, the circuit configuration of the plurality of detection electrodes 24 will be described. FIG. 10 is a circuit diagram showing an arrangement of detection electrodes. In addition, in FIG. 10 and the like, in order to make the explanation easy to understand, the detection electrodes 24 arranged in a matrix in 4 rows and 4 columns will be described as an example, but the description is not limited thereto. For example, a large number of detection electrodes 24 are arranged in 256 rows and 256 columns. Further, in FIG. 10, four gate lines GCL (1), GCL (2), GCL (3), GCL (4), two reference signal lines COM (1), COM (2) and four signal lines SGL. (1), SGL (2), SGL (3), SGL (4) are shown. When it is not necessary to distinguish between the gate line GCL (1), GCL (2), GCL (3), and GCL (4) in the following description, the gate line GCL is simply represented. Similarly, it may be expressed as a reference signal line COM and a signal line SGL.

A plurality of gate lines GCL and a plurality of signal lines SGL are provided so as to intersect with each other. A plurality of gate lines GCL and a plurality of reference signal lines COM are provided so as to intersect with each other. The gate line GCL, the signal line SGL, and the reference signal line COM are partitioned in a matrix. The detection electrode 24 is arranged in a region surrounded by the gate line GCL, the signal line SGL, and the reference signal line COM. Each of these one compartment areas functions as a sensor.

Here, the plurality of detection electrodes 24 arranged in the first direction Dx are referred to as a first detection electrode block BKx. The first detection electrode blocks BKx (1), BKx (2), BKx (3), and BKx (4) are arranged in the second direction Dy. A plurality of first switching elements Tr and second switching element xTr provided in the first detection electrode block BKx (1) are connected to a common gate line GCL (1). A plurality of first switching elements Tr and second switching element xTr provided in the first detection electrode block BKx (2) are connected to a common gate line GCL (2). The same applies to the first detection electrode block BKx (3) and the first detection electrode block BKx (4). The gate line GCL (1), GCL (2), GCL (3), and GCL (4) are each connected to the gate line drive circuit 15.

The signal line SGL is provided for each detection electrode 24 arranged in the first direction Dx. Here, a plurality of detection electrodes 24 arranged in the second direction Dy along the signal line SGL are referred to as a second detection electrode block BKY. The second detection electrode blocks BKy (1), BKy (2), BKy (3), and BKy (4) are arranged in the first direction Dx. A plurality of first switching elements Tr provided in the second detection electrode block BKy (1) are connected to a common signal line SGL (1). A plurality of first switching elements Tr provided in the second detection electrode block BKy (2) are connected to a common signal line SGL (2). The same applies to the second detection electrode blocks BKy (3) and BKy (4). That is, the signal line SGL is provided for each second detection electrode block BKy. The signal lines SGL (1), SGL (2), SGL (3), and SGL (4) are each connected to the signal line selection circuit 16. The reference signal line COM is provided between the detection electrodes 24 adjacent to the first direction Dx. The detection electrodes 24 adjacent to each other with the reference signal line COM interposed therebetween are connected to a common reference signal line COM via a second switching element xTr provided therein.

The gate line drive circuit 15 supplies the first gate drive signal VGH and the second gate drive signal VGL whose potentials are determined for each gate line GCL based on a predetermined code to each gate line GCL. As a result, the gate line drive circuit 15 is driven to select one or more gate line GCLs among the plurality of gate line GCLs based on a predetermined code. The gate line drive circuit 15 applies the first gate drive signal VGH to the gate of the first switching element Tr via the selected gate line GCL. As a result, one or more first detection electrode blocks BKx are selected as detection targets and connected to the signal line SGL. Further, the gate line drive circuit 15 applies the second gate drive signal VGL to the gate of the second switching element xTr via the gate line GCL to be non-detected. As a result, one or more first detection electrode blocks BKx are selected as non-detection targets and connected to the reference signal line COM.

The signal line selection circuit 16 is driven to select one or more signal line SGLs among a plurality of signal line SGLs based on a predetermined code. The signal line selection circuit 16 connects the selected signal line SGL to one output signal line Lout. As a result, the plurality of second detection electrode blocks BKy are connected to the AFE48 via one output signal line Lout.

FIG. 11 is an explanatory diagram for explaining an operation example of code division selection drive by the gate line drive circuit. FIG. 11 shows an operation example of CDM drive for the second detection electrode block BKy having four detection electrodes 24 for the sake of clarity. In FIG. 11, the detection electrode 24 to be detected is shown with diagonal lines. Further, in FIG. 11, the gate line GCL, the gate line drive circuit 15, the first switching element Tr, and the like are not shown.

Each detection electrode 24 of the second detection electrode block BKY can be connected to a common signal line SGL by the operation of the first switching element Tr. Here, the signal value output from each detection electrode 24 is defined as the signal value Si _q (q = 0, 1, 2, 3). The gate line drive circuit 15 selects one or a plurality of detection electrodes 24 based on a predetermined code among the detection electrodes 24 of the second detection electrode block BKY. The signal value in which the signal value Si _q of the selected detection electrode 24 is integrated is output as an output signal Sv _p (p = 0, 1, 2, 3) via the signal line SGL. The output signal Sv _p is represented by the following equation (1). That is, the output signal Sv _p is represented by the sum of the signal values Si _q output from the plurality of detection electrodes 24 to be detected in one second detection electrode block BKY.

Here, the signal value Si _q is a signal value corresponding to each detection electrode 24 of the first detection electrode block BKx (1), BKx (2), BKx (3), and BKx (4). The signal value Si _q is a signal value output according to the light applied to the organic material layer 31. The output signal Sv _p is an output signal of the second detection electrode block BKY, and is a value obtained by calculating the signal value Si _q of the detection electrode 24 selected based on a predetermined code in the second detection electrode block BKY. Is. The predetermined code is defined by, for example, the square matrix H of the following equation (2). The predetermined code is a code based on a square matrix, for example, a Hadamard matrix, in which "1" or "-1", or "1" or "0" is an element, and any two different rows are orthogonal matrices. ..

The degree of the square matrix H is 4, which is the number of detection electrodes 24 included in the second detection electrode block BKy, that is, the number of four first detection electrode blocks BKx. In the present embodiment, the second detection electrode block BKy including the four detection electrodes 24 will be described, but the number of the detection electrodes 24 included in the second detection electrode block BKy is not limited to this, and the number of the detection electrodes 24 is two, three, or the like. It may be 5 or more. In this case, the order of the square matrix H is also changed according to the number of detection electrodes 24.

In the first period ta1 and the first period ta1x shown in FIG. 11, the gate line drive circuit 15 receives the first gate drive signal VGH and the second gate drive signal VGL according to the selection signal corresponding to the first row of the square matrix H. Is supplied to each gate line GCL. As a result, the detection electrode 24 to be detected is selected. In the second period ta2 and the third period ta3, the detection electrode 24 is selected according to the selection signal corresponding to the second row of the square matrix H. In the fourth period ta4 and the fifth period ta5, the detection electrode 24 is selected according to the selection signal corresponding to the third row of the square matrix H. In the fourth period ta4 and the fifth period ta5, the detection electrode 24 is selected according to the selection signal corresponding to the fourth row of the square matrix H.

Specifically, in the first period ta1, the gate line drive circuit 15 transmits the first gate drive signal VGH whose potential is determined corresponding to the component “1” in the first row of the square matrix H to each gate line GCL. Supply to. The first gate drive signal VGH turns on the first switching element Tr, and the four detection electrodes 24 are connected to the common signal line SGL. As a result, the four detection electrodes 24 are selected as the first detection target. The detection electrode 24 to be detected first outputs the first output signal Sv ₀ (1) to the AFE 48 via the signal line SGL. The first output signal Sv ₀ (1) is a signal in which the detection signals of the four detection electrodes 24 are integrated.

Next, in the first period ta1x, since the component “-1” in the first row of the square matrix H does not exist, the detection electrode 24 is not selected as the second detection target corresponding to the component “-1”. The gate line drive circuit 15 supplies the second gate drive signal VGL to the gate line GCL corresponding to each detection electrode 24. Therefore, the signal value of the second output signal Sv ₀ (2) becomes 0. The signal processing unit 44 determines from the difference between the first output signal Sv ₀ (1) and the second output signal Sv ₀ (2) that the third output signal Sv ₀ (3) = Sv ₀ (1) −Sv ₀ (1). ) Is calculated.

Next, in the second period ta2, the gate line drive circuit 15 supplies the first gate drive signal VGH whose potential is determined corresponding to the component “1” in the second row of the square matrix H to each gate line GCL. do. As a result, two detection electrodes 24 belonging to the first detection electrode blocks BKx (1) and BKx (3) are selected as the first detection target. The detection electrode 24 to be detected first outputs the first output signal Sv ₁ (1) to the AFE 48 via the signal line SGL.

Next, in the third period ta3, the gate line drive circuit 15 sends the first gate drive signal VGH whose potential is determined corresponding to the component “-1” in the second row of the square matrix H to each gate line GCL. Supply. As a result, two detection electrodes 24 belonging to the first detection electrode blocks BKx (2) and BKx (4) are selected as the second detection target. The detection electrode 24 to be detected second outputs the second output signal Sv ₁ (2) to the AFE 48 via the signal line SGL. The signal processing unit 44 determines from the difference between the first output signal Sv ₁ (1) and the second output signal Sv ₁ (2) that the third output signal Sv ₁ (3) = Sv ₁ (1) -Sv ₁ (2). ) Is calculated.

Similarly, in the fourth period ta4, the gate line drive circuit 15 selects the first detection target corresponding to the component “1” in the third row of the square matrix H. In the fifth period ta5, the gate line drive circuit 15 selects the second detection target corresponding to the component “-1” in the third row of the square matrix H. In the sixth period ta6, the gate line drive circuit 15 selects the first detection target corresponding to the component “1” in the fourth row of the square matrix H. In the seventh period ta7, the gate line drive circuit 15 selects the second detection target corresponding to the component “-1” in the fourth row of the square matrix H.

As a result, the signal processing unit 44 calculates the four third output signals Sv ₀ (3), Sv ₁ (3), Sv ₂ (3), and Sv ₃ (3). Then, the signal processing unit decodes 44, 4 third output signals Sv ₀ (3), Sv ₁ (3), Sv ₂ (3), and Sv ₃ (3) by multiplying them with the square matrix H. As a result, the detection device 1 can obtain four times the signal strength without increasing the voltage value of the drive voltage VDD_ORG. Further, the detection device 1 can increase the signal strength without increasing the area of the detection electrode 24. Therefore, the detection device 1 can detect high-definition light. Further, the third output signal Sv _p (3) is obtained by the difference between the first output signal Sv _p (1) and the second output signal Sv _p (2). Therefore, even if noise invades from the outside or the characteristics of the organic material layer 31 fluctuate due to the influence of the measurement environment, the noise component of the first output signal Sh _p (1) and the second output signal. The noise component of Sh _p (2) is canceled. As a result, the detection device 1 can improve the detection reliability.

FIG. 12 is an explanatory diagram for explaining an operation example of the code division selection drive by the signal line selection circuit. FIG. 12 shows an operation example of CDM drive for the first detection electrode block BKx having four detection electrodes 24 for the sake of clarity.

The signal line selection circuit 16 connects a plurality of signal line SGLs to a common output signal line Lout based on a predetermined code. As a result, the signal line selection circuit 16 selects one or a plurality of detection electrodes 24 from the first detection electrode block BKx based on a predetermined code. Here, the signal value output from each detection electrode 24 is defined as the signal value Si _q . Similar to the equation (1), the signal value in which the signal value Si _q of the selected detection electrode 24 is integrated is output as the output signal Sh _p via the output signal line Lout. That is, the output signal Sh _p is represented by the sum of the signal values Si _q output from the plurality of detection electrodes 24 in one first detection electrode block BKx.

The predetermined code is defined by, for example, the square matrix H of the above-mentioned equation (2). The predetermined code may be, for example, a code based on the Hadamard matrix, or may be another square matrix.

As shown in FIG. 12, in the first partial period tb1, four detection electrodes 24 are selected as the first detection target corresponding to the component “1” in the first row of the square matrix H. Specifically, the signal line selection circuit 16 connects the four signal line SGLs corresponding to the component "1" in the first row of the square matrix H to the common output signal line Lout by the operation of the third switch SW3. do. As a result, the detection electrode 24 to be detected first outputs the first output signal Sh ₀ (1) to the AFE 48 via the common output signal line Lout. The first output signal Sh ₀ (1) is a signal in which the detection signals of the four detection electrodes 24 are integrated.

Next, in the first partial period tb1x, since the component "-1" in the first row of the square matrix H does not exist, the signal line selection circuit 16 shares four signal lines SGL by the operation of the third switch SW3. It is cut off from the output signal line Lout of. That is, the detection electrode 24 is not selected as the second detection target corresponding to the component “-1”. Therefore, the signal value of the second output signal Sh ₀ (2) becomes 0. The signal processing unit 44 determines from the difference between the first output signal Sh ₀ (1) and the second output signal Sh ₀ (2) that the third output signal Sh ₀ (3) = Sh ₀ (1) −Sh ₀ (1). ) Is calculated.

Next, in the second partial period tb2, the signal line selection circuit 16 uses the operation of the third switch SW3 to provide a common output signal line to the signal line SGL corresponding to the component “1” in the second row of the square matrix H. Connect to Lout. As a result, two detection electrodes 24 belonging to the second detection electrode blocks BKy (1) and BKy (3) are selected as the first detection target. The detection electrode 24 to be detected first outputs the first output signal Sh ₁ (1) to the AFE 48 via the output signal line Lout.

Next, in the third partial period tb3, the signal line selection circuit 16 causes the signal line SGL corresponding to the component “-1” in the second row of the square matrix H to be a common output signal by the operation of the third switch SW3. Connect to line Lout. As a result, two detection electrodes 24 belonging to the second detection electrode blocks BKy (2) and BKy (4) are selected as the second detection target. The detection electrode 24 to be detected second outputs the second output signal Sh ₁ (2) to the AFE 48 via the output signal line Lout. The signal processing unit 44 determines from the difference between the first output signal Sh ₁ (1) and the second output signal Sh ₁ (2) that the third output signal Sh ₁ (3) = Sh ₁ (1) -Sh ₁ (2). ) Is calculated.

Similarly, in the fourth subperiod tb4, the signal line selection circuit 16 selects the first detection target corresponding to the component “1” in the third row of the square matrix H. In the fifth partial period tb5, the signal line selection circuit 16 selects the second detection target corresponding to the component “-1” in the third row of the square matrix H. In the sixth subperiod tb6, the signal line selection circuit 16 selects the first detection target corresponding to the component “1” in the fourth row of the square matrix H. In the seventh subperiod tb7, the signal line selection circuit 16 selects the second detection target corresponding to the component “-1” in the fourth row of the square matrix H.

As a result, the signal processing unit 44 calculates the four third output signals Sh ₀ (3), Sh ₁ (3), Sh ₂ (3), and Sh ₃ (3). Then, the signal processing unit 44 decodes the four third output signals Sh ₀ (3), Sh ₁ (3), Sh ₂ (3), and Sh ₃ (3) by multiplying them with the square matrix H. As a result, the detection device 1 can further obtain four times the signal strength without increasing the voltage value of the drive voltage VDD_ORG.

The CDM drive by the gate line drive circuit 15 shown in FIG. 11 and the CDM drive by the signal line selection circuit 16 shown in FIG. 12 can be appropriately combined and executed. FIG. 13 is a table showing an example of the detection operation by the gate line drive circuit and the signal line selection circuit in the first to third periods. FIG. 14 is a table showing an example of the detection operation by the gate line drive circuit and the signal line selection circuit in the 4th to 7th periods.

In FIG. 13, the first gate drive signal VGH and the second gate drive signal VGL supplied to the gate lines GCL (1), GCL (2), GCL (3), and GCL (4) are subjected to the first period ta1 and th. It is shown for each of the 2nd period ta2 and the 3rd period ta3. Further, in FIG. 13, the AFE48 or the reference signal VR to which the second detection electrode blocks BKy (1), BKy (2), BKy (3), and BKy (4) are connected is connected to the first partial period tb1 to the seventh portion. It is shown for each period tb7. FIG. 14 also shows the fourth period ta4 to the seventh period ta7.

As shown in FIGS. 13 and 14, the first partial period tb1 to the seventh partial period tb7 are provided corresponding to each of the first period ta1 to the seventh period ta7. The order of each period may be changed as appropriate.

As shown in FIGS. 13 and 14, the gate line drive circuit 15 receives the first gate drive signal VGH and the second gate drive signal VGL whose potentials are determined based on the predetermined reference numerals shown in the equation (2). Supply to the gate line GCL. Specifically, in the first period ta1, the gate line drive circuit 15 corresponds to the component “1” in the first line of the equation (2), and all the gate lines GCL (1), GCL (2),. The first gate drive signal VGH is supplied to GCL (3) and GCL (4). The first period ta1x shown in FIG. 11 can be omitted because the component "-1" in the first row of the square matrix H does not exist. In the second period ta2, the gate line drive circuit 15 sends the first gate drive signal VGH to the gate lines GCL (1) and GCL (3) corresponding to the component “1” in the second line of the equation (2). Supply. Further, in the second period ta2, the gate line drive circuit 15 drives the gate lines GCL (2) and GCL (4) to the second gate corresponding to the component “-1” in the second line of the equation (2). The signal VGL is supplied.

Similarly, in the third period ta3 to the seventh period ta7, the gate line drive circuit 15 supplies the first gate drive signal VGH and the second gate drive signal VGL corresponding to each component of the equation (2) to the gate line GCL. do. As a result, the detection electrode 24 of the first detection target and the detection electrode 24 of the second detection target, which are different combinations for each period, are selected.

As shown in FIGS. 13 and 14, the signal line selection circuit 16 connects the signal line SGL corresponding to the predetermined code shown in the equation (2) to one output signal line Lout. As a result, the signal line selection circuit 16 selects the second detection electrode block BKy. Specifically, in the first partial period tb1, the signal line selection circuit 16 corresponds to the component “1” in the first line of the equation (2), and all the second detection electrode blocks BKy (1) and BKy. (2), BKy (3), BKy (4) are selected. The second detection electrode block BKy (1), BKy (2), BKy (3), and BKy (4) are connected to the AFE48 via the output signal line Lout. In this case, the detection of the first detection target or the second detection target selected by the gate wire drive circuit 15 among the second detection electrode blocks BKy (1), BKy (2), BKy (3), and BKy (4). The electrode 24 is connected to the output signal line Lout.

As a result, the first output signal Svh ₀ (1) is output to the AFE 48 from the second detection electrode blocks BKy (1), BKy (2), BKy (3), and BKy (4). Here, the first output signal Svh ₀ (1) is the detection electrode of the first detection target among the plurality of second detection electrode blocks BKy (1), BKy (2), BKy (3), and BKy (4). The 24 signals are integrated signals. Further, the second output signal Svh ₀ (0) is the detection electrode 24 to be detected second among the plurality of second detection electrode blocks BKy (1), BKy (2), BKy (3), and BKy (4). The signal of is an integrated signal. Further, since the component "-1" does not exist in the first row of the formula (2), the first partial period tb1x shown in FIG. 12 can be omitted. The signal processing unit 44 acquires the first output signal Svh ₀ (1) of the first partial period tb1 as the third output signal Svh ₀ (3).

In the second partial period tb2, the signal line selection circuit 16 selects the second detection electrode blocks BKy (1) and BKy (3) corresponding to the component “1” in the second line of the equation (2). The second detection electrode blocks BKy (1) and BKy (3) are connected to the AFE48 via the output signal line Lout. As a result, the first output signal Svh ₁ (1) is output to the AFE 48 from the second detection electrode blocks BKy (1) and BKy (3). In this case, of the second detection electrode blocks BKy (1) and BKy (3), the detection electrode 24 of the first detection target or the second detection target selected by the gate line drive circuit 15 is connected to the output signal line Lout. To. On the other hand, the reference signal VR is supplied to the non-selected second detection electrode blocks BKy (2) and BKy (4).

In the third partial period tb3, the signal line selection circuit 16 selects the second detection electrode blocks BKy (2) and BKy (4) corresponding to the component “-1” in the second line of the equation (2). .. The second detection electrode blocks BKy (2) and BKy (4) are connected to the AFE48 via the output signal line Lout. As a result, the second output signal Svh ₁ (2) (see FIG. 12) is output to the AFE 48 from the second detection electrode blocks BKy (2) and BKy (4). In this case, of the second detection electrode blocks BKy (2) and BKy (4), the detection electrode 24 of the first detection target or the second detection target selected by the gate line drive circuit 15 is connected to the output signal line Lout. To. On the other hand, the reference signal VR is supplied to the non-selected second detection electrode blocks BKy (1) and BKy (3). The signal processing unit 44 determines the third output signal Svh ₁ (2) from the difference between the first output signal Svh ₁ (1) of the second partial period tb2 and the second output signal Svh ₁ (2) of the third partial period tb3. 3) is calculated.

Similarly, the signal line selection circuit 16 selects the second detection electrode block BKy in the fourth subperiod tb4 to the seventh subperiod tb7 based on a predetermined code of the equation (2). As a result, the signal processing unit 44 has four third output signals Svh ₀ (3), Svh ₁ (3), Svh ₂ (3), Svh ₃ (3) in the first subperiod tb1 to the seventh subperiod tb7. ). Further, the signal processing unit 44 performs four third output signals Svh ₀ (3), Svh ₁ (3), Svh ₂ (3) in the first period ta1 to the seventh period ta7, as in the example shown in FIG. ), Svh ₃ (3) is acquired. That is, the signal processing unit 44 acquires a total of 16 third output signals Svh (3). Then, the signal processing unit 44 calculates the decoded signal for each detection electrode 24 by decoding the third output signal Svh (3). As a result, the detection device 1 can drive the CDM by the gate line drive circuit 15 and the signal line selection circuit 16.

As shown in FIG. 3, the detection electrode 24 and the signal line selection circuit 16 are provided on the substrate 21. Then, the plurality of detection electrodes 24 are connected to one AFE48 via the output signal line Lout. As a result, the number of AFE48s can be reduced even when the number of detection electrodes 24 is increased. Further, the number of wirings connecting the substrate 21 and the AFE 48 can be suppressed.

Next, the detailed configuration of the gate line drive circuit 15 will be described. FIG. 15 is a block diagram showing a configuration example of a sensor unit, a gate line drive circuit, and a signal line selection circuit. FIG. 16 is a block diagram of a gate line drive circuit.

As shown in FIG. 15, the substrate 21 is provided with a sensor unit 10, a gate line drive circuit 15, and a signal line selection circuit 16. Further, the substrate 21 is provided with a control signal generation circuit 17, an inverter 153, 154, and a protection circuit 155.

The protection circuit 155 includes a protection resistance element and a protection diode. Various signals supplied from the control board 101 (see FIG. 1) are supplied to the control signal generation circuit 17, the gate line drive circuit 15, and the signal line selection circuit 16 via the protection circuit 155. The output signal line Lout of the signal line selection circuit 16 is connected to the AFE 48 without the protection diode of the protection circuit 155. As a result, it is possible to suppress a decrease in the signal strength output from the sensor unit 10.

The inverter 153 receives the reset signal RST from the control board 101 and outputs the inverting reset signal xRST to the control signal generation circuit 17. The inverting reset signal xRST is a voltage signal obtained by inverting the reset signal RST. Further, the inverter 154 receives the clock signal CLK from the control board 101 and outputs the inverted clock signal xCLK to the control signal generation circuit 17. The inverting clock signal xCLK is a voltage signal obtained by inverting the clock signal CLK.

The control signal generation circuit 17 generates various control signals based on the reset signal RST, the clock signal CLK, the ground potential GND, and the power supply voltage VDD supplied from the external control board 101. The control signal generation circuit 17 supplies various control signals to the gate line drive circuit 15.

FIG. 17 is a timing waveform diagram showing various control signals output from the control signal generation circuit. As shown in FIG. 17, the control signal generation circuit 17 outputs the inversion control signal Vs, the first control signal Va1, Va2, Va3 and the second control signal Vb1, Vb2, Vb3. The inverting control signal Vs is supplied to the inverting input terminal S of the second code generation circuit 13. The first control signals Va1, Va2, and Va3 are supplied to the first input terminals A1, A2, and A3 of the first code generation circuit 12, respectively. The second control signals Vb1, Vb2, and Vb3 are supplied to the second input terminals B1, B2, and B3 of the second code generation circuit 13, respectively.

As shown in FIG. 17, the frequency of the second control signal Vb3 is 1/2 of the frequency of the inversion control signal Vs. The frequency of the second control signal Vb2 is ½ of the frequency of the second control signal Vb3. Similarly, the second control signal Vb1, the first control signal Va3, Va2, and Va1 are output from the control signal generation circuit 17, respectively.

As shown in FIGS. 15 and 16, the gate line drive circuit 15 includes a first code generation circuit 12, a second code generation circuit 13, a third code generation circuit 14, a buffer circuit 151, and a level shifter 152. Have. That is, the first code generation circuit 12, the second code generation circuit 13, the third code generation circuit 14, the buffer circuit 151, and the level shifter 152 are provided in the frame region GA of the substrate 21. In FIG. 16, the buffer circuit 151 and the level shifter 152 are omitted.

The first code generation circuit 12, the second code generation circuit 13, and the third code generation circuit 14 are decoder circuits. The first code generation circuit 12 generates the first partial selection signal Vd (see FIGS. 18 and 19) based on the first control signals Va1, Va2, and Va3, and the first partial selection signal Vd is used as the third code generation circuit 14. Supply to. The second code generation circuit 13 generates a second partial selection signal Vf (see FIGS. 20 and 21) based on the second control signals Vb1, Vb2, and Vb3, and uses the second partial selection signal Vf as the third code generation circuit 14. Supply to. The third code generation circuit 14 is, for example, an exclusive OR (XOR) circuit. The third code generation circuit 14 generates the first selection signal Vc based on the first partial selection signal Vd and the second partial selection signal Vf, and supplies the signal based on the first selection signal Vc to the gate line GCL.

As shown in FIG. 16, the first code generation circuit 12 has first input terminals A1, A2, A3, a terminal to which the power supply voltage VDD is input, and a plurality of output terminals Ya1, Ya2, ..., Ya8. Have. In the present embodiment, the number of output terminals Ya1, Ya2, ..., Ya8 of the first code generation circuit 12 is eight. The first control signals Va1, Va2, and Va3 are input from the control signal generation circuit 17 to the first input terminals A1, A2, and A3. The first code generation circuit 12 is a circuit that generates a first partial selection signal Vd based on the first control signals Va1, Va2, and Va3. The first code generation circuit 12 outputs the first partial selection signal Vd from the output terminals Ya1, Ya2, ..., Ya8 to the first selection signal lines LSa1, LSa2, ..., LSa8. The first partial selection signal Vd is a signal whose phase is determined for each of the plurality of gate lines GCL.

The second code generation circuit 13 has second input terminals B1, B2, B3, an inverting input terminal S, and a plurality of output terminals Yb1, Yb2, ..., Yb8. In the present embodiment, the number of output terminals Yb1, Yb2, ..., Yb8 of the second code generation circuit 13 is eight. The second control signals Vb1, Vb2, and Vb3 are input from the control signal generation circuit 17 to the second input terminals B1, B2, and B3. Further, the inversion control signal Vs is input from the control signal generation circuit 17 to the second code generation circuit 13. The second code generation circuit 13 is a circuit that generates a second partial selection signal Vf based on the second control signals Vb1, Vb2, Vb3 and the inversion control signal Vs. The inversion control signal Vs is a signal that inverts the components "1" and "-1" having a predetermined code. The second code generation circuit 13 outputs the second partial selection signal Vf from the output terminals Yb1, Yb2, ..., Yb8 to the second selection signal lines LSb1, LSb2, ..., LSb8. The second partial selection signal Vf is a signal whose phase is determined for each drive signal supply line block BKL.

As shown in FIG. 15, the level shifter 152 is provided between the first code generation circuit 12 and the second code generation circuit 13 and the third code generation circuit 14. The level shifter 152 is a circuit that changes the voltage (amplitude) of the input signal and outputs the changed signal. Specifically, the level shifter 152 receives the first partial selection signal Vd from the first code generation circuit 12 and temporarily holds it. Further, the level shifter 152 receives the second partial selection signal Vf from the second code generation circuit 13 and temporarily holds it. The level shifter 152 changes the voltage level of the first selection signal Vc by the power supply voltages VDD and VSS supplied from the control board 101. The amplitudes of the first partial selection signal Vd and the second partial selection signal Vf are increased and output to the third code generation circuit 14. The level shifter 152 may be provided on the output side of the third code generation circuit 14.

As shown in FIG. 16, a plurality of gate lines GCL (1), GCL (2), ..., GCL (n) are arranged. The gate line GCL is provided corresponding to the first detection electrode block BKx (see FIG. 10), respectively. The number of gate lines GCL is 64 (n = 64). Drive signal supply lines Ld1, Ld2, ..., Ldn (n = 64) are connected to the gate line GCL, respectively. The drive signal supply line partial blocks sBKL1, sBKL2, ..., SBKL7, and sBKL8 each include eight drive signal supply lines Ld.

The first selection signal lines LSa1, LSa2, ..., LSa8 are each connected to one drive signal supply line Ld for each drive signal supply line partial block sBKL. As a result, the first selection signal lines LSa1, LSa2, ..., LSa8 are connected in parallel to the plurality of drive signal supply line partial blocks sBKL1, sBKL2, ..., SBKL7, sBKL8. The first selection signal lines LSa1, LSa2, ..., LSa8 are connected to drive signal supply lines Ld different from each other. In other words, the plurality of drive signal supply lines Ld included in one drive signal supply line partial block sBKL are connected to the first selection signal lines LSa1, LSa2, ..., LSa8, respectively. For example, the drive signal supply lines Ld1, Ld2, ..., Ld8 included in the drive signal supply line partial block sBKL1 are connected to the first selection signal lines LSa1, LSa2, ..., LSa8, respectively. The same applies to the drive signal supply line partial blocks sBKL2, ..., sBKL7, and sBKL8.

The third code generation circuits 14-1, 14-2, ..., 14-7, 14-8 are provided corresponding to the drive signal supply line partial blocks sBKL1, sBKL2, ..., sBKL7, and sBKL8, respectively. Further, the second selection signal lines LSb1, LSb2, ..., LSb8 are connected to the third code generation circuits 14-1, 14-2, ..., 14-8, respectively. In other words, the second selection signal lines LSb1, LSb2, ..., LSb8 are connected to the drive signal supply line partial blocks sBKL1, sBKL2, ..., SBKL8, respectively. In one third code generation circuit 14, a plurality of first selection signal lines LSa are connected, and one second selection signal line LSb is connected. In the present embodiment, the plurality of first-selection signal lines LSa and the plurality of second-selection signal lines LSb are provided so as to intersect the drive signal supply line Ld in a plan view.

The plurality of third code generation circuits 14 generate the first selection signal Vc based on the first partial selection signal Vd and the second partial selection signal Vf, and generate the first selection signal Vc in the buffer circuit 151 (see FIG. 15). Supply.

As shown in FIG. 15, the buffer circuit 151 temporarily holds the first selection signal Vc supplied from the third code generation circuit 14. Then, the buffer circuit 151 supplies the first gate drive signal VGH and the second gate drive signal VGL corresponding to the first selection signal Vc to the plurality of selected gate lines GCL substantially simultaneously.

Next, the operations of the first code generation circuit 12, the second code generation circuit 13, and the third code generation circuit 14 will be described. FIG. 18 is a circuit diagram showing an example of the first code generation circuit. FIG. 19 is a table showing the relationship between the first control signal and the first partial selection signal. As shown in FIG. 18, the first code generation circuit 12 includes a plurality of exclusive OR circuits 51-1, 51-2, ..., 51-7. The exclusive OR circuits 51-1, 51-2, ..., 51-7 have one of the first control signals Va1, Va2, and Va3, and an output signal from the power supply voltage VDD or the other exclusive OR circuit 51. Is entered. In the exclusive OR circuits 51-1, 51-2, ..., 51-7, the value of the exclusive OR of the signals input to each is set as the first partial selection signals Vd2, Vd3, ..., Vd8 and the first selection signal. Output to the lines LSa2, ..., LSa8. Further, the same signal as the power supply voltage VDD is output to the first selection signal line LSa1 as the first partial selection signal Vd1.

The first code generation circuit 12 generates the first partial selection signals Vd1, Vd2, ..., Vd8 corresponding to the first control signals Va1, Va2, Va3 and the power supply voltage VDD according to the truth table shown in FIG. In FIG. 19, "1" is assigned when each signal has a high level voltage, and "0" is assigned when each signal has a low level voltage. As a result, the first code generation circuit 12 outputs the first partial selection signals Vd1, Vd2, ..., Vd8 whose phases are determined based on a predetermined code to each drive signal supply line partial block sBKL. For example, the predetermined code is defined by the square matrix of the following equation (3). The order of the square matrix is 8, which is the number of the output terminals Ya1, Ya2, ..., Ya8 of the first code generation circuit 12.

The first code generation circuit 12 outputs the first partial selection signals Vd1, Vd2, ..., Vd8 for each period tc1, ct2, ..., Tc8. The patterns of on / off combinations of the first partial selection signals Vd1, Vd2, ..., Vd8 in each period ct1, ct2, ..., Tc8 are different. The pattern of the combination of the first partial selection signals Vd1, Vd2, ..., Vd8 on and off is eight, which is the same as the number of output terminals Ya1, Ya2, ..., Ya8.

FIG. 20 is a circuit diagram showing an example of the second code generation circuit. FIG. 21 is a table showing the relationship between the second control signal and the inversion control signal and the second partial selection signal. As shown in FIG. 20, the second code generation circuit 13 includes a plurality of exclusive OR circuits 52-1, 52-2, ..., 52-7, and an inverter 53. The inverter 53 is a circuit that generates a second partial selection signal Vf1, which is a voltage signal obtained by inverting the inversion control signal Vs. The inverter 53 outputs the second partial selection signal Vf1 to the second selection signal line LSb1. That is, the inverter 53 outputs a low level voltage signal when the inverting control signal Vs is a high level voltage, and outputs a high level voltage signal when the inverting control signal Vs is a low level voltage.

In the exclusive OR circuits 52-1, 52-2, ..., 52-7, any one of the second control signals Vb1, Vb2, Vb3, the output signal from the inverter 53, or the other exclusive OR circuit 52 is used. The output signal of is input. The inverting control signal Vs and the second control signals Vb1, Vb2, and Vb3 are output signals from the control signal generation circuit 17 shown in FIG. In the exclusive OR circuits 52-1, 52-2, ..., 52-7, the value of the exclusive OR of the signals input to each is set as the second partial selection signals Vf2, Vf3, ..., Vf8 and the second selection signal. Output to the lines LSb2, LSb3, ..., LSb8. The inverter 53 is not essential, and the second code generation circuit 13 may output the inversion control signal Vs as the second partial selection signal Vf1.

The second code generation circuit 13 generates the second partial selection signal Vf corresponding to the second control signals Vb1, Vb2, Vb3 and the inversion control signal Vs according to the truth table shown in FIG. As a result, the second code generation circuit 13 drives each of the second partial selection signals Vf1, Vf2, ..., Vf8 whose phase is determined based on a predetermined code for each period td1, td2, ..., Td16. Output to the signal supply line partial block sBKL. For example, the predetermined code is defined by the square matrix of the equation (2). When the inversion control signal Vs is off (“0”), the second partial selection signals Vf1, Vf2, ..., Vf8 corresponding to the component “1” of the square matrix are generated. When the inversion control signal Vs is on (“1”), the second partial selection signals Vf1, Vf2, ..., Vf8 corresponding to the component “-1” of the square matrix are generated.

The second code generation circuit 13 outputs the second partial selection signals Vf1, Vf2, ..., Vf8 from the output terminals Yb1, Yb2, ..., Yb8 for each period td1, td2, ..., Td16. The patterns of on / off combinations of the second partial selection signals Vf1, Vf2, ..., Vf8 in each period td1, td2, ..., Td16 are different.

Here, since the inversion control signal Vs is input to the second code generation circuit 13, the second code generation circuit 13 includes a pattern of a combination in which the on and off of the second partial selection signals Vf1, Vf2, ..., Vf8 are inverted. Specifically, in the periods td1, td3, td5, td7, td9, td11, td13, td15, the inversion control signal Vs is off, and in the periods td2, td4, td6, td8, td10, td12, td14, td16, The inverting control signal Vs is on. For example, in the period td1 and the period td2, the pattern is a combination in which the on and off of the second partial selection signals Vf1, Vf2, ..., Vf8 are inverted, respectively. Therefore, the number of patterns of the combination of the second partial selection signals Vf1, Vf2, ..., Vf8 on and off is 16 which is twice the number of the output terminals Yb1, Yb2, ..., Yb8.

FIG. 22 is a circuit diagram showing an example of a third code generation circuit. FIG. 23 is a diagram showing an example of a pattern code generated by the third code generation circuit when the inversion control signal has a high level voltage. FIG. 24 is a diagram showing an example of a pattern code generated by the third code generation circuit when the inversion control signal has a low level voltage. FIG. 25 is a table showing the relationship between the first control signal, the second control signal, and the inversion control signal.

FIG. 22 shows a third code generation circuit 14-1 provided in the drive signal supply line partial block sBKL1 among the plurality of drive signal supply line partial blocks sBKL. As shown in FIG. 22, the third code generation circuit 14-1 includes a plurality of exclusive OR circuits 54 (exclusive OR circuits 54-1, 54-2, ..., 54-8). The first partial selection signals Vd1, Vd2, ..., Vd8 are input from the first code generation circuit 12 to the exclusive OR circuits 54-1, 54-2, ..., 54-8, respectively. Further, the second partial selection signal Vf1 is input from the second code generation circuit 13 to the exclusive OR circuits 54-1, 54-2, ..., 54-8, respectively. The exclusive OR circuits 54-1, 54-2, ..., 54-8 calculate the exclusive OR of the first partial selection signals Vd1, Vd2, ..., Vd8 and the second partial selection signal Vf1. The value calculated by the exclusive OR circuits 54-1, 54-2, ..., 54-8 is the gate line GCL (1) via the drive signal supply lines Ld1, Ld2, ..., Ld8 as the first selection signal Vc. ), GCL (2), ..., GCL (8).

Similarly, in the third code generation circuits 14-2, 14-3, ..., 14-8 shown in FIG. 16, the first partial selection signal Vd1, Vd2, ..., Vd8 and the second partial selection signal input to each are input. The exclusive OR with Vf2, Vf3, ..., Vf8 is calculated.

As shown in FIG. 19, the pattern of the combination of the first partial selection signal Vd is 8. Further, as shown in FIG. 21, the pattern of the combination of the second partial selection signal Vf is 8 in each case where the inversion control signal Vs is 0 and 1, for a total of 16. Therefore, as shown in FIG. 23, the order of the pattern code (predetermined code) of the first partial selection signal Vd generated by the third code generation circuit 14 is 8 × 8 = when the inversion control signal Vs is 1. It becomes 64. Similarly, as shown in FIG. 24, the order of the pattern code of the first partial selection signal Vd generated by the third code generation circuit 14 is 8 × 8 = 64 when the inversion control signal Vs is 0. The pattern code shown in FIG. 24 is obtained by inverting "0" and "1" of the pattern code shown in FIG. 23.

The first code generation circuit 12, the second code generation circuit 13, and the third code generation circuit 14 generate the first selection signal Vc according to the pattern code shown in FIGS. 23 and 24 according to the truth table shown in FIG. 25. do. The gate line drive circuit 15 generates a high level voltage signal as the first selection signal Vc corresponding to the component "1" of the pattern code. Further, the gate line drive circuit 15 generates a low level voltage signal as the first selection signal Vc corresponding to the component “0” of the pattern code. As a result, the first gate drive signal VGH is supplied to the gate line GCL corresponding to the pattern code component "1", and the second gate drive signal VGL is supplied to the gate line GCL corresponding to the pattern code component "0". To.

As shown in FIG. 25, the period in which the inversion control signal Vs is 1 and the period in which the inversion control signal Vs is 0 are alternately executed. Therefore, the interval between the detection times of the first output signal Svh (1) and the second output signal Svh (2) is shortened. Therefore, even when a noise component is input from the outside, the noise component is canceled by calculating the difference between the first output signal Svh (1) and the second output signal Svh (2). Therefore, the detection device 1 can improve the detection accuracy.

The order of combination of the first partial selection signal Vd and the second partial selection signal Vf is not limited to that shown in FIG. 25. For example, a period in which the inversion control signal Vs is 1 may be continuously executed a plurality of times, and then a period in which the inversion control signal Vs is 0 may be continuously executed a plurality of times.

As described above, the detection device 1 of the present embodiment includes the substrate 21, the organic material layer 31 provided on the upper side of the substrate 21 and detecting a predetermined physical quantity, and the substrate 21 and the organic material in the direction perpendicular to the substrate 21. A plurality of detection electrodes 24 provided between the layers 31 and a first switching element Tr provided in each of the plurality of detection electrodes 24, connected to the first switching element Tr and extending in the first direction Dx. It has a plurality of gate line GCLs, a plurality of signal lines SGL connected to the first switching element Tr and extending in the second direction Dy intersecting the first direction Dx, and a drive circuit (gate line drive circuit 15). .. The gate line drive circuit 15 transmits a gate drive signal (first gate drive signal VGH and second gate drive signal VGL) whose potential is determined based on a predetermined code to a plurality of first gate lines GCL via a plurality of gate line GCLs. It is supplied to each switching element Tr.

As a result, the gate wire drive circuit 15 drives the CDM on the first detection electrode block BKx (see FIG. 10). Therefore, even when the current value flowing from the organic material layer 31 to the detection electrode 24 according to the irradiated light is weak, the detection accuracy can be improved. Further, according to the present embodiment, the signal delay can be suppressed and the detection accuracy can be improved as compared with the case where the first selection signal Vc is supplied to all the gate lines GCL by, for example, a shift register.

Further, in the present embodiment, the gate line drive circuit 15 and the control signal generation circuit 17 are provided on the substrate 21. Therefore, the number of terminals connecting the board 21 and the control board 101 can be suppressed. As a result, the detection device 1 can suppress the circuit scale of the gate line drive circuit 15, and can reduce the manufacturing cost.

In this embodiment, the third code generation circuit 14 may calculate the negation (Xnor) of the exclusive OR of the first partial selection signal Vd and the second partial selection signal Vf. Alternatively, the circuit may perform an operation substantially equal to the logical operation of exclusive OR exclusion or the negation of other OR. Further, the configurations of the first code generation circuit 12 and the second code generation circuit 13 may be changed as appropriate in the same manner.

Next, the signal line selection circuit 16 will be described. FIG. 26 is a circuit diagram showing a signal line selection circuit. FIG. 26 shows 12 signal lines SGL from the signal line SGL (1) to the signal line SGL (12). The signal line selection circuit 16 includes a third switching element Tra, a fourth switching element Trax, a reference signal supply line Lr0, a third selection signal line Lr1, Lr2, ..., Lr6 and an output signal line Lout.

One output signal line Lout is provided corresponding to the signal line SGL (1) to the signal line SGL (6). One output signal line Lout is provided corresponding to the signal line SGL (7) to the signal line SGL (12). Each output signal line Lout is connected to AFE48. The signal line selection circuit 16 connects the selected signal line SGL from the plurality of signal line SGLs to the AFE 48 based on the signal line selection signal Vhsel. As a result, the signal line selection circuit 16 selects the detection electrode 24 (second detection electrode block BKy) to be detected.

The signal line selection signal Vhsel is output from, for example, a code generation circuit (not shown) similar to the second code generation circuit 13 shown in FIG. The code generation circuit that generates the signal line selection signal Vhsel may be included in the signal line selection circuit 16. In this case, the code generation circuit is provided on the same substrate 21 as the signal line selection circuit 16. The signal line selection circuit 16 may be configured not to include a code generation circuit. In this case, the code generation circuit is provided on the external control board 101, and the external control board 101 can output the signal line selection signal Vhsel.

The signal line selection signal Vhsel is a voltage signal whose phase is determined for each signal line SGL based on a predetermined code. The predetermined code is defined by the square matrix of the equation (3). In the example shown in FIG. 26, the six signal line selection signals Vhsel1, Vhsel2, ..., Vhsel6 are supplied to the third selection signal lines Lr1, Lr2, ..., Lr6, respectively. The signal line selection signals Vhsel1, Vhsel2, ..., Vhsel6 are generated, for example, based on any 6 components out of the 8 components included in each line of the equation (3). The signal line selection signals Vhsel1, Vhsel2, ..., Vhsel6 are supplied to the third switching element Tra and the fourth switching element Trax via the third selection signal lines Lr1, Lr2, ..., Lr6.

A third switching element Tra and a fourth switching element Trax are connected to each signal line SGL. The third switching element Tra and the fourth switching element Trax operate so that on and off are reversed when the same signal line selection signal Vhsel is supplied. That is, when the third switching element Tra is on, the fourth switching element Trax is turned off. Further, when the third switching element Tra is off, the fourth switching element Trax is turned on.

The connection state between the signal line SGL and the output signal line Lout is switched by the operation of the third switching element Tra and the fourth switching element Trax. When the third switching element Tra is on, the signal line SGL is connected to the output signal line Lout, and when the fourth switching element Trax is on, the signal line SGL is connected to the reference signal supply line Lr0.

When the signal line selection signal Vhsel of the high level voltage signal corresponding to the component “1” of the equation (3) is supplied, the third switching element Tra is turned on. Further, when the signal line selection signal Vhsel of the low level voltage signal corresponding to the component “-1” of the equation (3) is supplied, the fourth switching element Trax is turned on. As a result, the second detection electrode block BKy connected to the signal line SGL is selected based on a predetermined code, as in the operation example of the CDM drive shown in FIG.

Specifically, when a plurality of signal line SGLs corresponding to the component "1" of the equation (3) are selected, the selected signal line SGL is connected to the common output signal line Lout. The first output signal Sh (1) of the second detection electrode block BKy connected to the selected signal line SGL is output from the output signal line Lout to the AFE48. The non-selected signal line SGL is connected to the reference signal supply line Lr0, and the reference signal VR is supplied. Thereby, the capacitive coupling between the selected detection electrode 24 and the non-selective detection electrode 24 can be suppressed. Therefore, it is possible to suppress a detection error and a decrease in detection sensitivity.

When a plurality of signal line SGLs corresponding to the component "-1" of the equation (3) are selected, the selected signal line SGL is connected to the output signal line Lout. The second output signal Sh (2) of the second detection electrode block BKy connected to each selected signal line SGL is output from the output signal line Lout. The non-selected signal line SGL is connected to the reference signal supply line Lr0, and the reference signal VR is supplied. The signal processing unit 44 calculates the third output signal Sh (3), which is the value of the difference between the first output signal Sh (1) and the second output signal Sh (2). The signal processing unit 44 can calculate the decoded signal for each second detection electrode block BKY by decoding the third output signal Sh (3).

Next, a configuration example of the first switching element Tr and the second switching element xTr will be described. FIG. 27 is a plan view showing the relationship between the detection electrode, the first switching element, and the second switching element. FIG. 28 is a cross-sectional view showing a schematic cross-sectional configuration of the first switching element. In FIG. 27, the detection electrode 24 is shown by a two-dot chain line in order to make the drawing easier to see.

As shown in FIG. 27, the first switching element Tr has a semiconductor layer 61, a source electrode 62, a drain electrode 63, and a gate electrode 64. The material used for the semiconductor layer 61 is, for example, low temperature polysilicon. The semiconductor layer 61 is provided along the second direction Dy and intersects the gate line GCL in a plan view. The portion of the gate wire GCL that overlaps with the semiconductor layer 61 functions as the gate electrode 64. Further, a channel region is formed in a portion of the semiconductor layer 61 that overlaps with the gate line GCL. One end of the semiconductor layer 61 is connected to the source electrode 62 via the contact hole H1. The other end of the semiconductor layer 61 is connected to the drain electrode 63 via the contact hole H2.

The source electrode 62 is electrically connected to the signal line SGL. Further, the drain electrode 63 is electrically connected to the connecting portion 68. The connecting portion 68 is connected to the detection electrode 24 via the contact hole H5. Further, the gate electrode 64 is electrically connected to the gate wire GCL. With such a configuration, the first switching element Tr can switch between connection and disconnection between the detection electrode 24 and the signal line SGL.

The second switching element xTr includes a semiconductor layer 61a, a source electrode 62a, a drain electrode 63a, and a gate electrode 64a. The semiconductor layer 61a is provided along the second direction Dy and intersects with the gate electrode 64a in a plan view. A channel region is formed in a portion of the semiconductor layer 61a that overlaps with the gate electrode 64a. One end of the semiconductor layer 61a is connected to the source electrode 62a via the contact hole H4. The other end of the semiconductor layer 61a is connected to the drain electrode 63a via the contact hole H3.

The source electrode 62a is electrically connected to the connection portion 68. That is, the source electrode 62a of the second switching element xTr and the drain electrode 63 of the first switching element Tr are connected to the detection electrode 24 via a common connection portion 68. The drain electrode 63a is electrically connected to the reference signal line COM. The gate electrode 64a is connected to the gate wire GCL. In other words, the gate line GCL also functions as the gate electrode 64 of the first switching element Tr and the gate electrode 64a of the second switching element xTr. With such a configuration, the second switching element xTr can switch between connection and disconnection between the detection electrode 24 and the reference signal line COM.

In the detection electrodes 24 adjacent to the second direction Dy, the first switching element Tr provided on each detection electrode 24 has a line-symmetrical configuration with the reference line C1 as the axis of symmetry. Similarly, the second switching element xTr also has a line-symmetrical configuration with the reference line C1 as the axis of symmetry. Here, the reference line C1 is a virtual line that passes between the detection electrodes 24 adjacent to the second direction Dy and is along the first direction Dx. Further, the gate wire GCL is provided so as to overlap with the detection electrode 24. The gate line GCL is also arranged at a position of line symmetry with the reference line C1 as the axis of symmetry. Between the gate lines GCL adjacent to the second direction Dy, the first switching element Tr corresponding to each detection electrode 24 is provided adjacent to the second direction Dy. In the present embodiment, in the detection electrodes 24 adjacent to the second direction Dy, the relative positions of the gate line GCL in the second direction Dy with respect to each detection electrode 24 are different.

In the detection electrodes 24 adjacent to the first direction Dx, the first switching element Tr provided on each detection electrode 24 has a line-symmetrical configuration with the reference line C2 as the axis of symmetry. Similarly, the second switching element xTr also has a line-symmetrical configuration with the reference line C2 as the axis of symmetry. Here, the reference line C2 is a virtual line that passes between the detection electrodes 24 adjacent to the first direction Dx and is along the second direction Dy. The reference line C2 is a line that overlaps with the reference signal line COM. In the detection electrodes 24 adjacent to the first direction Dx, the second switching element xTr provided on each detection electrode 24 is connected to a common reference signal line COM. Therefore, the number of reference signal line COMs can be reduced by half as compared with the case where the reference signal line COM is provided for each of the detection electrode 24 and the second switching element xTr arranged in the first direction Dx. As a result, the detection device 1 can increase the opening area of the detection area AA and improve the detection performance. Here, the opening area is an area of a region where light transmission is not blocked by various wirings such as a signal line SGL, a first switching element Tr, a second switching element xTr, and the like.

Further, the signal line SGL is provided so as to overlap with the detection electrode 24. The signal line SGL is also arranged at a position of line symmetry with the reference line C2 as the axis of symmetry. Between the signal lines SGL adjacent to the first direction Dx, the first switching element Tr corresponding to each detection electrode 24 is provided adjacent to the first direction Dx. A second switching element xTr corresponding to each detection electrode 24 is also provided adjacent to the first direction Dx between the signal lines SGL adjacent to the first direction Dx. In the present embodiment, in the detection electrodes 24 adjacent to the first direction Dy, the relative positions of the signal lines SGL in the first direction Dx with respect to each detection electrode 24 are different.

As shown in FIG. 28, the light-shielding layer 65, the semiconductor layer 61, the gate electrode 64, the source electrode 62 and the drain electrode 63, and the detection electrode 24 are provided on one surface of the substrate 21 in this order. The first switching element Tr has a so-called top gate structure. That is, the semiconductor layer 61 is provided between the substrate 21 and the gate electrode 64 in the direction perpendicular to the substrate 21.

The light-shielding layer 65 is provided on one surface (upper surface) of the substrate 21 via the first insulating layer 25A-1. The light-shielding layer 65 is provided so as to overlap with at least the channel region of the semiconductor layer 61. For the light-shielding layer 65, for example, a metal material such as molybdenum (Mo), tungsten (W), aluminum (Al), titanium (Ti), or silver (Ag) is used. As a result, the light-shielding layer 65 can shield the light emitted from the other surface (lower surface) of the substrate 21 to the semiconductor layer 61. As a result, the first switching element Tr can suppress the leak current. The detection device 1 can satisfactorily detect the light emitted from the other surface of the substrate 21.

The second insulating layer 25A-2 is provided on the first insulating layer 25A-1 so as to cover the light shielding layer 65. The semiconductor layer 61 is provided on the second insulating layer 25A-2. A third insulating layer 25A-3 is provided on the semiconductor layer 61. The gate electrode 64 is provided on the third insulating layer 25A-3. The gate electrode 64 is provided in the same layer as the gate wire GCL (see FIG. 27). A fourth insulating layer 25A-4, which is a gate insulating layer, is provided on the gate electrode 64.

A source electrode 62 and a drain electrode 63 are provided on the fourth insulating layer 25A-4. The source electrode 62 and the drain electrode 63 are provided in the same layer as the signal line SGL (see FIG. 27). The source electrode 62 is connected to the semiconductor layer 61 via the contact holes H1 provided in the third insulating layer 25A-3 and the fourth insulating layer 25A-4. Similarly, the drain electrode 63 is also connected to the semiconductor layer 61 via the contact holes H2 provided in the third insulating layer 25A-3 and the fourth insulating layer 25A-4.

A detection electrode 24 is provided above the source electrode 62 and the drain electrode 63 via the hard coat layer 25B and the insulating layer 23. The organic material layer 31 and the driving electrode 32 are provided on the detection electrode 24. In FIG. 28, the protective layer 33 (see FIG. 5) is omitted. With such a laminated structure, the first switching element Tr can switch between connection and disconnection between the detection electrode 24 and the signal line SGL. The second switching element xTr also has the same laminated structure as the first switching element Tr. The semiconductor layer 61a, source electrode 62a, drain electrode 63a, and gate electrode 64a of the second switching element xTr are the same layer as the semiconductor layer 61, source electrode 62, drain electrode 63, and gate electrode 64 of the first switching element Tr, respectively. It is provided in.

(Second Embodiment)
FIG. 29 is a plan view showing the detection device according to the second embodiment. FIG. 30 is a block diagram showing a configuration example of the sensor unit, the gate line drive circuit, and the signal line selection circuit according to the second embodiment. FIG. 31 is a timing waveform diagram showing an operation example of the detection device according to the second embodiment.

In the detection device 1A of the present embodiment, the gate line drive circuit 15A does not have the first code generation circuit 12, the second code generation circuit 13, and the third code generation circuit 14. In this embodiment, the control board 101 is provided with a code generation circuit. For example, the control circuit 102 has a function of a code generation circuit and generates a first selection signal Vc whose phase is determined based on a predetermined code. The control circuit 102 supplies the first selection signal Vc to the gate line drive circuit 15A via the wiring LA.

As shown in FIG. 30, the gate line drive circuit 15A includes a shift register 18, a latch circuit 19, and a buffer circuit 151. The shift register 18 operates based on the reset signal RST, the clock signal CKV, and the start signal STV supplied from the control board 101. The shift register 18 has a shift signal output circuit corresponding to each of the plurality of gate lines GCL. The shift register 18 sequentially outputs a shift signal to the latch circuit 19 for each of the plurality of gate lines GCL.

As shown in FIG. 31, the shift register 18 resets a plurality of shift signal output circuits when the reset signal RST is turned on (high level voltage). Then, the shift register 18 starts operation based on the start signal STV. The shift signal output circuit sequentially outputs a shift signal to the latch circuit 19 based on the clock signal CKV. Each pulse of the clock signal CKV corresponds to the gate lines GCL (1), GCL (2), ..., GCL (n). The period t _CKV of the clock signal CKV can be appropriately changed according to the time required for detection. The timing at which the clock signal CKV is supplied is, for example, the time when a period of 1/4 of the period t _CKV (t _CKV / 4) has elapsed from the timing of the rise of the start signal STV.

As shown in FIG. 30, the latch circuit 19 operates based on the shift signal from the shift register 18, the inverting reset signal xRST, the first selection signal Vc, the control signal OE, and the inverting control signal xOE. The inverting reset signal xRST is a signal in which the reset signal RST is inverted by the inverter 153A. The inverting control signal xOE is a signal in which the control signal OE is inverted by the inverter 154A. The control signal OE is a signal that controls the output of the signal from the latch circuit 19 to the buffer circuit 151.

As shown in FIG. 31, the latch circuit 19 sequentially holds the first selection signal Vc according to the shift signal from the shift register 18. The first selection signal Vc is, for example, a signal whose potential is determined for each gate line GCL according to the pattern code (predetermined code) shown in FIG. 23.

When the control signal OE is turned on, the latch circuit 19 outputs the first selection signal Vc to the buffer circuit 151. The buffer circuit 151 changes the voltage level of the first selection signal Vc according to the power supply voltages VDD and VSS. As a result, the buffer circuit 151 outputs the first gate drive signal VGH and the second gate drive signal VGL corresponding to the first selection signal Vc to the sensor unit 10.

When the control signal OE is turned on, the control board 101 sequentially supplies the signal line selection signals Vhsel (1), Vhsel (2), ..., Vhsel (6) to the signal line selection circuit 16. The signal line selection signals Vhsel (1), Vhsel (2), ..., Vhsel (6) are signals corresponding to each row of the square matrix represented by the equation (3). As a result, the signal line selection circuit 16 drives the CDM as in the first embodiment.

As shown in FIG. 31, the selected signal line SGL and AFE48 are connected to the period t _{ASW_width} when the signal line selection signal Vhsel is on. During the period when the signal line selection signal Vhsel is off (low level voltage), the signal line SGL is cut off from AFE48. The period t _{ASW_shift} is a period from the rising timing of the control signal OE to the turning on of the signal line selection signal Vhsel. The period t _{ASW_delay} is a period between the timing of the fall of the signal line selection signal Vhsel and the timing of the rise of the next signal line selection signal Vhsel. The period t _{ASW_width} , the period t _{ASW_delay} , etc. can be appropriately changed according to the time required for detection.

After all the signal line selection signals Vhsel (1), Vhsel (2), ..., Vhsel (6) are supplied to the signal line selection circuit 16, the gate line drive circuit 15A is based on the next first selection signal Vc. The first gate drive signal VGH and the second gate drive signal VGL are supplied to the sensor unit 10. The first selection signal Vc in this case is, for example, a signal whose potential is determined for each gate line GCL according to the pattern code (predetermined code) shown in FIG. 24.

The timing waveform diagram shown in FIG. 31 is merely an example. For example, during the period after the control signal OE is turned off and during the period when a plurality of signal line selection signals Vhsel are supplied to the signal line selection circuit 16, the shift register 18 and the latch circuit 19 are set to the next order. 1 The operation of holding the selection signal Vc may be performed.

(Third Embodiment)
FIG. 32 is a circuit diagram showing the AFE and the inverting circuit according to the third embodiment. In this embodiment, the configurations of the detection electrode 24, the drive electrode 32, the first switching element Tr, the second switching element xTr, the gate line drive circuit 15, the signal line selection circuit 16, and the like are the same as those of the first embodiment described above. The same applies, and detailed description thereof will be omitted. In this embodiment, the detection electrode 24 is the cathode and the drive electrode 32 (see FIG. 5) is the anode. That is, the direction in which the current Ifh flows is opposite to that in the first embodiment. Therefore, an inverting circuit 49 is provided between the signal line SGL and the amplifier 481. Although the inverting circuit 49 is arranged in the AFE 48 in FIG. 32, it may be provided on the substrate 21 side.

The inverting circuit 49 is a circuit that inverts the current Ifh flowing through the signal line SGL and outputs it to the amplifier 481. The inverting circuit 49 is a so-called current mirror circuit. The inverting circuit 49 has a fifth switching element Trb1 and a sixth switching element Trb2. The fifth switching element Trb1 and the sixth switching element Trb2 are composed of, for example, a p-channel MOS type TFT.

The gate of the fifth switching element Trb1 and the gate of the sixth switching element Trb2 are electrically connected to the common signal line SGL via the first switch SW1. The source of the fifth switching element Trb1 is electrically connected to the signal line SGL via the first switch SW1. A common power supply voltage VDD is supplied to the drain of the fifth switching element Trb1 and the drain of the sixth switching element Trb2. The source of the sixth switching element Trb2 is connected to the input of the amplifier 481 of the AFE48.

With such a configuration, the direction of the current Ifh is reversed by the inverting circuit 49, and a current having the same magnitude as the current Ifh flows through the amplifier 481 of the AFE48. The AFE48 operates in the same manner as in the first embodiment. As a result, even when the detection electrode 24 is the cathode and the drive electrode 32 is the anode, the AFE 48 can detect the current Ifh output from the detection electrode 24 according to the irradiated light.

(Fourth Embodiment)
FIG. 33 is a plan view showing the detection device according to the fourth embodiment. FIG. 34 is a circuit diagram showing a drive circuit for one detection region. As shown in FIG. 33, the detection device 1B includes a sensor unit 10, a gate line drive circuit 15A, and a reset circuit 16A. The sensor unit 10 of the present embodiment is a temperature sensor that detects the temperature. Similar to the second embodiment, the gate line drive circuit 15A sends the first gate drive signal VGH and the second gate drive signal VGL to each gate line GCL based on the first selection signal Vc supplied from the control circuit 102. Supply. The reset circuit 16A is a circuit for resetting the input units of each signal line SGL and AFE48. That is, in this embodiment, the signal line selection circuit 16 is not provided. The detection device 1B only drives the CDM by the gate line drive circuit 15A. In this embodiment, the configurations of the detection electrode 24, the drive electrode 32, the first switching element Tr, the second switching element xTr, and the like are the same as those in the first embodiment described above, and detailed description thereof will be omitted.

As shown in FIG. 34, in the detection device 1B of the present embodiment, the sensor unit 10 is a temperature sensor having an organic material layer 31A. The characteristics (for example, resistance value) of the organic material layer 31A change depending on the temperature. In FIG. 34, the organic material layer 31A is represented equivalent to a resistance element. As a result, the sensor unit 10 outputs a detection signal corresponding to the temperature to the AFE48. As the organic material layer 31A, for example, the same material as in the first embodiment can be used.

As shown in FIG. 34, the circuit configurations of the detection electrode 24, the first switching element Tr, the second switching element xTr, the signal line SGL, the gate line GCL, the reference signal line COM, and the like are the same as those in the first embodiment. When the gate line drive circuit 15A supplies the first gate drive signal VGH to the gate line GCL, the first switching element Tr is turned on. As a result, the detection electrode 24 is selected as the detection target. A current Ifh corresponding to the temperature flows from the detection electrode 24 to the signal line SGL. On the other hand, the second switching element xTr is turned off. Therefore, the current Idh flowing from the detection electrode 24 to the reference signal line COM is suppressed. In this way, the sensor unit 10 changes the signal (current Ifh) output from the detection electrode 24 according to the temperature of the organic material layer 31A. As a result, the detection device 1B can detect the temperature.

When the gate line drive circuit 15A supplies the second gate drive signal VGL to the gate line GCL, the first switching element Tr is turned off. As a result, the current Idl flowing from the detection electrode 24 to the signal line SGL is suppressed, and the detection electrode 24 becomes a non-detection target. On the other hand, the second switching element xTr is turned on. Therefore, a current Ifl flows from the detection electrode 24 to the reference signal line COM. A reference signal Vcom is supplied to the reference signal line COM from the control board 101. As a result, fluctuations in the potential of the detection electrode 24 to be non-detected are suppressed.

FIG. 35 is a circuit diagram showing a reset circuit. As shown in FIG. 35, the reset circuit 16A has a plurality of seventh switching elements Trc, a reference signal supply line LB1 and a reset signal supply line LB2. In the present embodiment, the plurality of signal lines SGL are connected to AFE48, respectively. That is, the CDM drive of the signal line SGL is not performed, and the output signal of the detection electrode 24 is output to the AFE 48 via the signal line SGL.

A plurality of seventh switching elements Trc are provided for each signal line SGL. The plurality of seventh switching elements Trc are composed of, for example, a p-channel MOS type TFT. The gate of the seventh switching element Trc is connected to the common reset signal supply line LB2. The source of the seventh switching element Trc is connected to the common reference signal supply line LB1. The drain of the seventh switching element Trc is connected to the signal line SGL, respectively.

When the reset signal Reset has a high level voltage, the reference signal supply line LB1 and the signal line SGL are cut off. That is, the detection signal of the detection electrode 24 is output to the AFE 48 via the signal line SGL. When the reset signal Reset has a low level voltage, the reference signal supply line LB1 and the signal line SGL are connected. In this embodiment, all signal lines SGL are simultaneously connected to the reference signal supply line LB1. As a result, the reference signal VR is supplied to the input units of the signal lines SGL and AFE48. As a result, the input units of the signal lines SGL and AFE48 are reset.

The high level voltage reset signal Vreset is supplied to the reset signal supply line LB2 at the timing after the control signal OE shown in FIG. 31 is supplied. In other words, the detection period is the period during which the reset signal Vreset of the high level voltage is supplied after the first selection signal Vc is sequentially held in the latch circuit 19.

(Fifth Embodiment)
FIG. 36 is a cross-sectional view showing a schematic cross-sectional configuration of the detection device according to the fifth embodiment. FIG. 37 is a plan view schematically showing the detection device according to the fifth embodiment. FIG. 38 is a plan view showing the relationship between the detection electrode, the drive electrode, the eighth switching element, and the ninth switching element. FIG. 39 is an enlarged plan view showing the region C4 of FIG. 38.

The detection device 1C of the present embodiment is a temperature sensor as in the fourth embodiment. As shown in FIG. 36, the backplane 2 includes a substrate 21, a TFT layer 22, an insulating layer 23, a detection electrode 24A, and a drive electrode 32A. The TFT layer 22 is provided with circuits such as a gate line drive circuit 15A and a reset circuit 16A (see FIGS. 34 and 35). Further, the TFT layer 22 is provided with various wirings such as an eighth switching element Trd and a ninth switching element xTrd (see FIG. 38), a gate line GCL, and a signal line SGL (see FIG. 7). In the present embodiment, the detection electrode 24A and the drive electrode 32A are provided on the same insulating layer 23. In other words, the drive electrode 32A is provided adjacent to the detection electrode 24A in the same layer. For the detection electrode 24A and the drive electrode 32A, a conductive material having translucency such as ITO is used. The driving electrode 32A is not limited to this, and a metal material such as silver (Ag) or aluminum (Al) can also be used.

The organic sensor layer 3 includes an organic material layer 31 and a protective layer 33. The organic material layer 31 is provided on the plurality of detection electrodes 24A and the plurality of drive electrodes 32A. The organic material layer 31 has a resistance component between the adjacent detection electrodes 24A and the driving electrodes 32A.

As shown in FIG. 37, the plurality of partial detection regions SAA are arranged in a matrix over the entire detection region AA. The partial detection region SAA includes an organic material layer 31, a plurality of detection electrodes 24A, and a plurality of drive electrodes 32A. The organic material layer 31 is provided in a matrix shape separated from each other for each partial detection region SAA. The organic material layer 31 is patterned by, for example, a photolithography method.

The plurality of detection electrodes 24A and the plurality of drive electrodes 32A are alternately arranged in the second direction Dy. Further, the plurality of detection electrodes 24A and the plurality of drive electrodes 32A are respectively arranged in the first direction Dx. The partial detection region SAA includes two detection electrodes 24A and two drive electrodes 32A. In other words, two detection electrodes 24A and two drive electrodes 32A are provided so as to overlap with one organic material layer 31. Note that FIG. 37 is merely an example, and one partial detection region SAA may be provided with three or more detection electrodes 24A and three or more drive electrodes 32A.

FIG. 38 shows two partial detection regions SAA adjacent to each other in the first direction Dx. In FIG. 38, the organic material layer 31 is not shown in order to make the drawing easier to see. As shown in FIG. 38, the two partial detection regions SAA have an axisymmetric configuration with the reference line C3 as the axis of symmetry. Here, the reference line C3 is a virtual line that passes between the partial detection regions SAA adjacent to the first direction Dx and is along the second direction Dy. In the following description, the partial detection region SAA on the left side of the reference line C3 will be described.

As shown in FIG. 38, the partial detection region SAA is provided with two detection electrodes 24A, two drive electrodes 32A, an eighth switching element Trd, and a ninth switching element xTrd. The detection electrode 24A and the drive electrode 32A each have a rectangular shape having a length in the first direction Dx. Further, the detection electrode 24A and the drive electrode 32A are alternately provided in the second direction Dy. The organic material layer 31 forms a resistance component between the detection electrode 24A and the drive electrode 32A adjacent to each other in the second direction Dy.

One end of the two detection electrodes 24A is connected to the common eighth switching element Trd via the contact holes HC1 and HC3, respectively. By the operation of the eighth switching element Trd, one end of the two detection electrodes 24A is connected to the common signal line SGL. The other ends of the two detection electrodes 24A are connected to the common ninth switching element xTrd via the contact holes HC2 and HC4, respectively. By the operation of the ninth switching element xTrd, the other ends of the two detection electrodes 24A are connected to the common reference signal line COM. The plurality of detection electrodes 24A belonging to the plurality of partial detection regions SAA arranged in the second direction Dy are also similarly connected to the common signal line SGL and also to the common reference signal line COM.

In this example, the eighth switching element Trd is composed of an n-channel MOS type TFT. In this example, the ninth switching element xTrd is composed of a p-channel MOS type TFT.

FIG. 39 shows a connection portion between one end of the detection electrode 24A and the eighth switching element Trd. The eighth switching element Trd has a semiconductor layer 61b, a source electrode 62b, a drain electrode 63b, and a gate electrode 64b.

The gate electrode 64b is connected to the gate wire GCL and is provided along the second direction Dy. In the present embodiment, the gate line GCL is provided corresponding to the partial detection region SAA arranged in the second direction Dy. The gate electrode 64b is provided adjacent to the signal line SGL. The semiconductor layer 61b is provided so as to overlap with the gate electrode 64b. The width of the semiconductor layer 61b in the first direction Dx is larger than the width of the gate electrode 64b in the first direction Dx. One end (left end) of the semiconductor layer 61b is connected to the drain electrode 63b via a plurality of contact holes HC6. The other end (right end) of the semiconductor layer 61b is connected to the source electrode 62b via a plurality of contact holes HC5.

The drain electrode 63b and the source electrode 62b each extend in the second direction Dy. The width of the second direction Dy of the drain electrode 63b and the width of the second direction Dy of the source electrode 62b are larger than the width of the second direction Dy of the detection electrode 24A. The plurality of contact hole HC6 and the plurality of contact hole HC5 are arranged along the extending direction of the drain electrode 63b and the source electrode 62b, respectively.

The connection portion 63ba of the drain electrode 63b is connected to the detection electrode 24A via a plurality of contact holes HC1. The source electrode 62b is connected to the signal line SGL. In other words, a part of the signal line SGL functions as the source electrode 62b. A plurality of detection electrodes 24A belonging to the same partial detection region SAA (see FIG. 38) are connected to the drain electrode 63b.

The eighth switching element Trd is connected between layers via a plurality of contact hole HC1, a plurality of contact hole HC5, and a plurality of contact hole HC6. Therefore, the connection resistance of the eighth switching element Trd can be suppressed. As a result, the detection device 1C can improve the detection performance. The ninth switching element xTrd has the same configuration, and detailed description thereof will be omitted.

As shown in FIG. 38, the other end (right end) of the two drive electrodes 32A is connected to the common drive signal supply line Lvd via the contact holes HC7 and HC8, respectively. One end (left end) of the two drive electrodes 32A is not connected to other wiring or the like. The drive signal supply line Lvd passes between the partial detection regions SAA adjacent to the first direction Dx and is provided along the second direction Dy. The drive signal supply line Lvd is a wiring for supplying the drive signal VDD_ORG (see FIG. 34) to the drive electrode 32A. In the partial detection region SAA adjacent to each other with the drive signal supply line Lvd in between, a plurality of drive electrodes 32A (for example, four or more) are connected to a common drive signal supply line Lvd.

Also in this embodiment, CDM drive is performed by the gate line drive circuit 15A. The gate line drive circuit 15A supplies the first gate drive signal VGH and the second gate drive signal VGL whose potentials are determined based on a predetermined code to each gate line GCL. As a result, the detection electrodes 24A belonging to the plurality of partial detection regions SAA selected as detection targets are connected to the signal line SGL. The detection electrode 24A belonging to the plurality of partial detection regions SAA to be non-detected is connected to the reference signal line COM. The signal processing unit 44 can calculate the decoded signal for each partial detection area SAA by decoding a plurality of output signals.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various changes can be made without departing from the spirit of the present invention. Appropriate changes made without departing from the spirit of the present invention naturally belong to the technical scope of the present invention.

For example, in the detection device 1B of the fourth embodiment and the detection device 1C of the fifth embodiment, the gate line drive circuit 15A does not include a code generation circuit, but is not limited thereto. The detection devices 1B and 1C may have a gate line drive circuit 15 including a code generation circuit, as in the first embodiment. Further, the detection devices 1B and 1C may have a signal line selection circuit 16 as in the first embodiment.

1, 1A, 1B, 1C Detection device 2 Backplane 3 Organic sensor layer 10 Sensor unit 11 Detection control unit 12 1st code generation circuit 13 2nd code generation circuit 14 3rd code generation circuit 15 Gate line drive circuit 16 Signal line selection Circuit 16A Reset circuit 17 Control signal generation circuit 21 Board 22 TFT layer 24 Detection electrode 29 Drive electrode connection terminal 31 Organic material layer 31a Opening 32 Drive electrode 33 Protective layer 40 Detection unit 48 AFE
49 Inversion circuit 101 Control board AA Detection area BKx 1st detection electrode block BKy 2nd detection electrode block COM Reference signal line GA Frame area GCL Gate line LB1 Reference signal supply line LB2 Reset signal supply line Lout Output signal line SGL signal line Tr 1 switching element xTr 2nd switching element Vc 1st selection signal VDD_ORG drive signal VGH 1st gate drive signal VGL 2nd gate drive signal

Claims (11)

With the board
An organic material layer provided on the substrate and constituting an optical sensor,
A plurality of detection electrodes provided between the substrate and the organic material layer,
A first switching element provided in each of the plurality of detection electrodes, a second switching element different from the first switching element, and a second switching element.
A gate line connected to the first switching element and the second switching element and extending in the first direction,
A signal line connected to the first switching element and extending in the second direction intersecting the first direction,
A reference signal line connected to the second switching element and supplying a reference signal having a potential fixed to the detection electrode, and a reference signal line.
It has a drive circuit that supplies a gate drive signal to the gate line, and has.
The first switching element is a first conductive type TFT, and the second switching element is a second conductive type TFT.
Detection device. The first detection electrode block including the plurality of detection electrodes arranged in the first direction is connected to the drive circuit via the common gate wire.
The detection device according to claim 1. It has a code generation circuit that generates a selection signal whose phase is determined for each gate line based on a predetermined code.
The drive circuit generates the gate drive signal based on the selection signal.
The detection device according to claim 1 or 2. Further, it has a control board different from the above board and has a different control board.
The substrate has a detection region provided with the plurality of detection electrodes and a frame region outside the detection region.
The drive circuit includes the code generation circuit and is provided in the frame region of the substrate.
The code generation circuit is provided on the control board.
The detection device according to claim 3. An analog front-end circuit that receives signals output from the plurality of detection electrodes,
It has a signal line selection circuit provided on the substrate, and has.
The signal line selection circuit connects the signal line to be detected and the analog front-end circuit among the plurality of the signal lines based on a predetermined code.
The detection device according to any one of claims 1 to 4. The second detection electrode block including the plurality of detection electrodes arranged in the second direction is connected to the signal line selection circuit via the common signal line.
The detection device according to claim 5. The same gate drive signal is supplied from the drive circuit to the first switching element and the second switching element via the common gate line.
The first switching element connects the detection electrode to be detected and the signal line.
The second switching element connects the detection electrode to be non-detection target and the reference signal line.
The reference signal line supplies a reference signal having a fixed potential to the detection electrode of the non-detection target.
The detection device according to any one of claims 1 to 6. The reference signal line is provided between the two detection electrodes adjacent to each other in the first direction.
The two detection electrodes adjacent to each other in the first direction are connected to the common reference signal line via the second switching element provided in each of the two detection electrodes.
The detection device according to claim 7. It has a plurality of drive electrodes provided in the same layer as the plurality of detection electrodes.
The detection device according to any one of claims 1 to 8. The detection electrode is the cathode, the drive electrode is the anode, and
An inverting circuit that inverts and outputs the current flowing through the signal line is connected to the signal line.
The detection device according to claim 9. The signal output from the detection electrode changes according to the amount of light emitted to the organic material layer.
The detection device according to any one of claims 1 to 10.

Images