JP2022017550A - Silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device, capable of suppressing the expansion of stacking defects stably at low cost.

SOLUTION: A silicon carbide semiconductor device includes a semiconductor substrate 16 of a second conductivity type, a first semiconductor layer 3 of a first conductivity type, a second semiconductor layer 4 of the second conductivity type, a first semiconductor region 17 of the first conductivity type, a gate insulating film 5, and a gate electrode 6. Protons are injected into: a first region having a predetermined depth from the surface of the semiconductor substrate 16 on the side of the first semiconductor layer 3; a second region having a predetermined depth from the surface of the first semiconductor layer 3 on the side of the semiconductor substrate 16; a third region having a predetermined depth from the surface of the first semiconductor layer 3 on the side of the second semiconductor layer 4; and a fourth region having a predetermined depth from the surface of the second semiconductor layer 4 on the side of the first semiconductor layer 3.

SELECTED DRAWING: Figure 20

COPYRIGHT: (C)2022,JPO&INPIT

Description

The present invention relates to silicon carbide semiconductor devices.

Conventionally, silicon (Si) has been used as a constituent material of a power semiconductor device that controls a high voltage or a large current. There are multiple types of power semiconductor devices such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors: Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which can be used according to the application. Has been done.

For example, bipolar transistors and IGBTs have a higher current density than MOSFETs and can increase the current, but they cannot be switched at high speed. Specifically, the bipolar transistor is limited to use at a switching frequency of about several kHz, and the IGBT is limited to use at a switching frequency of about several tens of kHz. On the other hand, the power MOSFET has a lower current density than the bipolar transistor and the IGBT, and it is difficult to increase the current, but high-speed switching operation up to about several MHz is possible.

However, there is a strong demand in the market for power semiconductor devices that have both high current and high speed, and efforts are being made to improve IGBTs and power MOSFETs, and development is now progressing to near the material limit. .. Silicon carbide (SiC) is being studied as a semiconductor material that can replace silicon from the viewpoint of power semiconductor devices, and can manufacture (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics. Is attracting attention.

In the background, SiC is a chemically stable material, has a wide bandgap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. This is also because the maximum electric field strength is one order of magnitude higher than that of silicon. Since SiC has a high possibility of exceeding the material limit of silicon, future growth is expected in power semiconductor applications, especially MOSFETs. In particular, it is expected that the on-resistance is small, but a silicon carbide MOSFET having a lower on-resistance while maintaining high withstand voltage characteristics can be expected.

The structure of a conventional silicon carbide semiconductor device will be described by taking a vertical MOSFET having a trench structure as an example. FIG. 30 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. As shown in FIG. 30, a high-concentration n-type epitaxial layer 102 is deposited on the front surface of the n ⁺ type silicon carbide semiconductor substrate 101, and an n ^- type drift layer 103 is deposited on the surface of the high-concentration n-type epitaxial layer 102. Will be done. A p ⁺ type base region 104 is selectively provided on the surface of the n ^- type drift layer 103.

A trench structure is formed on the p ⁺ type base region 104 side of the silicon carbide semiconductor device. Specifically, the trench 115 penetrates the p ⁺ type base region 104 from the surface opposite to the n ⁺ type silicon carbide semiconductor substrate 101 side of the p ⁺ type base region 104 to form the n ^- type drift layer 103. Reach. A gate insulating film 105 is formed on the bottom and side walls of the trench 115 along the inner wall of the trench 115, and a gate electrode 106 is formed inside the gate insulating film 105 in the trench 115. Further, the n ⁺ type source region 108 and the p ⁺ type contact region 107 are selectively provided on the surface of the p ⁺ type base layer 104.

Here, FIG. 31 is a graph showing the impurity concentration of the conventional silicon carbide semiconductor device. FIG. 31 shows the impurity concentration of the AA1 portion of FIG. 30, the vertical axis shows the depth from the surface of the p ⁺ type contact region 107, and the horizontal axis shows the impurity concentration. The dotted line on the horizontal axis indicates the interface between the n ⁺ type silicon carbide semiconductor substrate 101 and the high-concentration n-type epitaxial layer 102. As shown in FIG. 31, the impurity concentration of the p ⁺ type contact region 107 is higher than the impurity concentration of the p ⁺ type base region 104, and the n ^- type drift layer 103, the high concentration n-type epitaxial layer 102, and the n ⁺ type silicon carbide semiconductor The impurity concentration increases in the order of the substrate 101.

Further, the interlayer insulating film 109 is provided so as to cover the gate electrode 106 embedded in the trench 115. The source electrode 110 is in contact with the n ⁺ type source region 108 and the p ⁺ type contact region 107 through the contact hole opened in the interlayer insulating film 109. A drain electrode (not shown) is provided on the back surface of the n ⁺ type silicon carbide semiconductor substrate 101.

A vertical MOSFET having such a structure incorporates a parasitic pn diode formed by a p ⁺ type base region 104 and an n ^- type drift layer 103 as a body diode between a source and a drain. This parasitic pn diode can be operated by applying a high potential to the source electrode 110, from the p ⁺ type contact region 107 to the p ⁺ type base region 104, the n ^- type drift layer 103, and the high concentration n-type epitaxial layer. A current flows in the direction toward the n ⁺ type silicon carbide semiconductor substrate 101 (the direction indicated by the arrow B in FIG. 30) via the 102. As described above, unlike the IGBT, the MOSFET has a built-in parasitic pn diode, so that the freewheeling diode (FWD: Free Wheeling Diode) used for the inverter can be omitted, which contributes to cost reduction and miniaturization. Hereinafter, the parasitic pn diode of the MOSFET is referred to as a built-in diode.

FIG. 32 is a graph showing the hole density of a conventional silicon carbide semiconductor device. Further, FIG. 33 is a graph showing the electron density of the conventional silicon carbide semiconductor device. 32 and 33 show the hole density and the electron density of the AA1 portion of FIG. 30, the vertical axis shows the depth from the surface of the p ⁺ type contact region 107, and the horizontal axis shows the hole density and the electron density, respectively. Is shown. The dotted line on the horizontal axis indicates the interface between the n ⁺ type silicon carbide semiconductor substrate 101 and the high-concentration n-type epitaxial layer 102.

As shown in FIGS. 32 and 33, holes are present in the p ⁺ type contact region 107, and electrons are present in the n ⁺ type silicon carbide semiconductor substrate 101 and the high concentration n-type epitaxial layer 102. Therefore, the built-in diode has a hole. When a current flows, holes are injected from the p ⁺ type contact region 107, and electron and hole recombination occurs in the n ⁻ type drift layer 103 or the n ⁺ type silicon carbide semiconductor substrate 101. At this time, if there is a defect in the crystal of the n ⁺ type silicon carbide semiconductor substrate 101, it is a kind of crystal defect existing in the n ⁺ type silicon carbide semiconductor substrate 101 due to the generated recombination energy (3eV) corresponding to the band gap. The basal plane dislocations move and the stacking defects sandwiched between the two basal plane dislocations expand. Here, FIG. 34 is a cross-sectional view showing a stacking defect of a conventional silicon carbide semiconductor device. FIG. 35 is a top view showing a stacking defect of a conventional silicon carbide semiconductor device. FIG. 34 shows an example in which the basal plane dislocations 111 grow into stacking defects 112. FIG. 35 is an example of a PL (Photoluminescence) image of an element in which a stacking defect has occurred after a current is applied, and it can be seen that a triangular stacking defect 113 and a strip-shaped stacking defect 114 have occurred.

When the stacking defect expands, the stacking defect does not easily carry current, so that the on-resistance of the MOSFET and the forward voltage of the built-in diode increase. If such an operation continues, the stacking defects are cumulatively expanded, so that the loss generated in the inverter circuit increases with time and the amount of heat generated also increases, which causes a device failure. In order to prevent this problem, a SiC-SBD (Schottky Barrier Diode) can be connected in antiparallel to the MOSFET so that current does not flow to the built-in diode of the MOSFET.

Further, as shown in FIG. 30, by providing the high-concentration n-type epitaxial layer 102, it is possible to prevent the growth of stacking defects. By forming such a high doping layer, a lifetime killer is introduced to capture holes from the n ^- type drift layer 103, and the generation of stacking defects and the expansion of the area thereof are suppressed.

Also, minority carriers in the boundary layer can be introduced by introducing a lifetime killer using either transition metal doping or intrinsic internal growth defects or externally generated intrinsic defects by electron or proton irradiation techniques during or after epitaxial growth. There is a technique for reducing the number of substances (see Patent Document 1 below). Further, there is a technique for forming crystal defects by injecting at least a proton, helium (He), rare gas, platinum (Pt), vanadium (V), group 4 ion or the like into a silicon carbide semiconductor substrate ( See Patent Document 2 below).

Japanese Patent No. 4939777 U.S. Patent Application Publication No. 2017/0012102

However, the high-concentration n-type epitaxial layer 102 requires, for example, a film thickness of 5 μm to 10 μm and an impurity concentration of 2 × 10 ¹⁸ / cm ³ or more. The film formation of such a thick high-concentration n-type epitaxial layer 102 has problems that it leads to an increase in cost due to a decrease in throughput of epitaxial growth, a decrease in yield due to an increase in defect density, and an increase in resistance of a substrate. Further, there is a problem that the accuracy of the lifetime due to the high-concentration n-type epitaxial layer 102 varies greatly depending on the density and the film thickness.

An object of the present invention is to provide a silicon carbide semiconductor device capable of stably suppressing expansion of stacking defects at low cost in order to solve the above-mentioned problems caused by the prior art.

In order to solve the above-mentioned problems and achieve the object of the present invention, the silicon carbide semiconductor device according to the present invention has the following features. A first conductive type first semiconductor layer is provided on the second conductive type semiconductor substrate. A second conductive type second semiconductor layer is provided on the side of the first semiconductor layer opposite to the semiconductor substrate side. The surface layer of the second semiconductor layer opposite to the first semiconductor layer is selectively provided with a first conductive type first semiconductor region having a higher impurity concentration than the first semiconductor layer. A gate electrode is provided at least a part on the surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer via a gate insulating film. A first region of the semiconductor substrate having a predetermined depth from the surface of the first semiconductor layer side, a second region of the first semiconductor layer having a predetermined depth from the surface of the semiconductor substrate side, the first semiconductor. Protons are generated in the third region of the layer at a predetermined depth from the surface on the second semiconductor layer side and in the fourth region of the second semiconductor layer from the surface on the first semiconductor layer side to a predetermined depth. It has been injected.

Further, in the above-described invention, the silicon carbide semiconductor device according to the present invention is the semiconductor of the first region of the semiconductor substrate, which is 2 μm or more from the surface of the first semiconductor layer side, and the first semiconductor layer. It is characterized in that protons having a concentration of 1 × 10 ¹³ / cm ³ or more and 1 × 10 ¹⁵ / cm ³ or less are injected into the second region of 3 μm or more from the surface on the substrate side.

According to the above-mentioned invention, the vicinity of the interface between the second conductive type semiconductor substrate and the first conductive type first semiconductor layer, and the first conductive type first semiconductor layer and the second conductive type second semiconductor layer. Protons are injected near the interface of the semiconductor as a lifetime killer. As a result, the hole density at the interface between the second conductive type semiconductor substrate and the first conductive type first semiconductor layer, and the interface between the first conductive type first semiconductor layer and the second conductive type second semiconductor layer. Can be reduced and the growth of crystal defects can be suppressed.

Further, when the first conductive type first semiconductor layer is formed by epitaxial growth, the accuracy of the lifetime varies greatly depending on the concentration and the film thickness. On the other hand, in the present invention, since proton irradiation is performed by ion implantation, the lifetime killer has good controllability and can be stably formed. Moreover, since it is performed by ion implantation, it can be produced at a lower cost than epitaxial growth.

According to the silicon carbide semiconductor device according to the present invention, there is an effect that expansion of stacking defects can be stably suppressed at low cost.

It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is a graph which shows the proton concentration of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is a graph which shows the hole density of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is a graph which shows the DLTS signal of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is a flowchart which shows a part of manufacturing of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 1). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 2). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 3). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 2. FIG. It is a graph which shows the proton concentration of the silicon carbide semiconductor device which concerns on Embodiment 2. It is a graph which shows the hole density of the silicon carbide semiconductor device which concerns on Embodiment 2. It is a graph which shows the characteristic of the built-in diode of the silicon carbide semiconductor device which concerns on Embodiment 2. It is a graph which shows the current characteristic at the time of the reverse recovery of the silicon carbide semiconductor device which concerns on Embodiment 2. It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 3. FIG. It is a graph which shows the proton concentration of the silicon carbide semiconductor device which concerns on Embodiment 3. It is a graph which shows the hole density of the silicon carbide semiconductor device which concerns on Embodiment 3. FIG. It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 4. FIG. It is a graph which shows the helium concentration of the silicon carbide semiconductor device which concerns on Embodiment 4. It is a graph which shows the hole density of the silicon carbide semiconductor device which concerns on Embodiment 4. It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 5. It is a graph which shows the proton concentration of the silicon carbide semiconductor device which concerns on Embodiment 5. It is a graph which shows the hole density of the silicon carbide semiconductor device which concerns on Embodiment 5. It is a graph which shows the IcVce characteristic of the silicon carbide semiconductor device which concerns on Embodiment 5. It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 6. It is a graph which shows the proton concentration of the silicon carbide semiconductor device which concerns on Embodiment 6. It is a graph which shows the CV characteristic of the silicon carbide semiconductor device which concerns on Embodiment 6. It is a graph which shows the proton concentration of the silicon carbide semiconductor device of an Example. It is a graph which shows the hole density of the silicon carbide semiconductor device of an Example. It is a graph which shows the hole density of the silicon carbide semiconductor device of the conventional example. It is sectional drawing which shows the structure of the conventional silicon carbide semiconductor device. It is a graph which shows the impurity concentration of the conventional silicon carbide semiconductor device. It is a graph which shows the hole density of the conventional silicon carbide semiconductor device. It is a graph which shows the electron density of the conventional silicon carbide semiconductor device. It is sectional drawing which shows the stacking defect of the conventional silicon carbide semiconductor device. It is a top view which shows the stacking defect of the conventional silicon carbide semiconductor device.

Hereinafter, preferred embodiments of the silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electron or hole is a large number of carriers in the layer or region marked with n or p, respectively. Further, + and-attached to n and p mean that the concentration of impurities is higher and the concentration of impurities is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted. Further, in the present specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after that, and a negative index is represented by adding "-" in front of the index.

(Embodiment 1)
FIG. 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment. In the first embodiment, the case where the silicon carbide semiconductor device is a MOSFET is shown. As shown in FIG. 1, the silicon carbide semiconductor device according to the first embodiment is a first main surface (front surface) of an n ⁺ type silicon carbide semiconductor substrate (first conductive type semiconductor substrate) 1, for example, ( An n-type boundary layer 2 and an n ^- type drift layer (first conductive type first semiconductor layer) 3 are deposited on the 0001) plane (Si plane).

The n ⁺ type silicon carbide semiconductor substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). The n-type boundary layer 2 is doped with nitrogen, for example, at an impurity concentration lower than that of the n ⁺ type silicon carbide semiconductor substrate 1. The n-type boundary layer 2 is provided so that the crystal defects of the n ⁺ type silicon carbide semiconductor substrate 1 are not transmitted to the n ^- type drift layer 3. The n ^- type drift layer 3 is a low-concentration n-type drift layer in which an impurity concentration lower than that of the n ⁺ type silicon carbide semiconductor substrate 1 and, for example, nitrogen is doped. Hereinafter, the n ⁺ type silicon carbide semiconductor substrate 1, the n-type boundary layer 2, the n ^- type drift layer 3, and the p ⁺ type base region (second conductive type second semiconductor layer) 4 described later are combined to form a silicon carbide semiconductor. Use as a substrate.

A back surface electrode (not shown) is provided on the second main surface (back surface, that is, the back surface of the silicon carbide semiconductor substrate) of the n ⁺ type silicon carbide semiconductor substrate 1. The back electrode constitutes a drain electrode. A drain electrode pad (not shown) is provided on the surface of the back surface electrode.

A trench structure is formed on the first main surface side (p ⁺ type base region 4 side) of the silicon carbide semiconductor substrate. Specifically, the trench 15 is a p ⁺ type base region from the surface of the p ⁺ type base region 4 opposite to the n ⁺ type silicon carbide semiconductor substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate). It penetrates 4 and reaches the n ^- type drift layer 3. A gate insulating film 5 is formed on the bottom and side walls of the trench 15 along the inner wall of the trench 15, and a gate electrode 6 is formed inside the gate insulating film 5 in the trench 15. The gate electrode 6 is insulated from the n ⁻ type drift layer 3 and the p ⁺ type base region 4 by the gate insulating film 5. A part of the gate electrode 6 may protrude from above the trench 15 (source electrode 10 side) toward the source electrode 10.

A p ⁺ type base region 4 is provided on the first main surface side of the substrate of the n ⁻ type drift layer 3. Inside the p ⁺ type base region 4, an n ⁺ type source region (first conductive type first semiconductor region) 8 and a p ⁺ type contact region 7 are selectively provided on the first main surface side of the substrate. .. The n ⁺ type source region 8 is in contact with the trench 15. Further, the n ⁺ type source region 8 and the p ⁺ type contact region 7 are in contact with each other.

Although only four trench MOS structures are shown in FIG. 1, more MOS gate (insulated gates made of metal-oxide film-semiconductor) structures of trench structures may be arranged in parallel.

The interlayer insulating film 9 is provided on the entire surface of the silicon carbide semiconductor substrate on the first main surface side so as to cover the gate electrode 6 embedded in the trench 15. The source electrode 10 is in contact with the n ⁺ type source region 8 and the p ⁺ type contact region 7 through the contact hole opened in the interlayer insulating film 9. The source electrode 10 is electrically insulated from the gate electrode 6 by the interlayer insulating film 9. A source electrode pad (not shown) is provided on the source electrode 10. A barrier metal (not shown) may be provided between the source electrode 10 and the interlayer insulating film 9 to prevent the diffusion of metal atoms from the source electrode 10 to the gate electrode 5 side, for example.

In the silicon carbide semiconductor device of the first embodiment, protons are injected as a lifetime killer in the vicinity of the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2. This proton serves as a lifetime killer and can reduce the hole density at the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2 by two orders of magnitude or more. This can reduce the recombination of holes and electrons and suppress the growth of crystal defects.

FIG. 2 is a graph showing the proton concentration of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 shows the proton concentration of the AA1 portion of FIG. 1, the vertical axis shows the depth from the surface of the p ⁺ type contact region 7, and the horizontal axis shows the proton concentration. The dotted line on the horizontal axis indicates the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2.

As shown in FIGS. 1 and 2, for example, the proton is a region of the n ⁺ type silicon carbide semiconductor substrate 1 having a depth of h1 (for example, 2 μm) or more from the surface on the n-type boundary layer 2 side, and an n-type. Protons are injected from the surface of the boundary layer 2 on the side of the n ⁺ type silicon carbide semiconductor substrate 1 to a region having a depth of h2 (for example, 3 μm) or more. Protons have a concentration of 1 × 10 ¹³ / cm ³ or more and 1 × 10 ¹⁵ / cm ³ or less. This is because if the concentration is lower than 1 × 10 ¹³ / cm ³ , it does not function sufficiently as a lifetime killer, and if it is higher than 1 × 10 ¹⁵ / cm ³ , no current flows through the built-in diode.

For example, by setting the proton to a concentration of 1 × 10 ¹⁴ / cm ³ , the hole density at the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2 is reduced to 1 × 10 ¹⁵ / cm ³ or less. It is possible to prevent crystal defects from occurring even at a current density of 1500 A / cm ² .

Further, FIG. 3 is a graph showing the hole density of the silicon carbide semiconductor device according to the first embodiment. FIG. 3 shows the hole density of the AA1 portion of FIG. 1, the vertical axis shows the depth from the surface of the p ⁺ type contact region 7, and the horizontal axis shows the hole density. The dotted line on the horizontal axis indicates the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2. As shown in FIG. 3, the hole density at the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2 is lower than that of the conventional example (see FIG. 32).

Here, FIG. 4 is a graph showing the DLTS signal of the silicon carbide semiconductor device according to the first embodiment. In FIG. 4, the vertical axis shows the intensity of the DLTS signal, the horizontal axis shows the temperature, and the unit is K (Kelvin). The DLTS (Deep Level Transient Spectroscopy) method is a method that can measure impurities and defects in a semiconductor with high sensitivity. FIG. 4 shows the DLTS signal of a proton-injected silicon carbide semiconductor and carbonization without proton injection. The DLTS signal of the silicon semiconductor is shown. As shown in FIG. 4, it can be seen that the silicon carbide semiconductor without proton injection has a peak at 300K, and the silicon carbide semiconductor with proton injection has a peak at 300K and 420K. Therefore, the DLTS method makes it possible to detect a silicon carbide semiconductor device in which a proton is injected into the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2.

(Manufacturing method of silicon carbide semiconductor device according to the first embodiment)
Next, a method for manufacturing the silicon carbide semiconductor device according to the first embodiment will be described. FIG. 5 is a flowchart showing a part of manufacturing of the silicon carbide semiconductor device according to the first embodiment. 6 to 8 are cross-sectional views schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 5 describes in detail the steps related to proton irradiation of the present invention.

First, an n ⁺ type silicon carbide semiconductor substrate 1 made of n-type silicon carbide is prepared. Then, an n-type boundary layer 2 made of silicon carbide is epitaxially grown on the first main surface of the n ⁺ type silicon carbide semiconductor substrate 1 while doping n-type impurities such as nitrogen atoms. Next, an n ^- type drift layer 3 made of silicon carbide is epitaxially grown on the n-type boundary layer 2 while doping n-type impurities such as nitrogen atoms. The state up to this point is shown in FIG.

Next, a p ⁺ type base region 4 doped with a p-type impurity such as aluminum is formed on the surface of the n ^- type drift layer 3. Next, an ion implantation mask having a predetermined opening is formed on the surface of the p ⁺ type base region 4 by photolithography, for example, with an oxide film. An n-type impurity such as phosphorus (P) is ion-implanted into this opening to form an n ⁺ -type source region 8 on a part of the surface of the p ⁺ -type base region 4. The impurity concentration of the n ⁺ type source region 8 is set to be higher than the impurity concentration of the p ⁺ type base region 4.

Next, the ion implantation mask used for forming the n ⁺ type source region 8 is removed, and an ion implantation mask having a predetermined opening is formed by the same method, and the surface of the p ⁺ type base region 4 is formed. A p-type impurity such as aluminum is ion-implanted into a part to form a p ⁺ type contact region 7. The impurity concentration of the p ⁺ type contact region 7 is set to be higher than the impurity concentration of the p ⁺ type base region 4. The state up to this point is shown in FIG.

Next, heat treatment (annealing) is performed in an inert gas atmosphere of about 1700 ° C. to activate the n ⁺ type source region 8 and the p ⁺ type contact region 7. As described above, each ion implantation region may be activated collectively by one heat treatment, or may be activated by heat treatment each time ion implantation is performed.

Next, a trench forming mask having a predetermined opening is formed on the surface of the p ⁺ type base region 4 by photolithography, for example, with an oxide film. Next, a trench 15 is formed by dry etching through the p ⁺ type base region 4 and reaching the n ⁻ type drift layer 3. Next, the trench forming mask is removed.

Next, a gate insulating film 5 is formed along the surfaces of the n ⁺ type source region 8 and the p ⁺ type contact region 7 and the bottom and side walls of the trench 15. The gate insulating film 5 may be formed by thermal oxidation by heat treatment at a temperature of about 1000 ° C. in an oxygen atmosphere. Further, the gate insulating film 5 may be formed by a method of depositing by a chemical reaction such as high temperature oxidation (HTO).

Next, a polycrystalline silicon layer doped with, for example, a phosphorus atom is provided on the gate insulating film 5. This polycrystalline silicon layer may be formed so as to fill the inside of the trench 15. The gate electrode 6 is formed by patterning this polycrystalline silicon layer by photolithography and leaving it inside the trench 15.

Next, for example, phosphorus glass is formed with a thickness of about 1 μm so as to cover the gate insulating film 5 and the gate electrode 6, and an interlayer insulating film 9 is formed (step S1). Next, a barrier metal (not shown) made of titanium (Ti) or titanium nitride (TiN) may be formed so as to cover the interlayer insulating film 9. Next, the interlayer insulating film 9 and the gate insulating film 5 are patterned by photolithography to form a contact hole in which the n ⁺ type source region 8 and the p ⁺ type contact region 7 are exposed (step S2). After that, heat treatment (reflow) is performed to flatten the interlayer insulating film 9.

Next, protons are irradiated from the first main surface side (p ⁺ type base region 4 side) of the silicon carbide semiconductor substrate (step S3). The protons irradiate the vicinity of the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2 as shown by the arrow C in FIG. The state up to this point is shown in FIG.

Next, a conductive film such as nickel (Ni) to be the source electrode 10 is formed in the contact hole and on the interlayer insulating film 9 (step S4). This conductive film is patterned by photolithography, leaving the source electrode 10 only in the contact hole.

Next, a back electrode made of nickel or the like is provided on the second main surface of the n ⁺ type silicon carbide semiconductor substrate 1. After that, heat treatment (annealing) is performed at a temperature of 420 ° C. or lower (step S5). This is because at a temperature higher than 420 ° C., crystal defects due to the injected protons disappear and the lifetime killer does not function. After that, a source electrode 10 and a back surface electrode for ohmic contact with the n ⁺ type source region 8, the p ⁺ type contact region 7, and the n ⁺ type silicon carbide semiconductor substrate 1 are formed.

Next, an aluminum film having a thickness of about 5 μm is deposited on the first main surface of the n ⁺ silicon carbide semiconductor substrate 1 by a sputtering method, and aluminum is applied by photolithography so as to cover the source electrode 10 and the interlayer insulating film 9. Remove to form a source electrode pad.

Next, a drain electrode pad (not shown) is formed by laminating, for example, titanium (Ti), nickel, and gold (Au) in this order on the surface of the back surface electrode. As described above, the silicon carbide semiconductor device shown in FIG. 1 is completed.

As described above, according to the silicon carbide semiconductor device according to the first embodiment, protons are injected as a lifetime killer in the vicinity of the interface between the n ⁺ type silicon carbide semiconductor substrate and the n-type boundary layer. As a result, the hole density at the interface between the n ⁺ type silicon carbide semiconductor substrate and the n-type boundary layer can be reduced, and the growth of crystal defects can be suppressed. Therefore, the silicon carbide semiconductor device according to the first embodiment can be used for an inverter in which a current can flow through the built-in diode and a feedback current flows through the built-in diode.

Further, when forming a high-concentration n-type epitaxial layer by epitaxial growth, the accuracy of the lifetime varies greatly depending on the concentration and the film thickness. On the other hand, in the first embodiment, since the proton irradiation is performed by ion implantation, the lifetime killer has good controllability and can be stably formed. Moreover, since it is performed by ion implantation, it can be produced at a lower cost than epitaxial growth.

(Embodiment 2)
FIG. 9 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the second embodiment. The difference between the silicon carbide semiconductor device according to the second embodiment and the silicon carbide semiconductor device according to the first embodiment is that protons are also injected into the n ^- type drift layer 3.

As shown in FIG. 9, protons are injected into the region of the n ^- type drift layer 3 at a depth of h3 from the surface on the n-type boundary layer 2 side. The depth h3 is, for example, the film thickness of the n ⁻ type drift layer 3. FIG. 10 is a graph showing the proton concentration of the silicon carbide semiconductor device according to the second embodiment. FIG. 10 shows the proton concentration of the AA1 portion of FIG. 9, the vertical axis shows the depth from the surface of the p ⁺ type contact region 7, and the horizontal axis shows the proton concentration. The dotted line on the horizontal axis indicates the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2.

As shown in FIG. 10, the concentration of the protons in the n ^- type drift layer 3 is lower than that of the protons injected into the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2. By injecting a low-concentration proton into the n ^- type drift layer 3, the Qrr (reverse recovery charge amount) of the silicon carbide semiconductor device can be reduced, and the switching loss can be reduced when used in an inverter or the like. can.

Further, FIG. 11 is a graph showing the hole density of the silicon carbide semiconductor device according to the second embodiment. 11 shows the hole density of the AA1 portion of FIG. 1, the vertical axis shows the depth from the surface of the p ⁺ type contact region 7, and the horizontal axis shows the hole density. The dotted line on the horizontal axis indicates the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2. FIG. 12 is a graph showing the characteristics of the built-in diode of the silicon carbide semiconductor device according to the second embodiment. In FIG. 12, the vertical axis indicates the forward current, and the unit is A. Further, the horizontal axis indicates a forward voltage, and the unit is V.

As shown in FIG. 11, when protons are injected, the hole density of the n ^- type drift layer 3 is lower than that without proton injection. However, as shown in FIG. 12, the decrease in the forward current is small, and the built-in diode is within the usable range. Further, FIG. 13 is a graph showing the current characteristics of the silicon carbide semiconductor device according to the second embodiment at the time of reverse recovery. In FIG. 13, the vertical axis represents current and the horizontal axis represents time. As shown in FIG. 13, it can be seen that when the proton is injected, the decrease in the current at the time of reverse recovery is small and the Qrr is decreased.

(Manufacturing method of silicon carbide semiconductor device according to the second embodiment)
The silicon carbide semiconductor device according to the second embodiment is n ⁺ type from the first main surface side (p ⁺ type base region 4 side) of the silicon carbide semiconductor substrate in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. It is manufactured by irradiating the n ^- type drift layer 3 with protons before or after irradiating the vicinity of the interface between the silicon carbide semiconductor substrate 1 and the n-type boundary layer 2 with protons.

As described above, according to the silicon carbide semiconductor device according to the second embodiment, protons are injected as a lifetime killer in the vicinity of the interface between the n ⁺ type silicon carbide semiconductor substrate and the n-type boundary layer. This has the same effect as that of the first embodiment. Further, in the second embodiment, the proton is also injected into the n ^- type drift layer 3. As a result, the Qrr of the silicon carbide semiconductor device can be reduced, and the switching loss can be reduced when used in an inverter or the like.

(Embodiment 3)
Since the structure of the silicon carbide semiconductor device according to the third embodiment is the same as the structure of the silicon carbide semiconductor device according to the first embodiment, the description thereof will be omitted. The difference between the silicon carbide semiconductor device according to the third embodiment and the silicon carbide semiconductor device according to the first embodiment is that protons are injected from the back surface.

(Manufacturing method of silicon carbide semiconductor device according to the third embodiment)
FIG. 14 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the third embodiment. The silicon carbide semiconductor device according to the third embodiment irradiates protons in the vicinity of the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2 in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. At this time, it is manufactured by irradiating protons from the second main surface (the back surface, that is, the back surface of the silicon carbide semiconductor substrate) of the n ⁺ type silicon carbide semiconductor substrate 1 as shown by the arrow C in FIG.

When irradiating protons from the back surface, for example, when the substrate has a film thickness of 100 μm, the protons are irradiated with an acceleration voltage of 4 MeV. By irradiating the protons from the back surface, it is possible to prevent the protons from entering the gate insulating film 5, and the threshold value of the silicon carbide semiconductor device does not change.

Here, FIG. 15 is a graph showing the proton concentration of the silicon carbide semiconductor device according to the third embodiment. FIG. 16 is a graph showing the hole density of the silicon carbide semiconductor device according to the third embodiment. 15 and 16 show the proton concentration and hole density of the AA1 portion of FIG. 1, the vertical axis shows the depth from the surface of the p ⁺ type contact region 7, and the horizontal axis shows the proton concentration and hole density, respectively. Is shown. The dotted line on the horizontal axis indicates the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2. As shown in FIGS. 15 and 16, even when the protons are irradiated from the back surface, the proton concentration and the hole density are the same as when the protons are irradiated from the first main surface side.

As described above, according to the silicon carbide semiconductor device according to the third embodiment, protons are injected from the back surface as a lifetime killer near the interface between the n ⁺ type silicon carbide semiconductor substrate and the n-type boundary layer. There is. This has the same effect as that of the first embodiment. Further, in the third embodiment, since protons are prevented from entering the gate insulating film, the threshold value of the silicon carbide semiconductor device does not change.

(Embodiment 4)
FIG. 17 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the fourth embodiment. The difference between the silicon carbide semiconductor device according to the fourth embodiment and the silicon carbide semiconductor device according to the first embodiment is that helium (He) is injected instead of the proton.

As shown in FIG. 17, helium is, for example, a region of the n ⁺ type silicon carbide semiconductor substrate 1 having a depth of h1'or more from the surface on the n-type boundary layer 2 side, and n ⁺ of the n-type boundary layer 2. Protons are injected into a region having a depth of h2'or more from the surface of the type silicon carbide semiconductor substrate 1 side. Here, the values of h1'and h2' may be the same values as h1 (for example, 2 μm) and h2 (for example, 3 μm) in the case of protons.

Like protons, helium serves as a lifetime killer, and the hole density at the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2 can be reduced by two orders of magnitude or more. This can reduce the recombination of holes and electrons and suppress the growth of crystal defects.

Here, FIG. 18 is a graph showing the helium concentration of the silicon carbide semiconductor device according to the fourth embodiment. FIG. 19 is a graph showing the hole density of the silicon carbide semiconductor device according to the fourth embodiment. 18 and 19 show the helium concentration and the hole density of the AA1 portion of FIG. 17, the vertical axis shows the depth from the surface of the p ⁺ type contact region 7, and the horizontal axis shows the helium concentration and the hole density, respectively. Is shown. The dotted line on the horizontal axis indicates the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2. As shown in FIGS. 18 and 19, even when helium is injected, the hole density at the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2 can be reduced by two orders of magnitude or more.

(Manufacturing method of silicon carbide semiconductor device according to the fourth embodiment)
The silicon carbide semiconductor device according to the fourth embodiment is n ⁺ type from the first main surface side (p ⁺ type base region 4 side) of the silicon carbide semiconductor substrate in the method for manufacturing the silicon carbide semiconductor device according to the fourth embodiment. It is manufactured by irradiating helium instead of irradiating the vicinity of the interface between the silicon carbide semiconductor substrate 1 and the n-type boundary layer 2 with protons. Helium is irradiated with, for example, an acceleration voltage of 3.5 MeV.

As described above, according to the silicon carbide semiconductor device according to the fourth embodiment, helium is injected as a lifetime killer in the vicinity of the interface between the n ⁺ type silicon carbide semiconductor substrate and the n-type boundary layer. This has the same effect as that of the first embodiment.

(Embodiment 5)
FIG. 20 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the fifth embodiment. In the fifth embodiment, the case where the silicon carbide semiconductor device is an IGBT is shown. As shown in FIG. 20, a p-type silicon carbide semiconductor substrate 16 is provided, and an n ⁺ type emitter region 17 is selectively provided inside the p ⁺ type base region 4 on the first main surface side of the substrate. ..

Further, the emitter electrode 18 is in contact with the n ⁺ type emitter region 17 and the p ⁺ type contact region 7 through the contact hole opened in the interlayer insulating film 9. A back surface electrode (not shown) is provided on the second main surface (back surface, that is, the back surface of the silicon carbide semiconductor substrate) of the p-type silicon carbide semiconductor substrate 16. The back electrode constitutes a collector electrode. A collector electrode pad (not shown) is provided on the surface of the back surface electrode. The other structure of the silicon carbide semiconductor device according to the fifth embodiment is the same as that of the silicon carbide semiconductor device according to the first embodiment.

In the silicon carbide semiconductor device of the fifth embodiment, the lifetime killer is located near the interface between the p-type silicon carbide semiconductor substrate 16 and the n-type boundary layer 2 and near the interface between the n ^- type drift layer 3 and the p ⁺ type base region 4. As a proton is injected. Since the IGBT operates bipolarly, crystal defects grow from the interface between the n ^- type drift layer 3 and the p ⁺ type base region 4, so that the vicinity of the interface between the n ^- type drift layer 3 and the p ⁺ type base region 4 Is also injected with protons.

This proton serves as a lifetime killer and can reduce the hole density at the interface between the p-type silicon carbide semiconductor substrate 16 and the n-type boundary layer 2 and the interface between the n ^- type drift layer 3 and the p ⁺ type base region 4. .. This can reduce the recombination of holes and electrons and suppress the growth of crystal defects.

FIG. 21 is a graph showing the proton concentration of the silicon carbide semiconductor device according to the fifth embodiment. 21 shows the proton concentration of the AA1 portion of FIG. 20, the vertical axis shows the depth from the surface of the p ⁺ type contact region 7, and the horizontal axis shows the proton concentration. The dotted line L1 on the horizontal axis indicates the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2, and the dotted line L2 on the horizontal axis represents the n ^- type drift layer 3 and the p ⁺ type base region 4. Indicates the interface of.

As shown in FIGS. 20 and 21, the protons are present in, for example, a region of the n ⁺ type silicon carbide semiconductor substrate 1 having a depth of h1 ″ or more from the surface on the n-type boundary layer 2 side, and the n-type boundary layer 2. , N ⁺ type silicon carbide Protons are injected from the surface on the semiconductor substrate 1 side into a region having a depth of h2 ″ or more. Further, the protons are, for example, a region of the n ^- type drift layer 3 having a depth of h4 "or more from the surface on the p ⁺ type base region 4 side, and a region of the p ⁺ type base region 4 on the n ^- type drift layer 3 side. Protons are injected into the region at a depth of h3 "or more from the surface of the.

Further, FIG. 22 is a graph showing the hole density of the silicon carbide semiconductor device according to the fifth embodiment. 22 shows the hole density of the AA1 portion of FIG. 20, the vertical axis shows the depth from the surface of the p ⁺ type contact region 7, and the horizontal axis shows the hole density. The dotted line L1 on the horizontal axis indicates the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2, and the dotted line L2 on the horizontal axis represents the n ^- type drift layer 3 and the p ⁺ type base region 4. Indicates the interface of. As shown in FIG. 22, the hole density at the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2 and the interface between the n ^- type drift layer 3 and the p ⁺ type base region 4 decreases. There is.

FIG. 23 is a graph showing the IcVce characteristics of the silicon carbide semiconductor device according to the fifth embodiment. In FIG. 23, the vertical axis represents the collector current Ic, and the unit is A. The horizontal axis indicates the collector-emitter voltage, and the unit is V. As shown in FIG. 23, even when the hole density is reduced by injecting a proton, the characteristics of the IGBT are not significantly changed.

(Manufacturing method of silicon carbide semiconductor device according to the fifth embodiment)
The silicon carbide semiconductor device according to the fifth embodiment irradiates protons in the vicinity of the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2 in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. It is produced by irradiating the vicinity of the interface between the n ^- type drift layer 3 and the p ⁺ type base region 4 with protons before or after irradiation.

As described above, according to the silicon carbide semiconductor device according to the fifth embodiment, the vicinity of the interface between the n ⁺ type silicon carbide semiconductor substrate and the n-type boundary layer, and the n ^- type drift layer and the p ⁺ type base region. Protons are injected near the interface with and as a lifetime killer. As a result, the IGBT has the same effect as that of the first embodiment.

(Embodiment 6)
FIG. 24 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the sixth embodiment. The difference between the silicon carbide semiconductor device according to the sixth embodiment and the silicon carbide semiconductor device according to the first embodiment is that protons are also injected into the gate insulating film 5.

FIG. 25 is a graph showing the proton concentration of the silicon carbide semiconductor device according to the sixth embodiment. FIG. 25 shows the proton concentration of the AA1 portion of FIG. 24, the vertical axis shows the depth from the surface of the p ⁺ type contact region 7, and the horizontal axis shows the proton concentration. The dotted line on the horizontal axis indicates the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n-type boundary layer 2. As shown in FIGS. 24 and 25, protons are injected into the region at a depth of h3 from the surface of the p ⁺ type base region 4 on the source electrode 10 side. The depth h3 is the depth of the trench 15 in which the gate insulating film 5 is provided.

FIG. 26 is a graph showing the CV characteristics of the silicon carbide semiconductor device according to the sixth embodiment. In FIG. 26, the vertical axis represents the capacitance of the gate insulating film 5, and the unit is F. The horizontal axis represents the gate voltage, and the unit is V. As shown in FIG. 26, the CV characteristics are improved by reducing the hole density of the gate insulating film 5 by injecting protons. Therefore, a high-quality gate insulating film 5 can be manufactured by proton injection.

(Method for Manufacturing Silicon Carbide Semiconductor Device According to Embodiment 6)
The silicon carbide semiconductor device according to the sixth embodiment is n ⁺ type from the first main surface side (p ⁺ type base region 4 side) of the silicon carbide semiconductor substrate in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. It is manufactured by irradiating the gate insulating film 5 with protons before or after irradiating the vicinity of the interface between the silicon carbide semiconductor substrate 1 and the n-type boundary layer 2 with protons.

As described above, according to the silicon carbide semiconductor device according to the sixth embodiment, protons are injected as a lifetime killer in the vicinity of the interface between the n ⁺ type silicon carbide semiconductor substrate and the n-type boundary layer. This has the same effect as that of the first embodiment. Further, in the sixth embodiment, the proton is also injected into the gate insulating film 5. As a result, the gate insulating film 5 with good quality can be manufactured, and the CV characteristics can be improved.

(Example)
FIG. 27 is a graph showing the proton concentration of the silicon carbide semiconductor device of the example. Further, FIG. 28 is a graph showing the hole density of the silicon carbide semiconductor device of the embodiment. Further, FIG. 29 is a graph showing the hole density of the conventional silicon carbide semiconductor device. In FIG. 27, the vertical axis indicates the proton concentration, and the unit is / cm ³ . The horizontal axis indicates the depth of the n ^- type drift layer 3 from the surface, and the unit is μm. In FIGS. 28 and 29, the vertical axis indicates the hole density, and the unit is / cm ³ . The horizontal axis indicates the depth of the n ^- type drift layer 3 from the surface, and the unit is μm.

FIG. 27 shows the proton concentration when the silicon carbide semiconductor device of the first embodiment is simulated. FIG. 28 shows the hole densities when the silicon carbide semiconductor device of the first embodiment and the conventional silicon carbide semiconductor device are simulated. 27 and 28 are examples of the case where the n-type boundary layer 2 is not provided in the silicon carbide semiconductor device of the first embodiment. Further, FIG. 29 shows the hole density when simulating a conventional silicon carbide semiconductor device.

As shown in FIGS. 28 and 29, protons become a lifetime killer, and the hole density at the interface between the n ⁺ type silicon carbide semiconductor substrate 1 and the n ^- type drift layer 3 is lower than that without proton injection. You can see that.

In the above, the present invention can be variously modified without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, and the like are set variously according to the required specifications and the like. Further, in each embodiment, the first conductive type is n-type and the second conductive type is p-type, but in the present invention, the first conductive type is p-type and the second conductive type is n-type. It holds. Further, although the present invention has described a semiconductor device having a MOS structure, the present invention can also be applied to a bipolar semiconductor device.

As described above, the silicon carbide semiconductor device according to the present invention is useful for a power conversion device using an inverter circuit in which a diode is connected in antiparallel to a silicon carbide MOSFET, a power supply device for various industrial machines, and the like.

1, 101 n ⁺ type silicon carbide semiconductor substrate 2 n type boundary layer 3, 103 n ^- type drift layer 4, 104 p ⁺ type base region 5, 105 gate insulating film 6, 106 gate electrode 7, 107 p ⁺ type contact region 8, 108 n ⁺ type source region 9, 109 interlayer insulating film 10, 110 source electrode 15, 115 trench 16 p-type silicon carbide semiconductor substrate 17 n ⁺ type emitter region 18 emitter electrode 102 high concentration n-type epitaxial layer 111 basal plane rearrangement 112 Stacking defect 113 Triangular stacking defect 114 Band-shaped stacking defect

Claims (2)

The second conductive type semiconductor substrate and
A first conductive type first semiconductor layer provided on the semiconductor substrate,
A second conductive type second semiconductor layer provided on the opposite side of the first semiconductor layer with respect to the semiconductor substrate side,
A first conductive type first semiconductor region having a higher impurity concentration than the first semiconductor layer, which is selectively provided on the surface layer of the second semiconductor layer on the opposite side of the first semiconductor layer.
A gate electrode provided via a gate insulating film on at least a part of the surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer.
Equipped with
A first region of the semiconductor substrate having a predetermined depth from the surface of the first semiconductor layer side, a second region of the first semiconductor layer having a predetermined depth from the surface of the semiconductor substrate side, and the first semiconductor. Protons are generated in the third region of the layer at a predetermined depth from the surface on the second semiconductor layer side and in the fourth region of the second semiconductor layer from the surface on the first semiconductor layer side to a predetermined depth. A silicon carbide semiconductor device characterized by being injected. 1 × 10 in the first region of the semiconductor substrate, which is 2 μm or more from the surface of the first semiconductor layer side, and in the second region of the first semiconductor layer, which is 3 μm or more from the surface of the semiconductor substrate side. The silicon carbide semiconductor device according to claim 1, wherein a proton having a concentration of ¹³ / cm ³ or more and 1 × 10 ¹⁵ / cm ³ or less is injected.

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