JP2022000928A5 - Thin film transistor and its manufacturing method - Google Patents
Thin film transistor and its manufacturing method Download PDFInfo
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- JP2022000928A5 JP2022000928A5 JP2021164592A JP2021164592A JP2022000928A5 JP 2022000928 A5 JP2022000928 A5 JP 2022000928A5 JP 2021164592 A JP2021164592 A JP 2021164592A JP 2021164592 A JP2021164592 A JP 2021164592A JP 2022000928 A5 JP2022000928 A5 JP 2022000928A5
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- insulating layer
- gate insulating
- forming
- thin film
- film transistor
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- 239000010409 thin film Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 11
- 239000010408 film Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229920000089 Cyclic olefin copolymer Polymers 0.000 claims description 2
- 229920001665 Poly-4-vinylphenol Polymers 0.000 claims description 2
- 239000004642 Polyimide Substances 0.000 claims description 2
- 239000004372 Polyvinyl alcohol Substances 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 238000005452 bending Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 2
- 229920002451 polyvinyl alcohol Polymers 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 230000003068 static effect Effects 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 238000004528 spin coating Methods 0.000 claims 1
Description
上記課題を解決するための本発明の一局面は、絶縁性の基板と、絶縁性の基板上に形成されたゲート電極と、ゲート電極上に形成された１層以上の膜で形成されるゲート絶縁層と、ゲート絶縁層上に形成された無機半導体層と、無機半導体層上に形成されたソース・ドレイン電極とを含み、ゲート絶縁層は、有機物を用いて形成され、少なくとも一部が無機半導体層と非接触である第１領域と、無機物を用いて形成され、無機半導体層と接触し、パターン面積が第１領域のパターン面積の１０％以下である第２領域とを有し、直径１ｍｍの金属棒を用いた静的屈曲試験後に、第２領域の表面にクラックがないことを特徴とする、薄膜トランジスタである。 One aspect of the present invention for solving the above problems is a gate formed of an insulating substrate, a gate electrode formed on the insulating substrate, and one or more films formed on the gate electrode. The gate insulating layer includes an insulating layer, an inorganic semiconductor layer formed on the gate insulating layer, and a source / drain electrode formed on the inorganic semiconductor layer, and the gate insulating layer is formed by using an organic substance, and at least a part thereof is inorganic. It has a first region that is not in contact with the semiconductor layer and a second region that is formed by using an inorganic substance and is in contact with the inorganic semiconductor layer and has a pattern area of 10% or less of the pattern area of the first region . It is a thin film transistor characterized by having no crack on the surface of the second region after a static bending test using a metal rod having a diameter of 1 mm .
第１ゲート絶縁層がポリビニルフェノール、ポリメタクリル酸メチル、ポリイミド、ポリビニルアルコール、シクロオレフィンポリマーのいずれかを含んでいてもよい。
また、第２ゲート絶縁層が酸化シリコン、窒化シリコン、シリコンオキシナイトライドのいずれかを含んでもよい。
The first gate insulating layer may contain any one of polyvinylphenol, polymethylmethacrylate, polyimide, polyvinyl alcohol, and cycloolefin polymer.
Further, the second gate insulating layer may contain any one of silicon oxide, silicon nitride, and silicon oxynitride.
また、本発明の他の一局面は、絶縁性の基板上にゲート電極を形成する工程と、ゲート電極上に１層以上の膜で形成されるゲート絶縁層を形成する工程と、ゲート絶縁層上に無機半導体層を形成する工程と、無機半導体層上にソース・ドレイン電極を形成する工程とを備え、ゲート絶縁層を形成する工程は、有機物を用い、スピンコート法にて成膜後、フォトリソグラフィー法にてパターニングする工程と、無機物を用い、スパッタリング法にて成膜後、フォトリソグラフィー法にてパターニングする工程とを含み、無機半導体層を形成する工程は、スパッタリング法にて成膜後、フォトリソグラフィー法にてパターニングする工程を有する、薄膜トランジスタの製造方法である。 Further, another aspect of the present invention includes a step of forming a gate electrode on an insulating substrate, a step of forming a gate insulating layer formed of one or more films on the gate electrode, and a gate insulating layer. A step of forming an inorganic semiconductor layer on the top and a step of forming a source / drain electrode on the inorganic semiconductor layer are provided. The step of forming the inorganic semiconductor layer includes a step of patterning by a photolithography method, a step of forming a film by a sputtering method using an inorganic substance, and then a step of patterning by a photolithography method. , A method for manufacturing a thin film transistor, which comprises a step of patterning by a photolithography method.
Claims (6)
前記絶縁性の基板上に形成されたゲート電極と、
前記ゲート電極上に形成された１層以上の膜で形成されるゲート絶縁層と、
前記ゲート絶縁層上に形成された無機半導体層と、
前記無機半導体層上に形成されたソース・ドレイン電極とを含み、
前記ゲート絶縁層は、
有機物を用いて形成され、少なくとも一部が前記無機半導体層と非接触である第１領域と、
無機物を用いて形成され、前記無機半導体層と接触し、パターン面積が前記第１領域のパターン面積の１０％以下である第２領域とを有し、
直径１ｍｍの金属棒を用いた静的屈曲試験後に、前記第２領域の表面にクラックがないことを特徴とする、薄膜トランジスタ。 Insulating board and
The gate electrode formed on the insulating substrate and
A gate insulating layer formed of one or more films formed on the gate electrode and a gate insulating layer.
The inorganic semiconductor layer formed on the gate insulating layer and
The source / drain electrode formed on the inorganic semiconductor layer is included.
The gate insulating layer is
A first region formed using an organic substance, which is at least partially non-contact with the inorganic semiconductor layer,
It has a second region formed of an inorganic substance, in contact with the inorganic semiconductor layer, and having a pattern area of 10% or less of the pattern area of the first region.
A thin film transistor characterized by having no cracks on the surface of the second region after a static bending test using a metal rod having a diameter of 1 mm .
前記絶縁性の基板上にゲート電極を形成する工程と、The process of forming a gate electrode on the insulating substrate and
前記ゲート電極上に１層以上の膜で形成されるゲート絶縁層を形成する工程と、A step of forming a gate insulating layer formed of one or more films on the gate electrode, and a step of forming the gate insulating layer.
前記ゲート絶縁層上に無機半導体層を形成する工程と、The step of forming the inorganic semiconductor layer on the gate insulating layer and
前記無機半導体層上にソース・ドレイン電極を形成する工程とを備え、A step of forming a source / drain electrode on the inorganic semiconductor layer is provided.
前記ゲート絶縁層を形成する工程は、The step of forming the gate insulating layer is
有機物を用い、スピンコート法にて成膜後、フォトリソグラフィー法にてパターニングする工程と、A process of forming a film by a spin coating method using an organic substance and then patterning by a photolithography method.
無機物を用い、スパッタリング法にて成膜後、フォトリソグラフィー法にてパターニングする工程とを含み、It includes a step of forming a film by a sputtering method using an inorganic substance and then patterning it by a photolithography method.
前記無機半導体層を形成する工程は、スパッタリング法にて成膜後、フォトリソグラフィー法にてパターニングする工程を有する、薄膜トランジスタの製造方法。The step of forming the inorganic semiconductor layer is a method for manufacturing a thin film transistor, which comprises a step of forming a film by a sputtering method and then patterning by a photolithography method.
Priority Applications (1)
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| JP2021164592A JP7392701B2 (en) | 2019-11-07 | 2021-10-06 | thin film transistor |
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| JP2019202467A JP6958603B2 (en) | 2019-11-07 | 2019-11-07 | Thin film transistor |
| JP2021164592A JP7392701B2 (en) | 2019-11-07 | 2021-10-06 | thin film transistor |
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| JP2019202467A Division JP6958603B2 (en) | 2019-11-07 | 2019-11-07 | Thin film transistor |
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| Publication Number | Publication Date |
|---|---|
| JP2022000928A JP2022000928A (en) | 2022-01-04 |
| JP2022000928A5 true JP2022000928A5 (en) | 2022-06-02 |
| JP7392701B2 JP7392701B2 (en) | 2023-12-06 |
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| CN1148600C (en) * | 1996-11-26 | 2004-05-05 | 三星电子株式会社 | Liquid crystal display using organic insulating material and manufacturing methods thereof |
| JP5621273B2 (en) * | 2010-02-23 | 2014-11-12 | ソニー株式会社 | THIN FILM TRANSISTOR STRUCTURE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE |
| JP2014032983A (en) * | 2012-08-01 | 2014-02-20 | Sony Corp | Semiconductor device, display device, and electronic equipment |
| KR102132412B1 (en) * | 2013-10-17 | 2020-07-09 | 엘지디스플레이 주식회사 | Thin fim transistor array substrate for display device and method fabricating the same |
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