JP2021077751A5

JP2021077751A5 -

Info

Publication number: JP2021077751A5
Application number: JP2019202467A
Authority: JP
Filing date: 2019-11-07
Publication date: 2021-08-05
Anticipated expiration: 2039-11-07

Description

上記課題を解決するための本発明の一局面は、絶縁性の基板と、絶縁性の基板上に形成されたゲート電極と、ゲート電極上に形成された１層以上の膜で形成されるゲート絶縁層と、ゲート絶縁層上に形成された無機半導体層と、無機半導体層上に形成されたソース・ドレイン電極とを含み、ゲート絶縁層は、有機物を用いて形成され、少なくとも一部が無機半導体層と非接触である第１領域と、無機物を用いて形成され、無機半導体層と接触し、膜厚が２ｎｍ以上５０ｎｍ以下であり、パターン面積が第１領域のパターン面積の１０％以下である第２領域とを有することを特徴とする、薄膜トランジスタである。 One aspect of the present invention for solving the above problems is a gate formed of an insulating substrate, a gate electrode formed on the insulating substrate, and one or more films formed on the gate electrode. The gate insulating layer includes an insulating layer, an inorganic semiconductor layer formed on the gate insulating layer, and a source / drain electrode formed on the inorganic semiconductor layer, and the gate insulating layer is formed by using an organic substance, and at least a part thereof is inorganic. a first region which is a semiconductor layer and a non-contact, is formed using an inorganic material in contact with the non-machine semiconductor layer, the thickness is at 2nm or 50nm or less, the pattern area 10% or less of the pattern area of the first region It is a thin film transistor characterized by having a second region.

また、ゲート絶縁層は、第１領域である第１ゲート絶縁層と、第２領域である第２ゲート絶縁層の積層構造であってもよい。 Further, the gate insulating layer may have a laminated structure of a first gate insulating layer which is a first region and a second gate insulating layer which is a second region.

また、第１ゲート絶縁層が感光性樹脂を含んでもよい。
また、第１ゲート絶縁層がポリビニルフェノール、ポリメタクリル酸メチル、ポリイミド、ポリビニルアルコール、シクロオレフィンポリマーのいずれかを含んでもよい。 Further, the first gate insulating layer may contain a photosensitive resin.
Further, the first gate insulating layer may contain any one of polyvinylphenol, polymethylmethacrylate, polyimide, polyvinyl alcohol, and cycloolefin polymer.

また、第２ゲート絶縁層が酸化シリコン、窒化シリコン、シリコンオキシナイトライドのいずれかを含んでもよい。 Further, the second gate insulating layer may contain any one of silicon oxide, silicon nitride, and silicon oxynitride.

また、無機半導体層がインジウム、ガリウム、および亜鉛の少なくとも一種を含む酸化物であってもよい。 Further, the inorganic semiconductor layer may be an oxide containing at least one of indium, gallium, and zinc.

Claims

An insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed of one or more films formed on the gate electrode, and a gate insulating layer formed on the gate insulating layer. The inorganic semiconductor layer and the source / drain electrode formed on the inorganic semiconductor layer are included.
The gate insulating layer is
It is formed using an organic material, a first region that is at least partially the inorganic semiconductor layer and the non-contact,
Is formed using an inorganic material, in contact with the pre-inorganic semiconductor layer, the thickness is at 2nm or 50nm or less, that a second region is a pattern area is 10% or less of the pattern area of the first region Characteristic ,
Thin film transistor.

The thin film transistor according to claim 1, wherein the gate insulating layer has a laminated structure of the first gate insulating layer which is the first region and the second gate insulating layer which is the second region.

The thin film transistor according to claim 2, wherein the first gate insulating layer contains a photosensitive resin.

The thin film transistor according to claim 2 or 3, wherein the first gate insulating layer contains any one of polyvinylphenol, polymethylmethacrylate, polyimide, polyvinyl alcohol, and a cycloolefin polymer.

The thin film transistor according to any one of claims 2 to 4, wherein the second gate insulating layer contains any one of silicon oxide, silicon nitride, and silicon oxynitride.

The thin film transistor according to any one of claims 1 to 5 , wherein the inorganic semiconductor layer is an oxide containing at least one of indium, gallium, and zinc.