JP2021502743A5 - - Google Patents

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JP2021502743A5
JP2021502743A5 JP2020524443A JP2020524443A JP2021502743A5 JP 2021502743 A5 JP2021502743 A5 JP 2021502743A5 JP 2020524443 A JP2020524443 A JP 2020524443A JP 2020524443 A JP2020524443 A JP 2020524443A JP 2021502743 A5 JP2021502743 A5 JP 2021502743A5
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JP
Japan
Prior art keywords
multiplication
share
variable
storage
shares
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JP2020524443A
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English (en)
Japanese (ja)
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JP2021502743A (ja
JP7191097B2 (ja
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Priority claimed from EP17201106.6A external-priority patent/EP3484093A1/en
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JP2020524443A 2017-11-10 2018-10-29 計算デバイス及び方法 Active JP7191097B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP17201106.6A EP3484093A1 (en) 2017-11-10 2017-11-10 A computation device and method
EP17201106.6 2017-11-10
PCT/EP2018/079537 WO2019091809A1 (en) 2017-11-10 2018-10-29 A computation device and method

Publications (3)

Publication Number Publication Date
JP2021502743A JP2021502743A (ja) 2021-01-28
JP2021502743A5 true JP2021502743A5 (enExample) 2021-12-09
JP7191097B2 JP7191097B2 (ja) 2022-12-16

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JP2020524443A Active JP7191097B2 (ja) 2017-11-10 2018-10-29 計算デバイス及び方法

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US (1) US11381379B2 (enExample)
EP (2) EP3484093A1 (enExample)
JP (1) JP7191097B2 (enExample)
CN (1) CN111480140B (enExample)
WO (1) WO2019091809A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3095709B1 (fr) * 2019-05-03 2021-09-17 Commissariat Energie Atomique Procédé et système de masquage pour la cryptographie
US11456855B2 (en) * 2019-10-17 2022-09-27 Arm Limited Obfuscating data at-transit
FR3112643B1 (fr) * 2020-07-15 2024-05-03 Banks And Acquirers Int Holding Dispositif, méthode et programme pour une communication sécurisée entre boîtes blanches
WO2025122159A1 (en) * 2023-12-08 2025-06-12 Pqsecure Technologies, Llc Computer processing system and method configured to effectuate lower-order masking in a higher-order masked design

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070150530A1 (en) 2005-12-13 2007-06-28 Intel Corporation Resisting cache timing based attacks
FR2917197B1 (fr) 2007-06-07 2009-11-06 Thales Sa Procede de masquage du resultat d'une operation de multiplication modulaire et dispositif associe.
JP2014145958A (ja) 2013-01-30 2014-08-14 Renesas Electronics Corp 半導体装置
US9959429B2 (en) * 2013-03-15 2018-05-01 Cryptography Research, Inc. Asymmetrically masked multiplication
MX2016000048A (es) * 2013-07-12 2016-08-18 Koninklijke Philips Nv Dispositivo y metodo para acuerdo de clave.
US10372886B2 (en) * 2015-05-05 2019-08-06 Nxp B.V. Protecting the input/output of modular encoded white-box RSA/ECC
US10235506B2 (en) * 2015-05-05 2019-03-19 Nxp B.V. White-box modular exponentiation
JP6006842B1 (ja) 2015-07-22 2016-10-12 日本電信電話株式会社 秘密計算装置、その方法、およびプログラム
NL2015599B1 (en) * 2015-10-12 2017-05-02 Koninklijke Philips Nv A cryptographic device and an encoding device.
CN108370311A (zh) * 2015-12-15 2018-08-03 皇家飞利浦有限公司 计算设备和方法

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