JP2021180355A - Logical state determination method and logical state determination circuit - Google Patents

Abstract

To provide a logical state determination method and a logical state determination circuit, capable of determining a logical state without increasing a measurement current limit circuit.SOLUTION: A logical state determination method includes steps for applying a signal to a bus line (6), releasing the signal application to the bus line (6), and determining a logical state for a signal level of the bus line (6) held by a bus hold part (5).SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a logic state determination method and a logic state determination circuit.

As a conventional technique for discriminating a high state, a low state, and a HiZ state in a logic input / output circuit, for example, there is a logic state determination circuit described in Patent Document 1. This circuit utilizes a measured current limiting circuit configured by an RC circuit that determines the logical state of the logical input / output circuit. The Hi-Z state is an electrically isolated state, and is treated as an open state that is neither a high state nor a low state.

Japanese Unexamined Patent Publication No. 63-316516

A logic input / output circuit such as a microcomputer, a complex programmable logic device (CPLD) or a field programmable gate array (FPGA) cannot configure a measurement current limiting circuit. Therefore, the logic state determination circuit described in Patent Document 1 needs to newly add a measurement current limiting circuit for determining the logic state, and has a problem of increasing the number of parts.

The present disclosure has been made to solve the above problems, and an object of the present invention is to obtain a logic state determination method and a logic state determination circuit capable of determining a logic state without increasing the number of measurement current limiting circuits.

The logic state determination method according to the present disclosure determines the logic state of the signal level of the bus line held in the bus hold unit, the step of applying the signal to the bus line, the step of releasing the application of the signal to the bus line. Have steps to do.

According to the present disclosure, a signal is applied to a bus line, the application of the signal to the bus line is released, and the logical state of the signal level of the bus line held in the bus hold unit is determined. Thereby, the logic state determination method according to the present disclosure can determine the logic state without increasing the measurement current limiting circuit.

It is a block diagram which shows the structure of the logic state determination circuit which concerns on Embodiment 1. FIG. It is a circuit diagram which shows the circuit (example 1) of the logic state determination target by the logic state determination circuit which concerns on Embodiment 1. FIG. It is a circuit diagram which shows the circuit (example 2) of the logic state determination target by the logic state determination circuit which concerns on Embodiment 1. FIG. It is a circuit diagram which shows the circuit (example 3) of the logic state determination target by the logic state determination circuit which concerns on Embodiment 1. FIG. It is a flowchart which shows the logical state determination method which concerns on Embodiment 1. It is a timing diagram which shows the logical state determination (example 1) which concerns on Embodiment 1. FIG. It is a timing diagram which shows the logical state determination (example 2) which concerns on Embodiment 1. FIG. It is a timing diagram which shows the logical state determination (example 3) which concerns on Embodiment 1. FIG. It is a circuit diagram which shows the circuit (example 4) of the logic state determination target by the logic state determination circuit which concerns on Embodiment 1. FIG. It is a circuit diagram which shows the circuit (example 5) of the logic state determination target by the logic state determination circuit which concerns on Embodiment 1. FIG.

Embodiment 1.
FIG. 1 is a block diagram showing a configuration of the logic state determination circuit 1 according to the first embodiment. The logic state determination circuit 1 is a circuit for determining the logic state of the signal at the measurement point M, and is a timing control unit 2, a determination level supply unit 3, a three-state buffer 4, a bus hold unit 5, a bus line 6, and a comparison unit 7. And a determination unit 8 is provided.

The timing control unit 2 controls the supply of the determination level to the three-state buffer 4 by the determination level supply unit 3 and the timing at which the determination unit 8 makes a determination. The determination level supply unit 3 outputs an output signal (OUT) to the three-state buffer 4 and sets an output enable signal (OE). The output signal is a high level (hereinafter referred to as H level) or low level (hereinafter referred to as L level) first signal. Similarly, the output enable signal is an H-level or L-level second signal.

The three-state buffer 4 inputs the output signal output from the determination level supply unit 3, and the output enable signal is set by the determination level supply unit 3, so that the signal of the level corresponding to the level of both signals is bus-lined. Apply to 6. The bus hold unit 5 holds the signal level applied to the bus line 6. The bus line 6 is connected to the measurement point M and has the same signal level state as the measurement point M.

The comparison unit 7 determines whether the signal level of the bus line 6 is the H level or the L level.

The determination unit 8 determines whether the state of the bus line 6 is a pull-down state, a pull-up state, or an open state based on the determination result by the comparison unit 7. Further, the determination unit 8 outputs a signal indicating the determination result of the logical state of the bus line 6.

The measurement point M whose logical state is determined by the logical state determination circuit 1 has the following circuit.
FIG. 2 is a circuit diagram showing a circuit (example 1) for which a logical state is determined by the logical state determination circuit 1. In FIG. 2, the measurement point M in FIG. 1 is _{a circuit that pulls} down the bus line 6 to the ground 10 via the pull-down resistor R pd. The buffer 9 holds an input signal (IN) used for confirming the state of the bus line 6. The input signal (IN) is a signal indicating the signal level of the bus line 6.

FIG. 3 is a circuit diagram showing a circuit (example 2) to be determined by the logic state determination circuit 1. In FIG. 3, the measurement point M in FIG. 1 is a circuit that pulls up the bus line 6 to the potential of the power supply 11 via _{the pull-up resistor Rpa.}

FIG. 4 is a circuit diagram showing a circuit (example 3) to be determined by the logic state determination circuit 1. In FIG. 4, the measurement point M in FIG. 1 is an open end 12 that opens the bus line 6.

In FIGS. 2, 3 and 4, the three-state buffer 4 has a resistor R _b connected to the output and can bring the bus line 6 into three states: L level, H level or open state. For example, the three-state buffer 4 enables output when an H-level output enable signal (OE) is set. That is, when the H-level output signal (OUT) is input, the three-state buffer 4 applies the H-level signal to the bus line 6, and when the L-level output signal (OUT) is input, the three-state buffer 4 is an L-level signal. Is applied to the bus line 6. Further, the three-state buffer 4 sets the output to the open state when the L level output enable signal is set. When the output is valid, the current I _b flowing through the three-state buffer 4 is the drive current.

The bus hold unit 5 operates to output an H level signal when the state of the bus line 6 is H level, and to output an L level signal when the state of the bus line 6 is L level. .. The bus hold unit 5 is composed of two inverters to which an input terminal and an output terminal are connected to each other, and a resistor _Rh is connected to one of the connection portions.

The influence of the bus hold unit 5 on the state of the bus line 6 is reduced by making the _{current I h (holding current) flowing with the resistor R h} a high resistance small. As a result, even if the element (measurement point M) that drives the bus line 6 is opened (opened), the level of the bus line 6 immediately before the opening is held by the bus hold unit 5.

The current I _pd is a current flowing through the pull-down resistor R _pd , and is an upper limit current value for keeping the signal level of the bus line 6 at the L level. The pull-down resistor R _pd shown in FIG. 2 is a value in which R _h >> R _pd >> R _b and the relationship of _{I b} >> I _pd >> I _{h holds.} That is, a value is selected for the pull-down resistor R _{pd so that a current that cancels the holding current I h} of the bus hold unit 5 _{can flow and is not affected by the drive current I b} of the three-state buffer 4.

The current I _pa is a current flowing through the pull-up resistor R _pa , and is a lower limit current value for keeping the signal level of the bus line 6 at the H level. The pull-up resistor R _pa shown in FIG. 3 is R _h >> R _pa >> R _b , and is a value that holds the relationship of _{I b} >> I _pa >> I _h. That is, a value is selected for the pull-up resistor R _{pa so that a current that cancels the holding current I h} of the bus hold unit 5 _{can flow and is not affected by the drive current I b} of the three-state buffer 4. Further, at the open end 12 shown in FIG. 4, the relationship of _{R h} >> R _{b is established.}

The logic state determination method according to the first embodiment is as follows.
FIG. 5 is a flowchart showing a logic state determination method according to the first embodiment. FIG. 6 is a timing diagram showing a logical state determination (Example 1) according to the first embodiment. The determination level supply unit 3 sends the H level output signal (OUT) and the H level output enable signal (OE) to the three-state buffer 4 during the period (1) of FIG. 6 according to the control of the timing control unit 2. Output (step ST1).

Next, the determination level supply unit 3 sets the L level output enable signal (OE) in the three-state buffer 4 during the period (2) of FIG. 6 under the control of the timing control unit 2 (step ST2). .. The output signal (OUT) is not specified as H level or L level. As a result, the output of the three-state buffer 4 becomes invalid and the three-state buffer 4 becomes an open state (I _b ≈ 0). Subsequently, the comparison unit 7 determines whether the input signal (IN) is at the H level or the L level according to the control of the timing control unit 2 (step ST3).

At the timing A when the state of the bus line 6 is confirmed, the determination unit 8 determines that the measurement point M is a pull-down connection when the result that the input signal (IN) is L level is obtained (step ST3; Low). (Step ST4). When the measurement point M is the L level, the current I _pd or more cannot be passed through the bus hold unit 5, and the H level of the bus line 6 cannot be maintained. Therefore, the state of the bus line 6 is the L level. It is judged that it became. Since the current I _{b flowing through the resistor R b} of the three-state buffer 4 is almost 0 (I _b ≈ 0), the current at the L level of the bus line 6 is a current having a value equal to or less than _{I pd.}

FIG. 7 is a timing diagram showing a logical state determination (Example 2) according to the first embodiment. When the signal (IN) is at the H level during the period (2) of FIG. 7 (step ST3; High), the bus hold unit 5 can maintain the H level state of the bus line 6 (timing B). That is, the bus line 6 is not pulled down. If the bus line 6 is not pulled down, it is in the open state (Hi-Z) or in the pull-up state.

The determination level supply unit 3 outputs an L level output signal (OUT) to the three-state buffer 4 during the period (3) of FIG. 7 according to the control of the timing control unit 2, and outputs an H level output enable signal (H level output enable signal). OE) is set in the three-state buffer 4 (step ST5). The output of the three-state buffer 4 becomes valid when the H level output enable signal (OE) is set, but since the output signal (OUT) is the L level, the bus line 6 has an L opposite to that immediately before. The state of the level is applied.

Next, the determination level supply unit 3 sets the L level output enable signal (OE) in the three-state buffer 4 during the period (4) of FIG. 7 under the control of the timing control unit 2 (step ST6). .. For the output signal (OUT), H level or L level is not specified. As a result, the output of the three-state buffer 4 becomes invalid and the three-state buffer 4 becomes an open state (I _b ≈ 0). Subsequently, the comparison unit 7 determines whether the input signal (IN) is at the H level or the L level according to the control of the timing control unit 2 (step ST7).

At the timing C when the state of the bus line 6 is confirmed, the determination unit 8 determines that the measurement point M is a pull-up connection when the result that the input signal (IN) is H level is obtained (step ST7; High). (Step ST8). When the measurement point M is the H level, the L level of the bus line 6 cannot be maintained in the bus hold unit 5, so that the state of the bus line 6 is changed to the H level by the current of _{the current I h} or more and the current I _{pa or less.} It is judged that it was done. The current I _{b flowing through the resistor R b} of the three-state buffer 4 is almost 0 (I _b ≈ 0), and the current at the H level of the bus line 6 is a current having a value of _{I h} or more and I _{pa or less.}

FIG. 8 is a timing diagram showing a logical state determination (Example 3) according to the first embodiment. When the input signal (IN) is at the L level during the period (4) of FIG. 8, the L level of the bus line 6 can be maintained in the bus hold unit 5. That is, since the bus line 6 is not at the H level due to _{the pull-up current I pa, it can be determined that the bus line 6 is not pulled up.} In step ST3, it is determined that the bus line 6 is in the open state (Hi-Z) or the pull-up state. Therefore, if the bus line 6 is not in the pull-up state, it is determined to be in the open state (Hi-Z). can.

At the timing D, the determination unit 8 determines that the measurement point M is in the open state (Hi-Z) when the result that the input signal (IN) is L level is obtained (step ST7; Low) (step ST9). ).

During the period (1) of FIG. 6, the period (1) of FIG. 7, and the period (1) of FIG. 8, the determination level supply unit 3 sets the H level output enable signal (OE) for the three-state buffer 4. , The L-level output signal (OUT) may be input by the three-state buffer 4, or the H-level output to the three-state buffer 4 during the period (3) of FIG. 7 and the period (3) of FIG. An enable signal (OE) may be set and an H-level output signal (OUT) may be input by the three-state buffer 4. In this case, the determination unit 8 determines the logical state of the measurement point M in the period (2) of FIG. 6, the period (4) of FIG. 7, or the period (4) of FIG.

FIG. 9 is a circuit diagram showing a circuit (example 4) for which the logical state is determined by the logical state determination circuit 1. In FIG. 9, the switch 13 is a measurement point M, and is a circuit that pulls down the bus line 6 to the ground 10, a circuit that pulls up the bus line 6 to the potential of the power supply 11, or an open end that opens the bus line 6. Switch to any of 12. The logical state of the circuit switched by the switch 13 is determined by a series of processes shown in FIG.

FIG. 10 is a circuit diagram showing a circuit (example 5) for which a logical state is determined by the logical state determination circuit 1. In FIG. 10, the jumper switch 14a is turned on to connect a circuit that pulls up the bus line 6 to the potential of the power supply 11 to the bus line 6, and is turned off from the bus line 6. Disconnect the pull-up connection. When the jumper switch 14b is turned on, a circuit for pulling down the bus line 6 to the ground 10 is connected to the bus line 6, and when the jumper switch 14b is turned off, the pull-down connection is disconnected from the bus line 6.

When both the jumper switches 14a and 14b are off, the end of the bus line 6 is the open end 12. The logical state of the circuit switched by the jumper switches 14a and 14b is determined by a series of processes shown in FIG.

As described above, in the logic state determination method according to the first embodiment, the signal is applied to the bus line 6, the application of the signal to the bus line 6 is released, and the bus line 6 held in the bus hold unit 5 is held. By determining the signal level, it is determined whether the state of the measurement point M is a pull-up state, a pull-down state, or an open state (Hi-Z). Thereby, the logic state determination method according to the first embodiment can determine the logic state without increasing the measurement current limiting circuit.

It is possible to modify any component of the embodiment or omit any component of the embodiment.

1 Logic state judgment circuit, 2 Timing control unit, 3 Judgment level supply unit, 4 Three-state buffer, 5 Bus hold unit, 6 Bus line, 7 Comparison unit, 8 Judgment unit, 9 Buffer, 10 Ground, 11 Power supply, 12 Open End, 13 switch, 14a, 14b jumper switch.

Claims (5)

The step of applying a signal to the bus line and
The step of releasing the application of the signal to the bus line and
A step of determining the logical state of the signal level of the bus line held in the bus hold unit, and
A logical state determination method characterized by being provided with. When the signal level of the bus line held in the bus hold unit is the same as the signal level applied to the bus line, a step of applying a signal of the opposite level to the immediately preceding bus line to the bus line.
The step of releasing the application of the signal to the bus line and
When the signal level of the bus line held in the bus hold unit is different from the signal level applied to the bus line, the state of the bus line changes according to the signal level applied to the bus line. The step to determine that it is in the pull-down state or pull-up state,
When the signal level of the bus line held in the bus hold unit is the same as the signal level applied to the bus line, the step of determining that the bus line is in the open state and
The logical state determination method according to claim 1, wherein the method is provided with. A bus hold unit that holds the signal level applied to the bus line,
By inputting the first signal and setting the second signal, a three-state buffer that applies a signal at a level corresponding to the values of the first signal and the second signal to the bus line. ,
A determination level supply unit that outputs the first signal to the three-state buffer and sets the second signal.
A comparison unit for determining whether the signal level state of the bus line held in the bus hold unit is high level or low level, and a comparison unit.
A determination unit that determines whether the logical state of the signal level of the bus line is a pull-down state, a pull-up state, or an open state based on the determination result by the comparison unit.
A logic state determination circuit characterized by being equipped with. The logic state determination circuit according to claim 3, further comprising a switch for switching the presence or absence of a pull-up resistor or a pull-down resistor connected to the bus line. The logic state determination circuit according to claim 3, further comprising a jumper switch for switching the presence or absence of a pull-up resistor or a pull-down resistor connected to the bus line.

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