JP2021174263A - Information processing apparatus and program - Google Patents

Abstract

To provide a highly safe information processing system configured to prevent a platform from being started when the platform other than a legitimate platform is connected to a slot of a relay device.SOLUTION: An information processing apparatus according to a first aspect of the invention includes: a connection unit capable of connecting an external information processing apparatus; and a control unit which transmits, before starting an external control unit of the external information processing apparatus, a control signal to an extension device of the external information processing apparatus via an extension pin other than pins to be used for communication based on a communication standard, out of pins of the connection unit, receives an output signal indicating a control result of the extension device from the extension device via the extension pin, determines whether the extension device is a predetermined device or not on the basis of the output signal and the control signal, and executes processing to stop the start of the external control unit when it is determined that the extension device is not the predetermined device.SELECTED DRAWING: Figure 3

Description

The present invention relates to an information processing device and a program.

Communicates with a platform (an example of an external information processing device) and a platform that has a slot (an example of a connection unit) to which the platform can be connected and is connected to the slot according to communication standards such as PCIe (Peripheral Component Interconnect Express). An information processing system equipped with a relay device (an example of an information processing device) is being developed.

Japanese Unexamined Patent Publication No. 2008-41027 Special Table 2012-504835

However, in the above information processing system, when a legitimate platform is connected to the slot of the relay device, the information processing system operates normally, but the slot of the relay device is legitimate. If a platform other than the platform is connected, the operation of the information processing system may malfunction.

On one side, the present invention provides a highly secure information processing system that can prevent the platform from starting when a platform other than the legitimate platform is connected to the slot of the relay device. It is an object of the present invention to provide an information processing device and a program capable of performing the information processing.

The information processing device according to the first aspect of the present invention has a connection unit to which an external information processing device can be connected and a pin of the connection unit prior to activation of the external control unit of the external information processing device. A control signal is transmitted to an expansion device of the external information processing device via an expansion pin other than the pin used for communication in accordance with our communication standard, and the expansion device transmits a control signal via the expansion pin. It receives an output signal indicating the control result of the expansion device, determines whether or not the expansion device is a predetermined device based on the output signal and the control signal, and determines that the expansion device is not the predetermined device. If so, the control unit is provided with a control unit that executes a process of stopping the activation of the external control unit.

The program according to the second aspect of the present invention sets the computer as a communication standard among the pins of the connection unit to which the external information processing device can be connected prior to the activation of the external control unit of the external information processing device. A control signal is output to the expansion device of the external information processing device via an expansion pin other than the pin used for the corresponding communication, and the expansion device controls the expansion device via the expansion pin. When an output signal indicating the result is received, it is determined whether or not the expansion device is a predetermined device based on the output signal and the control signal, and it is determined that the expansion device is not the predetermined device, the external device is used. It functions as a control unit that executes stop processing for starting the control unit.

According to the above aspect of the present invention, when a platform other than the legitimate platform is connected to the slot of the relay device, it is possible to prevent the platform from starting and provide a highly secure information processing system. It is possible to do.

FIG. 1 is a diagram showing an example of the overall configuration of the information processing system according to the present embodiment. FIG. 2 is a diagram showing an example of the hardware configuration of each device of the information processing system according to the present embodiment. FIG. 3 is a diagram showing an example of the hardware configuration of the platform and the power supply control board included in the information processing system according to the present embodiment. FIG. 4 is a sequence diagram showing an example of the flow of activation processing of the external microcomputer of the platform in the information processing system according to the present embodiment.

Hereinafter, an example of the information processing apparatus according to the present embodiment and the information processing system to which the program is applied will be described with reference to the attached drawings.

FIG. 1 is a diagram showing an example of the overall configuration of the information processing system according to the present embodiment. The information processing system 1 connects a platform 10-1 having an interface corresponding to active insertion / removal, which is an insertion / removal at the time of power-on, and a plurality of platforms 10-2 to 10-8 so as to be able to communicate with each other via a relay device 30. It is an information processing system. As shown in FIG. 1, the information processing system 1 according to the present embodiment includes platforms 10-1 to 10-8 and a relay device 30.

Platforms 10-1 to 10-8 are communicably connected to each other via a relay device 30. Platforms 10-1 to 10-8 are inserted (connected) into, for example, a slot (an example of a connection portion) on a board provided with a relay device 30. Further, any of the plurality of slots may be in an empty state in which platforms 10-1 to 10-8 are not inserted. In the following description, it is not necessary to distinguish each platform 10-1 to 10-8, and when any platform 10-1 to 10-8 is indicated, it is described as platform 10.

Platform 10-1 is a main information processing device that manages platforms 10-2 to 10-8 and causes platforms 10-2 to 10-8 to execute various processes.

A monitor 21 and an input device 22 are connected to the platform 10-1. The monitor 21 displays various screens such as a liquid crystal display device. The input device 22 accepts various operations such as a keyboard and a mouse.

Platforms 10-2 to 10-8 are sub-information processing devices that execute, for example, AI (Artificial Intelligence) inference processing, image processing, and the like based on the requirements of platform 10-1. Further, the platforms 10-2 to 10-8 may each have a different function, or may have a function for each of a plurality of platforms 10.

Platforms 10-1 to 10-8 have a root complex (RC: Root Complex) 11-1 to 11-8 that can operate as a host side. In the following description, it is not necessary to distinguish each route complex 11-1 to 11-8, and when an arbitrary route complex 11-1 to 11-8 is indicated, it is described as the root complex 11.

The route complex 11 executes communication with each endpoint 31-1 to 1-31-8 of the relay device 30. That is, the platform 10 and the relay device 30 are communicably connected to each other via a slot according to a communication standard such as PCIe (Peripheral Component Interconnect Express). The platform 10 and the relay device 30 may be connected by other communication standards, not limited to PCIe.

The relay device 30 has a plurality of endpoints (EPs: End Points) 31-1 to 1-31-8. In addition, the relay device 30 relays communication between a plurality of platforms 10 having a route complex 11 connected to endpoints 31-1 to 1-31-8.

Endpoints 31-1 to 1-31-8 perform communication with the root complex 11 of platform 10. In the following description, it is not necessary to distinguish each endpoint 31-1 to 1-31-8, and when an arbitrary endpoint 31-1 to 1-31-8 is indicated, it is described as endpoint 31.

FIG. 2 is a diagram showing an example of the hardware configuration of each device of the information processing system according to the present embodiment. Next, an example of the hardware configuration of each device of the information processing system 1 will be described with reference to FIG. Here, the hardware configuration of platform 10-1 (an example of an external information processing device) will be described as an example. However, platforms 10-2 to 10-8 have a similar configuration.

Platform 10-1 is a computer that performs arithmetic processing such as AI processing and image processing. The platform 10 includes a root complex 11-1 and a microcomputer (hereinafter referred to as an external microcomputer; an example of an external control unit) 16-1. The external microcomputer 16-1 includes a processor 12-1, a memory 13-1, a storage unit 14-1, and a communication unit 15-1. Further, the route complex 11-1, the processor 12-1, the memory 13-1, the storage unit 14-1, and the communication unit 15-1 are communicably connected via the bus. In the following description, it is not necessary to distinguish between the external microcomputers 16-1 to 16-8, and when any external microcomputer 16-1 to 16-8 is indicated, it is described as the external microcomputer 16.

Processor 12-1 controls the entire platform 10-1. Processor 12-1 may be a multiprocessor. Further, the processor 12-1 includes, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), a GPU (Graphics Processing Unit), a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), and a PLD (Programmable Logic Device). ) And FPGA (Field Programmable Gate Array). Further, the processor 12 may be a combination of two or more types of elements of the CPU, MPU, GPU, DSP, ASIC, PLD, and FPGA. In the following description, it is not necessary to distinguish between processors 12-1 to 12-8, and when any processor 12-1 to 12-8 is indicated, it is referred to as processor 12.

The memory 13-1 is a storage memory including a ROM (Read Only Memory) and a RAM (Random Access Memory). Various software programs and data for this program are written in the ROM of the memory 13-1. The software program on the memory 13-1 is appropriately read and executed by the processor 12. Further, the RAM of the memory 13-1 is used as a primary storage memory or a working memory. In the following description, it is not necessary to distinguish between the memories 13-1 to 13-8, and when an arbitrary memory 13-1 to 13-8 is indicated, it is described as the memory 13.

The storage unit 14-1 is a storage device such as a hard disk drive (HDD), SSD (Solid State Drive), and storage class memory (SCM), and stores various data. be. For example, various software programs are stored in the storage unit 14-1. In the following description, it is not necessary to distinguish between the storage units 14-1 to 14-8, and when any storage unit 14-1 to 14-8 is indicated, it is described as the storage unit 14.

In the platform 10, various functions are realized by the processor 12 executing a software program stored in the memory 13 and the storage unit 14.

The various software programs described above do not necessarily have to be stored in the memory 13 or the storage unit 14. For example, the platform 10 may read and execute a program stored in a storage medium that can be read by a medium reader or the like. The storage medium that can be read by the platform 10 corresponds to, for example, a CD-ROM, a DVD disk, a portable recording medium such as a USB (Universal Serial Bus) memory, a semiconductor memory such as a flash memory, a hard disk drive, or the like. Further, the information processing program may be stored in a device connected to a public line, the Internet, a LAN, or the like, and the platform 10 may read and execute the information processing program from these.

The communication unit 15-1 is an interface for executing communication with the power supply control board 40 of the relay device 30. For example, the communication unit 15-1 executes communication according to a communication standard such as I2C (Inter-Integrated Circuit). In the following description, it is not necessary to distinguish the communication units 15-1 to 15-8, and when any communication unit 15-1 to 15-8 is indicated, it is described as the communication unit 15.

Next, the relay device 30 will be described. The relay device 30 includes an endpoint 31-1 to 1-31-8 provided for each platform 10, a processor 32, a memory 33, a storage unit 34, an internal bus 35, a PCIe bus 36, and a power supply control board 40. And. In the following description, it is not necessary to distinguish each endpoint 31-1 to 1-31-8, and when an arbitrary endpoint 31-1 to 1-31-8 is indicated, it is described as endpoint 31.

The endpoint 31 is provided for each platform 10 and executes data transmission / reception. For example, when the endpoint 31 receives data from the connected platform 10, it transmits the received data to the endpoint 31 connected to the destination platform 10 via the PCIe bus 36.

For example, the route complex 11 transmits data to another platform 10 by DMA (Direct Memory Access) transfer. Further, the endpoint 31 transmits the received data to the connected platform 10 when the data is received from the endpoint 31 connected to the platform 10 from which the data is transmitted via the PCIe bus 36.

The processor 32 controls the entire relay device 30. The processor 32 may be a multiprocessor. Further, the processor 32 may be, for example, any one of CPU, MPU, GPU, DSP, ASIC, PLD, and FPGA. Further, the processor 32 may be a combination of two or more types of elements of the CPU, MPU, GPU, DSP, ASIC, PLD, and FPGA.

The memory 33 is a storage device including a ROM and a RAM. Various software programs and data for this program are written in the ROM. The program stored in the memory 33 is read into the processor 32 and executed. In addition, RAM is used as a working memory.

The storage unit 34 is a storage device such as a hard disk drive, SSD, and storage class memory, and stores various data. For example, various software programs are stored in the storage unit 34.

The internal bus 35 communicatively connects the processor 32, the memory 33, the storage unit 34, and the PCIe bus 36.

The PCIe bus 36 communicatively connects a plurality of endpoints 31 and an internal bus 35. That is, the PCIe bus 36 connects the plurality of endpoints 31 so that data can be transferred. Further, the PCIe bus 36 is, for example, a bus compliant with the PCIe standard.

The power supply control board 40 includes a microcomputer 41 (hereinafter referred to as an internal microcomputer, which is an example of a control unit) 41 that controls the supply of electric power to the platform 10 and the activation of the external microcomputer 16. The power supply control board 40 is, for example, an integrated circuit having a microcomputer or a microcontroller. The power control board 40 also supplies power to the platform 10 when the relay device 30 is restarted. Further, the power supply control board 40 is communicably connected to the platform 10 and the processor 32 of the relay device 30.

FIG. 3 is a diagram showing an example of the hardware configuration of the platform and the power supply control board included in the information processing system according to the present embodiment. Next, an example of the hardware configuration of the platform 10 and the power supply control board 40 will be described with reference to FIG.

First, an example of the hardware configuration of the platform 10 will be described. As shown in FIG. 3, the platform 10 includes an external microcomputer 16, a cooling fan 17, and a DCDC converter 19. Further, the platform 10 operates by receiving power of 12.0V and 3.3V from the PSU (Power Supply Unit) 50 via the power supply control board 40.

The cooling fan 17 is a cooling fan for the external microcomputer 16, and is an example of an expansion device included in the platform 10. Further, the cooling fan 17 rotates according to a FAN_PWM (Pulse Width Modulation) signal transmitted from the power supply control board 40 via the expansion pin of the slot S included in the relay device 30 to cool the external microcomputer 16.

Here, the expansion pin is a pin other than the pin of the slot S provided on the board of the relay device 30 and used for communication with the platform 10 according to the PCIe communication standard (hereinafter, referred to as a PCIe pin). Further, here, the FAN_PWM signal is an example of a control signal of the cooling fan 17, and is, for example, a fan control signal instructing the rotation speed of the cooling fan 17.

Further, the cooling fan 17 transmits a FAN_TACH (Tachometer) signal to the power supply control board 40 via the expansion pin. Here, the FAN_TACH signal is an example of an output signal indicating the control result of the cooling fan 17, and is, for example, a signal indicating the measurement result of the rotation speed of the cooling fan 17. In the present embodiment, the cooling fan 17 operates by receiving power of 5.0 V from the PSU 50 via the DCDC converter 19.

The DCDC converter 19 converts the voltage of the electric power supplied from the PSU 50 to the cooling fan 17. In the present embodiment, the DCDC converter 19 converts the 12.0V power supplied from the PSU 50 into 5.0V power and supplies it to the cooling fan 17.

The external microcomputer 16 is a microcomputer that executes arithmetic processing such as AI processing and image processing. In the present embodiment, the external microcomputer 16 executes the startup process according to the PCIE_P_BTN signal transmitted (input) from the power supply control board 40. Here, the PCIE_P_BTN signal is an example of an activation signal instructing the activation of the external microcomputer 16. In the present embodiment, the PCIE_P_BTN signal is high when the external microcomputer 16 is started, and low when the external microcomputer 16 is stopped.

Further, in the present embodiment, the external microcomputer 16 transmits a PCIE_STATE signal to the power supply control board 40. Here, the PCIE_START signal is a signal indicating the activation state of the external microcomputer 16 itself. In the present embodiment, the PCIE_STATE signal becomes high when the activation process of the external microcomputer 16 is completed, and becomes low when the activation of the external microcomputer 16 is not completed.

Next, an example of the hardware configuration of the power supply control board 40 will be described. As shown in FIG. 3, the power supply control board 40 includes an internal microcomputer 41, an inverting circuit 42, DCDC converters 43 and 44, and switches 45 and 46.

The switch 45 is a switch that turns on or off the supply of 12.0 V power from the PSU 50 to the platform 10. In the present embodiment, the switch 45 turns on or off the power supply to the platform 10 according to the PCIE_SW_ON signal input from the internal microcomputer 41. Here, the PCIE_SW_ON signal is a signal instructing on or off of the power supply to the platform 10. In the present embodiment, the PCIE_SW_ON signal is high when the power supply to the platform 10 is turned on, and low when the power supply to the platform 10 is turned off. The power supply control board 40 has switches 45 for the number of slots S of the relay device 30.

The DCDC converter 43 converts the voltage of the electric power supplied from the PSU 50 to the platform 10. Specifically, the DCDC converter 43 converts the 12.0 V power supplied from the PSU 50 into 3.3 V power and supplies it to the platform 10. In the present embodiment, the DCDC converter 43 uses the PCIE_SW_ON signal input from the internal microcomputer 41 to output 12.0 V of power supplied from the PSU 50 when the power supply to the platform 10 is instructed to be turned on. Converts to .3V power and supplies it to platform 10. The power supply control board 40 has DCDC converters 43 for the number of slots S of the relay device 30.

The DCDC converter 44 converts the voltage of the power supplied from the PSU 50 into the voltage of the standby power of the platform 10. Specifically, the DCDC converter 44 constantly (that is, whether or not the platform 10 is connected to the relay device 30) transfers 11.0 V power supplied from the PSU 50 to 3.3 V standby power. Convert to. The power supply control board 40 has DCDC converters 44 for the number of slots S of the relay device 30.

The switch 46 is a switch that turns on or off the supply of standby power from the PSU 50 to the platform 10. In this embodiment, the switch 46 turns on the supply of standby power from the PSU 50 to the platform 10 when the PCIE_PRESENT signal received from the platform 10 indicates that the platform 10 is connected to the relay device 30. On the other hand, the switch 46 turns off the supply of standby power from the PSU 50 to the platform 10 when the PCIE_PRESS signal input from the platform 10 indicates that the platform 10 is not connected to the relay device 30. The power control board 40 has switches 46 for the number of slots S of the relay device 30.

Here, the PCIE_PRESENT signal is a signal indicating whether or not the platform 10 is connected to the relay device 30 (slot S). In the present embodiment, the PCIE_PRESENT signal is high when the platform 10 is connected to the relay device 30, and low when the platform 10 is not connected to the relay device 30. The inverting circuit 42 inverts the level of the PCIE_PRESENT signal input from the platform 10.

In the internal microcomputer 41, the CPU, MPU, GPU, DSP, ASIC, PLD, FPGA, or other processor executes a software program stored in the storage unit to supply power to the platform 10 as described above. , And control the activation of the external microcomputer 16. Here, the storage unit corresponds to, for example, a portable recording medium such as a CD-ROM, a DVD disk, or a USB memory, a semiconductor memory such as a flash memory, a hard disk drive, or the like. Further, the information processing program may be stored in a device connected to a public line, the Internet, a LAN, or the like, and the platform 10 may read and execute the information processing program from these. In the present embodiment, the internal microcomputer 41 realizes the supply of power to the platform 10 and the control of starting the external microcomputer 16 by executing the software program stored in the storage unit by the processor. It is not limited to the above, and can be realized by hardware such as a circuit board. In the present embodiment, the internal microcomputer 41 controls the supply of electric power from the PSU 50 to the platform 10 by outputting a PCIE_SW_ON signal to the switch 45 and the DCDC converter 43.

Further, in the present embodiment, the internal microcomputer 41 transmits a PCIE_P_BTN signal to the external microcomputer 16 to control the activation process of the external microcomputer 16. Further, in the present embodiment, the internal microcomputer 41 receives the PCIE_STATE signal from the external microcomputer 16 and determines whether or not the activation process of the external microcomputer 16 is completed based on the PCIE_STATE signal.

By the way, in the conventional information processing system, when a legitimate platform is connected to the slot of the relay device, the information processing system can operate normally, but for the slot of the relay device, If a platform other than the legitimate platform is connected, the operation of the information processing system may malfunction. Further, in the conventional information processing system, the expansion device of the platform (for example, the fan for cooling the microcomputer of the platform) is controlled after the platform is started, so that even if there is an abnormality in the expansion device, the expansion device has an abnormality. Anomalies in extended devices can only be detected after the platform has booted.

Therefore, in the present embodiment, the internal microcomputer 41 transmits a FAN_PWM signal to the cooling fan 17, which is an example of the expansion device, via the expansion pin prior to the activation of the external microcomputer 16 included in the platform 10. Further, the internal microcomputer 41 receives the FAN_TACH signal transmitted from the cooling fan 17 via the expansion pin. Then, the internal microcomputer 41 determines whether or not the cooling fan 17 is a predetermined device based on the FAN_PWM signal and the FAN_TACH signal. Here, the predetermined device is a preset expansion device, which is an expansion device mounted on the legitimate platform 10.

When it is determined that the cooling fan 17 is not a predetermined device, the internal microcomputer 41 executes the start / stop process of the external microcomputer 16. As a result, when a platform 10 other than the regular platform 10 is connected, it is possible to prevent the platform 10 from being activated, so that it is possible to provide a highly secure information processing system. On the other hand, when it is determined that the cooling fan 17 is a predetermined device, the internal microcomputer 41 executes the activation process of the external microcomputer 16.

Here, the stop process includes a process of stopping the supply of electric power to the platform 10. As a result, the power supply to the platform 10 other than the regular platform 10 is continued to the slot S of the relay device 30, a short circuit between the power supply control board 40 and the platform 10, and the power supplied to the platform 10. It is possible to reduce the possibility that an abnormality such as heat generation of the platform 10 exceeding the rating will occur. In the present embodiment, the internal microcomputer 41 instructs the platform 10 to turn off the power supply by lowering the PCIE_SW_ON signal output to the switch 45 and the DCDC converter 43. Further, here, the stop process includes a process of not transmitting a start signal to the external microcomputer 16. As a result, when a platform 10 other than the regular platform 10 is connected, it is possible to prevent the platform 10 from being activated, so that it is possible to provide a highly secure information processing system. In the present embodiment, the internal microcomputer 41 instructs the external microcomputer 16 to stop starting by lowering the PCIE_P_BTN signal output to the external microcomputer 16. Here, the start-up process includes a process of transmitting a start-up signal to the external microcomputer 16. In the present embodiment, the internal microcomputer 41 instructs the external microcomputer 16 to start by setting the PCIE_P_BTN signal output to the external microcomputer 16 to high.

In the present embodiment, the internal microcomputer 41 is based on the rotation speed indicated by the duty ratio of the FAN_PWM signal transmitted to the cooling fan 17 and the rotation speed indicated by the FAN_TACH signal received from the cooling fan 17. , It is determined whether or not the cooling fan 17 is a predetermined device. As a result, it is possible to detect an abnormality in the cooling fan 17 before the platform 10 is started. Therefore, even though the cooling fan 17 has an abnormality, the platform 10 is started and the external microcomputer 16 is started. Can not be cooled, and it is possible to prevent the external microcomputer 16 from having a problem. For example, in the internal microcomputer 41, when the rotation speed indicated by the FAN_TACH signal received from the cooling fan 17 is the rotation speed indicated by the duty ratio of the FAN_PWM signal: 100%: 900 rpm or more, the cooling fan 17 is a predetermined device. Judge that. On the other hand, in the internal microcomputer 41, when the rotation speed indicated by the FAN_TACH signal output from the cooling fan 17 is less than the rotation speed: 900 rpm indicated by the duty ratio of the FAN_PWM signal: 100%, the cooling fan 17 is predetermined. Judge that it is not a device.

Further, for example, the internal microcomputer 41 changes the duty ratio of the FAN_PWM signal from 0% to 100% at a preset ratio (for example, 20%). Then, when the rotation speed indicated by the FAN_TACH signal output from the cooling fan 17 increases in response to the change in the duty ratio of the FAN_PWM signal, the internal microcomputer 41 determines that the cooling fan 17 is a predetermined device. do. On the other hand, in the internal microcomputer 41, if the rotation speed indicated by the FAN_TACH signal output from the cooling fan 17 does not increase according to the change in the duty ratio of the FAN_PWM signal, the cooling fan 17 must be a predetermined device. to decide.

FIG. 4 is a sequence diagram showing an example of the flow of activation processing of the external microcomputer of the platform in the information processing system according to the present embodiment. Next, an example of the flow of the startup process of the external microcomputer 16 will be described with reference to FIG.

The switch 46 is turned on when the input PCIE_PRESENT signal is high to supply 3.3 V of standby power to the platform 10 connected to the slot S to which the PCIE_PRESENT signal is input (step). S401). After that, when the power button for turning on the power of the PSU 50 is pressed, the PSU 50 starts supplying 12.0 V power from the PSU 50 to the power control board 40 (step S402).

The internal microcomputer 41 executes a check process for determining whether or not the bridge board fan, which is a fan for cooling the internal microcomputer 41 of the power supply control board 40, is operating normally (step S403). Then, when it is determined that the bridge board fan is operating normally, the internal microcomputer 41 starts supplying electric power from the PSU 50 to the power supply control board 40 to start the power supply control board 40 (step S404).

Further, the internal microcomputer 41 sets the PCIE_P_BTN signal transmitted to the external microcomputer 16 of the platform 10-1 functioning as the main information processing device among the platforms 10-1 to 10-8 to a high level, and sets the platform 10- The external microcomputer 16 of 1 is started. The external microcomputer 16 of the platform 10-1 is activated when the PCIE_P_BTN signal received from the internal microcomputer 41 reaches a high level, and executes a POST (Power On Self Test) process (step S405).

Based on the PCIE_PRESENT signal, the internal microcomputer 41 determines whether or not another platform 10 is connected to a slot S other than the slot S to which the platform 10-1 is connected (step S406). Then, the internal microcomputer 41 sets the PCIE_SW_ON signal output to the switch 45 and the DCDC converter 43 to high, and starts supplying power from the PSU 50 to the platform 10 connected to the slot S (step S407).

The cooling fan 17 receives power from the PSU 50 and rotates according to the FAN_PWM signal transmitted from the internal microcomputer 41 via the expansion pin. The internal microcomputer 41 determines whether or not the cooling fan 17 is a predetermined device based on the FAN_PWM signal transmitted to the cooling fan 17 and the FAN_TACH signal received from the cooling fan 17 via the expansion pin. The check process is executed (step S408).

Then, when it is determined that the cooling fan 17 is a predetermined device, the internal microcomputer 41 sets the PCIE_P_BTN signal transmitted to the external microcomputer 16 of the platform 10 connected to the slot to a high level, and sets the external microcomputer 16 to a high level. It is activated (step S409). After that, when the PCIE_STATE signal input from the external microcomputer 16 of the platform 10 connected to the slot S becomes high, the internal microcomputer 41 determines that the activation process of the external microcomputer 16 is completed (step S411).

On the other hand, when it is determined that the cooling fan 17 is not a predetermined device, the internal microcomputer 41 sets the PCIE_SW_ON signal output to the switch 45 and the DCDC converter 43 to low, and powers the platform 10 connected to the slot S from the PSU 50. A stop process for stopping the supply is executed (step S410).

As described above, according to the information processing system 1 according to the present embodiment, when a platform 10 other than the regular platform 10 is connected, it is possible to prevent the platform 10 from starting, so that highly secure information processing can be performed. It makes it possible to provide a system.

Further, according to the information processing system 1 according to the present embodiment, the power supply to the platform 10 other than the regular platform 10 is continued to the slot S of the relay device 30, and the power control board 40 and the platform 10 are used. It is possible to reduce the possibility of an abnormality such as a short circuit between the two, the power supplied to the platform 10 and the heat generation of the platform 10 exceeding the rating.

Further, according to the information processing system 1 according to the present embodiment, when a platform 10 other than the regular platform 10 is connected, it is possible to prevent the platform 10 from starting, so that a highly secure information processing system can be used. It is possible to provide.

Further, according to the information processing system 1 according to the present embodiment, the abnormality of the cooling fan 17 can be detected before the platform 10 is started, so that the cooling fan 17 has an abnormality. However, it is possible to prevent the platform 10 from being activated, the external microcomputer 16 cannot be cooled, and a problem occurs in the external microcomputer 16.

In the above-described embodiment, PCIe has been described as an example of the I / O interface of each part, but the interface is not limited to PCIe. For example, the interface of each part may be a technology capable of transferring data between a device (peripheral controller) and a processor by a data transfer bus. The data transfer bus may be a general-purpose bus capable of transferring data at high speed in a local environment (for example, one system or one device) provided in one housing or the like. The interface may be either a parallel interface or a serial interface.

In the case of serial transfer, the I / O interface may be configured so that point-to-point connection is possible and data can be transferred on a packet basis. The I / O interface may have a plurality of lanes in the case of serial transfer. The layer structure of the I / O interface may include a transaction layer that generates and decodes packets, a data link layer that performs error detection, and a physical layer that converts serial and parallel. The I / O interface also includes a root complex at the top of the hierarchy with one or more ports, an endpoint that is an I / O device, a switch to increase the number of ports, a bridge that translates the protocol, and the like. It's fine. The interface may multiplex the data to be transmitted and the clock signal by a multiplexer and transmit them. In this case, the receiving side may separate the data and the clock signal by a demultiplexer.

1 Information processing system 10-1 to 10-8 Platform 16-1 to 16-8 External microcomputer 17 Cooling fan 19,43,44 DCDC converter 30 Relay device 36 PCIe bus 40 Power supply control board 41 Internal microcomputer 42 Inversion circuit 45, 46 switch 50 PSU
S slot (example of connection part)

The information processing device according to the first aspect of the present invention has a connection unit to which an external information processing device can be connected and a pin of the connection unit prior to activation of the external control unit of the external information processing device. A control signal is transmitted to an expansion device of the external information processing device via an expansion pin other than the pin used for communication in accordance with our communication standard, and the expansion device transmits a control signal via the expansion pin. An output signal indicating a control result of the expansion device is received, and based on the output signal and the control signal, the expansion device is mounted on the expansion device that is preset and is a regular external information processing device. it is determined whether the predetermined device being, when the expansion device is determined not to be the predetermined device, and a control unit that performs a stop process of remains stopped the external control unit without let start, the Be prepared.

The program according to the second aspect of the present invention sets the computer as a communication standard among the pins of the connection unit to which the external information processing device can be connected prior to the activation of the external control unit of the external information processing device. A control signal is output to the expansion device of the external information processing device via an expansion pin other than the pin used for the corresponding communication, and the expansion device controls the expansion device via the expansion pin. A predetermined device that receives an output signal indicating a result, and based on the output signal and the control signal, the expansion device is a preset expansion device and is mounted on a legitimate external information processing device. When it is determined whether or not the extended device is present and it is determined that the extended device is not the predetermined device, the external control unit is made to function as a control unit that executes a stop process of keeping the external control unit stopped without starting it.

Claims (5)

A connection unit that can connect an external information processing device,
Prior to the activation of the external control unit of the external information processing device, the external information processing device is operated via an expansion pin other than the pin used for communication according to the communication standard among the pins of the connection unit. A control signal is transmitted to the expansion device having the device, an output signal indicating a control result of the expansion device is received from the expansion device via the expansion pin, and the output signal and the control signal are used as the basis for the output signal. A control unit that determines whether or not the expansion device is a predetermined device, and if it is determined that the expansion device is not the predetermined device, a control unit that executes a process of stopping the activation of the external control unit.
Information processing device equipped with. The information processing device according to claim 1, wherein the stop process includes a process of stopping the supply of electric power to the external information processing device. The information processing device according to claim 1 or 2, wherein the stop process includes a process of not transmitting an activation signal instructing the activation of the external control unit. The expansion device is a cooling fan for the external control unit.
The control signal is a signal indicating the rotation speed of the cooling fan.
The information processing device according to any one of claims 1 to 3, wherein the output signal is a signal indicating a measurement result of the rotation speed of the cooling fan. Computer,
Prior to the activation of the external control unit of the external information processing device, an expansion pin other than the pin used for communication according to the communication standard among the pins of the connection unit to which the external information processing device can be connected is used. A control signal is output to an expansion device included in the external information processing device, an output signal indicating a control result of the expansion device is received from the expansion device via the expansion pin, and the output signal and the expansion device are received. A control unit that determines whether or not the expansion device is a predetermined device based on a control signal, and if it is determined that the expansion device is not the predetermined device, executes a process of stopping the activation of the external control unit.
A program to function as.

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