JP2021168838A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2021168838A5 JP2021168838A5 JP2020073926A JP2020073926A JP2021168838A5 JP 2021168838 A5 JP2021168838 A5 JP 2021168838A5 JP 2020073926 A JP2020073926 A JP 2020073926A JP 2020073926 A JP2020073926 A JP 2020073926A JP 2021168838 A5 JP2021168838 A5 JP 2021168838A5
- Authority
- JP
- Japan
- Prior art keywords
- image
- display list
- circuit
- display
- control means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Description
ところで、この種の遊技機では、各種の演出を複雑化かつ豊富化したいところ、特に、液晶ディスプレイを使用する画像演出については、その要請が高い。そこで、出願人は、各種の提案をしているが（引用文献１～引用文献４）、画像演出の更なる高度化や、画像演出制御を中心とした各種の演出制御動作の更なる改善が望まれるところである。また、画像演出制御の制御負担が軽減できるよう、液晶ディスプレイの駆動動作についても改善が望まれる。 By the way, in this type of game machine, there is a desire to make various effects complicated and rich, and in particular, there is a high demand for image effects using a liquid crystal display. Therefore, the applicant has made various proposals (cited documents 1 to 4), but further enhancement of image effects and further improvement of various effect control operations centering on image effect control are needed. This is desired. In addition, it is desirable to improve the drive operation of the liquid crystal display so as to reduce the control burden of image presentation control.
上記の目的を達成するため、本発明は、表示装置の画面に表示すべき表示内容を特定するディスプレイリストを発行するＣＰＵ回路を有する画像制御手段と、前記画像制御手段が発行するディスプレイリストに記載された指示コマンドに基づいて、前記表示内容を実現する画像データを生成する描画回路を有する画像生成手段と、を有して構成され、前記画像生成手段は、前記画像制御手段から所定の取得ビット単位で受けるディスプレイリストの構成データを、所定の転送ビット単位で前記描画回路に転送可能なデータ転送回路を有して構成され、ディスプレイリストの全ビット長は、前記転送ビット単位の整数Ｎ倍（Ｎ≧１）である。 In order to achieve the above object, the present invention provides an image control means having a CPU circuit for issuing a display list specifying display contents to be displayed on a screen of a display device, and a display list issued by the image control means. and image generating means having a drawing circuit for generating image data for realizing the display content based on the received instruction command, wherein the image generating means receives a predetermined acquired bit from the image control means . The data transfer circuit is capable of transferring display list configuration data received in units to the drawing circuit in predetermined transfer bit units, and the total bit length of the display list is an integer N times the transfer bit unit ( N≧1) .
上記した本発明によれば、画像制御動作が改善される。 According to the invention described above, the image control operation is improved.
Claims (1)
前記画像生成手段は、
前記画像制御手段から所定の取得ビット単位で受けるディスプレイリストの構成データを、所定の転送ビット単位で前記描画回路に転送可能なデータ転送回路を有して構成され、
ディスプレイリストの全ビット長は、前記転送ビット単位の整数Ｎ倍（Ｎ≧１）である遊技機。 image control means having a CPU circuit for issuing a display list specifying display contents to be displayed on a screen of a display device; and image generation means having a rendering circuit for generating image data to be realized ,
The image generation means is
comprising a data transfer circuit capable of transferring display list configuration data received from the image control means in predetermined acquisition bit units to the rendering circuit in predetermined transfer bit units;
A game machine in which the total bit length of the display list is integer N times (N≧1) the transfer bit unit .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2020073926A JP2021168838A (en) | 2020-04-17 | 2020-04-17 | Game machine |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2020073926A JP2021168838A (en) | 2020-04-17 | 2020-04-17 | Game machine |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2021168838A JP2021168838A (en) | 2021-10-28 |
| JP2021168838A5 true JP2021168838A5 (en) | 2023-04-24 |
Family
ID=78119321
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020073926A Pending JP2021168838A (en) | 2020-04-17 | 2020-04-17 | Game machine |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2021168838A (en) |
-
2020
- 2020-04-17 JP JP2020073926A patent/JP2021168838A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI352336B (en) | Method and apparatus for displaying rotated images | |
| JP2017519244A (en) | Multiple display pipeline driving a split display | |
| US9117297B2 (en) | Reduced on-chip memory graphics data processing | |
| JP2021168838A5 (en) | ||
| JP6632864B2 (en) | Display driver and display device | |
| JP2021168839A5 (en) | ||
| US11100904B2 (en) | Image drawing apparatus and display apparatus with increased memory efficiency | |
| JP2021112246A5 (en) | ||
| JP2021168840A5 (en) | ||
| TW201317974A (en) | Display controller and display device including the same | |
| JP2016005612A5 (en) | ||
| WO2019220527A1 (en) | Head mounted display, image display method, and computer program | |
| JP2021166612A5 (en) | ||
| JP2021168837A5 (en) | ||
| CN106201401A (en) | The 3D rendering presented for virtual desktop accelerates display packing | |
| JP2021168836A5 (en) | ||
| JP2021166613A5 (en) | ||
| JP2019058816A5 (en) | ||
| JP2021168833A5 (en) | ||
| JP2019042576A5 (en) | ||
| CN102708832A (en) | Liquid crystal graph display controller and implementation method | |
| JP5407590B2 (en) | Image display device | |
| TW201606625A (en) | Virtual desktop client, control chip of virtual desktop client and method of controlling server device | |
| JP2021166608A5 (en) | ||
| JP2015083271A5 (en) |