JP2021164041A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of suppressing a decrease in conversion speed in analog-digital conversion processing and reducing noise.SOLUTION: A solid-state imaging device 1 includes: an analog-digital conversion unit having a comparison unit for comparing a reference signal and an analog processing target signal and a counter unit for performing a counting operation on the basis of the comparison result of the comparison unit after receiving the supply of a count clock signal, and acquiring digital data of the processing target signal on the basis of the output data of the counter unit; and a control unit having a first control unit for controlling an analog-digital conversion process to the processing target signal by making the number of execution times for a reset level and the number of execution times for a signal level different and a second control unit for controlling the analog-digital conversion unit so as to execute a digital integration process on the result of the analog-digital conversion process.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a semiconductor device having an analog-to-digital converter that converts an analog signal into a digital signal.

The analog signal to be subjected to analog-digital conversion processing is compared with the reference signal, and the digital data of the unit signal is acquired based on the count value obtained by performing the count processing during the count operation valid period based on the comparison processing result. A method analog-digital converter is known (see, for example, Patent Document 1). Further, in such an analog-to-digital converter, a technique for multiplexing analog-to-digital conversion processing is known (see, for example, Patent Document 2). In analog-to-digital conversion processing that performs multiplexing,
The n-bit analog-to-digital conversion process is repeated for each of the reset level (P phase) and the signal level (D phase) a predetermined number of times (W times), and the digital integration process of adding the digital values of each time is executed. In this way, the digital signal data obtained by the analog-to-digital conversion process W times is multiplied by W. On the other hand, the noise included in the W analog-to-digital conversion process is √W times. As a result, the problem of random noise such as quantization noise and circuit noise associated with analog-digital conversion, which does not exist in processing in the analog region, can be alleviated, and noise reduction can be realized.

Japanese Unexamined Patent Publication No. 2005-328135 Japanese Unexamined Patent Publication No. 2009-296423

However, when the n-bit analog-to-digital conversion process is repeated W times for each of the P-phase and the D-phase, the conversion time is W, respectively, as compared with the case where the analog-digital conversion process of the P-phase and the D-phase is performed once. Double. Therefore, the conventional technique has a problem that the analog-to-digital conversion processing period increases and the conversion speed decreases.

An object of the present disclosure is to provide a semiconductor device capable of suppressing a decrease in conversion speed in analog-to-digital conversion processing and reducing noise.

In order to achieve the above object, the semiconductor device according to one aspect of the present disclosure includes a comparison unit that compares a reference signal supplied from a reference signal generation unit and whose level gradually changes with an analog processing target signal, and an analog digital conversion. An analog-digital conversion unit that has a counter unit that receives the supply of the count clock signal for counting and performs a counting operation based on the comparison result of the comparison unit, and acquires digital data of the processing target signal based on the output data of the counter unit. The first control unit that controls the number of times the analog-digital conversion process for the signal to be processed is executed for the reset level and the number of times the analog-digital conversion process is executed for the signal level are different, and the result of the analog-digital conversion process. A control unit having a second control unit that controls the analog-digital conversion unit so as to execute a digital integration process is provided.

It is a block diagram which shows the schematic structure of the solid-state image sensor as a semiconductor device by 1st Embodiment of this disclosure. It is a block diagram which shows an example of the schematic structure of the main part of the drive control part provided in the solid-state image sensor as a semiconductor device by 1st Embodiment of this disclosure. It is a circuit diagram which shows an example of the schematic structure of the counter part provided in the solid-state image pickup apparatus as a semiconductor device according to 1st Embodiment of this disclosure. It is a figure which shows an example of the timing chart of the analog-to-digital conversion processing of the solid-state image sensor as a semiconductor device according to 1st Embodiment of this disclosure. It is a figure (the 1) which shows an example of the timing chart of the analog-to-digital conversion processing of the conventional solid-state image sensor. It is a figure (the 2) which shows an example of the timing chart of the analog-to-digital conversion processing of the conventional solid-state image sensor. FIG. 3 is a diagram (No. 3) showing an example of a timing chart of analog-to-digital conversion processing of a solid-state image sensor as a semiconductor device according to the first embodiment of the present disclosure. It is a block diagram which shows an example of the schematic structure of the main part of the drive control part provided in the solid-state image sensor as a semiconductor device by 2nd Embodiment of this disclosure. It is a circuit diagram which shows an example of the schematic structure of the counter part provided in the solid-state image pickup apparatus as a semiconductor device by 2nd Embodiment of this disclosure. It is a figure which shows an example of the timing chart of the analog-to-digital conversion processing of the solid-state image sensor as a semiconductor device by 2nd Embodiment of this disclosure. It is a circuit diagram which shows an example of the schematic structure of the counter part provided in the solid-state image pickup apparatus as a semiconductor device according to 3rd Embodiment of this disclosure. It is a figure which shows an example of the timing chart of the analog-to-digital conversion processing of the solid-state image sensor as a semiconductor device according to the 3rd Embodiment of this disclosure. It is a circuit diagram which shows an example of the schematic structure of the counter part provided in the solid-state image pickup apparatus as a semiconductor device according to 4th Embodiment of this disclosure. It is a block diagram which shows the schematic structure of the microelectrode array device as a semiconductor device according to 5th Embodiment of this disclosure.

[First Embodiment]
The semiconductor device according to the first embodiment of the present disclosure will be described with reference to FIGS. 1 to 7. As a semiconductor device according to the present embodiment, a solid-state image sensor will be described as an example. First, a schematic configuration of a solid-state image sensor as a semiconductor device according to the present embodiment will be described with reference to FIGS. 1 to 3.

FIG. 1 is a schematic configuration diagram of a CMOS solid-state image sensor (CMOS image sensor) as a semiconductor device according to the present embodiment.

The solid-state imaging device 1 has a pixel portion in which a plurality of pixels including a light receiving element that outputs a signal according to the amount of incident light are arranged in rows and columns (that is, in a two-dimensional matrix). The solid-state imaging device 1 is provided in parallel in a row and performs a correlated double sampling (CDS) process on a voltage signal output from each pixel, and an analog digital converter and a correlated double sampling function unit. : It has an analog-to-digital converter that executes ADC). Hereinafter, the correlated double sampling may be abbreviated as "CDS", the analog digital may be abbreviated as "AD", and the analog-to-digital converter may be abbreviated as "ADC".

"The CDS processing function unit and the AD conversion unit are provided in parallel in the column" means that a plurality of CDS processing function units and the digital conversion unit are provided substantially in parallel with the vertical signal line 19 in the vertical column. Means to be. When the device is viewed in a plan view, the plurality of functional units are arranged only on one edge side (output side arranged at the lower side of the figure) in the column direction with respect to the pixel unit 10. It may be provided, or on one edge side (output side arranged on the lower side of the figure) in the column direction and the other edge side (upper side of the figure) on the opposite side with respect to the pixel portion 10. It may have a form in which it is arranged separately. In the latter case, it is preferable that the horizontal scanning unit that performs read scanning (horizontal scanning) in the row direction is also arranged separately on each edge side so that each can operate independently.

For example, as a typical example in which a CDS processing function unit and an AD conversion unit are provided in parallel in columns, a CDS processing function unit and a digital conversion unit are provided for each vertical column in a portion called a column region provided on the output side of the imaging unit. It is a column type that is provided in the above and is read out to the output side in sequence. Further, not limited to the column type, one CDS processing function unit and AD conversion unit are assigned to a plurality of adjacent (for example, two) vertical signal lines 19 (vertical columns), and every N lines (N is , Natural numbers, that is, positive integers: N-1 lines are arranged between them) N vertical signal lines 19 (vertical columns) are assigned one CDS processing function unit and AD conversion unit. You can also.

In all forms except the column type, since a plurality of vertical signal lines 19 (vertical columns) are configured to use one CDS processing function unit and a digital conversion unit in common, a plurality of columns supplied from the pixel unit 10 side. A switching circuit (switch) for supplying a minute pixel signal to one CDS processing function unit and AD conversion unit is provided. Depending on the processing in the subsequent stage, it may be necessary to take measures such as providing a storage unit for holding the output signal.

In any case, the signal processing of each pixel signal is read out in pixel column units by adopting a form in which one CDS processing function unit or AD conversion unit is assigned to a plurality of vertical signal lines 19 (vertical columns). It can be performed later, and the configuration in each unit pixel can be simplified as compared with the case where the same signal processing is performed in each unit pixel, and it is possible to cope with the increase in the number of pixels, the miniaturization, the cost reduction, and the like of the image sensor.

Further, since a plurality of signal processing units arranged in parallel in columns can simultaneously process pixel signals for one row, one CDS processing function unit and AD conversion unit can be used on the output circuit side or outside the device. The signal processing unit can be operated at a lower speed than the case of performing the processing, which is advantageous in terms of power consumption, band performance, noise, and the like. Conversely, if the power consumption and bandwidth performance are the same, the entire sensor can operate at high speed.

In the case of the column type configuration, it can be operated at a low speed, which is advantageous in terms of power consumption, band performance, noise, etc., and also has an advantage that a switching circuit (switch) is not required. In the following embodiments, this column type will be described unless otherwise specified.

As shown in FIG. 1, in the solid-state image sensor 1 according to the present embodiment, a pixel unit (imaging unit) 10 in which a plurality of unit pixels 3 having a substantially square pixel shape are arranged in rows and columns (that is, in a square grid pattern). A drive control unit 7 provided outside the pixel unit 10, a column processing unit 26, a reference signal generation unit 27 that supplies a reference voltage for AD conversion to the column processing unit 26, and an output circuit 28 are provided. ing.

If necessary, an AGC (Auto Gain Control) circuit or the like having a signal amplification function may be provided in the same semiconductor region as the column processing unit 26 in the front stage or the rear stage of the column processing unit 26. When AGC is performed in the front stage of the column processing unit 26, analog amplification is performed, and when AGC is performed in the rear stage of the column processing unit 26, digital amplification is performed. If the n-bit digital data is simply amplified, the gradation may be impaired. Therefore, it is considered preferable to perform analog amplification and then digital conversion.

The drive control unit 7 has a control circuit function for sequentially reading the signals of the pixel unit 10. For example, the drive control unit 7 includes a horizontal scanning circuit (column scanning circuit) 12 for controlling column addresses and column scanning, a vertical scanning circuit (row scanning circuit) 14 for controlling row addresses and row scanning, and an internal clock. It is provided with a communication / timing control unit 20 having a function of generating and the like.

As shown by a dotted line in the vicinity of the communication / timing control unit 20 in FIG. 1, the solid-state imaging device 1 is an example of a high-speed clock generation unit, and generates a pulse having a clock frequency higher than the input clock frequency. The clock conversion unit 23 may be provided. The communication / timing control unit 20 generates an internal clock signal based on the input clock signal (master clock signal) CLK0 input via the terminal 5a and the high-speed clock signal generated by the clock conversion unit 23.

By using a signal originating from a high-speed clock signal generated by the clock conversion unit 23, AD conversion processing and the like can be operated at high speed. Further, the high-speed clock signal can be used to perform motion extraction and compression processing that require high-speed calculation. Further, the parallel data output from the column processing unit 26 can be converted into serial data and the video data D1 can be output to the outside of the solid-state image sensor 1. By doing so, the solid-state image sensor 1 can adopt a configuration in which high-speed operation output is performed with fewer terminals than the number of bits of AD-converted digital data.

The clock conversion unit 23 has a built-in multiplication circuit that generates a pulse having a clock frequency higher than the input clock frequency. The clock conversion unit 23 receives the low-speed clock signal CLK2 from the communication / timing control unit 20, and generates a clock signal having a frequency twice or more higher based on the received clock signal CLK2. As the multiplication circuit of the clock conversion unit 23, a k1 multiplication circuit may be provided when k1 is a multiple of the frequency of the low-speed clock signal CLK2, and various well-known circuits can be used.

In FIG. 1, a part of rows and columns is omitted for the sake of simplicity, but in reality, tens to thousands of unit pixels 3 are arranged in each row and each column, and the pixel portion 10 is formed. It is composed. The unit pixel 3 typically has a photodiode as a light receiving element (charge generation unit) and an in-pixel amplifier having a semiconductor element (for example, a transistor) for amplification.

As the intra-pixel amplifier, for example, an amplifier having a floating diffusion amplifier configuration is used. As an example of the in-pixel amplifier, for the charge generation unit, a read selection transistor which is an example of a charge reading unit (transfer gate unit / reading gate unit), a reset transistor which is an example of a reset gate unit, and a vertical selection transistor are used. , And an amplification transistor having a source follower configuration, which is an example of a detection element for detecting a potential change of floating diffusion, can be used as a CMOS sensor composed of four general-purpose transistors.

Alternatively, an amplification transistor connected to the drain line for amplifying the signal voltage corresponding to the signal charge generated by the charge generator, a reset transistor for resetting the charge generator, and transfer from the vertical shift register. It is also possible to use a transistor composed of three transistors having a read selection transistor (transfer gate portion) scanned via wiring.

The pixel portion 10 has, in addition to the effective image region (effective portion) 10a which is an effective region for capturing an image, a reference pixel region which is arranged around the effective image region (effective portion) 10a to give optical black. There is. As an example, reference pixels that give optical black for several rows (for example, 1 to 10 rows) are arranged vertically above and below the vertical column direction, and a number is arranged on the left and right in a horizontal parallel including an effective image region (effective portion) 10a. Reference pixels that provide optical black for pixels to several tens of pixels (for example, 3 to 40 pixels) are arranged.

The reference pixel that imparts optical black is shielded from light so that the light receiving surface side thereof does not allow light to enter the charge generating portion made of a photodiode or the like. The pixel signal from this reference pixel is used as a black reference for the video signal.

Further, in the solid-state image sensor 1 of the present embodiment, the pixel unit 10 is compatible with color imaging. That is, the light receiving surface on which the electromagnetic wave (light in this example) of each charge generating unit (photodiode or the like) in the pixel unit 10 is incident is color-separated by a combination of a plurality of color filters for capturing a color image. A color filter (not shown) of any of the filters is provided.

In the present embodiment, a so-called Bayer array basic color filter is used, and the unit pixels 3 arranged in a square grid pattern have three colors of red (R), green (G), and blue (B). The repeating unit of the color separation filter is arranged in 2 pixels × 2 pixels so as to correspond to the color filter, and constitutes the pixel unit 10.

For example, the odd-numbered rows and odd-numbered columns have a first color pixel for detecting the first color (for example, red: R), and the even-numbered rows and odd-numbered columns and the even-numbered rows and odd-numbered columns have a second color (for example, green). : A second color pixel for detecting G) is arranged, and a third color pixel for detecting a third color (for example, blue: B) is arranged in even rows and even columns. As a result, two color pixels of R / G or G / B, which are different for each row, are arranged in the pixel portion 10 in a checkered pattern.

In the color arrangement of the basic color filter of such a Bayer arrangement, two colors of R / G or G / B are repeated every two in both the row direction and the column direction.

Further, as other components of the drive control unit 7, a horizontal scanning circuit 12, a vertical scanning circuit 14, and a communication / timing control unit 20 are provided. The horizontal scanning circuit 12 has a function of a reading scanning unit that reads a count value from the column processing unit 26. Each component of the drive control unit 7 is integrally formed with the pixel unit 10 in a semiconductor region such as single crystal silicon by using the same technology as the semiconductor integrated circuit manufacturing technology, and is a solid-state image sensor which is an example of a semiconductor device. It is configured as (imaging device).

The unit pixel 3 is connected to the vertical scanning circuit 14 via a row control line 15 for row selection. Further, the unit pixel 3 is connected to a column processing unit 26 in which a column AD circuit 25 is provided for each vertical column via a vertical signal line 19. Here, the row control line 15 indicates the entire wiring that enters the pixel from the vertical scanning circuit 14.

The horizontal scanning circuit 12 and the vertical scanning circuit 14 are configured to include a decoder as described later, and start a shift operation (scanning) in response to control signals CN1 and CN2 given from the communication / timing control unit 20. It has become. Therefore, the row control line 15 includes various pulse signals (for example, reset pulse RST, transfer pulse TRF, DRN control pulse DRN, etc.) for driving the unit pixel 3.

Although not shown, the communication / timing control unit 20 receives the master clock signal CLK0 via the terminal 5a, receives the data DATA instructing the operation mode and the like via the terminal 5b, and further includes the information of the solid-state image sensor 1. It is equipped with a functional block of a communication interface that outputs data. Further, the communication / timing control unit 20 controls the number of times the analog-to-digital conversion process for the processing target signal output from the pixel unit 10 is executed for the reset level and the number of times for the signal level to be executed differently. It has a first control unit 201. Further, the communication / timing control unit 20 executes the digital integration process on the result of the analog-to-digital conversion process in the column AD circuit 25 (an example of the analog-digital conversion unit, details will be described later). It has a second control unit 202 that controls the above. That is, the communication / timing control unit 20 corresponds to an example of a control unit having the first control unit 201 and the second control unit 202. The first control unit 201 and the second control unit 202 are configured to function as a timing generator that supplies a clock signal necessary for the operation of each unit and a pulse signal at a predetermined timing.

For example, the communication / timing control unit 20 outputs the horizontal address signal to the horizontal decoder 12a and outputs the vertical address signal to the vertical decoder 14a. The horizontal decoder 12a selects a column corresponding to the horizontal address signal input from the communication / timing control unit 20. Further, the vertical decoder 14a selects a line corresponding to the vertical address signal input from the communication / timing control unit 20.

At this time, since the unit pixels 3 are arranged in a two-dimensional matrix, the analog pixel signals generated by the pixel signal generation unit 5 and output in the column direction via the vertical signal line 19 are row-by-row (column parallel). (In this example) Access and capture (vertical) scan Read, then access in the row direction, which is the arrangement direction of the vertical columns, and read the pixel signal (digitized pixel data in this example) to the output side (horizontal) scan. It is preferable to speed up the reading of the pixel signal and the pixel data by reading the data. Of course, not limited to scan reading, random access to read only the necessary information of the unit pixel 3 is also possible by directly addressing the unit pixel 3 to be read.

Further, in the communication / timing control unit 20 of the present embodiment, a clock signal CLK1 having the same frequency as the master clock (master clock) signal CLK0 input via the terminal 5a, a clock signal obtained by dividing the clock signal CLK1 by two, and the like A low-speed clock signal obtained by dividing the clock signal CLK1 by more than two divisions is supplied to each part in the solid-state imaging device 1, for example, a horizontal scanning circuit 12, a vertical scanning circuit 14, a column processing unit 26, and the like. Hereinafter, the clock signal having a frequency divided by two and the clock signal having a frequency equal to or lower than the frequency of the clock signal divided by two will be collectively referred to as a low-speed clock signal CLK2.

The vertical scanning circuit 14 selects a row of the pixel unit 10 and supplies a necessary pulse signal to the selected row. For example, the vertical scanning circuit 14 has a vertical decoder 14a that defines a read line in the vertical direction (selects a line of the pixel unit 10) and a unit pixel 3 on the read address (row direction) defined by the vertical decoder 14a. It has a vertical drive circuit 14b for supplying and driving a pulse signal to the row control line 15. In addition to the line for reading the signal, the vertical decoder 14a also selects a line for the electronic shutter and the like.

The horizontal scanning circuit 12 sequentially selects the column AD circuit 25 of the column processing unit 26 in synchronization with the low-speed clock signal CLK2, and outputs a signal from the selected column AD circuit 25 to the horizontal signal line (horizontal output line) 18. It leads to. For example, the horizontal scanning circuit 12 follows a horizontal decoder 12a that defines a horizontal read sequence (selects an individual column AD circuit 25 in the column processing unit 26) and a read address defined by the horizontal decoder 12a. It has a horizontal drive circuit 12b that guides each signal of the column processing unit 26 to the horizontal signal line 18. For example, if the number of bits n (n is a positive integer) handled by the column AD circuit 25, for example, 10 (= n) bits, 10 horizontal signal lines 18 are arranged corresponding to the number of bits. ..

In the solid-state image sensor 1 having such a configuration, the pixel signal output from the unit pixel 3 is supplied to the column AD circuit 25 of the column processing unit 26 via the vertical signal line 19 for each vertical column.

Each column AD circuit 25 of the column processing unit 26 receives a signal of one row of pixels and processes the received signal. For example, each of the column AD circuits 25 is configured to be able to convert an analog signal into, for example, 10-bit digital data by using, for example, a count clock signal CK0 having a frequency equivalent to that of the low-speed clock signal CLK2. It has an ADC (Analog Digital Converter) circuit.

Although the details will be described later, the column AD circuit 25 is a voltage for comparing the lamp-shaped reference signal (reference voltage) RAMP input from the reference signal generation unit 27 and the analog pixel signal input via the vertical signal line 19. The count clock signal CK0 starts counting at the same time as the comparison unit 252 and the reference signal RAMP are supplied, and holds the count number at the time when the output signal of the voltage comparison unit 252 is switched from, for example, a high level to a low level. It has a counter unit 254.

Further, at this time, by devising the circuit configuration, the signal level (noise level) immediately after the pixel reset and the true (noise level) and the true (noise level) of the voltage mode pixel signal input via the vertical signal line 19 together with the AD conversion are obtained. It is possible to perform a process of taking a difference from the signal level Vsig (according to the amount of received light). This makes it possible to remove noise signal components called fixed pattern noise (Fixed Pattern Noise: FPN) and reset noise.

The pixel data digitized by the column AD circuit 25 is transmitted to the horizontal signal line 18 via a horizontal selection switch (not shown) driven by a horizontal selection signal from the horizontal scanning circuit 12, and further input to the output circuit 28. .. The number of bits that the column AD circuit 25 converts an analog signal into digital data is not limited to 10 bits, and other values such as less than 10 bits (for example, 8 bits) and more than 10 bits (for example, 14 bits). May be.

With such a configuration, pixel signals are sequentially output for each vertical column for each row from the pixel unit 10 in which light receiving elements as charge generation units are arranged in a matrix. Then, one image, that is, a frame image corresponding to the pixel unit 10 in which the light receiving elements are arranged in a matrix is shown as a set of pixel signals of the entire pixel unit 10.

<Details of column AD circuit and reference signal generator>
The reference signal generation unit 27 is a digital-to-analog conversion circuit (Digital Analog Converter) which is a functional element that generates a reference signal for AD conversion according to the color type and arrangement of the color filters constituting the color separation filter in the pixel unit 10. : DAC) is provided individually. Hereinafter, the digital analog may be referred to as "DA", and the digital-to-analog conversion circuit may be referred to as "DAC".

When the pixel unit 10 (device) to be used is determined, the color type and arrangement of the color filter in the color separation filter are determined, and the number of colors of the color filter at an arbitrary position in the two-dimensional lattice position is uniquely specified. Can be done. Each repetition cycle in the row direction and the column direction of the color filter is also uniquely determined by the arrangement, and one processing target row to be processed by each of the column AD circuits 25 provided in parallel in the column is subjected to a color separation filter. There will only be pixel signals with fewer predetermined color combinations determined by the iteration cycle, rather than all the colors used.

In the present embodiment, paying attention to this property, it is a functional element that generates a reference signal for AD conversion supplied to the voltage comparison unit 252 when the column AD circuit 25 is configured by the voltage comparison unit 252 and the counter unit 254. , The DA conversion circuit, which is an example of the individual reference signal generation output unit, is not provided for all the colors used in the color separation filter. By setting only a few minutes according to the combination of color filters of a predetermined color existing in, the number is less than the total number of colors of the color filters existing in the repetition cycle of the color filters in two dimensions. A pixel signal corresponding to red or green is output to the pixel unit 10 of the present embodiment to output an even-numbered row of vertical signal lines 19, and a pixel signal corresponding to green or blue is output to an odd-numbered row of vertical signal lines 19. And are arranged. Therefore, the reference signal generation unit 27 is output from the DA conversion circuit 27a that generates the reference signal RAMPa to be compared with the pixel signal output from the vertical signal line 19 in the even row and the vertical signal line 19 in the odd row. It has a DA conversion circuit 27b that generates a reference signal RAMPb to be compared with a pixel signal.

The solid-state imaging device 1 has a signal line 252a into which the reference signal RAMPa output from the DA conversion circuit 27a is input, and a signal line 252a in which the reference signal RAMPb output from the DA conversion circuit 27b is input. .. A voltage comparison unit 252 corresponding to a color filter having a common color characteristic is connected to the signal line 252am252b. That is, the voltage comparison unit 252 in the even-numbered row, which uses the pixel signal output from the vertical signal line 19 in the even-numbered row as the processing target signal, is connected to the signal line 252a. The voltage comparison unit 252 in the odd-numbered row, which uses the pixel signal output from the vertical signal line 19 in the odd-numbered row as the signal to be processed, is connected to the signal line 252b. As a result, the reference signal RAMPa is transmitted to each of the voltage comparison units 252 in the even-numbered columns via the common signal line 252a, and the common signal line 252b is transmitted to each of the voltage comparison units 252 in the odd-numbered columns. The reference signal RAMPb is configured to be transmitted via the reference signal RAMPb.

Note that in a different direction, that is, a vertical column direction, which is a direction different from the row direction according to the reading unit, the change characteristic (specifically, the inclination) corresponding to the color characteristic of the color pixel, the black reference, and the circuit offset component. A color correspondence reference signal generator that changes with an initial value defined from the viewpoint of non-color characteristics different from color characteristics such as, is a color filter of a predetermined color that exists in the repetition cycle of the color filter in the vertical column direction. It is possible to provide each of the individual DA conversion circuits (reference signal generation output unit) for a number of colors according to the combination, and select one of the outputs according to the switching of the processing target line. ..

In this case, when a color filter of the same color exists in the repeating cycle of the color filter in two dimensions, for example, a bayer array, the individual DA conversion circuit (reference signal generation output unit) is used for the color filter of the same color. Each of the above may be configured to also (share) one color-corresponding reference signal generation unit.

Alternatively, for each of the individual DA conversion circuits (reference signal generation output unit), each time the processing target line is switched, the color combination that constitutes the repeating unit of the color filter array is changed due to the switching. Then, the communication / timing control unit 20 sets the initial value based on the change characteristic (specifically, the inclination) corresponding to the color characteristic of the corresponding color pixel and the viewpoint different from the color characteristic such as the black reference and the circuit offset component. You may set it. By doing so, it is not necessary to provide a selection unit for selecting either the color-corresponding reference signal generation unit or the color-corresponding reference signal generation unit in each of the individual DA conversion circuits (reference signal generation output unit).

In any configuration, in each of the DA conversion circuits (reference signal generation output unit), the DA conversion circuit switches according to the switching of the predetermined color combination existing in the processing target line by switching the processing target line. The change characteristic (specifically, the gradient) of the output reference signal (analog reference voltage) is switched and output according to the characteristic of the color filter, that is, the analog pixel signal. Further, the initial value is set based on a viewpoint different from the color characteristics, such as a black reference and an offset component of a circuit.

By doing so, the number of wires from the reference voltage generator (corresponding to the DA conversion circuit in this example) and the reference voltage generator can be reduced to be smaller than the number of color filters constituting the color separation filter. In addition, for each vertical column that selectively outputs the analog reference voltage (corresponding to the reference signal in this example) from each reference voltage generator, which was required when a reference voltage generator was prepared for each color filter. Since the selection means (multiplexer) is not required, the circuit scale can be reduced. The number of signal lines that transmit the reference signal corresponding to the color pixel to the input side of the comparator can be smaller than the number of color components of the color filter for capturing a color image.

In addition, the change characteristics (specifically, the inclination) and the initial value are DA-converted according to the change of the color combination constituting the repeating unit of the color filter array due to the switching each time the processing target row is switched. If it is set in the circuit, it is not necessary to provide a selection unit for switching between the color-corresponding reference signal generation unit and the color-corresponding reference signal generation unit according to the processing target line according to each of the color filters, and the reference signal generation unit 27 The scale of the overall configuration of can be further reduced.

In this example, the solid-state image sensor 1 uses a Bayer-type basic array, and as described above, the color filter is repeated every two rows and two columns. Since the pixel signal is read out row by row and the pixel signal is input to each column AD circuit 25 provided in column parallel for each vertical signal line 19, one R / G or G / B line can be processed. There is a pixel signal of only any two colors. Therefore, in this example, a DA conversion circuit 27a corresponding to an odd number of columns and a DA conversion circuit 27b corresponding to an even number of columns are provided.

The DA conversion circuits 27a and 27b are counted clock signals CKdaca and CKdacb (count clock signals CK0) from the communication / timing control unit 20 from the initial values indicated by the control data CN4 (CN4a, CN4b) from the communication / timing control unit 20. In synchronization with (may be the same as), a stepped sawtooth wave signal (ramp voltage) whose level (for example, voltage level) gradually changes is generated and output to the signal line 252a. The corresponding individual column AD circuits 25 of the column processing unit 26 use the sawtooth wave signals generated by the DA conversion circuits 27a and 27b as reference signals (ADC reference signals) RAMPa and RAMPb for AD conversion. ing. Although not shown, a noise prevention filter may be provided.

When the DA conversion circuits 27a and 27b perform AD conversion processing for the signal component Vsig in the pixel signal Vx at a predetermined position by using the voltage comparison unit 252 and the counter unit 254, the initial reference signals RAMPa and RAMPb generated by each of them are used. The voltage is set to a value different from that at the time of AD conversion processing for the reset component ΔV, reflecting the pixel characteristics and circuit variation, and each inclination is adjusted to match the pixel characteristics in consideration of the color filter arrangement. βa and βb may be set.

Specifically, first, it is assumed that the reference signals RAMPa and RAMPb initial voltages Vas and Vbs for the signal component Vsig are calculated based on the signals obtained from the pixels that generate an arbitrary plurality of black references. The pixel that generates the black reference is a pixel that has a light-shielding layer on a photodiode or the like as a photoelectric conversion element that forms a charge generation unit 32 arranged outside the color pixel. The arrangement form such as the arrangement place and the number of arrangements and the light-shielding means are not particularly limited, and a known mechanism can be adopted.

Further, it is assumed that this initial voltage includes a unique variation component generated by the characteristics of the DA conversion circuits 27a and 27b, respectively. Normally, the initial voltages Vas and Vbs are lowered by offsets OFFa and OFFb with respect to the initial voltages Var and Vbr of the reference signals RAMPa and RAMPb for the reset component ΔV, respectively.

Even if the initial voltages Var and Vbr of the reference signals RAMPa and RAMPb for the reset component ΔV are the same, the offsets OFFa and OFFb usually have different values. The voltages Vas and Vbs are different.

The initial voltages Vas and Vbs of the reference signals RAMPa and RAMPb for the signal component Vsig may include an arbitrary offset in addition to the signal obtained from the pixel that generates the black reference.

The offset control performed by the DA conversion circuits 27a and 27b of the reference signal generation unit 27 is, for example, a communication / timing control function for calculating the initial voltage based on the signals obtained from the reference pixels that generate an arbitrary plurality of black references. It may be provided in the unit 20 and performed based on the initial value indicated by the control data CN4 from the communication / timing control unit 20. Of course, the DA conversion circuits 27a and 27b may have a function of calculating the initial voltage and may calculate the initial voltage by themselves.

Alternatively, the communication / timing control unit 20 in the chip and the DA conversion circuits 27a and 27b do not have a function of calculating the initial voltage of the reference voltage, but are obtained from a reference pixel that generates a black reference in an external system outside the chip. The initial voltage is calculated based on the signal, and the communication / timing control unit 20 is notified of the information indicating the initial voltage as a part of the operation mode via the terminal 5b, and the control data CN4 from the communication / timing control unit 20 is used. The reference signal generation unit 27 may be notified.

The stepped reference signal emitted by the reference signal generation unit 27, specifically, the reference signal RAMPa emitted by the DA conversion circuit 27a and the reference signal RAMPb emitted by the DA conversion circuit 27b are high-speed clock signals from the clock conversion unit 23, for example, multiplication. By generating based on the multiplication clock generated by the circuit, it can be changed at a higher speed than the generation based on the master clock signal CLK0 input via the terminal 5a.

The control data CN4a and CN4b supplied from the communication / timing control unit 20 to the DA conversion circuit 27a of the reference signal generation unit 27 also include information indicating the slope of the lamp voltage (degree of change; amount of time change) for each comparison process. I'm out.

The column processing unit 26 has the same number of column AD circuits 25 as the vertical signal lines 19. The plurality of column AD circuits 25 have the same configuration as each other. The column AD circuit 25 is a voltage for comparing the reference signals RAMPa and RAMPb supplied from the reference signal generation unit 27 whose level gradually changes with the pixel signal (an example of an analog processing target signal) input from the vertical signal line 19. It has a comparison unit (an example of a comparison unit) 252. Further, the column AD circuit 25 has a counter unit 254 that receives the supply of the count clock signal CK0 for analog-to-digital conversion and performs a counting operation based on the comparison result of the voltage comparison unit 252. The column AD circuit 25 is configured to acquire digital data of a pixel signal based on the output data of the counter unit 254.

More specifically, the column AD circuit 25 has a reference signal RAMPa or DA conversion circuit 27b generated by the DA conversion circuit 27a of the reference signal generation unit 27, and a unit for each row control line 15 (H0, H1, ...). The voltage comparison unit 252 for comparing the analog pixel signal obtained from the pixel 3 via the vertical signal lines 19 (V0, V1, ...) And the voltage comparison unit 252 count the time until the comparison process is completed. It has a counter unit 254 that holds the result. The column processing unit 26 has the same number of column AD circuits 25 as the number of bits of digital data generated by analog-to-digital conversion. In the present embodiment, since the column processing unit 26 has n column AD circuits 25, it has an n-bit AD conversion function.

The communication / timing control unit 20 has a function of a control unit that switches the count processing mode in the counter unit 254 according to which of the pixel signal reset component ΔV and the signal component Vsig is being compared by the voltage comparison unit 252. have. A mode selection signal CN5 for instructing whether the counter unit 254 operates in the down count mode or the up count mode is input from the communication / timing control unit 20 to the counter unit 254 of each column AD circuit 25. There is.

One input terminal of the voltage comparison unit 252 in the even-numbered row is connected to the signal line 252a, and the other input terminal of the voltage comparison unit 252 in the even-numbered row is connected to the vertical signal line 19 in the even-numbered row. As a result, the stepped reference signal RAMPa generated by the reference signal generation unit 27 is input to one input terminal of the voltage comparison unit 252 in the even column, and the other input of the voltage comparison unit 252 in the even column. The pixel voltages V0, V2, ..., Vn-2 of the pixel signals output from the corresponding even-row vertical signal lines 19 are individually input to the terminals. One input terminal of the voltage comparison unit 252 in the odd-numbered row is connected to the signal line 252b, and the other input terminal of the voltage comparison unit 252 in the odd-numbered row is connected to the vertical signal line 19 in the odd-numbered row. As a result, the stepped reference signal RAMPb generated by the reference signal generation unit 27 is input to one input terminal of the voltage comparison unit 252 in the odd column, and the other input of the voltage comparison unit 252 in the odd column. The pixel voltages V1, ..., Vn-1 of the pixel signals output from the corresponding odd-row vertical signal lines 19 are individually input to the terminals.

The voltage comparison unit 252 is composed of, for example, a comparator circuit. The voltage comparison unit 252 in the even column has a signal level when the signal level (for example, voltage value) of the reference signal RAMPa is equal to or smaller than the signal level (for example, voltage value) of the pixel signal output from the vertical signal line 19. Output a high level output signal. On the other hand, the voltage comparison unit 252 in the even column indicates the signal level when the signal level (for example, voltage value) of the reference signal RAMPa is larger than the signal level (for example, voltage value) of the pixel signal output from the vertical signal line 19. Outputs a low level (reference potential level, i.e., ground level) output signal.

The voltage comparison unit 252 in the odd column has a signal level when the signal level (for example, voltage value) of the reference signal RAMPb is equal to or smaller than the signal level (for example, voltage value) of the pixel signal output from the vertical signal line 19. Outputs a high level output signal. On the other hand, when the signal level (for example, voltage value) of the reference signal RAMPb is larger than the signal level (for example, voltage value) of the pixel signal output from the vertical signal line 19, the voltage comparison unit 252 in the odd column has a signal level. Outputs a low level (reference potential level, i.e., ground level) output signal. The output signal of the voltage comparison unit 252 is supplied to the counter unit 254.

Here, the schematic configuration of the counter unit 254 will be described with reference to FIGS. 2 and 3.
As shown in FIG. 2, the plurality of counter units 254 have the same configuration as each other. The counter unit 254 has a counter circuit 254a, an integration circuit 254b, and a latch circuit 254c.

The counter circuit 254a is configured to count the count clock signal CK0 input from the communication / timing control unit 20. The output terminal of the voltage comparison unit 252 is connected to the counter circuit 254a. The counter circuit 254a is configured so that, for example, when the output signal of the voltage comparison unit 252 becomes low level, the input of the clock signal CL0 is stopped. As a result, the counter circuit 254a stops counting when the signal level of the reference signal RAMPa (or reference signal RAMPb) becomes higher than the signal level of the pixel signal output from the vertical signal line 19, and the digital data at the time of the stop. Can be retained. Further, the counter circuit 254a is configured to output digital data at the time when counting is stopped to the integration circuit 254b. Further, the counter circuit 254a is configured to change and hold the digital data indicating the value at the time when the counting is stopped to the digital data of the calculation result calculated by the integration circuit 254b. The specific configuration of the counter circuit 254a will be described later.

The integrating circuit 254b has a reset level (P phase) based on the number of AD conversion processes executed for the reset level (P phase) and the number of AD conversion processes executed for the signal level (D phase). It is configured to execute a predetermined arithmetic process on the result of the AD conversion process executed on the phase) or the result of the AD conversion process executed on the signal level (D phase). Therefore, the number of AD conversion processes executed for the reset level (P phase) is N (N is a natural number), and the number of AD conversion processes executed for the signal level (D phase) is M (M is M). Assuming that the column AD circuit 25 is a natural number different from N), the column AD circuit 25 obtains the result of the first calculation or the signal level (D phase) AD conversion process in which the result of the reset level (P phase) AD conversion process is multiplied by M / N. It has an integration circuit 254b (an example of a digital calculation unit) that executes a second calculation of N / M times.

The integrating circuit 254b is first when the number of AD conversion processes M executed for the signal level (D phase) is smaller than the number N of AD conversion processes executed for the reset level (P phase). The second operation is performed when the calculation is executed and the number of AD conversion processes M executed for the signal level (D phase) is larger than the number N of AD conversion processes executed for the reset level (P phase). Is configured to run. In the present embodiment, since the number of times M (for example, 3 times) is larger than the number of times N (for example, 1 time), the integrating circuit 254b determines the result of the AD conversion process executed for the reset level (P phase) as M /. The first operation (integration) to be N times is executed. More specifically, the integrating circuit 254b is digital data indicating a value at a time when the reference signal RAMPa (or reference signal RAMPb) is stopped because the signal level becomes larger than the reset level output from the vertical signal line 19. An integration process for multiplying the result of the AD conversion process by M / N is executed, and the digital data obtained by the integration process is output to the counter circuit 254a.

The latch circuit 254c is connected to the communication / timing control unit 20 and the counter circuit 254a. The latch circuit 254c is configured to store digital data held in the counter circuit 254a based on the control signal CN7 output from the second control unit 202 provided in the communication / timing control unit 20. .. Further, the latch circuit 254c is connected to the horizontal scanning circuit 12 and the horizontal signal line 18. The latch circuit 254c is configured to output digital data stored when the horizontal selection signal CH is input from the horizontal scanning circuit 12 to the horizontal signal line 18.

As shown in FIG. 3, the counter circuit 254a has a plurality of (n in this embodiment) D flip-flop circuits DFF0 to DFFn-1 connected in series. A switch SWc is connected between the clock input terminal CK of the first-stage D flip-flop circuit DFF0 and the communication / timing control unit 20. The opening and closing of the switch SWc is controlled by a control signal formed based on the signal level output from the voltage comparison unit 252. The control signal becomes low level for a predetermined period from the time when the signal level output from the voltage comparison unit 252 becomes low level. Therefore, the switch SWc is in the off state (open state) only for the predetermined period. The count clock signal CK0 output from the communication / timing control unit 20 is input to the switch SWc. Therefore, the count clock signal CK0 is not input to the clock input terminal CK of the D flip-flop circuit DFF0 during the predetermined period. Therefore, the counter circuit 254a stops counting in the predetermined period. Further, the counter circuit 254a also stops counting (counting) during a period in which the count clock signal CK0 having a constant signal level is input to the clock input terminal CK of the D flip-flop circuit DFF0.

The clock input terminals CK of the D flip-flop circuits DFF1 to DFFn-1 other than the first stage are the inverting output terminals / Q of the D flip-flop circuits DFF0 to DFFn-2 (D flip-flop circuits DFFn-2 are not shown) in the previous stage. It is connected to the. Further, each input terminal D of the D flip-flop circuits DFF0 to DFFn-1 is connected to each inverting output terminal / Q of the D flip-flop circuits DFF0 to DFFn-1. As described above, the counter circuit 254a in the present embodiment has an asynchronous counter circuit configuration.

The counter circuit 254a has multiplexers MX0 to MXn-1 in which input terminals are connected to the non-inverting output terminals Q and the inverting output terminals / Q of the D flip-flop circuits DFF1 to DFFn-1. The output signals bit [0] to bit [n-1] of the multiplexers MX0 to MXn-1 are the digital data output by the counter circuit 254a. The multiplexers MX0 to MXn-1 output signals output from the non-inverting output terminal Q and the inverting output terminal / Q based on the mode selection signal CN5 output from the communication / timing control unit 20. Output as bit [n-1]. Specifically, the multiplexers MX0 to MXn-1 output a signal output from the non-inverting output terminal Q when the counter circuit 254a functions as an upcounter based on the mode selection signal CN5 [0]. Output as ~ bit [n-1]. On the other hand, when the counter circuit 254a functions as a down counter based on the mode selection signal CN5, the multiplexers MX0 to MXn-1 output signals output from the inverting output terminal / Q to output signals bit [0] to bit [0] to bit [ n-1] is output.

The D flip-flop circuits DFF0 to DFFn-1 are configured to be reset or preset according to the signal level of the output signal output from the integration circuit 254b, which is the result of the integration processing of the integration circuit 254b (see FIG. 2). ing. That is, the D flip-flop circuits DFF0 to DFFn-1 are reset when the signal level of the output signal output from the integration circuit 254b (see FIG. 2) is low (the bit value of the digital data is "0"). .. On the other hand, the D flip-flop circuits DFF0 to DFFn-1 are preset when the signal level of the output signal output from the integration circuit 254b is high (the bit value of the digital data is "1"). For example, the D flip-flop circuit DFF0 is reset (the value of "0" is retained) when the bit value of the minimum bit of the digital data output from the integration circuit 254b is "0", and is output from the integration circuit 254b. When the bit value of the minimum bit of the digital data is "1", a preset (the value of "1" is retained) is performed. As a result, the counter circuit 254a can hold the result of the integration process of the integration circuit 254b by the D flip-flop circuits DFF0 to DFFn-1.

The counter unit 254 is designed to perform internal counting by inputting one count clock signal CK0. Similar to the stepped voltage waveform, the count clock signal CK0 is also generated based on the high-speed clock (for example, a multiplication clock) from the clock conversion unit 23, so that the count clock signal CK0 is faster than the master clock CLK0 input via the terminal 5a. can do.

Since the counter unit 254 can execute up-counting and down-counting by one system of D flip-flop circuits DFF0 to DFFn-1, the circuit is compared with the case where the up-counting and down-counting are provided in another system. The scale can be reduced.

When the counter unit 254 is a synchronous counter, the operation of the D flip-flop circuits DFF0 to DFFn-1 is limited by the count clock signal CK0. Therefore, when higher frequency operation is required, the counter unit 254 uses an asynchronous counter suitable for high-speed operation because its operation limiting frequency is determined only by the limiting frequency of the first-stage D flip-flop circuit DFF0. Is more preferable.

Returning to FIG. 1, a control pulse is input to the counter unit 254 from the horizontal scanning circuit 12 via the control line 12c. The counter unit 254 has a latch circuit 254c that holds the count result, and holds the counter output value until instructed by the control pulse via the control line 12c.

As described above, the column AD circuit 25 having such a configuration is arranged for each pixel voltage V0, V1, ... Of the pixel signals output from the plurality of vertical signal lines 19, and is an ADC block having a column parallel configuration. The column processing unit 26 is configured.

The output side of each column AD circuit 25 is connected to the horizontal signal line 18. As described above, the horizontal signal line 18 has a signal line corresponding to the bit width of the column AD circuit 25, which is n bits wide, and passes through n sense circuits corresponding to each output line (not shown). Then, it is connected to the output circuit 28.

In such a configuration, the column AD circuit 25 performs a counting operation in the pixel signal reading period corresponding to the horizontal blanking period, and outputs the counting result at a predetermined timing. That is, first, the voltage comparison unit 252 compares the lamp waveform voltage from the reference signal generation unit 27 with the pixel signal voltage input via the vertical signal line 19, and when both voltages are the same, the voltage comparison is performed. The comparator output of unit 252 is inverted (transition from H level to L level in this example).

The counter unit 254 starts the counting operation in the down count mode or the up count mode in synchronization with the lamp waveform voltage emitted from the reference signal generation unit 27, and the inverted information of the comparator output is notified to the counter unit 254. Then, the counting operation is stopped, and the AD conversion is completed by latching (holding / storing) the count value at that time as pixel data.

After that, the counter unit 254 sequentially stores and holds pixel data based on the shift operation by the horizontal selection signal CH (i) input from the horizontal scanning circuit 12 via the control line 12c at a predetermined timing. The data is output from the output terminal 5c to the outside of the column processing unit 26 and the outside of the chip having the pixel unit 10.

Although not shown in particular because the description of the present embodiment is not directly related, various other signal processing circuits and the like may be included in the components of the solid-state image sensor 1.

<Operation of solid-state image sensor>
The operation of the solid-state image sensor 1 as a semiconductor device according to the present embodiment will be described with reference to FIG. In FIG. 4, the number of AD conversion processes executed for the reset level (P phase) is 1 (N = 1), and the number of AD conversion processes executed for the signal level (D phase) is 3. It is a timing chart for explaining the multiple addition AD conversion and the digital CDS in the solid-state image sensor 1 when the number of times (M = 3) is set. “Slope” in FIG. 4 indicates a reference signal RAMP, “Signal” in FIG. 4 indicates a pixel signal output from the vertical signal line 19, and “CK0” in FIG. 4 indicates a count clock signal CK0. “Counter output” in FIG. 4 indicates an output signal (signal output to the latch circuit 254c) of the counter circuit 254a (see FIG. 2) of the counter unit 254.

As shown in FIG. 4, first, at the time of AD processing for the reset level (P phase), the count value of the D flip-flop circuits DFF0 to DFFn-1 (see FIG. 3) provided in the counter unit 254 is the initial value “0”. Will be reset to. Next, the counter unit 254 is set to the down count mode, and the comparison process between the reference signal RAMP and the reset level Srst by the voltage comparison unit 252 (see FIGS. 1 and 2) and the count process by the counter unit 254 are performed in parallel. Make it work. As a result, the AD conversion process for the reset level (P phase) is performed. As a result, the counter circuit 254a provided in the counter unit 254 after the first processing shows a digital value Drst corresponding to the magnitude of the reset level Srst (indicating a sign, it indicates -Drst). Is retained.

The counter unit 254 executes a digital integration process for integrating 3 (= M / N) into the digital value Drst in the integration circuit 254b (see FIG. 2), and holds the digital value 3 · Drst of the calculation result in the counter circuit 254a. ..

Subsequently, during the AD conversion process for the first signal level (D phase), the digital value 3 corresponding to the reset level Srst of the pixel voltage Vx of the pixel signal acquired during the reading of the signal level (P phase) and the AD conversion. Starting from Drst (which is a negative value here), the counter unit 254 is set to the upcount mode opposite to the reset level (P phase), and the reference signal RAMP and signal level Ssig by the voltage comparison unit 252 are set. The comparison process with the above and the count process by the counter circuit 254a provided in the counter unit 254 are operated in parallel. In this way, the AD conversion process for the first signal level (D phase) is executed. As a result, the counter unit 254 that has completed the AD conversion process of the first signal level (D phase) holds a count value indicating "-2. Drst + Dsig" (= -3. Drst + (Dsig + Drst)).

Subsequently, during the AD conversion process for the second signal level (D phase), the reference signal by the voltage comparison unit 252 is set in the same upcount mode as the first time, starting from the first count result (-2 · Drst + Dsig). The comparison processing between the RAMP and the signal level Sig and the counting processing by the counter circuit 254a provided in the counter unit 254 are operated in parallel. In this way, the AD conversion process for the second signal level (D phase) is executed. As a result, the counter unit 254 after the second processing holds a count value indicating "-Drst + 2 · Dsig" (= -2 · Drst + Dsig + (Dsig + Drst)).

Subsequently, during the AD conversion process for the third signal level (D phase), the voltage comparison unit 252 is in the same upcount mode as the first and second times, starting from the second count result (-Drst + 2 · Dsig). The comparison processing of the reference signal RAMP and the signal level Sig by the above and the counting processing by the counter circuit 254a provided in the counter unit 254 are operated in parallel. In this way, the AD conversion process for the third signal level (D phase) is executed. As a result, the counter unit 254 after the third processing holds a count value indicating "3 · Dsig" (= −Drst + 2 · Dsig + (Dsig + Drst)).

As described above, in the present embodiment, the reference signal comparison type AD conversion process is executed in the continuous down count mode N times (once in this example) for the reset level (P phase), and the AD conversion process is performed. The result is digitally integrated by M / N. Subsequently, using the result of the digital integration processing as the start value of the counter circuit 254a, the reference signal comparison type AD conversion processing in the continuous upcount mode M times (3 times in this example) with respect to the signal level (D phase) is performed. Run. By doing so, the addition operation processing of N times data (negative value when the sign is added) for the reset level (P phase) and M times data for the D phase is performed. Thereby, in the present embodiment, the number of executions of the AD conversion process for the reset level (P phase) can be reduced as compared with the AD conversion process for the signal level (D phase). As a result, the entire execution period of the AD conversion process in the solid-state image sensor 1 can be shortened. Further, the CDS processing of the same reset level Srst and signal level Sig can be performed, and the operation of adding can be performed. Such AD conversion processing and CDS processing by sampling M times are referred to as multiple addition AD conversion processing, digital integration processing N times and M times addition AD conversion processing, M times integration AD conversion processing, and the like.

The added data M · Dsig obtained by this multiple addition AD conversion process is sent to the output circuit 28 by horizontal transfer. The output circuit 28 acquires the added and averaged data Dsig by dividing the added data by the number of executions M of the AD conversion process with respect to the signal level (D phase) by the digital signal processing. The signal component is M times, but the random noise is √M times. Therefore, the noise characteristic (S / N) can be improved.

Next, the effect of the solid-state image sensor 1 as a semiconductor device according to the present embodiment will be described with reference to FIGS. 5 to 7. In FIG. 5, the number of AD conversion processes executed for the reset level (P phase) is set to 1 (N = 1), and the number of AD conversion processes executed for the signal level (D phase) is 1. It is a timing chart for explaining the multiple addition AD conversion and the digital CDS in the conventional solid-state image sensor when the number of times (M = 1) is set. In FIG. 6, the number of AD conversion processes executed for the reset level (P phase) is 3 times (N = 3), and the number of AD conversion processes executed for the signal level (D phase) is 3. It is a timing chart for explaining the multiple addition AD conversion and the digital CDS in the conventional solid-state image sensor when the number of times (M = 3) is set. In FIG. 7, the number of AD conversion processes executed for the reset level (P phase) is 3 times (N = 3), and the number of AD conversion processes executed for the signal level (D phase) is 1. It is a timing chart for explaining the multiple addition AD conversion and the digital CDS in the solid-state image sensor 1 according to this embodiment when the number of times (M = 1) is set.

As shown in FIG. 5, the number of AD conversion processes executed for the reset level (P phase) is set to 1 (N = 1), and the AD conversion process executed for the signal level (D phase) is performed. When the number of times is one (M = 1), the period of the multiple addition AD conversion and the digital CDS is the period Tconv1.

As shown in FIG. 6, when the number of AD conversion processes M executed for the signal level (D phase) is set to 3, the number of AD conversion processes M executed for the signal level (D phase) M. The period of the AD conversion process is tripled as compared with the case where is set to once. On the other hand, the first period T1 when the AD conversion process for the reset level (P phase) is executed is a common period in the AD conversion process three times. Similarly, the first period T2 when the AD conversion process for the signal level (D phase) is executed is a common period in the three AD conversion processes. Therefore, the total period of each of the three times of the AD conversion process for the reset level (P phase) and the AD conversion process for the signal level (D phase) is not three times the period Tconv1, and in the example shown in FIG. 6, it is about 2. It will be tripled. That is, although the S / N ratio is improved by √3 times, the A / D conversion processing speed is reduced by 1 / 2.3 times.

As shown in FIG. 7, the number of AD conversion processes executed for the reset level (P phase) is set to 3 times (N = 1), and the AD conversion process executed for the signal level (D phase) is performed. When the number of times is set to 1 (M = 1), the period of these AD conversion processes is 1.4 times the period Tconv1, which is shorter than the example shown in FIG. Further, in the present embodiment, the integration circuit 254b sets the AD conversion processing result for the reset level (P phase) to M / N times (when M> N) or the AD conversion processing result for the signal level (D phase) to N. After multiplying by / M (when N> M), digital CDS processing is performed. Although not shown, in the case of this example, the P-phase AD conversion process is performed three times, the D-phase AD conversion process is performed once, and then the D-phase AD conversion process result is tripled to obtain a digital CDS. Perform processing. As a result, the offset component fixedly superimposed on the P phase becomes the same amount as the offset component fixedly superimposed on the D phase, and is therefore canceled by the digital CDS processing.

As described above, the solid-state imaging device 1 as a semiconductor device according to the present embodiment is a voltage comparison unit that compares the reference signal RAMP supplied from the reference signal generation unit 27 and whose level gradually changes with the analog processed image signal. It has a counter unit 254 that receives 252 and a count clock signal CK0 for analog-to-digital conversion and performs a counting operation based on the comparison result of the voltage comparison unit 252, and digital data of an image signal based on the output data of the counter unit 254. The column AD circuit 25 for acquiring the image signal and the analog-to-digital conversion process for the image signal are controlled by different times between the number of times the reset level (P phase) is executed and the number of times the signal level (D phase) is executed. It includes a first control unit 201 and a communication / timing control unit 20 having a second control unit 202 that controls the column AD circuit 25 so as to execute a digital integration process on the result of the analog-to-digital conversion process.

According to the solid-state image sensor 1 having such a configuration, it is possible to suppress a decrease in the conversion speed in the analog-digital conversion process and reduce noise.

[Second Embodiment]
The semiconductor device according to the second embodiment of the present disclosure will be described with reference to FIGS. 8 to 10. The solid-state image sensor as a semiconductor device according to the present embodiment is characterized in that digital integration processing is executed by bit shifting in the counter unit. The schematic configuration of the solid-state image sensor according to the present embodiment is the same as the schematic configuration of the solid-state image sensor 1 according to the first embodiment. Therefore, the components having the same functions and functions as the components of the solid-state image sensor 1 according to the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 8, the counter unit 254 in the present embodiment has the same configuration as the counter unit 254 in the first embodiment, except that the integration circuit 254b is not provided. In the present embodiment, the counter circuit 254d provided in the counter unit 254 exerts the function of the integration circuit 254b.

As shown in FIG. 9, the counter circuit 254d has a plurality of (n in this embodiment) D flip-flop circuits DFF0 to DFFn-1 connected in series, similarly to the counter circuit 254a in the first embodiment. Have. A switch SWc1 is connected between the clock input terminal CK of the first-stage D flip-flop circuit DFF0 and the communication / timing control unit 20. The switch SWc1 exhibits the same function as the switch SWc in the first embodiment.

The counter circuit 254d has a switch SWc2 connected between each input terminal D of the D flip-flop circuits DFF0 to DFFn-1 and each inverting output terminal / Q of the D flip-flop circuits DFF0 to DFFn-1. doing. As a result, the input terminals D of the D flip-flop circuits DFF0 to DFFn-1 and the inverting output terminals / Q of the D flip-flop circuits DFF0 to DFFn-1 are connected and disconnected by the switch SWc2. It has become.

The counter circuit 254d is located between the wiring Lc connected to the second control unit 202 provided in the communication / timing control unit 20 and the input terminals D of the wiring Lc and the D flip-flop circuits DFF0 to DFFn-1. Each has switches SWs1 connected to it.

The counter circuit 254d has switches SWs2 connected between the second control unit 202 provided in the communication / timing control unit 20 and the input terminal D of the D flip-flop circuit DFF0.

The counter circuit 254d has a configuration in which the counter function and the shift register function can be switched by controlling the opening and closing of the switch SWc1, the switch SWc2, the switch SWs1 and the switch SWs2. The counter circuit 254d exhibits a counter function when the switches SWc1 and SWc2 are turned on (connected state) and the switches SWs1 and SWs2 are turned off (open state). When the counter circuit 254d operates by exerting the counter function, the counter circuit 254d counts the count clock signal CK0 by the same operation as the counter circuit 254a in the first embodiment.

On the other hand, the counter circuit 254d exhibits the shift register function when the switches SWc1 and SWc2 are in the off state (open state) and the switches SWs1 and SWs2 are in the on state (connection state). When the counter circuit 254d operates by exerting the shift register function, a pulse signal PS having a high signal level is input from the second control unit 202 to the wiring Lc. Since the pulse signal PS is input to the respective clock input terminals CK of the D flip-flop circuits DFF0 to DFFn-1, the D flip-flop circuits DFF0 to DFFn-1 hold the data input to the input terminals D. .. Since a low level signal is input to the first stage D flip-flop circuit DFF0 via the switch SWs1, the D flip-flop circuit DFF0 holds the data “0”. The D flip-flop circuits DFF1 to DFFn-1 each hold the data held in the D flip-flop circuits DFF0 to DFFn-2 (the D flip-flop circuit DFFn-2 is not shown) in the previous stage. As a result, the data held in the D flip-flop circuits DFF0 to DFFn-1 are shifted by 1 bit. In this way, the counter circuit 254d bit-shifts the data held in the D flip-flop circuits DFF0 to DFFn-1, so that the value of the output signal is multiplied by 2 ⁿ (n is the digital converted by the counter circuit 254d). The number of bits of data). As a result, the result of the AD conversion process for the reset level (P phase) can be multiplied by M / N. However, in the present embodiment, the result of the AD conversion process for the reset level (P phase) can be multiplied by M / N only when M> N and M / N is 2 ^n.

As described above, the bit shift circuit is composed of the D flip-flop circuits DFF0 to DFFn-1, the switch SWc1, the switch SWc2, the switch SWs1 and the switch SWs2. Therefore, the column AD circuit 25 is configured to convert an analog pixel signal (an example of a signal to be processed) into n-bit digital signals bit [0] to bit [n-1], and the counter unit 254. Has a bit shift circuit that bit shifts the count result.

<Operation of solid-state image sensor>
The operation of the solid-state image sensor as a semiconductor device according to the present embodiment will be described with reference to FIG. In FIG. 10, the number of AD conversion processes executed for the reset level (P phase) is 1 (N = 1), and the number of AD conversion processes executed for the signal level (D phase) is 2. It is a timing chart for explaining the multiple addition AD conversion and the digital CDS in the solid-state image sensor when the number of times (M = 2) is set. “Slope” in FIG. 10 indicates a reference signal RAMP, “Signal” in FIG. 10 indicates a pixel signal output from the vertical signal line 19 (see FIG. 1), and “CK0” in FIG. 10 is a count clock. The signal CK0 is shown, and the “counter output” in FIG. 10 indicates the output signal (signal output to the latch circuit 254c) of the counter circuit 254d (see FIG. 2) of the counter unit 254. “Count” in FIG. 10 indicates a control signal for controlling the opening / closing of the switch SWc1 and the switch SWc2, and “shift” in FIG. 10 indicates a control signal for controlling the opening / closing of the switch SWs1 and the switch SWs2. “PS” indicates the pulse signal PS input to the wiring Lc.

As shown in FIG. 10, first, at the time of AD processing for the reset level (P phase), the count value of the D flip-flop circuits DFF0 to DFFn-1 (see FIG. 9) provided in the counter unit 254 is the initial value “0”. Will be reset to. Next, the counter unit 254 is set to the down count mode, and the comparison process between the reference signal RAMP and the reset level Srst by the voltage comparison unit 252 (see FIG. 8) and the count process by the counter unit 254 are operated in parallel. As a result, the AD conversion process for the reset level (P phase) is performed. As a result, the counter circuit 254d provided in the counter unit 254 after the first processing shows a digital value Drst corresponding to the magnitude of the reset level Srst (indicating a sign, it indicates -Drst). Is retained.

Here, a low-level control signal is input to the control terminals of the switch SWc1 and the switch SWc2, and the switch SWc1 and the switch SWc2 are turned off (open state). Further, a high level control signal is input to the control terminals of the switch SWs1 and the switch SWs2, and the switch SWs1 and the switch SWs2 are turned on (short state). The operations of the switch SWc1 and the switch SWc2 and the switches SWs1 and the switch SWs2 are controlled almost at the same time. Further, after the switch SWc1 and the switch SWc2 are turned off and the switch SWs1 and the switch SWs2 are turned on, the pulse signal PS having a high signal level is input to the wiring Lc. As a result, the counter circuit 254d exerts a shift register function. As a result, the counter circuit 254d executes a digital integration process for integrating 2 (= M / N) into the digital value Drst, and holds the digital value 2 · Drst.

Subsequently, during the AD conversion process for the first signal level (D phase), the digital value 2 corresponding to the reset level Srst of the pixel voltage Vx of the pixel signal acquired during the reading of the signal level (P phase) and the AD conversion. Starting from Drst (which is a negative value here), the counter unit 254 is set to the upcount mode opposite to the reset level (P phase), and the reference signal RAMP and signal level Ssig by the voltage comparison unit 252 are set. The comparison process with the above and the count process by the counter circuit 254d provided in the counter unit 254 are operated in parallel. In this way, the AD conversion process for the first signal level (D phase) is executed. As a result, the counter unit 254 that has completed the AD conversion process of the first signal level (D phase) holds a count value indicating "-Drst + Dsig" (= -2. Drst + (Dsig + Drst)).

Subsequently, during the AD conversion process for the second signal level (D phase), the reference signal RAMP by the voltage comparison unit 252 is set in the same upcount mode as the first time, starting from the first count result (-Drst + Dsig). The comparison process with the signal level Ssig and the count process by the counter circuit 254a provided in the counter unit 254 are operated in parallel. In this way, the AD conversion process for the second signal level (D phase) is executed. As a result, the counter unit 254 after the second processing holds a count value indicating "2. Dsig" (= −Drst + Dsig + (Dsig + Drst)).

As described above, in the present embodiment, the reference signal comparison type AD conversion process is executed in the continuous down count mode N times (once in this example) for the reset level (P phase), and the AD conversion process is performed. The digital integration process is executed by bit-shifting the result. Subsequently, the result of the digital integration processing is used as the start value of the counter circuit 254d, and the reference signal comparison type AD conversion processing in the continuous upcount mode M times (twice in this example) with respect to the signal level (D phase) is performed. Run. By doing so, the addition operation processing of N times data (negative value when the sign is added) for the reset level (P phase) and M times data for the D phase is performed. Thereby, in the present embodiment, the number of executions of the AD conversion process for the reset level (P phase) can be reduced as compared with the AD conversion process for the signal level (D phase). As a result, the entire execution period of the AD conversion process in the solid-state image sensor 1 can be shortened. Further, the CDS processing of the same reset level Srst and signal level Sig can be performed, and the operation of adding can be performed.

The added data M · Dsig obtained by this multiple addition AD conversion process is sent to the output circuit 28 by horizontal transfer. The output circuit 28 acquires the added and averaged data Dsig by dividing the added data by the number of executions M of the AD conversion process with respect to the signal level (D phase) by the digital signal processing. The signal component is M times, but the random noise is √M times. Therefore, the noise characteristic (S / N) can be improved.

As described above, the solid-state image sensor as a semiconductor device according to the present embodiment has the same effect as the solid-state image sensor 1 as a semiconductor device according to the first embodiment.

[Third Embodiment]
The semiconductor device according to the third embodiment of the present disclosure will be described with reference to FIGS. 11 and 12. The solid-state image sensor as a semiconductor device according to the present embodiment is characterized in that the frequency of the count clock signal input to the counter unit can be changed. The schematic configuration of the solid-state image sensor according to the present embodiment is the same as the schematic configuration of the solid-state image sensor 1 according to the first embodiment. Therefore, the components having the same functions and functions as the components of the solid-state image sensor 1 according to the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 11, in the solid-state imaging device as a semiconductor device according to the present embodiment, one of a plurality of clock signals CCLK1 and clock signals CCLK2 having different frequencies (two in the present embodiment) is counter unit 254. A clock signal selection unit 22 for selecting as the count clock signal CK0 supplied to the device is provided.

The clock signal CCLK1 and the clock signal CCLK2 input to the clock signal selection unit 22 are supplied from the communication / timing control unit 20. The clock signal selection unit 22 is controlled by the second control unit 202 provided in the communication / timing control unit 20 to select one of the clock signal CCLK1 and the clock signal CCLK2. Here, the number of AD conversion processes executed for the reset level (P phase) is N (N is a natural number), and the number of AD conversion processes executed for the signal level (D phase) is M (M). Is a natural number different from N). In this case, the clock signal selection unit 22 is controlled by the second control unit 202 to supply the count clock signal CK0 for the period during which the AD conversion process for the reset level (P phase) is performed, and the AD for the signal level (D phase). The clock signal supplied from the communication / timing control unit 20 is selected so that the frequency relationship with the count clock signal CK0 supplied during the conversion process is M / N times.

For example, the number of AD conversion processes N executed for the reset level (P phase) is "1", and the number of AD conversion processes M executed for the signal level (D phase) is "3". Suppose there is. In this case, the AD conversion process executed for the reset level (P phase) is performed on the frequency of the count clock signal CK0 supplied during the period of performing the AD conversion process executed for the signal level (D phase). The frequency of the count clock signal CK0 supplied during the period is tripled. As a result, the result of the AD conversion process executed for the signal level (D phase) can be tripled.

<Operation of solid-state image sensor>
The operation of the solid-state image sensor as a semiconductor device according to the present embodiment will be described with reference to FIG. In FIG. 12, the number of AD conversion processes executed for the reset level (P phase) is 1 (N = 1), and the number of AD conversion processes executed for the signal level (D phase) is 2. It is a timing chart for explaining the multiple addition AD conversion and the digital CDS in the solid-state image sensor when the number of times (M = 2) is set. “Slope” in FIG. 12 indicates a reference signal RAMP, “Signal” in FIG. 12 indicates a pixel signal output from the vertical signal line 19 (see FIG. 1), and “CK0” in FIG. 12 is a count clock. The signal CK0 is shown, and the “counter output” in FIG. 12 indicates the output signal (signal output to the latch circuit 254c) of the counter circuit 254d (see FIG. 2) of the counter unit 254.

As shown in FIG. 12, first, at the time of AD processing for the reset level (P phase), the count value of the D flip-flop circuits DFF0 to DFFn-1 (not shown) provided in the counter unit 254 becomes the initial value "0". It will be reset. Next, the counter unit 254 is set to the down count mode, and the comparison process between the reference signal RAMP and the reset level Srst by the voltage comparison unit 252 (see FIG. 8) and the count process by the counter unit 254 are operated in parallel. In the period of AD conversion processing for the reset level (P phase), the clock signal CCLK1 having a frequency twice as high as the frequency of the count clock signal CK0 in the period of AD conversion processing for the signal level (D phase) is used as the count clock signal CK0. It is selected by the clock signal selection unit 22. As a result, the counter circuit 254d provided in the counter unit 254 after the first processing shows a digital value of 2 · Drst corresponding to the magnitude of the reset level Srst (-2 · Drst if a code is added). (Indicated) The count value is retained.

Subsequently, during the AD conversion process for the first signal level (D phase), the digital value 2 corresponding to the reset level Srst of the pixel voltage Vx of the pixel signal acquired during the reading of the signal level (P phase) and the AD conversion. Starting from Drst (which is a negative value here), the counter unit 254 is set to the upcount mode opposite to the reset level (P phase), and the reference signal RAMP and signal level Ssig by the voltage comparison unit 252 are set. The comparison process with the above and the count process by the counter circuit 254d provided in the counter unit 254 are operated in parallel. The frequency of the count clock signal CK0 used in the AD conversion process for the first signal level (D phase) is 1/2 of the frequency of the count clock signal CK0 used in the AD conversion process for the reset level (P phase). be. Therefore, the counter unit 254 after the AD conversion process of the first signal level (D phase) holds a count value indicating "-Drst + Dsig" (= -2. Drst + (Dsig + Drst)).

Subsequently, during the AD conversion process for the second signal level (D phase), the reference signal RAMP by the voltage comparison unit 252 is set in the same upcount mode as the first time, starting from the first count result (-Drst + Dsig). The comparison process with the signal level Ssig and the count process by the counter circuit 254a provided in the counter unit 254 are operated in parallel. The frequency of the count clock signal CK0 used in the AD conversion process for the second signal level (D phase) is 1/2 of the frequency of the count clock signal CK0 used in the AD conversion process for the reset level (P phase). be. Therefore, the counter unit 254 after the second processing holds a count value indicating "2. Dsig" (= −Drst + Dsig + (Dsig + Drst)).

As described above, in the present embodiment, the reset level (P phase) is changed by changing the frequency of the count clock signal CK0 used in each of the AD conversion process for the reset level (P phase) and the AD conversion process for the signal level (D phase). The addition operation processing of N times data (negative value when the code is added) for N times (phase) and M times data for signal level (D phase) is performed. Thereby, in the present embodiment, the number of executions of the AD conversion process for the reset level (P phase) can be reduced as compared with the AD conversion process for the signal level (D phase). As a result, the entire execution period of the AD conversion process in the solid-state image sensor can be shortened. Further, the CDS processing of the same reset level Srst and signal level Sig can be performed, and the operation of adding can be performed.

The added data M · Dsig obtained by this multiple addition AD conversion process is sent to the output circuit 28 by horizontal transfer. The output circuit 28 acquires the added and averaged data Dsig by dividing the added data by the number of executions M of the AD conversion process with respect to the signal level (D phase) by the digital signal processing. The signal component is M times, but the random noise is √M times. Therefore, the noise characteristic (S / N) can be improved.

As described above, the solid-state image sensor as a semiconductor device according to the present embodiment has the same effect as the solid-state image sensor 1 as a semiconductor device according to the first embodiment.

[Fourth Embodiment]
The semiconductor device according to the fourth embodiment of the present disclosure will be described with reference to FIG. The solid-state image sensor as a semiconductor device according to the present embodiment is characterized in that it includes an amplifier that amplifies a pixel signal with respect to a reset level. The schematic configuration of the solid-state image sensor according to the present embodiment is the same as that of the solid-state image sensor 1 according to the first embodiment, except that the solid-state image sensor 1 has a configuration capable of amplifying the pixel signal level with respect to the reset level. Therefore, the components having the same functions and functions as the components of the solid-state image sensor 1 according to the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 13, the solid-state image sensor as a semiconductor device according to the present embodiment includes an amplifier 31 that amplifies and outputs a pixel signal level (an example of a signal level) with respect to a reset level. The amplifier 31 is arranged between the pixel signal output from the vertical signal line 19 and one input terminal of the voltage comparison unit 252. The amplifier 31 is arranged in a one-to-one relationship with the vertical signal line 19.

The solid-state image sensor according to the present embodiment has a switch SWa arranged between the amplifier 31 and one input terminal of the voltage comparison unit 252. Further, the column processing unit 26 has a wiring Lr into which a reset level signal is input, and a switch SWr arranged between the wiring Lr and one input terminal of the voltage comparison unit 252.

The reset level signal is input to the voltage comparison unit 252 from a path different from the pixel signal. Further, the switch SWr and the switch SWa are controlled so that the switch SWa is in the off state when the switch SWr is on, and the switch SWa is in the on state when the switch SWr is in the off state. As a result, the solid-state image sensor according to the present embodiment can output the pixel signal to the column processing unit 26, although it is amplified with respect to the reset level signal in the AD conversion process for the signal level (D phase).

The signal level of the pixel signal supplied in the AD conversion process for the signal level (D phase) is amplified. Therefore, the pixel signal contributes more to the S / N ratio than the reset level signal supplied in the AD conversion process for the reset level (P phase). When the amplification factor of the amplifier 31 is sufficiently large, the contribution of the reset level to the S / N ratio can be almost ignored with respect to the result of the AD conversion process. That is, the effect of the AD conversion process on the reset level (P phase) becomes weak, and the multiplexing effect in the AD conversion process on the signal level (D phase) becomes dominant with respect to the S / N ratio. For example, the number of AD conversion processes for the reset level (P phase) is set to 1 (N = 1), and the number of AD conversion processes for the signal level (D phase) is set to 3 times (M = 3). That is, by making the number of AD conversion processes for the signal level (D phase) having a large contribution to the S / N ratio larger than the number of AD conversion processes for the reset level (P phase) having a small contribution to the S / N ratio. , The increase in the execution period of the AD conversion process can be suppressed while effectively improving the S / N ratio.

Since the operation of the solid-state image sensor 1 according to the present embodiment is the same as the operation of the solid-state image sensor 1 according to the first embodiment except that the signal level of the pixel signal is different, the description thereof will be omitted.

As described above, the solid-state image sensor as a semiconductor device according to the present embodiment has the same effect as the solid-state image sensor 1 as a semiconductor device according to the first embodiment.

[Fifth Embodiment]
The semiconductor device according to the fifth embodiment of the present disclosure will be described with reference to FIG. In the present embodiment, as a semiconductor device, a microelectrode array device that amplifies and reads out the electrode output with a differential amplifier will be described as an example.

FIG. 14 is a block diagram showing a schematic configuration of the microelectrode array device 50 as a semiconductor device according to the present embodiment.
As shown in FIG. 14, the microelectrode array device 50 has a read cell area 51 in which a plurality of read cells are arranged in a matrix, and a reference cell area 52 in which a plurality of reference cells are arranged. The read cell area 51 is an area in which circuit elements constituting one of the input transistors of the differential amplifier are arranged. The read cell region 51 is, for example, a region in which a living cell is cultured directly above and the action potential thereof is acquired. The reference cell region 102 is a region in which circuit elements constituting the other input transistor of the differential amplifier are arranged. Here, the leftmost row of the plurality of read cell areas 51 and the plurality of reference cell areas 52 will be described with reference to.

As shown in FIG. 14, two read cells 511, 512 are arranged in the leftmost row of the read cell area 51, and one reference cell 521 is arranged in the leftmost row of the reference cell area 52. .. The reference cell 521 is shared by the read cell 511 and the read cell 512. Therefore, the input transistor Tr of the read cell 511 constitutes one of the differential amplifiers, and the input transistor Tr of the reference cell 521 constitutes the other of the differential amplifiers. Further, the input transistor Tr of the read cell 512 constitutes one of the differential amplifiers, and the input transistor Tr of the reference cell 521 constitutes the other of the differential amplifiers.

The differential amplifier composed of the input transistor Tr of the read cell 511 and the input transistor Tr of the reference cell 521 has a voltage Vx of the difference in potential detected by each of the input transistor Tr of the read cell 511 and the input transistor Tr of the reference cell 521. Is configured to be output to the vertical signal line 53. Similarly, the differential amplifier composed of the input transistor Tr of the read cell 512 and the input transistor Tr of the reference cell 521 has a potential difference detected by each of the input transistor Tr of the read cell 512 and the input transistor Tr of the reference cell 521. The voltage Vx of the above is output to the vertical signal line 53.

A drive control unit 54 similar to the drive control unit 9 provided in the solid-state image sensor as a semiconductor device according to the fourth embodiment is connected to the end of the vertical signal line 53. Although detailed description will be omitted, the drive control unit 54 can operate in the same manner as the drive control unit 9.

The signal supplied to the vertical signal line 53 is a differential amplifier composed of the input transistor Tr of the read cell 511 and the input transistor Tr of the reference cell 521, or the input transistor Tr of the read cell 512 and the input transistor Tr of the reference cell 521. It is amplified by the differential amplifier that is configured. Further, in the present embodiment, the signal amplified by these differential amplifiers and the reset level signal are switched by the two switch SWs and input to the voltage comparison unit 55 via different paths.

Therefore, the signal output from the vertical signal line 53 contributes more to the S / N ratio than the reset level signal supplied in the AD conversion process for the reset level (P phase). When the amplification factor of the differential amplifier is sufficiently large, the contribution of the reset level to the S / N ratio can be almost ignored with respect to the result of the AD conversion process. That is, the effect of the AD conversion process on the reset level (P phase) becomes weak, and the multiplexing effect in the AD conversion process on the signal level (D phase) becomes dominant with respect to the S / N ratio. For example, the number of AD conversion processes for the reset level (P phase) is set to 1 (N = 1), and the number of AD conversion processes for the signal level (D phase) is set to 3 times (M = 3). That is, by making the number of AD conversion processes for the signal level (D phase) having a large contribution to the S / N ratio larger than the number of AD conversion processes for the reset level (P phase) having a small contribution to the S / N ratio. , The increase in the execution period of the AD conversion process can be suppressed while effectively improving the S / N ratio.

As described above, the microelectrode array device 50 according to the present embodiment includes an amplifier composed of the input transistor Tr of the read cell 511 and the input transistor Tr of the reference cell 521, which amplifies and outputs the signal level with respect to the reset level. ing. Further, the microelectrode array device 50 is composed of an input transistor Tr of the read cell 512 and an input transistor Tr of the reference cell 521, and includes an amplifier that amplifies and outputs the signal level with respect to the reset level. The amplifier is composed of a differential amplifier.

As described above, the microelectrode array device 50 as a semiconductor device according to the present embodiment can suppress a decrease in conversion speed in analog-to-digital conversion processing and can reduce noise.

The present disclosure is not limited to the above embodiment, and various modifications can be made.
In the first to fifth embodiments, the number of AD conversion processes for each of the reset level (P phase) and the signal level (D phase) is fixed, but the present disclosure is not limited to this. For example, the semiconductor device may be configured so that at least one of the number of AD conversion processes for the reset level (P phase) and the number of AD conversion processes for the signal level (D phase) can be changed. For example, when the frame rate for detecting data from the pixel portion or the read cell area becomes higher than usual, the number of times may be decreased, and in the case of a normal frame rate, the number of times may be increased. For example, it may be configured so that the user of the semiconductor device can appropriately change the number of times.

The technique according to the present disclosure can be applied to the above-mentioned semiconductor devices.

The embodiments of the present disclosure are not limited to the above-described embodiments, and various changes can be made without departing from the gist of the present disclosure. Further, the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.

For example, the present disclosure may have the following structure.

(1)
Based on the comparison result of the comparison unit that compares the reference signal supplied from the reference signal generation unit and whose level gradually changes with the analog processing target signal, and the comparison unit that receives the supply of the count clock signal for analog-digital conversion. An analog-digital conversion unit that has a counter unit that performs a counting operation and acquires digital data of the signal to be processed based on the output data of the counter unit.
For the first control unit that controls the number of times the analog-to-digital conversion process for the signal to be processed is executed for the reset level and the number of times for the signal level to be executed differently, and for the result of the analog-digital conversion process. A semiconductor device including a control unit having a second control unit that controls the analog-to-digital conversion unit so as to execute a digital integration process.
(2)
The number of analog-to-digital conversion processes executed for the reset level is N (N is a natural number), and the number of analog-to-digital conversion processes executed for the signal level is M (M is a natural number different from N). ) Then
The analog-to-digital conversion unit performs a first operation for multiplying the result of the analog-digital conversion process at the reset level by M / N, or a second operation for multiplying the result of the signal level analog-digital conversion process by N / M. It has a digital arithmetic unit to execute
The semiconductor according to (1) above, wherein the digital arithmetic unit executes the first operation when M is smaller than N, and executes the second operation when M is larger than N. device.
(3)
The analog-to-digital conversion unit is configured to convert the analog signal to be processed into an n-bit digital signal.
The semiconductor device according to (1) above, wherein the counter unit has a bit shift circuit for bit-shifting the count result.
(4)
The item according to any one of (1) to (3) above, which includes a clock signal selection unit that selects one of a plurality of clock signals having different frequencies as a count clock signal supplied to the counter unit. Semiconductor device.
(5)
The semiconductor device according to any one of (1) to (4) above, comprising an amplifier that amplifies and outputs the signal level with respect to the reset level.
(6)
The semiconductor device according to (5) above, wherein the amplifier is composed of a differential amplifier.

1 Solid-state image sensor 3 Unit pixel 5 pixel Signal generation unit 5a, 5b Terminal 5c Output terminal 7, 9 Drive control unit 10 Pixel unit 10a Effective image area (effective unit)
12 Horizontal scanning circuit (row scanning circuit)
12a Horizontal decoder 12b Horizontal drive circuit 12c Control line 14 Vertical scanning circuit (row scanning circuit)
14a Vertical decoder 14b Vertical drive circuit 15 lines Control line 18 Horizontal signal line (horizontal output line)
19 Vertical signal line 20 Communication / timing control unit 22 Clock signal selection unit 23 Clock conversion unit 25 Column AD circuit 26 Column processing unit 27 Reference signal generation unit 27a DA conversion circuit 27b DA conversion circuit 28 Output circuit 31 Amplifier 32 Charge generation unit 51 Read cell area 52 Reference cell area 53 Vertical signal line 54 Drive control unit 55 Voltage comparison unit 102 Reference cell area 201 First control unit 202 Second control unit 252 Voltage comparison unit 252a Signal line 252b Signal line 254 Counter unit 254a, 254d Counter Circuit 254b Integration circuit 254c Latch circuit 511 and 512 Read cell 521 Reference cell

Claims (6)

Based on the comparison result of the comparison unit that compares the reference signal supplied from the reference signal generation unit and whose level gradually changes with the analog processing target signal, and the comparison unit that receives the supply of the count clock signal for analog-digital conversion. An analog-digital conversion unit that has a counter unit that performs a counting operation and acquires digital data of the signal to be processed based on the output data of the counter unit.
For the first control unit that controls the number of times the analog-to-digital conversion process for the signal to be processed is executed for the reset level and the number of times for the signal level to be executed differently, and for the result of the analog-digital conversion process. A semiconductor device including a control unit having a second control unit that controls the analog-to-digital conversion unit so as to execute a digital integration process. The number of analog-to-digital conversion processes executed for the reset level is N (N is a natural number), and the number of analog-to-digital conversion processes executed for the signal level is M (M is a natural number different from N). ) Then
The analog-to-digital conversion unit performs a first operation for multiplying the result of the analog-digital conversion process at the reset level by M / N, or a second operation for multiplying the result of the signal level analog-digital conversion process by N / M. It has a digital arithmetic unit to execute
The semiconductor device according to claim 1, wherein the digital arithmetic unit executes the first operation when the M is smaller than N, and executes the second operation when the M is larger than N. .. The analog-to-digital conversion unit is configured to convert the analog signal to be processed into an n-bit digital signal.
The semiconductor device according to claim 1, wherein the counter unit has a bit shift circuit for bit-shifting the count result. The semiconductor device according to claim 1, further comprising a clock signal selection unit that selects one of a plurality of clock signals having different frequencies as a count clock signal supplied to the counter unit. The semiconductor device according to claim 1, further comprising an amplifier that amplifies and outputs the signal level with respect to the reset level. The semiconductor device according to claim 5, wherein the amplifier is composed of a differential amplifier.

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