JP2021163813A - Substrate tray - Google Patents

Substrate tray Download PDF

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JP2021163813A
JP2021163813A JP2020062216A JP2020062216A JP2021163813A JP 2021163813 A JP2021163813 A JP 2021163813A JP 2020062216 A JP2020062216 A JP 2020062216A JP 2020062216 A JP2020062216 A JP 2020062216A JP 2021163813 A JP2021163813 A JP 2021163813A
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pocket
substrate
semiconductor substrate
sides
square
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訓太 吉河
Kunita Yoshikawa
暢 入江
Noboru Irie
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Kaneka Corp
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Kaneka Corp
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Priority to JP2020062216A priority Critical patent/JP2021163813A/en
Priority to CN202110325079.5A priority patent/CN113463055B/en
Publication of JP2021163813A publication Critical patent/JP2021163813A/en
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/50—Substrate holders
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4581—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber characterised by material of construction or surface finish of the means for supporting the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/67333—Trays for chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/67346—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders characterized by being specially adapted for supporting a single substrate or by comprising a stack of such individual supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

To provide a substrate tray capable of making a film production gas less likely to go around to the back of a semiconductor substrate at film production due to warpage of the semiconductor substrate.SOLUTION: A substrate tray 1 for holding a square or semi-square substrate W has a pocket 10 composed of a square recess for accommodating the substrate W. A bottom of the pocket 10 has a peripheral bottom part 31 and a central bottom part 33 in order from sides of four side walls 20 of the pocket 10 toward the inside of the pocket 10. The peripheral bottom part 31 is configured to be shallower than the central bottom part 33 to support a rear face of the substrate W at four sides of the substrate, and is curved so as to be gradually shallower from each center between corners of the pocket 10 toward the corners in directions along the side walls 20 of the pocket 10.SELECTED DRAWING: Figure 2

Description

本発明は、基板トレイに関する。 The present invention relates to a substrate tray.

例えば太陽電池セルの製造工程、特にＣＶＤ（Chemical Vapor Deposition：化学気相堆積）法またはＰＶＤ（Physical Vapor Deposition：物理気相堆積）法等を用いた半導体層またはＴＣＯ（Transparent Conductive Oxide）層等の製膜工程において、スクエア（四角）形状またはセミスクエア（四角形状の四隅をカットした八角）形状の半導体基板（半導体ウェハ）をホールドする基板トレイが用いられる。このような基板トレイとして、特許文献１にはポケットタイプの基板トレイが開示されており、特許文献２にはピンタイプの基板トレイが開示されている。 For example, a semiconductor layer or a TCO (Transparent Conductive Oxide) layer using a solar cell manufacturing process, particularly a CVD (Chemical Vapor Deposition) method or a PVD (Physical Vapor Deposition) method. In the film forming process, a substrate tray for holding a square (square) -shaped or semi-square (octagonal cut corners) -shaped semiconductor substrate (semiconductor wafer) is used. As such a substrate tray, Patent Document 1 discloses a pocket type substrate tray, and Patent Document 2 discloses a pin type substrate tray.

特開２０１６−１９２４５３号公報Japanese Unexamined Patent Publication No. 2016-192453 特開２０１４−１１８６３１号公報Japanese Unexamined Patent Publication No. 2014-118631

ピンタイプの基板トレイでは、半導体基板の角以外にピンを設けることにより半導体基板をホールドするため、いわゆる製膜時の製膜ガスの裏回り（半導体基板の製膜面と反対側の裏側に製膜ガスが回り込み、半導体基板の裏側も製膜されること）の抑制効果が低い。 In the pin type substrate tray, since the semiconductor substrate is held by providing pins other than the corners of the semiconductor substrate, it is manufactured on the back side of the film-forming gas during so-called film-forming (on the back side opposite to the film-forming surface of the semiconductor substrate). The film gas wraps around and the back side of the semiconductor substrate is also formed), which has a low suppressing effect.

一方、ポケットタイプの基板トレイでは、スクエア形状の窪みからなるポケットに半導体基板が収容されるため、製膜時の製膜ガスの裏回りの抑制効果が高い。しかし、ポケットタイプの基板トレイでも、自重により半導体基板が反ってしまうことにより、製膜時の製膜ガスの裏回りが増加してしまうことがある。 On the other hand, in the pocket type substrate tray, since the semiconductor substrate is housed in the pocket formed of the square-shaped recess, the effect of suppressing the backside of the film-forming gas at the time of film-forming is high. However, even in a pocket-type substrate tray, the backing of the film-forming gas at the time of film-forming may increase due to the warp of the semiconductor substrate due to its own weight.

本発明は、ポケットタイプの基板トレイにおいて、半導体基板の反りに起因する製膜時の製膜ガスの裏回りを低減する基板トレイを提供することを目的とする。 An object of the present invention is to provide a pocket-type substrate tray that reduces the backing of the film-forming gas during film-forming due to the warp of the semiconductor substrate.

本発明に係る基板トレイは、スクエア形状またはセミスクエア形状の基板をホールドする基板トレイであって、前記基板を収容するスクエア形状の窪みで構成されるポケットを有する。前記ポケットの底は、前記ポケットの４つの側壁側から前記ポケットの内側に向けて順に周底部と中央底部とを有する。前記周底部は、前記中央底部よりも浅く、前記基板の４つの辺部の裏面を支持し、前記ポケットの前記側壁に沿う方向に、前記ポケットのコーナー間の中央から前記コーナーに向けて次第に浅くなるように湾曲している。 The substrate tray according to the present invention is a substrate tray for holding a square-shaped or semi-square-shaped substrate, and has a pocket formed of a square-shaped recess for accommodating the substrate. The bottom of the pocket has a peripheral bottom portion and a central bottom portion in this order from the four side wall sides of the pocket toward the inside of the pocket. The peripheral bottom portion is shallower than the central bottom portion, supports the back surfaces of the four side portions of the substrate, and gradually becomes shallower from the center between the corners of the pocket toward the corner in the direction along the side wall of the pocket. It is curved so that it becomes.

本発明によれば、ポケットタイプの基板トレイにおいて、半導体基板の反りに起因する製膜時の製膜ガスの裏回りを低減することができる。 According to the present invention, in a pocket-type substrate tray, it is possible to reduce the backing of the film-forming gas during film-forming due to the warp of the semiconductor substrate.

本実施形態に係る基板トレイを示す平面図である。It is a top view which shows the substrate tray which concerns on this embodiment. 図１に示す基板トレイにおけるII部分（ポケット）を拡大して示す平面図である。FIG. 5 is an enlarged plan view showing a portion II (pocket) of the substrate tray shown in FIG. 1. 図２に示す基板トレイのポケットの一例の斜視図である。It is a perspective view of an example of the pocket of the substrate tray shown in FIG. 図２に示す基板トレイのポケットの一例におけるIVA-IVA線端面（半分）、IVB-IVB線端面（半分）、IVC-IVC線端面（半分）、IVD-IVD線端面（半分）、IVE-IVE線端面（半分）、およびIVF-IVF線端面（半分）を重ねて示す図である。IVA-IVA wire end face (half), IVB-IVB wire end face (half), IVC-IVC wire end face (half), IVD-IVD wire end face (half), IVE-IVE in an example of the substrate tray pocket shown in FIG. It is a figure which shows the line end face (half) and IVF-IVF line end face (half) overlapped. 半導体基板の一例の反り（撓み）特性のシミュレーション結果である。It is a simulation result of the warp (deflection) characteristic of an example of a semiconductor substrate. 半導体基板の辺部における支持位置による、半導体基板の一例の辺部の反り（撓み）特性のシミュレーション結果である。This is a simulation result of the warp (deflection) characteristic of the side portion of an example of the semiconductor substrate depending on the support position on the side portion of the semiconductor substrate. 図６における半導体基板の辺部の支持位置を示す図である。It is a figure which shows the support position of the side part of the semiconductor substrate in FIG.

以下、添付の図面を参照して本発明の実施形態の一例について説明する。なお、各図面において同一または相当の部分に対しては同一の符号を附すこととする。また、便宜上、ハッチングや部材符号等を省略する場合もあるが、かかる場合、他の図面を参照するものとする。 Hereinafter, an example of the embodiment of the present invention will be described with reference to the accompanying drawings. In addition, the same reference numerals are given to the same or corresponding parts in each drawing. In addition, for convenience, hatching, member codes, and the like may be omitted, but in such cases, other drawings shall be referred to.

図１は、本実施形態に係る基板トレイを示す平面図である。図１に示す基板トレイ１は、例えば太陽電池セルの製造工程、特にＣＶＤ法またはＰＶＤ法等を用いた半導体層またはＴＣＯ層等の製膜工程において、スクエア形状またはセミスクエア形状の半導体基板（半導体ウェハ）をホールドする基板トレイである。基板トレイ１の材料としては、特に限定されないが、例えばアルミニウムが挙げられる。基板トレイ１は、半導体基板を収容するスクエア形状の窪みで構成される複数のポケット１０を有する。複数のポケット１０は、例えば２次元状に配列されている。 FIG. 1 is a plan view showing a substrate tray according to the present embodiment. The substrate tray 1 shown in FIG. 1 is a square-shaped or semi-square-shaped semiconductor substrate (semiconductor) in, for example, in a solar cell manufacturing process, particularly in a film forming process such as a semiconductor layer or a TCO layer using a CVD method or a PVD method. A substrate tray for holding a wafer). The material of the substrate tray 1 is not particularly limited, and examples thereof include aluminum. The substrate tray 1 has a plurality of pockets 10 formed of square-shaped recesses for accommodating semiconductor substrates. The plurality of pockets 10 are arranged in a two-dimensional manner, for example.

図２は、図１に示す基板トレイにおけるポケット（II部分）を拡大して示す平面図である。図３は、図２に示す基板トレイのポケットの一例の斜視図であり、図４は、図２に示す基板トレイのポケットの一例におけるIVA-IVA線端面（半分）、IVB-IVB線端面（半分）、IVC-IVC線端面（半分）、IVD-IVD線端面（半分）、IVE-IVE線端面（半分）、およびIVF-IVF線端面（半分）を重ねて示す図である。 FIG. 2 is an enlarged plan view showing a pocket (II portion) in the substrate tray shown in FIG. FIG. 3 is a perspective view of an example of the substrate tray pocket shown in FIG. 2, and FIG. 4 shows an IVA-IVA line end face (half) and an IVB-IVB line end surface (half) of the substrate tray pocket example shown in FIG. It is the figure which shows the IVC-IVC line end face (half), IVD-IVD line end face (half), IVE-IVE line end face (half), and IVF-IVF line end face (half) overlapped.

図２〜図４に示すように、ポケット１０は、４つの側壁２０を有する。ポケット１０の底は、４つの側壁２０からポケット１０の内側に向けて順に周底部３１と中央底部３３とを有する。ポケット１０の底と反対側には、半導体基板Ｗを収容または取り出すための開口を有する。 As shown in FIGS. 2 to 4, the pocket 10 has four side walls 20. The bottom of the pocket 10 has a peripheral bottom portion 31 and a central bottom portion 33 in this order from the four side walls 20 toward the inside of the pocket 10. On the side opposite to the bottom of the pocket 10, there is an opening for accommodating or taking out the semiconductor substrate W.

周底部３１は、中央底部３３よりも浅く、半導体基板Ｗの周縁部、すなわち４つの辺部、の裏面を支持する。周底部３１は、４つの側壁２０からポケット１０の内側に向けて次第に深くなるように傾斜している。 The peripheral bottom portion 31 is shallower than the central bottom portion 33 and supports the back surface of the peripheral edge portion of the semiconductor substrate W, that is, the four side portions. The peripheral bottom portion 31 is inclined so as to gradually become deeper from the four side walls 20 toward the inside of the pocket 10.

ここで、図５に、半導体基板Ｗの一例（６インチ×１７０μｍ（厚さ））の反り（撓み）特性のシミュレーション結果を示す。図５に示すように、半導体基板Ｗは、自重により３次元的に反る（撓む）ことがある。図５では、半導体基板Ｗの辺部の中央部が１５０μｍ〜１７５μｍの範囲に位置するのに対して、半導体基板Ｗの角部は２００μｍ〜２２５μｍの範囲に位置する。本願発明者（ら）の知見によれば、例えば６インチ×１７０μｍ（厚さ）の半導体基板Ｗでは、半導体基板Ｗの辺部の中央部に対して、半導体基板Ｗの角部は４０μｍ〜７０μｍほど反る（撓む）ことがある。 Here, FIG. 5 shows a simulation result of the warp (deflection) characteristic of an example (6 inches × 170 μm (thickness)) of the semiconductor substrate W. As shown in FIG. 5, the semiconductor substrate W may warp (bend) three-dimensionally due to its own weight. In FIG. 5, the central portion of the side portion of the semiconductor substrate W is located in the range of 150 μm to 175 μm, whereas the corner portion of the semiconductor substrate W is located in the range of 200 μm to 225 μm. According to the findings of the inventors of the present application, for example, in a semiconductor substrate W of 6 inches × 170 μm (thickness), the corner portion of the semiconductor substrate W is 40 μm to 70 μm with respect to the central portion of the side portion of the semiconductor substrate W. It may warp (bend).

これに対して、基板トレイのポケットの周底部の側壁に沿う方向の高さが均一であると、半導体基板Ｗの辺部の中央部が支持され、半導体基板Ｗの角部が浮いてしまう。すると、製膜時の製膜ガスの裏回りが発生してしまう。 On the other hand, if the height in the direction along the side wall of the peripheral bottom portion of the pocket of the substrate tray is uniform, the central portion of the side portion of the semiconductor substrate W is supported and the corner portion of the semiconductor substrate W floats. Then, the backside of the film-forming gas at the time of film-forming occurs.

この点に関し、本実施形態では、周底部３１を、半導体基板Ｗの反り（撓み）に追従した形状とする。具体的には、図３および図４に示すように、周底部３１は、側壁２０に沿う方向に、ポケット１０のコーナー間の中央からコーナーに向けて次第に浅くなるように湾曲している。 Regarding this point, in the present embodiment, the peripheral bottom portion 31 has a shape that follows the warp (deflection) of the semiconductor substrate W. Specifically, as shown in FIGS. 3 and 4, the peripheral bottom portion 31 is curved in the direction along the side wall 20 so as to gradually become shallower from the center between the corners of the pocket 10 toward the corners.

換言すると、周底部３１の４つの側壁２０からポケット１０の内側へ向けた傾斜は、ポケット１０のコーナー間の中央からコーナーに向けて次第に急になっている。 In other words, the inclination of the four side walls 20 of the peripheral bottom portion 31 toward the inside of the pocket 10 gradually becomes steeper from the center between the corners of the pocket 10 toward the corner.

ここで、図６に、半導体基板Ｗの辺部における支持位置による、半導体基板Ｗの一例（６インチ×１７０μｍ（厚さ））の辺部の反り（撓み）特性のシミュレーション結果（４辺の平均値）を示す。図６に示すように、半導体基板Ｗの角部（図７のＧ）の裏面のみを支持するときに、半導体基板Ｗの４つの辺部の反り（撓み）が最大となり（曲線Ｇ）、半導体基板Ｗの４辺部の中央部（図７のＨ）の裏面のみを支持するときの半導体基板Ｗの４辺部の反り（撓み）が最小となる（曲線Ｈ）。 Here, FIG. 6 shows a simulation result (average of four sides) of the warp (deflection) characteristic of the side portion of an example (6 inches × 170 μm (thickness)) of the semiconductor substrate W depending on the support position on the side portion of the semiconductor substrate W. Value) is shown. As shown in FIG. 6, when only the back surface of the corner portion (G in FIG. 7) of the semiconductor substrate W is supported, the warp (deflection) of the four side portions of the semiconductor substrate W becomes maximum (curve G), and the semiconductor. When only the back surface of the central portion (H in FIG. 7) of the four side portions of the substrate W is supported, the warp (deflection) of the four side portions of the semiconductor substrate W is minimized (curve H).

この点に関し、本実施形態では、周底部３１の側壁２０に沿う方向の湾曲は、半導体基板Ｗの角部の裏面のみを支持するときの半導体基板Ｗの４つの辺部の反り（撓み）の湾曲よりも緩やかであり、半導体基板Ｗの４つの辺部の中央部の裏面のみを支持するときの半導体基板Ｗの４辺部の反り（撓み）の湾曲よりも急である。 In this regard, in the present embodiment, the curvature of the peripheral bottom portion 31 in the direction along the side wall 20 is the warp (deflection) of the four sides of the semiconductor substrate W when only the back surface of the corner portion of the semiconductor substrate W is supported. It is gentler than the curvature, and is steeper than the curvature of the warp (deflection) of the four sides of the semiconductor substrate W when only the back surface of the central portion of the four sides of the semiconductor substrate W is supported.

以上説明したように、本実施形態の基板トレイ１によれば、ポケット１０における、半導体基板Ｗの４つの辺部の裏面を支持する周底部３１は、ポケット１０の側壁２０に沿う方向に、ポケット１０のコーナー間の中央からコーナーに向けて次第に浅くなるように湾曲している。すなわち、ポケット１０の周底部３１は、ポケット１０の辺部の反り（撓み）に追従した形状である。これにより、半導体基板の反りに起因する、半導体基板Ｗの角部の浮きを低減することができ、製膜時の製膜ガスの裏回りを低減することができる。 As described above, according to the substrate tray 1 of the present embodiment, the peripheral bottom portion 31 of the pocket 10 that supports the back surfaces of the four sides of the semiconductor substrate W is pocketed in the direction along the side wall 20 of the pocket 10. It is curved so as to gradually become shallower from the center between the 10 corners toward the corners. That is, the peripheral bottom portion 31 of the pocket 10 has a shape that follows the warp (deflection) of the side portion of the pocket 10. As a result, it is possible to reduce the floating of the corners of the semiconductor substrate W due to the warp of the semiconductor substrate, and it is possible to reduce the backing of the film-forming gas during film-forming.

また、本実施形態の基板トレイ１によれば、ポケット１０の周底部３１の側壁２０に沿う方向の湾曲は、半導体基板Ｗの角部の裏面のみを支持するときの半導体基板Ｗの４つの辺部の反りの湾曲よりも緩やかであり、半導体基板Ｗの４辺部の中央部の裏面のみを支持するときの半導体基板Ｗの４つの辺部の反りの湾曲よりも急である。すなわち、周底部３１の側壁２０に沿う方向の湾曲は、図５に示す半導体基板Ｗの４つの辺部の反り（撓み）の最大と最小との間に設定される。これにより、半導体基板の反りに起因する、半導体基板Ｗの角部の浮きをより低減することができ、製膜時の製膜ガスの裏回りをより低減することができる。 Further, according to the substrate tray 1 of the present embodiment, the curvature of the peripheral bottom portion 31 of the pocket 10 in the direction along the side wall 20 is the four sides of the semiconductor substrate W when only the back surface of the corner portion of the semiconductor substrate W is supported. It is gentler than the curvature of the warp of the portion, and is steeper than the curvature of the warp of the four side portions of the semiconductor substrate W when supporting only the back surface of the central portion of the four side portions of the semiconductor substrate W. That is, the curvature of the peripheral bottom portion 31 in the direction along the side wall 20 is set between the maximum and minimum of the warp (deflection) of the four side portions of the semiconductor substrate W shown in FIG. As a result, the floating of the corners of the semiconductor substrate W due to the warp of the semiconductor substrate can be further reduced, and the backing of the film-forming gas at the time of film-forming can be further reduced.

また、本実施形態の基板トレイ１によれば、ポケット１０の周底部３１は、４つの側壁２０からポケット１０の内側に向けて深くなるように傾斜している。これにより、半導体基板Ｗの周縁部の裏面のみを支持することができ、半導体基板Ｗの周縁部以外の裏面がポケット１０の底に触れることが抑制され、太陽電池の性能低下を抑制することができる。 Further, according to the substrate tray 1 of the present embodiment, the peripheral bottom portion 31 of the pocket 10 is inclined so as to be deeper from the four side walls 20 toward the inside of the pocket 10. As a result, only the back surface of the peripheral edge portion of the semiconductor substrate W can be supported, the back surface other than the peripheral edge portion of the semiconductor substrate W is suppressed from touching the bottom of the pocket 10, and the deterioration of the performance of the solar cell can be suppressed. can.

また、中央底部３３を深くすることにより、半導体基板Ｗの反りが生じても、半導体基板Ｗの裏面がポケット１０の底に触れることが抑制される。 Further, by deepening the central bottom portion 33, even if the semiconductor substrate W is warped, the back surface of the semiconductor substrate W is prevented from touching the bottom of the pocket 10.

更に、周底部３１を次第に深くすることにより、半導体基板Ｗの周縁部の裏面側の空間を小さくできる。このように、半導体基板Ｗの周縁部の裏面側の空間が小さいと、製膜時の製膜ガスの裏回りが低減される。 Further, by gradually deepening the peripheral bottom portion 31, the space on the back surface side of the peripheral edge portion of the semiconductor substrate W can be reduced. As described above, when the space on the back surface side of the peripheral edge portion of the semiconductor substrate W is small, the backside of the film-forming gas at the time of film-forming is reduced.

以上、本発明の実施形態について説明したが、本発明は上述した実施形態に限定されることなく、種々の変更および変形が可能である。例えば、上述した実施形態では、太陽電池の製造工程、特にＣＶＤ法またはＰＶＤ法等を用いた半導体層またはＴＣＯ層等の製膜工程において用いられる基板トレイを例示した。しかし、本発明はこれに限定されず、スクエア形状またはセミスクエア形状の種々の基板をホールドする基板トレイに適用可能である。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and modifications can be made. For example, in the above-described embodiment, a substrate tray used in a solar cell manufacturing process, particularly a film forming process such as a semiconductor layer or a TCO layer using a CVD method or a PVD method, has been exemplified. However, the present invention is not limited to this, and is applicable to a substrate tray for holding various square-shaped or semi-square-shaped substrates.

１ 基板トレイ
１０ ポケット
２０ 側壁
３１ 周底部
３３ 中央底部 1 Board tray 10 Pocket 20 Side wall 31 Peripheral bottom 33 Central bottom

Claims (4)

スクエア形状またはセミスクエア形状の基板をホールドする基板トレイであって、
前記基板を収容するスクエア形状の窪みで構成されるポケットを有し、
前記ポケットの底は、前記ポケットの４つの側壁側から前記ポケットの内側に向けて順に周底部と中央底部とを有し、
前記周底部は、
前記中央底部よりも浅く、前記基板の４つの辺部の裏面を支持し、
前記ポケットの前記側壁に沿う方向に、前記ポケットのコーナー間の中央から前記コーナーに向けて次第に浅くなるように湾曲している、
基板トレイ。 A board tray that holds a square or semi-square board.
It has a pocket composed of a square-shaped recess for accommodating the substrate.
The bottom of the pocket has a peripheral bottom and a central bottom in this order from the four side wall sides of the pocket toward the inside of the pocket.
The peripheral bottom is
It is shallower than the central bottom and supports the back surfaces of the four sides of the substrate.
It is curved so as to gradually become shallower from the center between the corners of the pocket toward the corner in the direction along the side wall of the pocket.
Board tray. 前記周底部は、４つの前記側壁側から前記ポケットの内側に向けて次第に深くなるように傾斜している、請求項１に記載の基板トレイ。 The substrate tray according to claim 1, wherein the peripheral bottom portion is inclined so as to gradually become deeper from the four side wall sides toward the inside of the pocket. 前記周底部の４つの前記側壁側から前記ポケットの内側へ向けた傾斜は、前記ポケットのコーナー間の中央から前記コーナーに向けて次第に急になっている、請求項２に記載の基板トレイ。 The substrate tray according to claim 2, wherein the inclination of the four side walls of the peripheral bottom toward the inside of the pocket gradually becomes steeper from the center between the corners of the pocket toward the corner. 前記周底部の前記側壁に沿う方向の湾曲は、前記基板の角部の裏面のみを支持するときの前記基板の４つの辺部の反りの湾曲よりも緩やかであり、前記基板の４辺部の中央部の裏面のみを支持するときの前記基板の４つの辺部の反りの湾曲よりも急である、請求項１〜３のいずれか１項に記載の基板トレイ。 The curvature of the peripheral bottom portion in the direction along the side wall is gentler than the curvature of the warp of the four sides of the substrate when only the back surface of the corner portion of the substrate is supported, and the curvature of the four sides of the substrate is gentler. The substrate tray according to any one of claims 1 to 3, which is steeper than the curvature of the warp of the four sides of the substrate when only the back surface of the central portion is supported.
JP2020062216A 2020-03-31 2020-03-31 Substrate tray Pending JP2021163813A (en)

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