JP2021153262A - Filter device, transmission system and reception system - Google Patents

Abstract

To enable reducing, in a digital filter having delay blocks, a delay time between an input and an output, irrespective of the number of delay blocks.SOLUTION: A filter device includes: N delay blocks connected in series; (N+1) multiplication parts provided corresponding to the inputs and outputs of N delay blocks to multiply input data by a coefficient; an addition part which calculates the sum of the multiplication result by the (N+1) multiplication parts; and a data supply part which supplies data, included in an input data string, to the N delay blocks and the (N+1) multiplication parts. At first timing, the data supply part supplies the top data of the input data string from an input end to the (N+1)th multiplication part, and also supplies N data from the next data of the top data of the input data string to the (N+1)th data to corresponding N delay blocks and corresponding N multiplication parts, respectively. There are also provided a transmission system and a reception system.SELECTED DRAWING: Figure 2

Description

The present invention relates to a filter device, a transmitting system, and a receiving system.

There are known FIR (Finite Impulse Response) filters and the like that have delay blocks connected in series and sequentially input data from the beginning of an input data string from the beginning of the delay block. Further, a technique for switching the characteristics of such an FIR filter during operation is also known (see, for example, Patent Documents 1 and 2).

Japanese Unexamined Patent Publication No. 11-11289 Japanese Unexamined Patent Publication No. 2001-119270

It is generally known that the FIR filter generally has a frequency response closer to an ideal frequency response as the number of delay blocks called the number of taps is larger. On the other hand, the larger the number of taps, the larger the delay time between input and output because the result of filtering after passing through a plurality of delay blocks is output, which is a technical problem.

Therefore, the present invention has been made in view of these points, and an object of the present invention is to shorten the delay time between input and output in a digital filter having delay blocks regardless of the number of delay blocks. ..

In the first aspect of the present invention, N delay blocks (N is an integer of 2 or more) connected in series between the input end and the output end, and the input and output of the N delay blocks. Correspondingly provided, N + 1 multiplying parts for multiplying the input data by a coefficient, an adding part for calculating the sum of the multiplication results of N + 1 said multiplying parts, N said delay blocks and N + 1 pieces. The multiplication unit is provided with a data supply unit that supplies data included in the input data string, and the data supply unit supplies the head data of the input data string at the first timing to the input end at the first timing. The Nth data from the next data of the head data in the first timing of the input data string to the N + 1th data are supplied to the multiplication unit connected to the output of the Nth delay block. It is supplied to the N delay blocks and the corresponding N multiplication units connected to the input side of the N delay blocks, respectively, and from the input end at each processing timing after the first timing. Provided is a filter device that sequentially supplies N + 1th and subsequent data from the head data in the first timing to the first delay block and the multiplication unit connected to the input end.

The filter device supplies a coefficient supply unit that supplies N + 1 the coefficients corresponding to the N + 1 multiplication units, and a control signal based on the first timing that executes a filtering process on the input data string. And a control unit that supplies the coefficient supply unit, and the coefficient supply unit may supply N + 1 of the coefficients to the N + 1 multiplication unit according to the control signal.

The control unit supplies a control signal based on a second timing different from the first timing to the data supply unit and the coefficient supply unit, and at the second timing, the data supply unit receives the input data string. The head data at the second timing is supplied to the multiplication unit connected to the output of the delay block Nth from the input end, and from the data next to the head data at the second timing of the input data string. N data up to the N + 1th are supplied to the corresponding N delay blocks and the corresponding N multiplication units connected to the input side of the N delay blocks, respectively, and the coefficient is supplied. The unit may supply N + 1 of the coefficients having a value different from the N + 1 of the coefficients supplied in response to the control signal based on the first timing to the N + 1 multiplication units.

When supplying L coefficients (L is an integer of 2 or more and N or less) to the N + 1 multiplication units, the coefficient supply unit corresponds to the L multiplication units closer to the output end. The L coefficients may be supplied, and the remaining N + 1-L multiplication units may be supplied with the coefficients having a value of 0.

In the second aspect of the present invention, a transmitter for transmitting a signal having a predetermined frequency and the filter device according to the first aspect are provided, and the filter device is used for signal data transmitted by the transmitter. On the other hand, a transmission system that executes the filtering process from the first timing is provided.

In the third aspect of the present invention, a receiver for receiving a signal having a predetermined frequency and the filter device according to the first aspect are provided, and the filter device is used for signal data received by the receiver. On the other hand, a receiving system that executes the filtering process from the first timing is provided.

According to the present invention, in a digital filter having delay blocks, there is an effect that the delay time between input and output can be shortened regardless of the number of delay blocks.

A configuration example of the filter device 10 to be compared is shown. A first configuration example of the filter device 100 according to the present embodiment is shown. A second configuration example of the filter device 100 according to the present embodiment is shown. A configuration example of the transmission system 200 according to the present embodiment is shown. A configuration example of the receiving system 300 according to the present embodiment is shown.

[Configuration example of filter device 10 to be compared]
FIG. 1 shows a configuration example of the filter device 10 to be compared. The filter device 10 is a digital filter that has a delay block and operates based on a clock signal. The filter device 10 is, for example, an FIR filter. The filter device 10 includes an acquisition unit 20, a delay block 30, a multiplication unit 40, and an addition unit 50.

The acquisition unit 20 acquires a data string for filtering processing. The acquisition unit 20 acquires a data string from, for example, an AD converter, a storage device, or the like. Further, the acquisition unit 20 may be connected to a network or the like and acquire a data string stored in a database or the like. As an example, the data string includes a plurality of data arranged in a time series. In the present embodiment, the data string is x [n], the first data is x [1], and the second data is x [2].

As an example, the acquisition unit 20 acquires the data of the data string x [n] one by one. Further, the acquisition unit 20 supplies the acquired data to one corresponding delay block 30 and one corresponding multiplication unit 40 one by one.

The delay block 30 is connected in series between the input end 32 and the output end 34. The filter device 10 is provided with N delay blocks 30. Here, N is an integer of 2 or more. 1, a plurality of delay block 30 connected in series, from the input end 32 to output end 34, shown from D ₁ and D _N. The first data in the data string is input from the acquisition unit 20 to the _first delay block 30 (D 1) from the input end 32, for example, in synchronization with one clock signal. The first delay block 30 (D _{1 ) from the input end 32 supplies data to the second} delay block 30 (D 2) from the input end 32 in synchronization with the next clock signal, and supplies the next data. Received from the acquisition unit 20.

The second and subsequent delay blocks 30 (D ₂ ) from the input terminal 32 also operate in the same manner as the _first delay block 30 (D 1) in synchronization with the clock. Then, the Nth delay block 30 ( _DN ) from the input terminal 32 outputs the first data to the output terminal 34 in synchronization with the Nth clock signal, and the N-1st delay block 30 (DN). Receive the second data from ( _DN-1). In this way, when there are N delay blocks 30, a delay of N times the clock cycle occurs from the time when the first data in the data string is input to the input terminal 32 to the time when the data is output to the output terminal 34. become.

The multiplication unit 40 is provided corresponding to the inputs and outputs of the N delay blocks 30. For example, the first multiplication unit 40 is connected to the input end 32 and the input of the first delay block 30. Further, the second multiplication unit 40 is connected to the output of the first delay block 30 and the input of the second delay block 30. Then, the N + 1th multiplication unit 40 is connected to the output of the Nth delay block 30. As described above, the filter device 10 is provided with N + 1 multiplication units 40 corresponding to N delay blocks 30. _{FIG. 1 shows a plurality of multiplication units 40 as M 1} to _{MN + 1} from the input end 32 toward the output end 34 according to the numbers of the connected delay blocks 30.

The multiplication unit 40 multiplies the input data by a coefficient. For example, let h [n-1] be the coefficient of the nth multiplication unit 40 from the input end 32. In this case, since the N + 1th data x [N + 1] of the data string is input to the first _{multiplication unit 40 (M 1) from the input end 32 in synchronization with the Nth clock signal, the first multiplication unit 40 (M 1).} The multiplication unit 40 (M ₁ ) outputs the multiplication result of h [0] and x [N + 1]. Similarly, the second multiplication unit 40 (M ₂ ) outputs the multiplication result of h [1] · x [N], and the N + 1th multiplication unit 40 ( _{MN + 1} ) outputs h [N] · x [ 1] Outputs the multiplication result.

The addition unit 50 calculates the sum of the multiplication results of N + 1 multiplication units 40. The addition unit 50 outputs the sum of the multiplication results for each clock in synchronization with the clock. The addition unit 50 outputs the multiplication result for each clock as a data string y [n] as a result of the filtering process. For example, y [N + 1] = h [0] · x [N + 1] + h [1] · x [N] + ... + h [N] · x [1].

As described above, as shown by the following equation, the filter device 10 performs an operation corresponding to convolution on the input data string x [n] and outputs the output data string y [n].

The filter device 10 is known as an FIR filter, and it is known that the larger the number N of delay blocks called the number of taps, the closer the frequency response approaches the ideal frequency response. However, it is difficult for the filter device 10 to respond at high speed because the larger the number N of the delay blocks is, the longer the time until the filtered data is output is delayed. Therefore, in the filter device according to the present embodiment, in the digital filter having the delay block 30, the delay time between the input and output is shortened regardless of the number of the delay blocks 30. Such a filter device will be described below.

[First Configuration Example of Filter Device 100]
FIG. 2 shows a first configuration example of the filter device 100 according to the present embodiment. In the filter device 100 of the first configuration example, those substantially the same as the operation of the filter device 10 to be compared shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. The filter device 100 shortens the delay time between input and output by supplying data corresponding to each of the plurality of delay blocks 30 at the timing of starting the filtering process. The filter device 100 further includes a storage unit 110, a data supply unit 120, and a control unit 130.

The storage unit 110 stores the data string x [n] acquired by the acquisition unit 20. In other words, the acquisition unit 20 stores the acquired data string x [n] in the storage unit 110. In this case, the acquisition unit 20 may acquire the data string x [n] part by part, or may acquire all the data strings x [n] at once.

The storage unit 110 stores intermediate data, calculation results, coefficients, threshold values, parameters, and the like generated (or used) by the filter device 100 in the process of operation. The storage unit 110 may supply the stored data to the request source in response to a request from each unit in the filter device 100.

When a computer such as a server operates as a filter device 100, the storage unit 110 may store information on an OS (Operating System) for functioning as the filter device 100 and a program. Further, the storage unit 110 may store various information including a database referred to when the program is executed. For example, a computer such as a server functions as a filter device 100 by executing a program stored in the storage unit 110.

The storage unit 110 includes, for example, a ROM (Read Only Memory) for storing a BIOS (Basic Input Output System) of a computer or the like, and a RAM (Random Access Memory) serving as a work area. Further, the storage unit 110 may include a large-capacity storage device such as an HDD (Hard Disk Drive) and / or an SSD (Solid State Drive). Further, the computer may further include a GPU (Graphics Processing Unit) and the like.

The data supply unit 120 supplies the data included in the input data string x [n] to the N delay blocks 30 and the N + 1 multiplication units 40. For example, the data supply unit 120 reads N + 1 data stored in the storage unit 110 according to the control signal, and at the first timing, the delay block 30 and the multiplication unit 40 corresponding to the read N + 1 data are read. To supply to.

Here, as an example, the first timing is a timing at which the data x [1] of the data string x [n] is input to the filter device 100 and the filtering process is started. In the case of the filter device 10 to be compared, as described above, in the first timing, the acquisition unit 20 corresponds the data x [1] to the first delay block 30 (D ₁ ) from the input end 321. It is supplied to the third multiplication unit 40 (M _1). On the other hand, in the filter device 100 of the present embodiment, at the first timing, the delay corresponding to N + 1 data from the data x [1] to the data x [N + 1] read from the storage unit 110 by the data supply unit 120. It is supplied to the block 30 and the multiplication unit 40.

In this case, in the first timing, the data supply unit 120 has N pieces from the data x [2] next to the first data x [1] in the first timing of the input data string to the N + 1th data x [N + 1]. Data is supplied to the corresponding N delay blocks 30, respectively. The data supply unit 120 supplies, for example, the N + 1th data x [N + 1] from the beginning to the _{first delay block 30 (D 1) from the input end 32.}

Similarly, the data supply unit 120 inputs the Nth data x [N] from the beginning to _{the delay block 30 (D 2) second from the input end 32.} In this way, the data supply unit 120 inputs the N + 1-kth data x [N + 1-k] from the beginning to the k + 1th delay block 30 from the input end 32. Here, k represents N integers from 0 to N-1. As described above, in the filter device 100 of the present embodiment, N data from the data x [2] to the data x [N + 1] are input to the corresponding N delay blocks 30 at the first timing.

Further, in the first timing, the data supply unit 120 connects the head data x [1] of the input data string at the first timing to the output of the _{Nth delay block 30 (DN) from the input end 32.} It is supplied to the N + 1th multiplication unit 40 ( _{MN + 1).} Further, in the first timing, the data supply unit 120 has N pieces of data from the data x [2] next to the first data x [1] in the first timing of the input data string to the N + 1th data x [N + 1]. Is supplied to the corresponding N delay blocks 30 respectively.

The data supply unit 120 supplies, for example, the N + 1th data x [N + 1] from the beginning to _{the multiplication unit 40 (M 1) which is the first from the input end 32.} Similarly, the data supply unit 120 inputs the Nth data x [N] from the beginning to _{the multiplication unit 40 (M 2) second from the input end 32.} In this way, the data supply unit 120 inputs the N + 1-kth data x [N + 1-k] from the beginning to the k + 1th delay block 30 from the input end 32.

As described above, in the filter device 100 of the present embodiment, N + 1 data from the data x [1] to the data x [N + 1] are input to the corresponding N + 1 multiplication units 40 at the first timing. Therefore, the addition unit 50 can calculate the sum of the multiplication results of N + 1 multiplication units 40 at the first timing. For example, the addition unit 50 synchronizes with one clock corresponding to the first timing and adds the sum of the multiplication results to y [1] = h [0] · x [N + 1] + h [1] · x [N] +. ... Output as + h [N] · x [1].

Further, as described above, the corresponding data is input to all of the N delay blocks 30 of the filter device 100 at the first timing. Therefore, after the first timing, the addition unit 50 can continuously output the multiplication result for each clock by executing the same operation as that of the filter device 10 to be compared. In this case, the data supply unit 120 includes the first delay block 30 (D ₁ ) from the input terminal 32 and the multiplication unit 40 (M ₁ ) connected to the input terminal 32 for each processing timing after the first timing. Data x [N + 2], x [N + 3], x [N + 4], ...

In this way, the data supply unit 120 supplies N data to the corresponding N delay blocks 30 and N + 1 data to the corresponding N + 1 delay blocks 30 at the first timing. Then, after the first timing, the data supply unit 120 supplies one data for each processing timing to the first delay block 30 and the first multiplication unit 40 from the input end 32. In order to express such an operation of the data supply unit 120, FIG. 1 shows an example in which the data supply unit 120 has N switches 36 on each output side of the N delay blocks 30.

The switch 36 connects the data supply unit 120 with the corresponding delay block 30 and the multiplication unit 40 at the first timing. Since the Nth switch 36 from the input end does not have the corresponding delay block 30, the data supply unit 120 and the corresponding N + 1th multiplication unit 40 ( _{MN + 1} ) are connected. Then, after the first timing, the switch 36 connects the delay block 30 in the previous stage with the corresponding delay block 30 and the multiplication unit 40. Since the Nth switch 36 from the input end does not have a corresponding delay block 30, the Nth delay block 30 ( _DN ) in the previous stage and the corresponding N + 1th multiplication unit 40 ( _{MN + 1} ) are connected. ..

As described above, as shown by the following equation, the filter device 100 applies an operation corresponding to convolution to the input data string x [n] from the first timing, and outputs the output data string y [n] from the first timing. ] Can be output.

The control unit 130 controls each unit of the filter device 100. The control unit 130 supplies, for example, a control signal based on the first timing for executing the filtering process to the input data string to the data supply unit 120. The control unit 130 is, for example, a computer such as a CPU. The control unit 130 generates the first timing according to the acquisition of the number of data in the input data string that can be filtered, such as N + 1 data from the beginning, by the acquisition unit 20. Let me. The control unit 130 supplies a signal indicating the first timing generated in this way as a control signal.

Alternatively or additionally, the control unit 130 may generate the first timing based on the execution of the program. Further, the control unit 130 may generate the first timing according to the timing signal received from an external device or the like.

As described above, since the filter device 100 according to the present embodiment inputs appropriate data to the plurality of delay blocks in synchronization with the timing of starting the filtering process, it is between the input and output regardless of the number of delay blocks. The delay time can be shortened. Therefore, the filter device 100 can output the data after the filtering process at a higher speed, for example, about one clock, while bringing the frequency response closer to the ideal frequency response.

Further, since the filter device 100 according to the present embodiment can output the output data corresponding to the input data at a higher speed, for example, even if the input data is switched to the input data of a different data string, the output data after the switching can be output at a higher speed. Can be output to. The filter device 100 according to the present embodiment can output the filtering processing result after the switching at high speed even if the filtering characteristics are switched as well as the input data is switched. Such a filter device 100 will be described below.

[Second Configuration Example of Filter Device 100]
FIG. 3 shows a second configuration example of the filter device 100 according to the present embodiment. In the filter device 100 of the second configuration example, those substantially the same as the operation of the filter device 100 of the first configuration example shown in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted. The filter device 100 of the second configuration example further includes a coefficient supply unit 140. In the present embodiment, an example will be described in which the filter device 100 of the second configuration example starts the filtering process of the input data string at the first timing and switches the filtering characteristics at the second timing.

The coefficient supply unit 140 supplies N + 1 coefficients corresponding to N + 1 multiplication units 40 according to the control signal. Here, the coefficient used by the multiplication unit 40 is stored in, for example, the storage unit 110. It is desirable that the storage unit 110 stores a set of a plurality of coefficients corresponding to the plurality of filtering characteristics.

In this case, the control unit 130 supplies, for example, a control signal based on the first timing for executing the filtering process to the input data string to the coefficient supply unit 140. Further, the control unit 130 may include an instruction of setting a coefficient used for the filtering process in the control signal. The coefficient supply unit 140 reads N + 1 coefficients corresponding to the instructions from the storage unit 110 and supplies them to the corresponding N + 1 multiplication units according to the control signal. As a result, the filter device 100 can start an appropriate filtering process from the first timing.

Then, the control unit 130 supplies a control signal based on the second timing different from the first timing to the data supply unit 120 and the coefficient supply unit 140. Here, the second timing is a timing at which a predetermined time has elapsed from the first timing. For example, the second timing is a timing at which a sufficient time has elapsed to output the result of the filtering process started at the first timing.

Further, the control unit 130 may include an instruction of a set of coefficients used in the filtering process starting from the second timing in the control signal. Instead of this, the storage unit 110 may store a plurality of set of coefficients in association with the information of the set of coefficients used at each timing. As a result, the coefficient supply unit 140 multiplies N + 1 coefficients whose values are different from the N + 1 coefficients supplied according to the control signal based on the first timing in the second timing according to the control signal. Supply to the department.

The data supply unit 120 executes the same operation as the first timing at the second timing according to the control signal. For example, in the second timing, the data supply unit 120 connects the head data x [m] of the input data string at the second timing to the output of the _{Nth delay block 30 (DN) from the input end 32.} It is supplied to the N + 1th multiplication unit 40 ( _{MN + 1).} Further, in the second timing, the data supply unit 120 has N pieces of data from the next data x [m + 1] to the N + 1th data x [m + N] of the first data x [m] in the second timing of the input data string. Is supplied to the corresponding N delay blocks 30 and the corresponding N multiplication units 40 connected to the input side of the N delay blocks 30, respectively.

As a result, the filter device 100 of the second configuration example performs an operation corresponding to convolution on the input data string x [m] from the second timing, as in the equation in which n in the equation (Equation 2) is replaced with m. Therefore, the output data string y [m] can be output from the second timing. That is, even if the filter device 100 switches from the first filtering process to the second filtering process having different filtering characteristics at the second timing, the filter device 100 promptly outputs the result of the second filtering process in synchronization with the second timing. can do.

[Filtering process with different tap numbers]
In the filter device 100 of the second configuration example described above, the coefficient supply unit 140 has described an example in which N + 1 coefficients are read from the storage unit 110 and supplied to the corresponding N + 1 multiplication units 40. That is, the example in which the filter device 100 executes the filtering process using N + 1 coefficients has been described. However, the number of coefficients supplied by the coefficient supply unit 140 is not limited to this. The filter device 100 may execute a filtering process using N or less coefficients.

In this case, the coefficient supply unit 140 reads out L coefficients (L is an integer of 2 or more and N or less) from the storage unit 110. Then, when the coefficient supply unit 140 supplies the L coefficients to the N + 1 multiplication units 40, the coefficient supply unit 140 supplies the L coefficients corresponding to the L multiplication units 40 closer to the output end 34. Here, the L multiplication units 40 closer to the output end 34 are, for example, from the N + 1th multiplication unit 40 ( _{MN + 1} ) closest to the output end 34 to the N + 2-Lth multiplication unit 40 from the input end 32. There are L multiplication units 40 up to ( _{MN + 2-L).} Further, the coefficient supply unit 140 supplies the remaining N + 1-L multiplication units 40 with coefficients having a value of 0. Here, the remaining N + 1-L multiplication units 40 are _{from the first} multiplication unit 40 (M 1) closest to the input end to the N + 1-Lth multiplication unit 40 ( _{MN + 1-L} ) from the input end. N + 1-L number of multiplication units 40.

As a result, the filter device 100 can execute FIR filtering processing using L-1 delay blocks 30 and L coefficients in a pseudo manner. In this case, the filter device 100 extends from the N + 2-Lth delay block 30 ( _{DN + 2-L} ) to the Nth delay block 30 ( _DN ) on the side closer to the output end 34 of the N delay blocks 30. L-1 delay blocks 30 and the corresponding L multiplication units 40 are substantially used.

As a result, the filter device 100 can easily execute the filtering process of different tap numbers. Therefore, the filter device 100 can not only switch between two filtering processes having the same number of taps but also switch between two filtering processes having the same number of taps, but also switch between two filtering processes having different numbers of taps at a higher speed.

In the filter device 100 according to the present embodiment described above, it has been described that the delay time between input and output can be shortened by using the example of the FIR filter, but the present invention is not limited to this. Similarly, in the case of a filter having a plurality of delay blocks 30 connected in series, by supplying data corresponding to the plurality of delay blocks 30 at one timing, the filter can be input regardless of the number of delay blocks 30. The delay time between outputs can be reduced. For example, the filter device 100 may be a moving average filter. Further, the filter device 100 may be a processing device including a convolution process.

Since the above filter device 100 can switch the filtering process at high speed, it can be applied to a communication system or the like. An example in which the filter device 100 is applied to a communication system will be described below.

[Example applied to communication system]
FIG. 4 shows a configuration example of the transmission system 200 according to the present embodiment. The transmission system 200 includes a filter device 100, a transmitter 210, and a transmission unit 212. The transmitter 210 transmits a signal having a predetermined frequency. The transmitter 210 transmits signals of one or more frequencies. The transmitter 210 may transmit signals in a plurality of bands. Further, the transmitter 210 may transmit signals having different frequencies by switching in time.

As an example, the transmission system 200 transmits a signal via the transmission unit 212. The transmission unit 212 may have, for example, a DA converter and an antenna, convert the transmission signal into an analog signal, and then transmit the transmission signal via the antenna. Further, the transmission unit 212 may have a connector or the like and transmit a signal via a cable or the like.

The filter device 100 executes the filtering process from the first timing described above on the signal data transmitted by the transmitter 210. As a result, the transmission system 200 can transmit a signal that has been filtered by the FIR filter. In the transmission system 200, it is desirable that the transmitter 210 supplies a signal for notifying the first timing to the filter device 100.

For example, when the transmitter 210 outputs a signal of one frequency and the filter device 100 operates as a low-pass filter, a high-pass filter, or a band-pass filter that passes the one frequency, the transmission system 200 reduces the noise component. It operates as a system for transmitting the transmitted signal of the one frequency. In this case, the transmission system 200 can transmit signal data by switching various filtering characteristics such as the pass band, cutoff frequency, and full width at half maximum of the filter device 100 at high speed.

Instead, for example, the transmitter 210 may output signals of a plurality of frequencies, and the filter device 100 may operate as a filter that selectively passes one of the plurality of frequencies. Even in this case, the transmission system 200 can operate as a system that transmits one selected frequency with reduced noise components.

In this case, the filter device 100 may execute the filtering process from the second timing described above on the signal data transmitted by the transmitter 210. For example, after the second timing, the filter device 100 selectively passes one frequency different from the one frequency selectively passed from the first timing among the plurality of frequencies output by the transmitter 210. It may operate as a filter to be made to operate. As a result, the transmission system 200 can switch the frequency of the signal to be transmitted at high speed by changing the filtering characteristics of the filter device 100.

Instead, for example, the transmitter 210 may output a signal of one frequency, and the frequency of the transmitted signal may be switched to a different frequency after the second timing. In this case, the filter device 100 receives a notification from the transmitter 210 based on the frequency switching timing. It is desirable that the notification include frequency information after the transmitter 210 has switched signals. As a result, the filter device 100 can switch the pass band according to the frequency switching of the transmitter 210.

FIG. 5 shows a configuration example of the receiving system 300 according to the present embodiment. The receiving system 300 includes a filter device 100, a receiver 310, and a receiving unit 312. The receiver 310 receives a signal of a predetermined frequency. The receiver 310 may receive signals in one or more frequency bands. Further, the receiver 310 may switch signals having different frequencies in time to receive the signals.

As an example, the receiving system 300 receives a signal via the receiving unit 312. The receiving unit 312 has, for example, an antenna and an AD converter, and converts a signal received via the antenna into a digital signal. Further, the receiving unit 312 may have a connector or the like and receive a signal via a cable or the like.

The filter device 100 executes the filtering process from the first timing described above on the signal data received by the receiver 310. As a result, the receiving system 300 can receive the signal filtered by the FIR filter. In the receiving system 300, it is desirable that the receiver 310 supplies a signal for notifying the first timing to the filter device 100.

For example, if the receiver 310 is provided to receive a signal of one frequency and the filter device 100 operates as a low-pass filter, a high-pass filter, or a bandpass filter that passes the one frequency, the receiving system 300 It operates as a system that receives the one frequency with the noise component reduced. In this case, the receiving system 300 can receive signal data by switching various filtering characteristics such as the pass band, cutoff frequency, and full width at half maximum of the filter device 100 at high speed.

Here, for example, the transmitted signal may include signals of a plurality of frequencies, and the filter device 100 may operate as a filter that selectively passes one of the plurality of frequencies. Alternatively, the filter device 100 may switch to pass a signal having a frequency different from that of the transmitted signal. As a result, the receiver 310 can receive the noise component and the like contained in the transmitted signal.

In this case, the filter device 100 may execute the filtering process from the second timing described above on the signal data received by the receiver 310. For example, the filter device 100 selectively passes one frequency different from the one frequency selectively passed from the first timing among the frequencies received by the receiver 310 after the second timing. May operate as. As a result, the receiving system 300 can switch the frequency of the received signal at high speed by changing the filtering characteristic of the filter device 100.

The transmission system 200 and the reception system 300 described above have been described as separate and independent systems, but the present invention is not limited thereto. The transmitting system 200 and the receiving system 300 may be combined to form a transmitting / receiving system.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments, and various modifications and changes can be made within the scope of the gist thereof. be. For example, all or a part of the device can be functionally or physically distributed / integrated in any unit. Also included in the embodiments of the present invention are new embodiments resulting from any combination of the plurality of embodiments. The effect of the new embodiment produced by the combination also has the effect of the original embodiment.

10 Filter device 20 Acquisition unit 30 Delay block 32 Input end 34 Output end 36 Switch 40 Multiplication unit 50 Addition unit 100 Filter device 110 Storage unit 120 Data supply unit 130 Control unit 140 Coefficient supply unit 200 Transmission system 210 Transmitter 212 Transmitter unit 300 Reception system 310 Receiver 312 Receiver

Claims (6)

N delay blocks (N is an integer of 2 or more) connected in series between the input end and the output end,
N + 1 multiplication units, which are provided corresponding to the inputs and outputs of the N delay blocks and multiply the input data by a coefficient,
An addition part that calculates the sum of the multiplication results of N + 1 pieces of the multiplication part,
The N delay blocks and the N + 1 multiplication units are provided with a data supply unit that supplies data included in the input data string.
The data supply unit is in the first timing.
The head data of the input data string at the first timing is supplied to the multiplication unit connected to the output of the delay block Nth from the input end.
N data from the data next to the first data in the first timing of the input data string to the N + 1th are connected to the corresponding N delay blocks and the input side of the N delay blocks. Supply to each of the corresponding N multiplication units
For each processing timing after the first timing, N + 1th and subsequent data from the head data in the first timing are applied to the delay block first from the input end and the multiplication unit connected to the input end. Supply sequentially,
Filter device. A coefficient supply unit that supplies N + 1 of the coefficients corresponding to N + 1 of the multiplication units, and a coefficient supply unit.
A control unit that supplies a control signal based on the first timing for executing a filtering process to the input data string to the data supply unit and the coefficient supply unit is further provided.
The coefficient supply unit supplies N + 1 of the coefficients to the N + 1 multiplication units in response to the control signal.
The filter device according to claim 1. The control unit supplies a control signal based on a second timing different from the first timing to the data supply unit and the coefficient supply unit.
At the second timing
The data supply unit
The head data of the input data string at the second timing is supplied to the multiplication unit connected to the output of the delay block Nth from the input end.
N data from the data next to the first data in the second timing of the input data string to the N + 1th are connected to the corresponding N delay blocks and the input side of the N delay blocks. Supply to each of the corresponding N multiplication units
The coefficient supply unit supplies N + 1 the coefficients having a value different from the N + 1 coefficients supplied in response to the control signal based on the first timing to the N + 1 multiplication units.
The filter device according to claim 2. When supplying L coefficients (L is an integer of 2 or more and N or less) to the N + 1 multiplication units, the coefficient supply unit corresponds to the L multiplication units closer to the output end. The filter device according to claim 2 or 3, wherein L of the coefficients are supplied, and the remaining N + 1-L of the multiplication units are supplied with the coefficients having a value of 0. A transmitter that transmits a signal with a predetermined frequency, and
The filter device according to any one of claims 1 to 4 is provided.
The filter device executes a filtering process from the first timing on the signal data transmitted by the transmitter.
Transmission system. A receiver that receives a signal of a predetermined frequency, and
The filter device according to any one of claims 1 to 4 is provided.
The filter device executes a filtering process from the first timing on the signal data received by the receiver.
Receiving system.

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