JP2021150713A - Delta-sigma adc circuit - Google Patents

Abstract

To provide a delta-sigma ADC circuit capable of improving performance without increase in power consumption.SOLUTION: The delta-sigma ADC circuit comprises: a first integrator which has an amplifier circuit and integrates a first differential signal obtained by differentiating a feedback signal from an input signal; a second integrator which does not have an amplifier circuit but has a resistance element and a capacity element, and integrates a second differential signal obtained by differentiating the feedback signal from a first integrated signal output from the first integrator; a comparator which binarizes a second integrated signal output from the second integrator; a quantizer which outputs a digital signal based on a binarized signal output from the comparator; and a digital-to-analog converter for generating the feedback signal by converting the digital signal to an analog signal.SELECTED DRAWING: Figure 1

Description

Embodiments herein relate to delta-sigma ADC circuits.

Conventionally, a delta sigma ADC (Analog-to-digital converter) circuit (hereinafter referred to as a delta-sigma ADC circuit) converts an analog signal into a digital signal by using a delta-sigma modulation method. At this time, the output signal output from the ΔΣ ADC circuit is reduced in noise by noise shaping. In order to improve the signal-to-noise ratio (hereinafter referred to as SNR) in the ΔΣ ADC circuit, it is necessary to increase the oversampling rate or increase the order of the integrator in the ΔΣ ADC circuit. Increasing the oversampling rate is equivalent to increasing the clock frequency. Also, in applications where the clock frequency is specified, increasing the order of the integrator is selected.

Japanese Unexamined Patent Publication No. 2018-12190

In the prior art, increasing the order of the integrators in the ΔΣADC circuit increases the number of integrators used in the ΔΣADC circuit. Since each integrator has an amplifier circuit, there is a problem that the power consumption in the ΔΣ ADC circuit increases as the order of the integrator is increased.

An object of the present invention has been made in view of the above, and an object of the present invention is to provide a delta-sigma ADC circuit capable of improving performance without increasing power consumption.

In order to solve the above-mentioned problems and achieve the object, the delta sigma ADC circuit of the present invention includes a first integrator which has an amplification circuit and integrates a first difference signal obtained by subtracting a feedback signal from an input signal. A second integrator which has a resistance element and a capacitance element without an amplification circuit and integrates a second difference signal obtained by subtracting the feedback signal from the first integrator output from the first integrator, and the above. A comparator that binarizes the second integrated signal output from the second integrator, a quantizer that outputs a digital signal based on the binarized signal output from the comparator, and an analog digital signal. It includes a digital-analog converter that generates the feedback signal by converting it into a signal.

According to the present invention, it is possible to provide a ΔΣ ADC circuit capable of improving performance without increasing power consumption.

FIG. 1 is a configuration diagram showing an example of the configuration of the ΔΣ ADC circuit according to the embodiment. FIG. 2 is a diagram showing an example of a configuration of a continuous-time type single-ended ΔΣ ADC circuit having two pre-stage integrators according to an embodiment. FIG. 3 is a diagram showing an example of the configuration of a fourth-order ΔΣ ADC circuit according to a comparative example of the embodiment. FIG. 4 is a diagram showing an example of a circuit configuration equivalent to that of the fourth integrator in FIG. 3, according to a comparative example of the embodiment. FIG. 5 is a diagram showing an example of comparison of noise shaping waveforms in the conventional ΔΣ ADC circuit (3rd order) and the ΔΣ ADC circuit (4th order) according to the present embodiment at the same power consumption. FIG. 6 is a diagram showing an example of FOM with respect to frequency in the ΔΣ ADC circuit according to the present embodiment having the same order as the conventional ΔΣ ADC circuit. FIG. 7 is a diagram showing an example of a continuous-time type and differential type fourth-order ΔΣ ADC circuit according to an application example of the present embodiment.

Hereinafter, embodiments of a delta-sigma ADC (Analog-to-digital converter) circuit will be described in detail with reference to the drawings. In the following embodiments, the parts with the same reference numerals perform the same operation, and duplicate description will be omitted as appropriate.

(Embodiment)
FIG. 1 is a configuration diagram showing an example of the configuration of a delta-sigma ADC circuit (hereinafter, referred to as a ΔΣ ADC circuit) 1 according to the present embodiment. As shown in FIG. 1, the ΔΣ ADC circuit 1 includes a first integrator 3, a second integrator 5, a comparator 7, a quantizer 9, and a digital-to-analog converter: hereinafter, It has a circuit 11 (referred to as a DAC). At least one integrator similar to the first integrator 3 (hereinafter, referred to as a previous integrator) may be arranged in series in the front stage of the first integrator 3.

When the first-stage integrator is not mounted on the ΔΣ ADC circuit 1, the input end of the first integrator 3 is electrically connected to the input node IN1 of the ΔΣ ADC circuit 1. When the pre-stage integrator is mounted on the ΔΣ ADC circuit 1, the input end of the first integrator 3 is electrically connected to the last-stage pre-stage integrator. The other input ends of the first integrator 3 are electrically connected to the DAC circuit 11. The output end of the first integrator 3 is electrically connected to the second integrator 5. The first integrator 3 has an amplifier circuit. The first integrator 3 integrates a signal obtained by subtracting a feedback signal from a signal input to the first integrator 3 (hereinafter referred to as an input signal) (hereinafter referred to as a first difference signal). The feedback signal corresponds to the output signal from the DAC circuit 11. The first difference signal (hereinafter referred to as the first integrator signal) integrated by the first integrator 3 is output from the first integrator 3 to the second integrator 5. The circuit configuration of the first integrator 3 will be described later.

The input end of the second integrator 5 is electrically connected to the output end of the first integrator 3. The other input end of the second integrator 5 is electrically connected to the DAC circuit 11. The output end of the second integrator 5 is electrically connected to the comparator 7. The second integrator 5 does not have an amplifier circuit, but has a resistance element and a capacitance element (capacitor). The second integrator 5 integrates a signal obtained by subtracting a feedback signal from the first integrator signal output from the first integrator 3 (hereinafter, referred to as a second integrator signal). The second difference signal (hereinafter referred to as the second integrator signal) integrated by the second integrator 5 is output from the second integrator 5 to the comparator 7. The circuit configuration of the second integrator 5 will be described later.

The input end of the comparator 7 is electrically connected to the output end of the second integrator 5. The output end of the comparator 7 is electrically connected to the quantizer 9. The comparator 7 binarizes the second integrated signal using a predetermined reference value. The comparator 7 is realized by, for example, an operational amplifier. At this time, the comparator 7 binarizes the second integrated signal and amplifies it with a predetermined gain. The binarized and amplified signal (hereinafter referred to as a binarized signal) is output to the quantizer 9.

The input end of the quantizer 9 is electrically connected to the comparator 7. The output end of the quantizer 9 is electrically connected to the output node ON1 of the ΔΣ ADC circuit 1 and the input end of the DAC circuit 11. The quantizer 9 outputs a digital signal based on the binarized signal output from the comparator 7. Specifically, the quantizer 9 converts a binarized signal into a digital signal by using a clock signal having a predetermined clock frequency generated by a clock generation circuit (not shown). The digital signal corresponds to, for example, a pulse density modulation (hereinafter referred to as PDM) signal. At this time, the quantizer 9 is realized by, for example, a D flip-flop.

The D flip-flop delays the binarized signal over one sampling period in the clock signal in the generation of the PDM signal. That is, the PDM signal is delayed with respect to the input signal for one sampling period by the D flip-flop. The PCM signal is output to the output node ON1 and the DAC circuit 11. The circuit that realizes the quantizer 9 is not limited to the D flip-flop. When the quantizer 9 does not cause a delay with respect to the input signal, a delay circuit is arranged between the quantizer 9 and the DAC circuit 11 or after the DAC circuit 11.

The input end of the DAC circuit 11 is electrically connected to the quantizer 9. The output end of the DAC circuit 11 is electrically connected to the first integrator 3 and the second integrator 5. The DAC circuit 11 generates a feedback signal by converting a PDM signal, which is a digital signal, into an analog signal. The feedback signal is output from the DAC circuit 11 to the first integrator 3 and the second integrator 5. When a pre-stage integrator is provided in front of the first integrator 3, the output end of the DAC circuit 11 is electrically connected to the pre-stage integrator. At this time, the feedback signal is also output to the pre-stage integrator. The DAC circuit 11 is realized by any type of circuit such as a pulse width modulation type, a ΔΣ type, a resistance string type, a resistance ladder type, a capacitance array type, and a current output type.

When one pre-stage integrator is mounted on the ΔΣ ADC circuit 1, the input end of one pre-stage integrator is electrically connected to the input node IN1 of the ΔΣ ADC circuit 1. The other input end of one pre-stage integrator is electrically connected to the DAC circuit 11. The output end of one integrator is electrically connected to the first integrator 3.

When a plurality of pre-stage integrators are mounted on the ΔΣ ADC circuit 1, the input end of the front-stage pre-integrator (hereinafter referred to as the front-stage integrator) among the plurality of pre-stage integrators is the input of the ΔΣ ADC circuit 1. It is electrically connected to node IN1. Further, the other input end of the front integrator is electrically connected to the DAC circuit 11. Of the plurality of integrators, the input end of the integrator after the integrator (hereinafter referred to as the integrator in the latter stage) is electrically connected to the output end of the integrator in the previous stage immediately before. The other input ends of the post-stage integrator are electrically connected to the DAC circuit 11. The output ends of the rear-stage integrators other than the last-stage front-stage integrator (hereinafter referred to as the last-stage integrator) among the plurality of front-stage integrators are electrically connected to the rear-stage front-stage integrator. The output end of the last stage integrator is electrically connected to the first integrator 3. Since the function of the first-stage integrator is the same as that of the first integrator 3, the description thereof will be omitted.

Hereinafter, in order to make the description concrete, it is assumed that there are two pre-stage integrators mounted on the ΔΣ ADC circuit 1, and the ΔΣ ADC circuit 1 is a single-ended system. The number of pre-stage integrators mounted on the ΔΣ ADC circuit 1 is not limited to two, and can be set from 0 to any natural number. Further, the ΔΣ ADC circuit 1 is not limited to the single-ended system, and may be a differential system.

Further, it is assumed that the ΔΣ ADC circuit 1 is a continuous time type ΔΣ ADC circuit. The ΔΣ ADC circuit 1 according to the embodiment is not limited to the continuous time type, and may be, for example, a discrete time type. Further, the present ΔΣ ADC circuit 1 may be used in combination with an ADC of another method such as a pipeline type ADC, a sequential approximation (SAR) type ADC, and a flash (parallel) type ADC.

FIG. 2 is a diagram showing an example of the configuration of a continuous-time type single-ended ΔΣ ADC circuit 1 having two pre-stage integrators. As shown in FIG. 2, the ΔΣ ADC circuit 1 includes a first integrator 31, a second integrator 32, a first integrator 3, a second integrator 5, a comparer 7, and a quantizer. It has 9 and a plurality of DAC circuits 111, 112, 113, 114. In the ΔΣ ADC circuit 1 shown in FIG. 2, the order corresponding to the number of integrators is 4.

The plurality of DAC circuits 111, 112, 113, 114 shown in FIG. 2 may be integrated as one DAC circuit 11 as shown in FIG. Of the plurality of DAC circuits 111, 112, 113, 114, the output end of the DAC circuit 111 regarding the input to the first pre-stage integrator 31 is electrically connected to one end of the resistance element R1. The other end of the resistance element R1 is electrically connected to the node N1. One end of the capacitor C1 is electrically connected to the ground potential G. The other end of the capacitor C1 is electrically connected to the node N1. One end of the resistance element R2 is electrically connected to the node N1. The other end of the resistance element R2 is electrically connected to the diffifier S31 in the first pre-stage integrator 31.

The output end of the DAC circuit 112 is electrically connected to the diffifier S32 in the second pre-stage integrator 32. The output end of the DAC circuit 113 is electrically connected to the diffifier S3 in the first integrator 3. The output end of the DAC circuit 114 is electrically connected to the difference device S5 in the second integrator 5. Since the comparator 7, the quantizer 9, and the DAC circuit 11 shown in FIG. 2 overlap with the description of FIG. 1, the description thereof will be omitted.

The first first-stage integrator 31 includes a resistance element R31, an adder A31, a capacitor C31, a differencer S31, and an amplifier circuit 311. One end of the resistance element R31 is electrically connected to the input node IN1 in the ΔΣ ADC circuit 1. The other end of the resistance element R31 is electrically connected to the adder A31. One end of the capacitor C31 is electrically connected to the diff S31. The other end of the capacitor C31 is electrically connected to the node N31. The difference device S31 and the adder A31 are electrically connected. The input end of the amplifier circuit 311 is electrically connected to the adder A31. The output end of the amplifier circuit 311 is electrically connected to the node N31.

The differencer S31 executes the difference between the signal output from the capacitor C31 and the feedback signal corresponding to the integration result in the first first-stage integrator 31, and outputs the difference signal due to the difference to the adder A31. The adder A31 adds the signal input from the input node IN1 of the ΔΣ ADC circuit 1 and passing through the resistance element R31 and the difference signal. The amplifier circuit 311 amplifies the adder signal output from the adder A31. The output from the amplifier circuit 311 is output to the capacitor C31 and the second pre-stage integrator 32 via the node N31. That is, the first first stage integrator 31 differentiates the signal input from the input node IN1 and the feedback signal, and executes integration on the signal of the difference result.

The second first-stage integrator 32 includes a resistance element R32, an adder A32, a capacitor C32, a differencer S32, and an amplifier circuit 321. One end of the resistance element R32 is electrically connected to the node N31 in the first pre-stage integrator 31. The other end of the resistance element R32 is electrically connected to the adder A32. One end of the capacitor C32 is electrically connected to the differencer S32. The other end of the capacitor C32 is electrically connected to the node N32. The difference device S32 and the adder A32 are electrically connected. The input end of the amplifier circuit 321 is electrically connected to the adder A32. The output end of the amplifier circuit 321 is electrically connected to the node N32.

The diffifier S32 executes the difference between the signal output from the capacitor C32 and the feedback signal corresponding to the integration result in the second pre-stage integrator 32, and outputs the difference signal due to the difference to the adder A32. The adder A32 adds the signal input from the node N31 and passed through the resistance element R32 and the difference signal. The amplifier circuit 321 amplifies the adder signal output from the adder A32. The output from the amplifier circuit 321 is output to the capacitor C32 and the first integrator 3 via the node N32. That is, the second pre-stage integrator 32 differentiates the signal input from the node N31 and the feedback signal, and executes integration on the signal of the difference result.

The first integrator 3 includes a resistance element R3, an adder A3, a capacitance element (capacitor) C3, a differencer S3, and an amplifier circuit 30. One end of the resistance element R3 is electrically connected to the node N32 in the second pre-stage integrator 32. The other end of the resistance element R3 is electrically connected to the adder A3. One end of the capacitor C3 is electrically connected to the differencer S3. The other end of the capacitor C3 is electrically connected to the node N3. The difference device S3 and the adder A3 are electrically connected. The input end of the amplifier circuit 30 is electrically connected to the adder A3. The output end of the amplifier circuit 30 is electrically connected to the node N3.

The differencer S3 executes the difference between the signal output from the capacitor C3 and the feedback signal corresponding to the integration result in the first integrator 3, and outputs the difference signal due to the difference to the adder A3. The adder A3 adds the signal input from the node N32 and passed through the resistance element R3 and the difference signal. The amplifier circuit 30 amplifies the adder signal output from the adder A3. The output from the amplifier circuit 30 is output to the capacitor C3 and the second integrator 5 via the node N3. That is, the first integrator 3 integrates the first difference signal obtained by subtracting the feedback signal from the input signal input from the node N32.

The second integrator 5 includes a resistance element R5, a differencer S5, and a capacitor (capacitive element) C5. One end of the resistance element R5 is electrically connected to the node N3 in the first integrator 3. The other end of the resistance element R5 is electrically connected to the diffifier S5. One end of the capacitor C5 is electrically connected to the node N5. The other end of the capacitor C5 is electrically connected to the ground potential G.

As shown in FIG. 2, the second integrator 5 corresponds to a low-pass filter (hereinafter referred to as LPF (Low Pass Filter)). The resistance value of the resistance element R5, which is a passive element, is R _LPF , the capacitance value of the capacitive element C5, which is a passive element, is C _LPF, and the input signal to the second integrator 5 is X _LPF . _Assuming that the output is Y LPF, the transfer function (Y _LPF / X _LPF ) of the LPF which is the second integrator 5 can be expressed by the following equation (1) using the variable s in the Laplace conversion.
Y _LPF / X _LPF = 1 / (R _LPF・ C _LPF・ (s)) (1)

The diffifier S5 differentiates the feedback signal from the signal input from the node N3 and passed through the resistance element R5. The capacitor C5 stores the electric charge related to the second difference signal output from the difference device S5. As a result, the second integrator 5 integrates the second difference signal obtained by subtracting the feedback signal from the first integrator signal input from the node N3.

_{Hereinafter, the setting of the resistance value R LPF} of the resistance element R5 and the capacitance value C _LPF of the capacitance element C5 in the second integrator 5 in the present embodiment will be described. FIG. 3 is a diagram showing an example of the configuration of a fourth-order ΔΣ ADC circuit (hereinafter, referred to as comparative ΔΣ ADC) 2 as a comparative example. The fourth-order comparison ΔΣADC2 shown in FIG. 3 has two integrators (third integrator 33 and fourth integrator 34) similar to the second integrator 32 in the subsequent stage of the second integrator 32. Since the circuit configuration and function of the third integrator 33 and the fourth integrator 34 are the same as those of the second integrator 32, the description thereof will be omitted.

The difference between FIGS. 2 and 3 lies in the circuit configuration of the second integrator 5 in FIG. 2 and the circuit configuration of the fourth integrator 34 in FIG. FIG. 4 is a diagram showing an example of a circuit configuration equivalent to that of the fourth integrator 34 in FIG. 3 as a comparative example of the embodiment. The fourth integrator 34 shown in FIG. 4 corresponds to a negative feedback circuit. If the amplification factor of the signal in the negative feedback circuit is A, the input signal to the negative feedback circuit is X _nf , the output from the negative feedback circuit is Y _nf, and the feedback rate of the signal is β, the transfer function of the negative feedback circuit. (Y _nf / X _nf ) can be expressed by the following equation (2) using the variable s in the Laplace transform.
Y _nf / X _nf = A · (s) / (1 + β · A · (s)) (2)

The amplification factor A corresponds to the amplification factor of the amplifier circuit 321 in the fourth integrator 34. Further, the feedback rate β of the integrator circuit configured with the resistance value of the resistance element R34 in the fourth integrator 34 as R _nf and the capacitance value of the capacitance element (capacitor) C34 in the fourth integrator 34 as C _{nf is determined.}
β = R _nf · C _nf
Is. Therefore, when the equation (2) is applied to the fourth integrator 34, the transfer function (Y _nf / X _nf ) of the fourth integrator 34 can be expressed as the following equation (3).
Y _nf / X _nf = A · (s) / (1 + β · A · (s))
= A · (s) / (1 + R _nf · C _nf · A · (s)) (3)

Assuming that the amplification factor A is sufficiently larger than 1 (A >> 1), the transfer function (Y _nf / X _nf ) shown in the equation (3) can be expressed as the equation (4).
Y _nf / X _nf = A · (s) / (1 + R _nf · C _nf · A · (s))
≈ 1 / (R _nf・ C _nf・ (s)) (4)

On the other hand, in the equation (1), the gain in the comparator 7 is γ, and the coefficient α is used to show the following relationship (5).
R _LPF・ C _LPF = α ・ R _nf・ C _nf (5)
When α, R _LPF, and C _LPF are set so that, the transfer function (Y _LPF / X _LPF ) of the second integrator 5 including the comparator 7 can be expressed by the following equation (6).
Y _LPF / X _LPF = (1 / (R _LPF・ C _LPF・ (s))) ・ γ
= Γ / (α ・ R _nf・ C _nf・ (s)) (6)

In the relationship of the equation (5) set to be the equation (6) in the actual circuit, when the capacitance value C _nf of the capacitance element (capacitor) C34 in the fourth integrator 34 is multiplied by the coefficient α, the C _LPF A large capacity value is required. At this time, since the power consumption of the capacitive element C5 in the second integrator 5 is higher than that of the capacitive element C34 in the fourth integrator 34, the following equation (7) is set as the equation (5).
α · R _nf = R _LPF , C _nf = C _LPF (7)

When the equation (7) is applied to the equation (6), α and γ are sufficiently large (α >> 1, γ >> 1), and α≈γ, the equation (6) is as follows. It can be expressed by equation (8).
Y _LPF / X _LPF = γ / (α ・ R _nf・ C _nf・ (s))
≈ 1 / (R _nf · C _nf · (s))
≒ Y _nf / X _nf (8)

In equation (8), when A >> 1 and α≈γ >> 1, the transfer function (Y _LPF / X _LPF ) for the second integrator 5 including the gain γ of the comparer 7 on the left side is on the right side. It is shown that it is equal to the transfer function (Y _nf / X _{nf) of the fourth integrator 34.} That is, when α≈γ >> 1 and the relationship of the equation (7) are maintained and the resistance value R _LPF of the resistance element R5 in the second integrator 5 and the capacitance value C _LPF of the capacitance element C5 are set, the second The integrator 5 can realize the same transfer function (Y _nf / X _{nf) as the fourth integrator 34.}

Further, since the circuit configuration of the fourth integrator 34 and the first integrator 3 is the same, the transfer function of the first integrator 3 (hereinafter referred to as the first transfer function) is shown (Y _nf / X _nf ). , The transfer function of the second integrator 5 (hereinafter referred to as the second transfer function) is the same as _{(Y LPF} / X _LPF). Therefore, the resistance value R _LPF of the resistance element R5 and the capacitance value C _LPF of the capacitance element C5 are the gain γ in the comparator 7, the amplification factor A in the amplification circuit 30 in the first integrator 3, and the first integrator. It is set based on _{the resistance value R nf} of the resistance element R3 _{in No. 3 and the capacitance value C nf} of the capacitor C3 in the first integrator 3.

_{Specifically, the capacitance value C LPF} of the capacitance element C5 in the second integrator 5 is set to be equal to _{the capacitance value C nf} of the capacitance element C3 in the first integrator 3 _{(C LPF} = C _nf ). .. _{In addition, the resistance value R LPF} of the resistance element R5 in the second integrator 5 is equal to the value _{obtained by multiplying the resistance value R nf} of the resistance element R3 in the first integrator 3 by the gain γ in the comparer 7. It is set (R _LPF = γ · R _nf ). As a result, the ΔΣ ADC circuit 1 according to the present embodiment has the same performance as the comparative ΔΣ ADC 2 shown in FIG. 3, and the second integrator 5 does not have an amplifier circuit, so that the power consumption is higher than that of the comparative ΔΣ ADC 2. Can be reduced.

As described above, the ΔΣ ADC circuit 1 according to the embodiment does not have the first integrator 3 which has the amplification circuit 30 and integrates the first difference signal obtained by differentiating the feedback signal from the input signal, and the amplification circuit. A second integrator 5 which has a resistance element R5 and a capacitance element C5 and integrates a second difference signal obtained by subtracting a feedback signal from the first integrator 3 output from the first integrator 3 and a second integrator 5 A comparator 7 that binarizes the second integrated signal output from, a quantizer 9 that outputs a digital signal based on the second integrated signal binarized by the comparator 7, and an analog signal for the digital signal. A digital-analog converter 11 that generates a feedback signal by converting to is provided.

At this time, the resistance value R _LPF of the resistance element R5 and the capacitance value C _LPF of the capacitance element C5 are the gain γ in the comparator 7, the amplification factor A in the amplification circuit 30 in the first integrator 3, and the first integrator. It is set based on _{the resistance value R nf} of the resistance element R3 _{in No. 3 and the capacitance value C nf} of the capacitor C3 in the first integrator 3. As a result, according to the ΔΣ ADC circuit 1 according to the embodiment, the first transfer function (Y _nf / X _nf ) and the second transfer function (Y _LPF / X _LPF ) are the same.

From these facts, since the ΔΣ ADC circuit 1 according to the embodiment does not have an amplifier circuit that consumes power in the second integrator 5 in the previous stage of the comparator 7, the order of the ΔΣ ADC circuit can be determined without increasing the power consumption. You can raise one. As a result, according to the ΔΣ ADC circuit 1 according to the embodiment, the performance can be improved without increasing the power consumption.

FIG. 5 is a diagram showing an example of comparison of noise shaping (NS) waveforms in the conventional ΔΣ ADC circuit (3rd order) and the ΔΣ ADC circuit (4th order) according to the present embodiment at the same power consumption. .. PA in FIG. 5 shows a noise shaping waveform related to a conventional ΔΣ ADC circuit. EI in FIG. 5 shows a noise shaping waveform related to the ΔΣ ADC circuit 1 according to the present embodiment. As shown in FIG. 5, in the frequency band AFB after the input signal IS, the conventional noise shaping waveform PA has a third-order noise shaping waveform (gradient: 60 dB / decline), whereas the noise according to the present embodiment. The shaping waveform EI is a fourth-order noise shaping waveform (gradient: 80 dB / decade). In addition, as shown in FIG. 5, in the frequency band BFB before the input signal IS, the noise shaping waveform EI according to the present embodiment has a smaller amplitude than the conventional noise shaping waveform PA. From these facts, according to the ΔΣ ADC circuit 1 according to the embodiment, the performance of the ΔΣ ADC circuit is improved without power consumption, that is, the signal-to-noise ratio (Signal-noise ratio: hereinafter referred to as SNR) is improved. Can be done.

FIG. 6 is a diagram showing an example of an index of power efficiency with respect to frequency (hereinafter referred to as FOM (Figure of Merit)) in the ΔΣ ADC circuit according to the present embodiment having the same order as the conventional ΔΣ ADC circuit. As shown in FIG. 6, the FOM in the ΔΣ ADC circuit according to the present embodiment is increased as compared with the conventional ΔΣ ADC circuit. That is, according to the ΔΣ ADC circuit 1 according to the embodiment, the power efficiency can be improved, that is, the power consumption can be reduced as compared with the conventional ΔΣ ADC circuit in the same order.

FIG. 7 is a diagram showing an example of a continuous-time type and differential type fourth-order ΔΣ ADC circuit 4 as an application example of the present embodiment. At this time, the ΔΣ ADC circuit 4 becomes stronger against common mode noise, that is, noise of the in-phase signal due to the differential voltage. Further, in the ΔΣ ADC circuit 4 shown in FIG. 7, a route of local feedback (local feedback) is described. As a result, the stability of the ΔΣ ADC circuit 4 is improved. The local feedback can be omitted as appropriate.

From the above, according to the ΔΣ ADC circuit 1 or the ΔΣ ADC circuit 4 according to the present embodiment, the power consumption can be reduced as compared with the conventional ΔΣ ADC circuit if the order is the same, and the power consumption is the same. , As shown in FIG. 5, the performance can be improved, that is, the SNR can be improved.

Although the embodiments of the present invention have been described above, the above-described embodiments are presented as examples and are not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalent scope thereof.

1 ΔΣADC circuit 2 Comparison ΔΣADC
3 1st integrator 4 ΔΣADC circuit 5 2nd integrator 7 Comparer 9 Quantifier 11 DAC circuit 30 Amplifier circuit 31 1st integrator 32 2nd integrator 33 3rd integrator 34 4th integrator 111, 112, 113, 114 Multiple DAC circuits 311 Amplifier circuit 321 Amplifier circuit

Claims (4)

A first integrator that has an amplifier circuit and integrates the first difference signal that is the difference between the input signal and the feedback signal.
A second integrator that does not have an amplification circuit, has a resistance element and a capacitance element, and integrates a second difference signal obtained by subtracting the feedback signal from the first integrator output from the first integrator.
A comparator that binarizes the second integrator signal output from the second integrator, and
A quantizer that outputs a digital signal based on the binarized signal output from the comparator, and
A digital-to-analog converter that generates the feedback signal by converting the digital signal into an analog signal.
Delta-sigma ADC circuit with. The first transfer function of the first integrator and the second transfer function of the second integrator are the same.
The delta-sigma ADC circuit according to claim 1. The second integrator is a low-pass filter.
The delta-sigma ADC circuit according to claim 1 or 2. The resistance value of the resistance element and the capacitance value of the capacitance element are the gain in the comparator, the amplification factor in the amplifier circuit in the first integrator, the resistance value of the resistance element in the first integrator, and the above. Set based on the capacitance value of the capacitive element in the first integrator,
The delta-sigma ADC circuit according to any one of claims 1 to 3.

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