JP2021125874A - Power amplification circuit and semiconductor device - Google Patents

Abstract

To strengthen the thermal coupling between transistors in a power amplification circuit.SOLUTION: A power amplification circuit includes: a transistor 101 formed on a semiconductor substrate 301; a transistor 111 supplying bias current to the transistor 101 on the basis of a part of control current; a transistor 112 in which the current flowing therein increases as the temperature increases; and a wiring part W1 connected electrically to an emitter of the transistor 111 and including a second emitter wire 202 and a bump 203 stacked to face the semiconductor substrate 301. At least one of the second emitter wire 202 and the bump 203 extends so as to overlap with an arrangement region where the transistor 112 is disposed from at least a part of an arrangement region where the transistor 101 is disposed in a plan view of the semiconductor substrate 301.SELECTED DRAWING: Figure 3

Description

The present invention relates to power amplifier circuits and semiconductor devices.

A power amplifier circuit is used to amplify a radio frequency (RF) signal in mobile communication. In a power amplifier circuit that amplifies power by a bipolar transistor formed on a semiconductor substrate, the characteristics of the transistor change due to heat generated by the transistor during amplification. The power amplifier circuit disclosed in Patent Document 1 prevents efficiency deterioration caused by an increase in the junction temperature of the transistors by thermally coupling a plurality of transistors.

Japanese Unexamined Patent Publication No. 2000-332124

In the power amplification circuit disclosed in Patent Document 1, the power amplification transistor and the potential generation transistor of the bias circuit that supplies the bias current to the power amplification transistor are thermally coupled by the metal electrode layer.

A semiconductor chip having a power amplifier circuit may be mounted on a substrate by a flip chip connection. In the flip chip connection, bumps are provided in the power amplifier circuit. The semiconductor chip is mounted on the substrate through bumps. When a semiconductor chip having a power amplifier circuit disclosed in Patent Document 1 is flip-chip mounted, heat conduction to the substrate side through the bump affects heat conduction between the transistors through the metal electrode layer, and sufficient heat is obtained. The bond cannot be realized.

The present invention has been made in view of such circumstances, and an object of the present invention is to strengthen the thermal coupling between transistors in a power amplifier circuit.

In the power amplification circuit according to one aspect of the present invention, the first transistor formed on the semiconductor substrate and the first current formed on the semiconductor substrate and which is a part of the control current are supplied to the base, and the first one. A second transistor that supplies a bias current based on the current to the first transistor, a second current that is formed on the semiconductor substrate and is a part of the control current is supplied, and a third current based on the second current is output. A current output element in which the second current increases as the temperature rises, and at least a part of the first arrangement region in which the first transistor is arranged, the first arrangement region, and the current output element are arranged. A wiring portion having a plurality of metal layers which are provided so as to overlap the region between the second arrangement region and which are electrically connected to the emitter of the first transistor and are laminated so as to face the semiconductor substrate. At least one of the plurality of metal layers is stretched so as to overlap at least a part of the first arrangement region to the second arrangement region in the plan view of the semiconductor substrate.

According to the present invention, it is possible to strengthen the thermal coupling between transistors in a power amplifier circuit.

It is a circuit diagram of the power amplifier circuit which concerns on 1st Embodiment. It is a layout figure of the power amplifier circuit which concerns on 1st Embodiment. It is sectional drawing at the cutting line III-III shown in FIG. It is a schematic diagram of another layout of the power amplifier circuit which concerns on 1st Embodiment. It is a schematic diagram of another layout of the power amplifier circuit which concerns on 1st Embodiment. It is a schematic diagram of another layout of the power amplifier circuit which concerns on 1st Embodiment. It is a schematic diagram of another layout of the power amplifier circuit which concerns on 1st Embodiment. It is a figure explaining an example of the operation of the power amplifier circuit. It is a figure explaining the rise of the output of the power amplifier circuit which concerns on 1st Embodiment. It is a layout figure of the modification of the power amplifier circuit which concerns on 1st Embodiment. It is sectional drawing in the cutting line XI-XI shown in FIG. It is a layout figure of another modification of the power amplifier circuit which concerns on 1st Embodiment. It is sectional drawing in the cutting line XIII-XIII shown in FIG. It is a layout figure of another modification of the power amplifier circuit which concerns on 1st Embodiment. It is sectional drawing in the cutting line XV-XV shown in FIG. It is a layout figure of another modification of the power amplifier circuit which concerns on 1st Embodiment. It is sectional drawing in the cutting line XVII-XVII shown in FIG. It is another cross-sectional view of the power amplifier circuit shown in FIG. It is a layout figure of the power amplifier circuit which concerns on 3rd Embodiment. It is sectional drawing in the cutting line XX-XX shown in FIG. It is sectional drawing in the cutting line XXI-XXI shown in FIG. It is a layout figure of the power amplifier circuit which concerns on 3rd Embodiment. FIG. 2 is a cross-sectional view taken along the line XXIII-XXIII shown in FIG. FIG. 2 is a cross-sectional view taken along the line XXIV-XXIV shown in FIG. It is a circuit diagram of the power amplifier circuit which concerns on 4th Embodiment. It is a layout figure of the power amplifier circuit which concerns on 4th Embodiment. It is a layout figure of the power amplifier circuit which concerns on 5th Embodiment. It is sectional drawing in the cutting line XXVIII-XXVII shown in FIG. 27. FIG. 2 is a cross-sectional view taken along the line XXVIV-XXVIV shown in FIG. 27.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same elements are designated by the same reference numerals, and duplicate explanations will be omitted as much as possible.

The power amplifier circuit 10 according to the first embodiment will be described. FIG. 1 shows a circuit diagram of the power amplifier circuit 10. The power amplifier circuit 10 includes transistors 101 to 10n, 111, 112, 113, capacitors 114, 131, resistance elements 115, 121, inductor 141, and matching circuit 151. The transistors 101 to 10n, 111, 112, and 113 are, for example, transistors such as a heterojunction bipolar transistor (HBT).

The transistors 101 to 10n are provided in the arrangement region A1 on the semiconductor substrate (not shown).

In each of the transistors 101 to 10n, the base is connected to the capacitor 131 and the resistance element 121, the collector is connected to the matching circuit 151, and the emitter is connected to the ground. A power supply voltage Vcc is supplied to the collector of each of the transistors 101 to 10n through the inductor 141.

Each transistor (first transistor) of the transistors 101 to 10n amplifies the signal RFin input from the input terminal 161. Each transistor of the transistors 101 to 10n amplifies the signal input to the base of each transistor based on the bias current Ib output by the transistor 111 (second transistor) described later. The signal amplified by each transistor is output as a signal RFout through the matching circuit 151.

The transistors 111, 112, 113, the capacitor 114, and the resistance element 115 are provided in the arrangement region A3 on the semiconductor substrate.

In the transistor 111 (second transistor), the base is connected to the resistance element 115, the collector is connected to the power supply, and the emitter is connected to the resistance element 121. The transistor 111 is switched between the on state and the off state by the current I1 supplied from the control input terminal 181 and supplied to the base based on the control current Ic flowing through the resistance element 115. When the transistor 111 is turned on, the transistor 111 outputs a bias current Ib.

The transistor 112 (current output element) is a diode-connected transistor, the collector is connected to the emitter of the transistor 113, and the emitter is connected to the ground. A current I2 is supplied to the collector of the transistor 112. The transistor 112 outputs the current I3 from the emitter based on the current I2. The transistor 112 is provided in the arrangement region A2 on the semiconductor substrate.

The transistor 113 is a diode-connected transistor, the collector is connected to the base of the resistance element 115 and the transistor 111, and the emitter is connected to the collector of the transistor 112. The transistor 113 outputs the current I2 to the collector of the transistor 112 based on the current I4 flowing through the collector based on the control current Ic.

One end of the capacitor 114 is connected to the base of the transistor 111, and the other end is connected to the ground. The capacitor 114 functions to allow an AC component of the control current Ic to flow to the ground. The resistance element 115 is provided to generate a predetermined voltage drop based on the control current Ic input from the control input end 181.

A bias circuit is composed of transistors 111, 112, 113, a capacitor 114, and a resistance element 115.

One end of the matching circuit 151 is connected to the collector of the transistors 101 to 10n, and the other end is connected to the output end 171. The matching circuit 151 matches the impedance between the collector of the transistors 101 to 10n and the output terminal 171.

The layout of the power amplifier circuit 10 according to the first embodiment on the semiconductor substrate will be described with reference to FIG. In FIG. 2, transistors 101, 102, 111, 112, 113 are schematically shown. Bias current is supplied to the transistors 101 and 102 from the transistor 111 through the power supply wiring 201. The signal RFin input from the input end (not shown) is also supplied to the transistors 101 and 102 through the power supply wiring 201.

The transistors 101 and 102 are arranged in the direction along the x-axis in the coordinate system of FIG. In the power amplifier circuit 10, a plurality of transistors 103 to 10n (not shown) are also arranged along the x-axis direction.

The transistors 112 are arranged so as to overlap each other in the arrangement direction of the transistors 101 to 10n. The transistor 113 and the transistor 111 are provided at positions separated from the transistor 112 along the y-axis direction.

The arrangement region A1 is covered with a boundary with an isolation region provided to electrically insulate the transistors 101 to 10n and other active devices formed on the same semiconductor substrate on the semiconductor substrate. Refers to the internal area.

When the isolation region is formed for each of the individual transistors 101 to 10n, the arrangement region A1 is determined by the envelope of each isolation region so as to include the isolation region of each transistor. ..

The arrangement region A3 is an isolation region provided for electrically insulating the plurality of active elements for supplying the bias current Ib to the transistors 101 to 10n and the other active elements on the semiconductor substrate. Based on. The arrangement region A3 refers to an internal region in which the outermost sides of the boundary line with the isolation region of each active element in each of the x-axis direction and the y-axis direction are enveloped by a straight line parallel to each of the x-axis and the y-axis. ..

The arrangement region A2, like the arrangement regions A1 and A3, refers to an internal region covered by the boundary of an isolation region provided to insulate the transistor 112 and other active elements on the semiconductor substrate.

The second emitter wiring 202 is provided on the transistors 101 to 10n and the transistor 112 so as to be connected to the transistors 101 to 10n and the transistor 112. The second emitter wiring 202 extends from the arrangement region A1 to the arrangement region A2. That is, the second emitter wiring 202 is extended along the x-axis direction.

The bump 203 is provided along the second emitter wiring 202 so as to cover the transistors 101 to 10n and the transistor 112. The bump 203 extends from the placement area A1 to the placement area A2. That is, the bump 203 is stretched along the x-axis direction. The bump is, for example, a copper pillar bump.

In the layout described with reference to FIG. 2, the bump 203 may be provided so as to cover the transistors 101 to 10n and the transistor 112. The arrangement direction of the transistors 101 to 10n and the positions of the transistors 111, 112, 113 are not limited to the layout shown in FIG.

Examples of other layouts are shown in FIGS. 4 to 7. The layout diagrams of FIGS. 4 to 7 show variations in the arrangement region based on the relationship between each transistor and the isolation region of each transistor. In FIGS. 4 to 7, an isolation region B1 is provided on the semiconductor substrate 301, and the relationship between the isolation region B1 and the arrangement regions A1 to A3 is shown.

The cross-sectional structure of the power amplifier circuit 10 will be described with reference to FIG.

Transistors 101 and 102 will be described. Transistors 101 and 102 are formed on the semiconductor substrate 301. The detailed structure describes the transistor 102. The sub-collector layer 302 is formed on the semiconductor substrate 301. The material of the semiconductor substrate 301 is, for example, semi-insulating GaAs. The material of the sub-collector layer 302 is, for example, a high-concentration n-type GaAs. The thickness of the sub-collector layer 302 is, for example, 0.5 μm.

The collector layer 303 is formed on the sub collector layer 302. The material of the collector layer 303 is, for example, n-type GaAs. The thickness of the collector layer 303 is, for example, 1 μm. The base layer 304 is formed on the collector layer 303. The material of the base layer 304 is, for example, p-type GaAs. The thickness of the base layer 304 is, for example, 100 nm.

The emitter layer 305 is formed on the base layer 304. The emitter layer 305 has an intrinsic emitter layer 305A and an emitter mesa layer 305B. The intrinsic emitter layer 305A is formed on the base layer 304. An emitter mesa layer 305B is formed on the intrinsic emitter layer 305A. The material of the intrinsic emitter layer 305A is, for example, n-type InGaP. The thickness of the intrinsic emitter layer 305A is, for example, 30 nm or more and 40 nm or less. The material of the emitter mesa layer 305B is, for example, a high concentration n-type GaAs and a high concentration n-type InGaAs. In the emitter mesa layer 305B, for example, a layer of high-concentration n-type InGaAs having a thickness of 100 nm is formed on a high-concentration n-type GaAs layer having a thickness of 100 nm.

A ledge layer 306 is formed in a region on the upper surface of the base layer 304 where the emitter layer 305 is not formed. The ledge layer 306 is formed at the same time as the intrinsic emitter layer 305A and has the same composition as the intrinsic emitter layer 305A. Since the emitter mesa layer 305B is not formed on the ledge layer 306, the ledge layer 306 is depleted. Therefore, it does not function as a transistor emitter. Therefore, the intrinsic emitter layer 305A and the emitter mesa layer 305B are referred to as the emitter layer 305, and the ledge layer 306 is distinguished from the emitter layer 305.

The transistor 102 is composed of the collector layer 303, the base layer 304, and the emitter layer 305. The same applies to the transistor 101.

The base electrode 331 is provided on the base layer 304. The base electrode 331 makes ohmic contact with the base layer 304 through an opening provided in the ledge layer 306. In the transistors 101 and 102, the base electrode 331 is provided between the emitter layers 305 of each transistor.

The collector electrode 332 is provided on the sub-collector layer 302. The collector electrode 332 is in ohmic contact with the sub-collector layer 302. The collector electrode 332 is provided between the transistor 101 and the transistor 102 in the x-axis direction. The collector electrode 332 is connected to the collector layer 303 through the sub collector layer 302. The collector electrode 332 is commonly used for the transistor 101 and the transistor 102.

The emitter electrode 333 is provided on the emitter layer 305. The emitter electrode 333 makes ohmic contact with the emitter layer 305.

The base electrode 331 is formed by sequentially laminating, for example, a Ti film, a Pt film, and an Au film on the base layer 304. The collector electrode 332 is formed by, for example, laminating an AuGe film, a Ni film, and an Au film on the sub-collector layer 302 in this order. The emitter electrode 333 is formed of, for example, a Ti film having a thickness of 50 nm.

The sub-collector layer 302 is provided with an isolation region 3021 for performing isolation between elements. The isolation region 3021 is formed by insulating a part of the sub-collector layer 302 by using, for example, an ion implantation technique. The part of the sub-collector layer 302 is a part in the xy plane. The isolation region 3021 is formed in a part thereof over the entire z-axis direction of the sub-collector layer 302. The isolation region 3021 may be formed so as to include a part of the semiconductor substrate 301 in addition to the sub-collector layer 302 in the z-axis direction.

The transistor 112 will be described. The sub-collector layer 3022 is formed on the semiconductor substrate 301. A collector layer 3031 is formed on the sub collector layer 3022. The base layer 3041 is formed on the collector layer 3031. An emitter layer 3051 and a ledge layer 3061 are formed on the base layer 3041. The emitter layer 3051 has an intrinsic emitter layer 3051A and an emitter mesa layer 3051B. The relationship between the intrinsic emitter layer 3051A, the emitter mesa layer 3051B, and the ledge layer 3061 is the same as the relationship between the intrinsic emitter layer 305A, the emitter mesa layer 305B, and the ledge layer 306.

The collector layer 3031, the base layer 3041, and the emitter layer 3051 constitute the transistor 112.

The transistor 112 is formed by the same process as the formation of the transistors 101 and 102. Therefore, the transistor 112 has the same temperature characteristics as the transistors 101 and 102.

The base electrode 3311 is provided on the base layer 3041. The base electrode 3311 makes ohmic contact with the base layer 3041 through an opening provided in the ledge layer 3061. The collector electrode 3321 is provided on the sub-collector layer 3022. The collector electrode 3321 makes ohmic contact with the sub-collector layer 3022. The collector electrode 3321 is connected to the collector layer 3031 through the sub collector layer 3022. The emitter electrode 3331 is provided on the emitter layer 3051. The emitter electrode 3331 makes ohmic contact with the emitter layer 3051.

The base electrode 3311, the collector electrode 3321, and the emitter electrode 3331 are formed by the same process in which the base electrode 331, the collector electrode 332, and the emitter electrode 333 are formed, respectively.

The first insulating layer 321 is provided so as to cover the transistors 101, 102 and 112. The first insulating layer 321 has, for example, a laminated structure of a SiN layer and a resin layer. The first insulating layer 321 may be formed only by the SiN layer.

The first insulating layer 321 is provided with the first layer collector wirings 341 and 3411. The collector wiring 341 of the first layer is provided so as to pass through the first insulating layer 321 and connect to the collector electrode 332. The collector wiring 3411 of the first layer is provided so as to pass through the first insulating layer 321 and connect to the collector electrode 3321.

The first emitter wirings 351 and 3511 are provided on the first insulating layer 321. The first emitter wiring 351 is provided in each of the transistors 101 and 102, respectively. The first emitter wiring 351 connects the emitter electrode 333 of each transistor. The collector wiring 341 of the first layer and the emitter wiring 351 of the first layer have a laminated structure including, for example, a Ti film having a thickness of 10 nm or more and 50 nm or less and an Au film having a thickness of 1 μm or more and 2 μm or less. The first emitter wiring 3511 is provided on the transistor 112. The material and structure of the first emitter wiring 3511 are the same as those of the first emitter wiring 351.

A second insulating layer 322 is provided on the first insulating layer 321 so as to cover the first collector wirings 341 and 3411 and the first emitter wirings 351 and 3511. The second insulating layer 322 has, for example, a laminated structure of a SiN layer and a resin layer. The second insulating layer 322 may be formed only by the SiN layer.

A second emitter wiring 202 is provided on the second insulating layer 322. The second emitter wiring 202 is connected to the first emitter wiring 351 through an opening provided in the second insulating layer 322. The first emitter wiring 351 of the transistors 101 and 102 arranged in the x-axis direction is connected by the second emitter wiring 202. The second emitter wiring 202 has a laminated structure including, for example, a Ti film having a thickness of 10 nm or more and 50 nm or less and an Au film having a thickness of 2 μm or more and 4 μm or less. The second emitter wiring 202 extends to the top of the transistor 112.

A third insulating layer 323 is provided on the second emitter wiring 202 so as to cover the second emitter wiring 202. The third insulating layer 323 has, for example, a laminated structure composed of a SiN film and a resin film. The third insulating layer 323 may be formed only of the SiN film. The third insulating layer 323 functions as a protective film that protects the transistors 101, 102, 112.

The bump 203 is provided on the third insulating layer 323. The bump 203 is connected to the second emitter wiring 202 through the opening of the third insulating layer 323. The bump 203 has a laminated structure in which the under bump metal layer 3111, the metal post 3112, and the solder layer 3113 are laminated in this order.

For the underbump metal layer 3111, for example, a Ti film having a thickness of 50 nm or more and 100 nm or less is used. The underbump metal layer 3111 has a function of improving the adhesion of the bump 203 to the third insulating layer 323.

For the metal post 3112, for example, a Cu film having a thickness of 30 μm or more and 50 μm or less is used. For the solder layer 3113, for example, a Sn or SnAg alloy film having a thickness of 10 μm or more and 30 μm or less is used.

A barrier metal layer made of Ni or the like for preventing mutual diffusion may be arranged between the metal post 3112 and the solder layer 3113.

The bump 203 functions as a metal member for releasing the heat generated by the transistors 101 and 102 to the outside.

The wiring portion W1 is composed of the second emitter wiring 202 and the bump 203, which are two metal layers. Further, the second emitter wiring 202 and the bump 203 are members having different shapes.

The heat transfer and thermal coupling generated by the transistors 101 and 102 will be described.

Transistors 101 and 102 generate heat during operation. The transistors 101 and 102 operate by supplying a bias current Ib from the transistor 111.

In the transistors 101 and 102, an operating current flows from the collector layer 303 through the base layer 304 to the emitter layer 305. Of the collector layer 303, the base layer 304, and the emitter layer 305, the region in which the operating current actually flows flows substantially coincides with the emitter layer 305 in a plan view. When the operating current flows through the collector layer 303, the base layer 304, and the emitter layer 305, Joule heat is generated and the temperatures of the transistors 101 and 102 rise.

The heat generated in the transistors 101 and 102 flows to the second emitter wiring 202 through the emitter electrode 333. The heat flowing through the second emitter wiring 202 flows through the second emitter wiring 202 in the x-axis direction and the z-axis direction.

The heat flowing from the second emitter wiring 202 in the z-axis direction flows to the bump 203. The heat flowing to the bump 203 flows in the x-axis direction and the z-axis direction. The heat flowing in the z-axis direction in the bump 203 flows to the substrate on which the semiconductor chip is installed when the semiconductor chip having the power amplification circuit 10 is flip-chip connected.

The heat flowing in the x-axis direction in the second emitter wiring 202 raises the temperature of the second emitter wiring 202 above the transistor 112. The heat flowing in the x-axis direction of the bump 203 raises the temperature of the bump 203 above the transistor 112. When the temperature of the second emitter wiring 202 and the bump 203 near the upper part of the transistor 112 rises, the temperature of the transistor 112 rises due to heat conduction in the z-axis direction.

When the second emitter wiring 202 and the bump 203 are not extended to the vicinity of the upper part of the transistor 112, the heat conduction to the transistor 112 by the second emitter wiring 202 and the bump 203 is not sufficiently performed. In this case, the amount of increase in the temperature of the transistor in the bias circuit is smaller than the amount of increase in the temperature of the transistor 112.

Like the relationship between the transistor 112 and the transistors 101 and 102, the change in temperature of one element so that the temperature of the other element approaches the temperature of one element is called thermal coupling. In the power amplifier circuit 10, the temperature of the transistor 112 changes so as to be closer to the temperature of the transistors 101 and 102 as compared with the case where the second emitter wiring 202 and the bump 203 are not extended to the vicinity of the upper portion of the transistor 112. That is, the thermal coupling between the transistors 101 and 102 and the transistor 112 becomes stronger.

The operation of the circuit will be described with reference to FIG. When the transistors 101 to 10n operate, the temperature of the transistors 101 to 10n rises. As the temperature of the transistors 101 to 10n rises, the collector current of the transistors 101 to 10n increases. As the collector current increases, the gain of the transistors 101 to 10n increases.

With the second emitter wiring 202 and bump 203, the heat generated by the transistors 101-10n raises the temperature of the transistor 112. When the temperature of the transistor 112 rises, the forward voltage of the transistor 112 as a diode decreases. As the forward voltage drops, the current I2 and the current I3 increase. As the current I2 and the current I3 increase, the current I1 which is the base current of the transistor 111 decreases.

When the current I1 decreases, the bias current Ib output by the transistor 111 decreases. As the bias current Ib decreases, the current supplied to each base of the transistors 101 to 10n decreases, so that the collector current of the transistors 101 to 10n decreases. In the power amplifier circuit 10, the collector current can be further reduced as compared with the case where the thermal coupling is insufficient. By further suppressing the increase in the collector current, it is possible to further suppress the gain fluctuation accompanying the increase in the gain of the transistors 101 to 10n.

The transistor 112 as a current output element can also be replaced by a diode such that the forward voltage decreases and the current I2 increases as the temperature rises. Further, as the current output element, any element can be used as long as it is a current output element in which the current I2 increases as the temperature rises.

An example of suppressing gain fluctuation by the power amplifier circuit 10 is shown. FIG. 8 shows the time change of the collector current of the transistor that performs the intermittent operation. The intermittent operation means an operation in which, in addition to the signal amplified by the transistor as shown between the times T2 and T3, the idle current flowing when the transistor is in the off state is started up and down immediately before the signal is input. do.

The current in intermittent operation changes as follows. The idle current is turned on at time T1. At time T2, the amplification signal is turned on in addition to the idle current. At time T3, the amplified signal is turned off. At time T4, the idle current is turned off.

A transistor that performs such an intermittent operation may cause a gain fluctuation due to heat generation after the time T2. In the power amplifier circuit 10, the balance of the temperature states of the transistors 101 to 10n and the transistors 112 is ensured through the second emitter wiring 202 and the bump 203, so that the gain increase can be suppressed.

Further, the temperature of the transistor that performs the intermittent operation changes because the calorific value of the emitter changes significantly before the time T1 when the idle current is turned on and between the time T1 and the time T2. Gain fluctuations can also occur due to this temperature fluctuation. Similarly, in the power amplifier circuit 10, it is possible to secure the balance of the temperature states of the transistors 101 to 10n and the transistors 112 and suppress the increase in gain.

The gain increase can be suppressed by balancing the temperature states of the transistors 101 to 10n and the transistor 112 not only in the intermittent operation but also in the change of the current that may cause the temperature increase.

FIG. 9 shows a performance comparison between a power amplifier circuit having the configuration of the power amplifier circuit 10 and a power amplifier circuit (comparative example) in which the wiring portion W1 is not extended near the upper portion of the transistor 112. The horizontal axis of FIG. 5 is the time t [ms], and the vertical axis is the output power Pout [dBm]. The frequency of the input signal is 3.75 GHz. In FIG. 5, the fluctuation of the output power Pout is shown until the output power Pout reaches the target value of 20 dBm. In the case of the comparative example shown by the broken line in FIG. 5, the fluctuation amount of the output power Pout until reaching 20 dBm is 0.4 dBm. In the case of the power amplifier circuit 10 shown by the solid line in FIG. 5, the fluctuation amount of the output power Pout is 0.2 dBm. As described above, in the power amplifier circuit 10, since the gain fluctuation due to the temperature fluctuation is suppressed, the fluctuation amount of the output power Pout is smaller than that in the comparative example.

Further, as shown in the layout diagram of FIG. 10 and the cross-sectional view of FIG. 11, the second emitter wiring 202 and the bump 203 do not necessarily completely cover the arrangement region A2 in which the transistor 112 is arranged. The temperature state of the transistor in the arrangement region A1 may be transmitted to the transistor in the arrangement region A2 by the second emitter wiring 202 and the bump 203.

In the layout diagram of FIG. 10 and the cross-sectional view of FIG. 11, the second emitter wiring 202 reaches the transistor 112 in the arrangement region A2, but the bump 203A does not reach the transistor 112. In this case, the wiring portion W2 is composed of the second emitter wiring 202 and the bump 203A, which are two metal layers.

Further, in the layout diagram of FIG. 12 and the cross-sectional view of FIG. 13, the bump 203 reaches the transistor 112 in the arrangement region A2, but the second emitter wiring 202A does not reach the transistor 112. In this case, the wiring portion W3 is composed of the second emitter wiring 202A and the bump 203, which are two metal layers.

The bump 203 may be formed so as to be arranged from the arrangement area A1 in the area between the arrangement area A1 and the arrangement area A3 including the arrangement area A2. More specifically, the second emitter wiring 202 and the bump 203 may cover the transistors 111, 112, 113 arranged in the arrangement region A3. FIG. 14 shows a layout diagram in which the second emitter wiring 202B and the bump 203B are extended to the transistor 113.

FIG. 15 shows a cross-sectional view taken along the cutting line XV-XV of FIG. The positions of the electrodes of the transistor 112 are reversed as compared with the case of FIG.

The transistor 113 will be described. Like the transistor 112, the transistor 113 has a collector layer 15031, a base layer 15041, an emitter layer 15051, and a ledge layer 15061 on the sub-collector layer 15022. The emitter layer 15051 has an intrinsic emitter layer 15051A and an emitter mesa layer 15051B. The transistor 113 is composed of the collector layer 15031, the base layer 15041, and the emitter layer 15051. Similar to the transistor 112, the transistor 113 is formed with a base electrode 15311, a collector electrode 15321, and an emitter electrode 15331.

Transistors 113 are formed by the same process as the formation of transistors 101 and 102. Therefore, the transistor 113 has the same temperature characteristics as the transistors 101 and 102.

The first insulating layer 321 is provided with the first-layer collector wiring 15411 as well as the first-layer collector wiring 3411. The first insulating layer 321 is provided with the first emitter wiring 15511 as well as the first emitter wiring 3511. The collector wiring 3411 of the first layer and the emitter wiring 15511 of the first layer are connected by the wiring 1501 provided in the first insulating layer 321.

A second emitter wiring 202B and a bump 203B are extended from the transistor 112 side on the transistor 113.

When the bump 203 is stretched in this way, the current fluctuations based on the changes in the temperature characteristics of the transistor 112 and the transistor 113 cancel each other out so as not to affect the bias current Ib. That is, the tendency of the transistor 112 to increase I2 and the tendency of the transistor 113 to decrease the collector current caused by the transistor 111's base current I1 cancel each other out. Therefore, the thermal coupling between the transistors 101 to 10n and the transistors 112 can be strengthened in the same manner as in the power amplifier circuit 10.

The second emitter wiring 202 or bump 203 may be extended from the transistors 101 and 102 to the vicinity of the upper portion of the transistor 113 only. In this case, the transistor 113 functions as a current output element. Heat conduction is performed from the transistors 101 and 102 to the transistor 113 through the emitter wiring 202 or the bump 203. Therefore, the thermal coupling between the transistors 101 to 10n and the transistors 113 can be strengthened in the same manner as in the power amplifier circuit 10. By raising the temperature of the transistor 113 by thermal coupling, the collector current of the transistors 101 to 10n can be reduced and the gain fluctuation during operation can be suppressed as in the case where the transistor 112 is thermally coupled.

The second embodiment will be described. In the second and subsequent embodiments, the description of matters common to those of the first embodiment will be omitted, and only the differences will be described. In particular, the same action and effect due to the same configuration will not be mentioned sequentially for each embodiment.

In the power amplifier circuit according to the second embodiment, as shown in FIG. 16, each transistor is provided as in the first embodiment. FIG. 17 shows a cross-sectional view taken along the cutting line XVII-XVII.

The power amplifier circuit according to the second embodiment shown in FIG. 17 is different from the power amplifier circuit according to the first embodiment in that a protruding portion 2021 is provided in the second emitter wiring 202C.

The protrusion 2021 extends toward the first emitter wiring 3511 through the opening of the second insulating layer 322. The protrusion 2021 makes ohmic contact with the first emitter wiring 3511.

In the power amplifier circuit according to the second embodiment, the second emitter wiring 202C on the upper part of the transistor 112 is located closer to the transistor 112 as shown in FIG. As a result, more heat is conducted from the second emitter wiring 202C to the transistor 112. Therefore, the temperature of the transistor 112 rises further and becomes closer to the temperature of the transistors 101 and 102. That is, the thermal coupling becomes stronger than in the case of the power amplifier circuit according to the first embodiment. When the thermal coupling becomes stronger, the change in the characteristics of the transistor due to the temperature fluctuation can be more appropriately balanced, and the gain can be suppressed more strongly.

Further, the protruding portion may be provided on the bump 203. In the cross-sectional view of another power amplifier circuit according to the second embodiment of FIG. 18, the case where the protrusion 2031 is provided on the bump 203C by the under bump metal layer 3111A and the metal post 3112A is shown. The protrusion 2031 extends toward the second emitter wiring 202 through the opening of the third insulating layer 323. The protrusion 2031 makes ohmic contact with the second emitter wiring 202. Even with this configuration, the thermal coupling becomes stronger than in the case of the power amplifier circuit according to the first embodiment. Therefore, the gain can be suppressed more strongly.

A third embodiment will be described. FIG. 19 is a layout diagram of the power amplifier circuit according to the third embodiment. In the power amplifier circuit according to the third embodiment, the second emitter wiring 202 in the above-described embodiment is provided on the second emitter wiring 202a provided on the transistors 101 to 10n and the transistor 112 and on the transistor 113. It is separated from the second emitter wiring 202b.

In the power amplifier circuit according to the third embodiment, wiring 1901 is provided between the bump 203D and the second emitter wirings 202a and 202b in the z-axis direction. Wiring 1901 is made of a metal material. The wiring 1901 is provided along the emitter wiring 202 of the transistors 101 to 10n in the arrangement region A1 and so as to overlap the transistor 113 in the arrangement region A3. The parts other than the wiring 1901 on the same layer as the wiring 1901 are isolated for insulation. Wiring 1901 can also be called rewiring.

FIG. 20 shows a cross-sectional view taken along the cutting line XX-XX. Wiring 1901 has a first metal portion 2001 and a second metal portion 2002. The wiring 1901 is isolated by the insulating layer 2003 as needed. The second emitter wiring 202b, wiring 1901, and bump 203 are located above the transistor 113. Further, protrusions 20011a and 2031 are provided on the wiring 1901 and the bump 203A on the transistor 113, respectively. The wiring portion W7 is composed of the second emitter wiring 202, the wiring 1901, and the bump 203D, which are three metal layers.

Further, FIG. 21 shows a cross-sectional view taken along the cutting line XXI-XXI. In FIG. 21, the second emitter wiring 202a and wiring 1901 are located above the transistor 112. Further, the second emitter wiring 202a and the wiring 1901 on the transistor 112 are provided with protruding portions 2021,2001b and 20011c, respectively. In this case, the wiring portion W7 is partially composed of two metal layers, a second emitter wiring 202a and wiring 1901.

In this way, even when the second emitter wiring 202 is separated into the second emitter wiring 202a and the second emitter wiring 202b, the arrangement area A1 is changed to the arrangement areas A2 and A3 through the wiring 1901. It becomes possible to transport heat. Therefore, the gain fluctuation during operation can be suppressed more effectively.

Further, as a modification of the third embodiment, even when the layout shown in FIG. 22 is made, heat transfer can be performed by similarly providing wiring. In the layout shown in FIG. 22, the second emitter wiring 202 is the second emitter wiring 202c provided on the transistors 101 to 10n, the second emitter wiring 202d provided on the transistor 112, and the transistor 113. It is separated from the second emitter wiring 202e provided above.

In the layout shown in FIG. 22, the wiring 2201 is provided between the bump 203E and the second emitter wirings 202c, 202d, 202e in the z-axis direction. Wiring 2201 is made of a metal material. The wiring 2201 is provided so as to overlap the transistors 101 to 10n, 112, and 113 in the arrangement regions A1, A2, and A3, respectively. The parts other than the wiring 2201 on the same layer as the wiring 2201 are isolated for insulation. The wiring 2201 can also be called rewiring.

FIG. 23 shows a cross-sectional view taken along the cutting line XXIII-XXIII. The wiring 2201 has a first metal portion 2301 and a second metal portion 2302. The wiring 2201 is isolated by the insulating layer 2303 as needed. The second emitter wiring 202d, wiring 2201 and bump 203E are located above the transistor 113. Further, the wiring 2201 on the transistor 113 is provided with a protruding portion 23011a. The wiring portion W8 is composed of the second emitter wiring 202, the wiring 2201 and the bump 203E, which are three metal layers.

Further, FIG. 24 shows a cross-sectional view taken along the cutting line XXIV-XXIV. In FIG. 24, the second emitter wiring 202d and wiring 2201 are located above the transistor 112. The second emitter wiring 202d on the transistor 112 is provided with a protrusion 2021A. The wiring 2201 is provided with protrusions 23011b and 23011c, respectively.

From the modified examples shown in FIGS. 22 to 24, it is clear that the wiring 2201 dramatically improves the degree of freedom in designing the thermal coupling in the arrangement regions A1, A2 and A3.

A fourth embodiment will be described. FIG. 25 shows a circuit diagram of the power amplifier circuit 10A according to the fourth embodiment. The power amplifier circuit 10A is different from the power amplifier circuit according to the conventional embodiments in that the transistors 101 to 10n are provided in the two arrangement regions A11 and the arrangement region A22. The transistor 111 supplies the bias current Ib to the transistors 101 to 10n through the resistance elements 121a and 121b.

FIG. 26 shows a layout diagram of the power amplifier circuit 10A. In the power amplifier circuit 10A, the second emitter wiring 202 is provided on a part of the transistors 101 to 10n, that is, on the arrangement region A11, and the second emitter wiring 202f and another part of the transistors 101 to 10n. On the top, that is, the second emitter wiring 202g provided on the arrangement region A12, the second emitter wiring 202h provided on the transistor 112, and the second emitter wiring 202i provided on the transistor 113. It is separated.

In the layout shown in FIG. 26, the wiring 2601 is provided between the bumps 203a and 203b in the z-axis direction and the second emitter wirings 202f, 202g, 202h and 202i. The wiring 2601 is made of a metal material. The wiring 2601 is provided so as to overlap the transistors 101 to 10n, 112 and 113 in the arrangement regions A11, A12, A2 and A3. The parts other than the wiring 2601 on the same layer as the wiring 2601 are isolated for insulation. The wiring 2601 can also be called rewiring.

As shown in FIG. 26, even when the arrangement region A11 is divided into a plurality of regions like the arrangement area A12, the gain fluctuation during operation can be suppressed by applying the present invention. At this time, the arrangement area A1 having the arrangement areas A11 and A12 and the arrangement area A2 are connected by the wiring 2601.

A fifth embodiment will be described. FIG. 27 shows a layout diagram of the power amplifier circuit according to the fifth embodiment.

In the layout shown in FIG. 27, the second emitter wiring 202 is provided on the second emitter wiring 202j provided on the first emitter wiring 351a of the transistor 101 and on the first emitter wiring 351b of the transistor 101. It is separated into a second emitter wiring 202k and a second emitter wiring 202l provided on the transistor 113. Further, the wiring 2701 is provided along the collector wiring 341 shown in FIG. 3 and so as to connect the ground between the transistors 101 to 10n. Further, a bump 2702 is provided on the wiring 2701.

Wiring 2703 is provided between the bump 203F and the bump 2702 and the second emitter wiring 202j, 202k, 202l and the wiring 2701 in the z-axis direction. Wiring 2703 is made of a metal material. The wiring 2703 is provided so as to overlap the transistors 101 to 10n, 112 and 113 in the arrangement regions A1, A2 and A3, respectively. The parts other than the wiring 2701 on the same layer as the wiring 2703 are isolated for insulation.

FIG. 28 shows a cross-sectional view taken along the cutting line XXVIII-XXVIII. Wiring 2703 has a first metal portion 2801 and a second metal portion 2802. Wiring 2703 is isolated as needed by the insulating layer 2803. The second emitter wiring 202l and wiring 2703 are located above the transistor 113. Further, the wiring 2703 on the transistor 113 is provided with a protruding portion 28011a. The wiring portion W9 is composed of the second emitter wiring 202, the wiring 2703, the bump 203F, the wiring described later, and the like, which are three metal layers.

Further, FIG. 29 shows a cross-sectional view taken along the cutting line XXIX-XXIX. In FIG. 29, the wiring 2701 and the wiring 2703 are located above the transistor 112. Further, the wiring 2703 on the transistor 112 is provided with protrusions 28011b and 28011c, respectively. Also with this configuration, the thermal coupling between the transistors 101 to 10n and the transistors 112 can be strengthened, and the gain fluctuation during operation can be suppressed. The wiring portion W9 is composed of the wiring 2701, the wiring 2703, and the bump 203E, which are three metal layers.

The exemplary embodiments of the present invention have been described above. In the power amplification circuit 10 according to the first embodiment, the transistor 101 formed on the semiconductor substrate 301 and the current I1 formed on the semiconductor substrate 301 and which is a part of the control current Ic are supplied to the base, and the current I1 The transistor 111 that supplies the bias current Ib based on the current Ib to the transistor 101, and the transistor 112 that is formed on the semiconductor substrate 301 and is supplied with the current I2 that is a part of the control current Ic and outputs the current I3 based on the current I2. Therefore, the transistor 112 whose current I2 increases as the temperature rises overlaps with at least a part of the arrangement area A1 in which the transistor 101 is arranged and the area between the arrangement area A1 and the arrangement area A2 in which the transistor 112 is arranged. It has a second emitter wiring 202 which is electrically connected to the emitter of the transistor 111 and is laminated so as to face the semiconductor substrate 301, and a wiring portion W1 having a bump 203. At least one of the second emitter wiring 202 and the bump 203 is extended so as to overlap the arrangement region A2 from at least a part of the arrangement region A1 in the plan view of the semiconductor substrate 301.

With this configuration, heat can be transferred through the emitter wiring 202 and the bump 203. Therefore, the thermal coupling between the transistors 101 and 102, which generate heat during operation, and the transistor 112 becomes stronger. By strengthening the thermal coupling, the bias current Ib can be adjusted according to the change in the characteristics due to the temperature change of the transistor 101, so that the gain fluctuation during operation can be suppressed.

Further, in the power amplifier circuit 10, both the second emitter wiring 202 and the bump 203 of the wiring portion W1 may be extended so as to overlap the arrangement region A1 and the arrangement region A2. This allows heat to be conducted closer to the transistor 112. Therefore, the thermal coupling between the transistor 101 and the transistor 112 becomes stronger.

The uppermost metal layer of the wiring portion W1 is the bump 203. As a result, when the semiconductor device having the power amplifier circuit 10 is flip-chip connected, the bump 203, which is a heat path to the substrate side, is extended to the vicinity of the transistor 112. Therefore, the thermal coupling between the transistors 101 and 102 and the transistor 112 can be strengthened.

Further, in the power amplifier circuit according to the second embodiment, the second emitter wiring 202C has a protruding portion 2021 extending toward the transistor 112. As a result, the thermal coupling between the transistor 101 and the transistor 112 becomes stronger.

Further, as another power amplifier circuit, the wiring portion may be extended so as to overlap between the arrangement area 1 and the arrangement area A3. This aspect also makes it possible to strengthen the thermal coupling between the transistor 101 and the transistor 112.

Further, the wiring portion is extended so as to overlap the area between the arrangement area A1 and the arrangement area A2 and to overlap the arrangement area A3 which is the area between the arrangement area A1 and the arrangement area A3 and other than the area. May be good. This aspect also makes it possible to strengthen the thermal coupling between the transistor 101 and the transistor 112.

In the power amplification circuit according to the fourth embodiment, the transistor 101 formed on the semiconductor substrate 301 and the current I1 formed on the semiconductor substrate 301 and which is a part of the control current Ic are supplied to the base and become the current I1. A transistor 111 that supplies a bias current Ib based on the current Ib to the transistor 101, and a transistor 112 that is formed on the semiconductor substrate 301 and is supplied with a current I2 that is a part of the control current Ic and outputs a current I3 based on the current I2. The transistor 112 is provided so as to overlap the region between the transistor 112 in which the current I2 increases as the temperature rises, the arrangement region A1 in which the transistor 101 is arranged, and the arrangement area A1 in which the transistor 101 is arranged, and the arrangement area A2 in which the transistor 112 is arranged. It has a wiring portion W9 having a wiring 2701, a wiring 2703, and a bump 2702 that are electrically connected to the collector of 111 and are laminated so as to face the semiconductor substrate 301. Any one of the wiring 2701, the wiring 2703, and the bump 2702 is extended so as to overlap the arrangement region A2 from the arrangement region A1 in the plan view of the semiconductor substrate 301. This aspect also makes it possible to strengthen the thermal coupling between the transistor 101 and the transistor 112.

In addition, each embodiment described above can be used for each amplification stage of a power amplifier circuit. For example, in a power amplification circuit having a three-stage configuration, the thermal coupling between the transistor of the amplification stage and the bias circuit of the amplification stage can be strengthened in at least one amplification stage.

Further, as an example, in a power amplifier circuit having a three-stage configuration, not only the final stage but also the second stage transistor and its bias circuit, and the final stage transistor and its bias circuit are strengthened by strengthening the thermal coupling. , The gain increase is suppressed more.

It should be noted that each of the embodiments described above is for facilitating the understanding of the present invention, and is not for limiting the interpretation of the present invention. The present invention can be modified / improved without departing from the spirit thereof, and the present invention also includes an equivalent thereof. That is, those skilled in the art with appropriate design changes to each embodiment are also included in the scope of the present invention as long as they have the features of the present invention. For example, each element included in each embodiment and its arrangement, material, condition, shape, size, and the like are not limited to those exemplified, and can be changed as appropriate. Further, each embodiment is an example, and it goes without saying that the configurations shown in different embodiments can be partially replaced or combined, and these are also included in the scope of the present invention as long as the features of the present invention are included. ..

10, 10A ... Power amplifier circuit, 101, 102, 111, 112, 113 ... Transistor, 202, 202A, 202B, 202C ... Second emitter wiring, 2021, 2021A ... Projection, 203, 203A, 203B, 203C, 203D , 203E, 203F, 2702 ... Bump, 301 ... Semiconductor substrate, 1901,201,2601,2701,273 ... Wiring

Claims (16)

The first transistor formed on the semiconductor substrate and
A second transistor formed on the semiconductor substrate, a first current that is a part of the control current is supplied to the base, and a bias current based on the first current is supplied to the first transistor.
A current output device formed on the semiconductor substrate, supplied with a second current that is a part of the control current, and outputs a third current based on the second current, and the second current is generated as the temperature rises. With the current output element that increases
The first arrangement region is provided so as to overlap at least a part of the first arrangement region in which the first transistor is arranged and the region between the first arrangement region and the second arrangement region in which the current output element is arranged. It has a wiring portion that is electrically connected to the emitter of one transistor and has a plurality of metal layers that are laminated so as to face the semiconductor substrate.
A power amplifier circuit in which at least one of the plurality of metal layers is extended so as to overlap the second arrangement region from at least a part of the first arrangement region in a plan view of the semiconductor substrate. The power amplifier circuit according to claim 1.
A power amplifier circuit in which all layers of the plurality of metal layers of the wiring portion are extended so as to overlap the first arrangement region and the second arrangement region. The power amplifier circuit according to claim 1 or 2.
A power amplifier circuit in which the uppermost metal layer among the plurality of metal layers of the wiring portion is a bump. The power amplifier circuit according to any one of claims 1 to 3.
A power amplifier circuit in which at least one of the plurality of metal layers in the second arrangement region has a protrusion extending toward the current output element. The power amplifier circuit according to claim 4.
The wiring unit is a power amplifier circuit that is electrically connected to the current output element. The first transistor formed on the semiconductor substrate and
A second transistor formed on the semiconductor substrate, a first current that is a part of the control current is supplied to the base, and a bias current based on the first current is supplied to the first transistor.
A current output device formed on the semiconductor substrate, supplied with a second current that is a part of the control current, and outputs a third current based on the second current, and the second current is generated as the temperature rises. With the current output element that increases
A third transistor formed on the semiconductor substrate, a fourth current that is a part of the control current is supplied to the collector, and the second current is output from the emitter based on the fourth current.
In the plan view of the first arrangement region in which the first transistor is arranged and the semiconductor substrate, the second arrangement region, the current output element, and the third arrangement region in which the third transistor is arranged It has a wiring portion provided so as to overlap the intermediate region between the two, electrically connected to the emitter of the first transistor, and having a plurality of metal layers laminated so as to face the semiconductor substrate.
A power amplifier circuit in which at least one of the plurality of metal layers is extended so as to overlap the first arrangement region and the third arrangement region in the plan view. The power amplifier circuit according to claim 6.
A power amplifier circuit in which all layers of the plurality of metal layers of the wiring portion are extended so as to overlap the first arrangement region and the third arrangement region. The power amplifier circuit according to claim 6 or 7.
A power amplifier circuit in which the uppermost metal layer among the plurality of metal layers of the wiring portion is a bump. The power amplifier circuit according to any one of claims 6 to 8.
A power amplifier circuit in which at least one of the plurality of metal layers in the third arrangement region has a protrusion extending toward the current output element. The power amplifier circuit according to claim 9.
The wiring unit is a power amplifier circuit that is electrically connected to the current output element. The power amplifier circuit according to any one of claims 6 to 10.
The intermediate region is the first intermediate region.
A power amplifier circuit in which the at least one metal layer is provided so as to overlap a second intermediate region between the first arrangement region and the arrangement region in which the second transistor is arranged. The power amplifier circuit according to claim 11.
The wiring part is
Electric power including a first metal layer provided so as to overlap the first arrangement region and the first intermediate region, and a second metal layer provided so as to overlap the first arrangement region and the second intermediate region. Amplifier circuit. The power amplifier circuit according to any one of claims 1 to 12.
The first arrangement region is a power amplifier circuit having a plurality of divided regions. The first transistor formed on the semiconductor substrate and
A second transistor formed on the semiconductor substrate, a first current that is a part of the control current is supplied to the base, and a bias current based on the first current is supplied to the first transistor.
A current output device formed on the semiconductor substrate, supplied with a second current that is a part of the control current, and outputs a third current based on the second current, and the second current is generated as the temperature rises. With the current output element that increases
The first arrangement region is provided so as to overlap at least a part of the first arrangement region in which the first transistor is arranged and the region between the first arrangement region and the second arrangement region in which the current output element is arranged. It has a wiring portion that is electrically connected to the collector of one transistor and has a plurality of metal layers that are laminated so as to face the semiconductor substrate.
A power amplifier circuit in which at least one of the plurality of metal layers is extended so as to overlap the second arrangement region from at least a part of the first arrangement region in a plan view of the semiconductor substrate. The power amplifier circuit according to claim 14.
A power amplifier circuit in which the uppermost metal layer among the plurality of metal layers of the wiring portion is a bump. The power amplifier circuit according to claim 14 or 15.
A power amplifier circuit in which at least one of the plurality of metal layers in the second arrangement region has a protrusion extending toward the current output element.

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