JP2021125624A - Semiconductor device - Google Patents

Abstract

To provide a Fan-Out type semiconductor device with high heat dissipation.SOLUTION: A semiconductor device A1 includes: a semiconductor element 3 including an element main surface 3a and an element back surface 3b, and a main surface electrode 31 disposed on the element main surface 3a; an insulating layer 1 covering the element main surface 3a, and including an insulating layer back surface 1b facing the element main surface 3a and an insulating layer main surface 1a facing the opposite side of the insulating layer back surface 1b; sealing resin 4 including a resin main surface 4a in contact with the insulating layer back surface 1b and a resin back surface 4b facing the opposite side of the resin main surface 4a, and covering a part of the semiconductor element 3; an external terminal 601 exposed from the resin back surface 4b and electrically connected to the main surface electrode 31; and a re-wiring part 212 disposed in the insulating layer 1, overlapping with the semiconductor element 3 at least partially in a view along a z-direction, and existing at least partially outside the semiconductor element 3. The sealing resin 4 includes a resin opening 4c overlapping with the semiconductor element 3 in the view along the z-direction on the resin back surface 4b side.SELECTED DRAWING: Figure 5

Description

The present disclosure relates to a so-called Fan-Out type semiconductor device.

With the miniaturization of electronic devices in recent years, the miniaturization of semiconductor devices used in the electronic devices has been promoted. In response to these trends, so-called Fan-Out type semiconductor devices have been developed. The semiconductor device includes a semiconductor element having a plurality of electrodes, an insulating layer in contact with the semiconductor element, a plurality of connection wirings arranged in the insulating layer and connected to the plurality of electrodes, and the semiconductor element in contact with the insulating layer. It is provided with a sealing resin that partially covers it. In the thickness direction view, the plurality of connection wirings include a portion located outside the semiconductor element. This has the advantage that the shape of the wiring pattern of the wiring board on which the semiconductor device is mounted can be flexibly adapted while reducing the size of the semiconductor device.

Patent Document 1 discloses an example of a Fan-Out type semiconductor device. The semiconductor device is formed inside a semiconductor element having a plurality of electrodes on the main surface, an insulating layer in contact with the main surface of the semiconductor element, a sealing resin in contact with the insulating layer and covering a part of the semiconductor element, and an insulating layer. It is provided with a plurality of connecting wires including a portion located outside the semiconductor element in the thickness direction. The semiconductor element is covered with an insulating layer and a sealing resin. Since the semiconductor device does not include an interposer or a printed wiring board, it can be made thinner.

Further, in recent years, there has been a demand for a semiconductor device which is a compact high-power power module. For example, converters and inverters are being miniaturized by using power modules including semiconductor elements that are HEMTs (High Electron Mobility Transistors) using gallium nitride (GaN).

When a semiconductor device, which is a high-power power module, is formed of a Fan-Out type, the semiconductor device has a high heat generation density due to its small size and thinness, and the semiconductor element is covered with an insulating layer and a sealing resin. The heat dissipation is low due to the presence. This causes a problem that the semiconductor device malfunctions due to heat.

Japanese Unexamined Patent Publication No. 2019-29557

The present disclosure has been conceived under the above circumstances, and an object of the present invention is to provide a Fan-Out type semiconductor device having high heat dissipation.

The semiconductor device provided by the first aspect of the present disclosure includes a semiconductor device having an element main surface and an element back surface facing opposite sides in the thickness direction, and a main surface electrode formed on the element main surface. An insulating layer having an insulating layer back surface that covers the element main surface and is in contact with the element main surface, and an insulating layer main surface that faces the opposite side of the insulating layer back surface in the thickness direction, and the insulation. From the sealing resin having a resin main surface in contact with the back surface of the layer and a resin back surface facing the opposite side of the resin main surface in the thickness direction and covering a part of the semiconductor element, and the resin back surface. It is formed inside the insulating layer and an external terminal that is exposed and conducts to the main surface electrode, and at least a part thereof overlaps the semiconductor element in the thickness direction view, and at least a part thereof overlaps with the semiconductor element. It includes a heat transfer metal layer located outside the semiconductor element, and the sealing resin has a resin opening on the back surface side of the resin that overlaps the semiconductor element in the thickness direction.

The semiconductor device of the present disclosure is mounted on a wiring board by an external terminal exposed from the back surface of the resin. In the semiconductor element, the element main surface facing the same direction as the resin main surface is directed to the side opposite to the wiring board, and is arranged in the semiconductor device in a so-called face-up manner. Further, the sealing resin has a resin opening on the back surface side of the resin that overlaps the semiconductor element in the thickness direction. As a result, the heat generated by the semiconductor element is released from the resin opening to the wiring board. Therefore, the semiconductor device of the present disclosure has high heat dissipation as compared with the conventional semiconductor device in which the semiconductor element is covered with the insulating layer and the sealing resin.

Other features and advantages of the present disclosure will become more apparent with the detailed description given below with reference to the accompanying drawings.

It is a top view which shows the semiconductor device which concerns on 1st Embodiment of this disclosure. It is a top view which shows the semiconductor device of FIG. 1, and is the figure which transmitted through the 2nd insulating layer. It is a top view which shows the semiconductor device of FIG. 1, and is also the figure which transmitted through the 1st insulation layer and the connection wiring. It is a bottom view which shows the semiconductor device of FIG. It is sectional drawing which follows the VV line of FIG. It is a partially enlarged view of FIG. It is a partially enlarged view of FIG. It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG. It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG. It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG. It is a partially enlarged view of FIG. It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG. It is a partially enlarged view of FIG. It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG. It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG. It is a top view which shows the 1st modification of a concavo-convex portion. It is a top view which shows the 2nd deformation example of a concavo-convex portion. It is a partially enlarged cross-sectional view which shows the 3rd deformation example of the concavo-convex portion. It is a partially enlarged sectional view which shows the semiconductor device which concerns on 2nd Embodiment of this disclosure. It is sectional drawing which shows the semiconductor device which concerns on 3rd Embodiment of this disclosure. It is sectional drawing which shows the semiconductor device which concerns on 4th Embodiment of this disclosure. It is a top view which shows the semiconductor device which concerns on 5th Embodiment of this disclosure. It is sectional drawing which shows the semiconductor device of FIG. It is a top view which shows the semiconductor device which concerns on 6th Embodiment of this disclosure. It is a top view which shows the semiconductor device of FIG. 24, and is the figure which transmitted through the 2nd insulating layer. It is sectional drawing which shows the semiconductor device which concerns on 7th Embodiment of this disclosure.

Hereinafter, preferred embodiments of the present disclosure will be specifically described with reference to the drawings.

In the present disclosure, "something A is formed on a certain thing B" and "something A is formed on a certain thing B" means "there is a certain thing A" unless otherwise specified. It includes "being formed directly on the object B" and "being formed on the object B with the object A while interposing another object between the object A and the object B". Similarly, "something A is placed on something B" and "something A is placed on something B" means "something A is placed on something B" unless otherwise specified. It includes "being placed directly on B" and "being placed on a certain thing B while having another thing intervening between a certain thing A and a certain thing B". Similarly, "something A is located on something B" means "something A is in contact with something B and some thing A is on something B" unless otherwise specified. "What you are doing" and "The thing A is located on the thing B while another thing is intervening between the thing A and the thing B". In addition, "something A overlaps with some thing B when viewed in a certain direction" means "something A overlaps with all of some thing B" and "something A overlaps" unless otherwise specified. "Overlapping a part of a certain object B" is included.

<First Embodiment>
1 to 7 show an example of the semiconductor device according to the present disclosure. The semiconductor device A1 of the present embodiment includes an insulating layer 1, a plurality of connection wirings 21, two semiconductor elements 3, a sealing resin 4, two heat spreaders 5, and a plurality of electrodes 6. The insulating layer 1 includes a first insulating layer 11 and a second insulating layer 12. The semiconductor device A1 is a Fan-Out type package that is surface-mounted on a wiring board.

FIG. 1 is a plan view showing the semiconductor device A1. FIG. 2 is a plan view showing the semiconductor device A1 and is a view that has passed through the second insulating layer 12. FIG. 3 is a plan view showing the semiconductor device A1, and is a view through which the first insulating layer 11 and the connecting wiring 21 have passed through. FIG. 4 is a bottom view showing the semiconductor device A1. FIG. 5 is a cross-sectional view taken along the line VV of FIG. FIG. 6 is a partially enlarged view of FIG. FIG. 7 is a partially enlarged view of FIG.

The semiconductor device A1 has a plate shape and a rectangular shape in the thickness direction (planar view). For convenience of explanation, the thickness direction (plan view direction) of the semiconductor device A1 is the z direction, and the direction along one side of the semiconductor device A1 orthogonal to the z direction (the left-right direction in FIGS. 1 to 7) is the x direction. The direction orthogonal to the z direction and the x direction (the vertical direction in FIGS. 1 to 4) is defined as the y direction. The z direction corresponds to the "thickness direction" of the present disclosure. The size of the semiconductor device A1 is not particularly limited.

The semiconductor element 3 is an element that exerts an electrical function of the semiconductor device A1. In this embodiment, the semiconductor device A1 includes two semiconductor elements 3. When the two semiconductor elements 3 are described separately, one is referred to as a semiconductor element 301 and the other is referred to as a semiconductor element 302. When the two are not distinguished, it is simply referred to as the semiconductor element 3. In the present embodiment, the semiconductor element 3 is a high electron mobility transistor (HEMT) having an electron traveling layer made of a nitride semiconductor, and gallium nitride (GaN) is used in the present embodiment.

Each semiconductor element 3 has a rectangular plate shape in the z-direction, and includes an element main surface 3a, an element back surface 3b, and a plurality of main surface electrodes 31, 32, 33. The element main surface 3a and the element back surface 3b face opposite to each other in the z direction. The element main surface 3a is a surface facing upward in FIG. The back surface 3b of the element is a surface facing downward in FIG. As shown in FIG. 3, a plurality of main surface electrodes 31, 32, 33 are arranged on the element main surface 3a. The main surface electrode 31 is, for example, a drain electrode. The main surface electrode 32 is, for example, a source electrode. The main surface electrode 33 is, for example, a gate electrode.

As shown in FIG. 3, the semiconductor element 301 and the semiconductor element 302 are arranged side by side in the y direction slightly to the right of the center of the semiconductor device A1 in the x direction in the z-direction view. In the present embodiment, the semiconductor element 301 is arranged on the upper side of FIG. 3, and the semiconductor element 302 is arranged on the lower side of FIG. The type, number, and arrangement position of the semiconductor element 3 are not limited.

The heat spreader 5 has a rectangular plate shape in the z-direction, and is a member for radiating the heat generated by the semiconductor element 3 to the wiring substrate on which the semiconductor device A1 is mounted. In the present embodiment, the semiconductor device A1 includes two heat spreaders 5 according to the number of semiconductor elements 3. One heat spreader 5 is bonded to the semiconductor element 301, and the other heat spreader 5 is bonded to the semiconductor element 302. Each heat spreader 5 is made of a material having high thermal conductivity, and in this embodiment, is made of Cu. The material of the heat spreader 5 is not limited, and may be another metal such as Al or ceramic. Each heat spreader 5 includes a spreader main surface 5a and a spreader back surface 5b. The spreader main surface 5a and the spreader back surface 5b face each other in the z direction. The spreader main surface 5a is a surface facing upward in FIG. The back surface 5b of the spreader is a surface facing downward in FIG. The heat spreader 5 is joined to the element back surface 3b of the semiconductor element 3 with the spreader main surface 5a facing the semiconductor element 3. In the present embodiment, the dimensions of the heat spreader 5 in the x-direction and the y-direction match the dimensions of the semiconductor element 3. That is, the dimension L2 of the heat spreader 5 in the x direction (see FIG. 4) is equal to the dimension L1 of the semiconductor element 3 in the x direction (see FIG. 3). Further, the dimension W2 of the heat spreader 5 in the y direction (see FIG. 4) is equal to the dimension W1 of the semiconductor element 3 in the y direction (see FIG. 3). Although the dimension L2 and the dimension W2 are not limited, it is desirable that the dimension L2 is 0.8 times or more and 1.5 times or less of the dimension L1, and the dimension W2 is 0.8 times or more and 1.5 times or more the dimension W1. It is desirable that it is less than double. The back surface 5b of the spreader of the heat spreader 5 is exposed from the sealing resin 4. When the semiconductor device A1 is mounted on the wiring board, the spreader back surface 5b is joined to the wiring board by a joining member such as solder. As a result, the heat spreader 5 releases the heat generated by the semiconductor element 3 to the wiring board.

The sealing resin 4 covers a part of each of the semiconductor element 3 and the heat spreader 5. The sealing resin 4 is made of a material containing, for example, a black epoxy resin. The sealing resin 4 includes a resin main surface 4a, a resin back surface 4b, and a resin opening 4c. The resin main surface 4a and the resin back surface 4b face each other in the z direction. The resin main surface 4a is a surface facing upward in FIG. The resin back surface 4b is a surface facing downward in FIG. In the present embodiment, the resin main surface 4a is flush with the element main surface 3a of the semiconductor element 3 and is in contact with the insulating layer 1. The main surface electrodes 31, 32, 33 may be exposed from the sealing resin 4, and a part of the element main surface 3a may be covered with the sealing resin 4. The resin back surface 4b is a surface facing the wiring board when the semiconductor device A1 is mounted on the wiring board. The resin opening 4c is an opening formed on the resin back surface 4b side and overlaps with the semiconductor element 3 in the z-direction view. In the present embodiment, the back surface 5b of the spreader of the heat spreader 5 is exposed from the resin opening 4c, and the back surface 4b of the resin and the back surface 5b of the spreader are flush with each other. The back surface 5b of the spreader may be partially exposed from the back surface 4b of the resin, and may be partially covered with the sealing resin 4.

As shown in FIG. 5, the dimension t1 of the sealing resin 4 in the z direction is larger than the dimension t2 of the heat spreader 5 in the z direction. Further, the linear expansion coefficient α1 of the sealing resin 4 is smaller than the linear expansion coefficient α2 of the heat spreader 5. When the Young's modulus of the sealing resin 4 is E1 and the Young's modulus of the heat spreader 5 is E2, the dimension t2 of the heat spreader 5 in the z direction satisfies the following formula.

The plurality of electrodes 6 are made of a conductor, and in this embodiment, are made of Cu. The electrodes 6 are arranged at both ends of the semiconductor device A1 in the x direction in the z-direction view, and are separated from each other. In the present embodiment, three electrodes 6 arranged at equal intervals in the y direction are arranged at one end of the semiconductor device A1 (right end in FIG. 3), and at the other end (left end in FIG. 3). , Six electrodes 6 arranged at equal intervals in the y direction are arranged. In the present embodiment, as shown in FIG. 3, the electrode 6 includes an electrode 61, an electrode 62, an electrode 63, an electrode 64, and an electrode 65. The electrode 61 is an electrode 6 arranged at the upper right in FIG. 3, and conducts to the main surface electrode 31 of the semiconductor element 301. The electrode 63 is an electrode 6 arranged at the lower right in FIG. 3, and conducts to the main surface electrode 32 of the semiconductor element 302. The electrode 62 is an electrode 6 arranged between the electrode 61 and the electrode 63, and conducts to the main surface electrode 32 of the semiconductor element 301 and the main surface electrode 31 of the semiconductor element 302. The electrode 64 is the electrode 6 arranged at the top on the left side in FIG. 3, and conducts to the main surface electrode 33 of the semiconductor element 301. The electrode 65 is the fourth electrode 6 from the top on the left side in FIG. 3, and conducts to the main surface electrode 33 of the semiconductor element 302. The number, material, and arrangement of each electrode 6 are not limited.

Most of each electrode 6 is covered with the sealing resin 4. As shown in FIG. 5, each electrode 6 includes an external terminal 601, an internal terminal 602, and a connection portion 603. The internal terminal 602 has a rectangular plate shape in the z-direction, is located above in FIG. 5, and one surface is exposed from the sealing resin 4. One of the surfaces is connected to the semiconductor element 3 or the like via the connection wiring 21. The external terminal 601 has a rectangular plate shape in the z-direction, is located at the lower side in FIG. 5, and one surface is exposed from the resin back surface 4b of the sealing resin 4. When the semiconductor device A1 is mounted on the wiring board, the one surface is joined to the wiring of the wiring board by a joining member such as solder. On one of the surfaces, for example, a metal layer in which a nickel (Ni) layer, a palladium layer (Pd), and a gold (Au) layer are laminated in this order may be formed, and a bump portion made of a material containing tin (Sn) may be formed. May be formed. The external terminal 601 functions as an external terminal of the semiconductor device A1. The connection portion 603 is connected to the external terminal 601 and the internal terminal 602, and makes the external terminal 601 and the internal terminal 602 conductive. The cross-sectional shape of the connecting portion 603 orthogonal to the z direction is not limited, and the number is not limited. The configuration of each electrode 6 is not limited to that described above.

In the electrode 61, the internal terminal 602 is connected to the main surface electrode 31 (drain electrode) of the semiconductor element 301 via the connection wiring 21 (see FIG. 5), and the external terminal 601 is a Vin to which a DC voltage is applied from the outside. Functions as a terminal. In the electrode 63, the internal terminal 602 is connected to the main surface electrode 32 (source electrode) of the semiconductor element 302 via the connection wiring 21, and the external terminal 601 functions as a PGND terminal connected to the ground. In the electrode 62, the internal terminal 602 is connected to the main surface electrode 32 (source electrode) of the semiconductor element 301 and the main surface electrode 31 (drain electrode) of the semiconductor element 302 via the connection wiring 21, and the external terminal 601 is connected to the main surface electrode 31 (drain electrode). It functions as a SW terminal that outputs a switching signal. In the electrode 64, the internal terminal 602 is connected to the main surface electrode 33 (gate electrode) of the semiconductor element 301 via the connection wiring 21 (see FIG. 5), and the external terminal 601 sends a drive signal to the semiconductor element 301. Functions as an input signal terminal. In the electrode 65, the internal terminal 602 is connected to the main surface electrode 33 (gate electrode) of the semiconductor element 302 via the connection wiring 21, and the external terminal 601 serves as a signal terminal for inputting a drive signal to the semiconductor element 302. Function.

As shown in FIG. 5, the insulating layer 1 is in contact with the element main surface 3a of each semiconductor element 3 and the resin main surface 4a of the sealing resin 4. The insulating layer 1 is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that constitutes a part of a plurality of connecting wirings 21. The synthetic resin is, for example, an epoxy resin or a polyimide resin. The insulating layer 1 has an insulating layer main surface 1a and an insulating layer back surface 1b. The main surface 1a of the insulating layer and the back surface 1b of the insulating layer face opposite to each other in the z direction. The main surface 1a of the insulating layer is a surface facing upward in FIG. The back surface 1b of the insulating layer is a surface facing downward in FIG. The back surface 1b of the insulating layer is in contact with the element main surface 3a of each semiconductor element 3 and the resin main surface 4a of the sealing resin 4 facing each other, and the element main surface 3a of each semiconductor element 3 and the resin main surface of the sealing resin 4 are in contact with each other. It covers the surface 4a. The back surface 1b of the insulating layer does not have to be in contact with the element main surface 3a of each semiconductor element 3.

Further, the insulating layer 1 is provided with the uneven portion 15. The uneven portion 15 is formed on the main surface 1a side of the insulating layer and functions as a heat sink for releasing the heat generated by the semiconductor element 3. As shown in FIG. 1, the uneven portion 15 has a rectangular shape in the z-direction view, and overlaps the semiconductor element 301 and the semiconductor element 302 as a whole. The uneven portion 15 may overlap only a part of the semiconductor element 301 and the semiconductor element 302 in the z-direction view. Further, only a part of the uneven portion 15 may overlap the semiconductor element 301 and the semiconductor element 302 in the z-direction view.

The uneven portion 15 includes a concave portion 151 and a plurality of convex portions 152. As shown in FIG. 7, the recess 151 is recessed in the z direction from the main surface 1a of the insulating layer, and is rectangular in the z direction as shown in FIG. The concave portion 151 defines the outer shape of the uneven portion 15 in the z-direction view. The plurality of convex portions 152 are arranged inside the concave portion 151, and as shown in FIG. 7, project from the bottom surface of the concave portion 151 in the z direction. As shown in FIG. 1, each convex portion 152 has an elongated rectangular shape that is long in the y direction in the z-direction view, and is arranged in a staggered manner. Each convex portion 152 may have a long rectangular shape that is long in the x direction in the z direction. In the present embodiment, the uneven portion 15 is formed by a laser, as will be described later. That is, the uneven portion 15 is formed by irradiating a predetermined region of the insulating layer 1 from the main surface 1a side of the insulating layer with a laser to remove a part of the insulating layer 1 to leave the convex portion 152 in the manufacturing process. NS. In the present embodiment, the depth D (dimension in the z direction) of the concave portion 151 is the height of the convex portion 152. The larger the depth D, the higher the heat dissipation effect, but it takes time to form. Further, the depth D needs to be set so as not to reach the connection wiring 21 arranged inside the insulating layer 1. The depth D is preferably 5 μm or more and 300 μm or less. The depth D is not limited.

The insulating layer 1 includes a first insulating layer 11 and a second insulating layer 12. As shown in FIG.
The first insulating layer 11 and the second insulating layer 12 are laminated on the sealing resin 4 in this order. The first insulating layer 11 is in contact with the element main surface 3a of each semiconductor element 3 and the resin main surface 4a of the sealing resin 4, and includes the back surface 1b of the insulating layer. The second insulating layer 12 is in contact with the first insulating layer 11 and includes the main surface 1a of the insulating layer. The uneven portion 15 is arranged on the second insulating layer 12.

The plurality of connection wirings 21 are conductors that connect each electrode 6 and each semiconductor element 3 and the like, and form a conductive path for supplying electric power to the semiconductor element 3 and inputting / outputting signals. As shown in FIG. 5, the plurality of connection wirings 21 are arranged inside the insulating layer 1. Each connection wiring 21 includes an embedded portion 211 and a rewiring portion 212, respectively. As shown in FIGS. 5 and 6, at least a part (all in the present embodiment) of the embedded portion 211 is embedded in the first insulating layer 11. As shown in FIG. 6, the side surface of the embedded portion 211 is inclined with respect to the z direction, and a taper is formed in which the area of the cross section of the embedded portion 211 orthogonal to the z direction becomes smaller as it approaches the back surface 1b of the insulating layer. Has been done. As shown in FIGS. 5 and 6, the rewiring portion 212 is arranged between the first insulating layer 11 and the second insulating layer 12. The rewiring portion 212 is connected to the embedded portion 211. As shown in FIG. 2, the rewiring portion 212 of each connection wiring 21 partially overlaps each semiconductor element 3 in the z-direction view, and a part is located outside each semiconductor element 3. The rewiring portion 212 corresponds to the "heat transfer metal layer" of the present disclosure. The semiconductor device A1 overlaps only the semiconductor element 3 in the z-direction view, and has no portion located outside the semiconductor element 3 or only outside the rewiring portion 212 or the semiconductor element 3. The rewiring portion 212 located may be included.

As shown in FIG. 6, each of the embedded portion 211 and the rewiring portion 212 has a base layer 201 and a plating layer 202. The base layer 201 is composed of a metal element contained in the additive contained in the first insulating layer 11, and is in contact with the first insulating layer 11. The plating layer 202 is made of, for example, a material containing copper (Cu) and is in contact with the base layer 201. The base layer 201 of the embedded portion 211 is in contact with the first insulating layer 11. The plating layer 202 of the embedded portion 211 is surrounded by the base layer 201 of the embedded portion 211. The base layer 201 of the rewiring portion 212 is in contact with the first insulating layer 11. The plating layer 202 of the rewiring portion 212 covers the base layer 201 of the rewiring portion 212 and is surrounded by the base layer 201 of the rewiring portion 212 and the second insulating layer 12.

Next, an example of the manufacturing method of the semiconductor device A1 will be described below with reference to FIGS. 8 to 15. 8 to 15 are diagrams showing one step of an example of a manufacturing method of the semiconductor device A1, respectively. 8 to 10, FIG. 12, FIG. 14, and FIG. 15 are cross-sectional views, which correspond to FIGS. 5. FIG. 11 is a partially enlarged view of FIG. 10, which corresponds to FIG. FIG. 13 is a partially enlarged view of FIG. 12, which corresponds to FIG.

First, as shown in FIG. 8, the semiconductor element 3 to which the heat spreader 5 is bonded and the electrode 6 are embedded in the sealing resin 81. The sealing resin 81 is made of a material containing a black epoxy resin. In the semiconductor element 3, the main surface electrodes 31, 32, 33 are arranged on the element main surface 3a, and the heat spreader 5 is bonded to the element back surface 3b. In this step, the material of the sealing resin 81, the semiconductor element 3 to which the heat spreader 5 is bonded, and the electrode 6 are arranged in the mold, and then compression molding is performed. At this time, the main surface electrodes 31, 32, 33 and the back surface 5b of the spreader of the heat spreader 5 are exposed from the sealing resin 81.

Next, as shown in FIG. 9, a first insulating layer 82 is formed, which is laminated on the sealing resin 81 and covers the main surface electrodes 31, 32, 33 of the semiconductor element 3. The first insulating layer 82 is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that constitutes a part of a plurality of connection wirings 83 (details will be described later). The synthetic resin is, for example, an epoxy resin or a polyimide resin. The first insulating layer 82 is formed by compression molding.

Next, as shown in FIGS. 10 to 13, a plurality of connection wirings 83 connected to the main surface electrodes 31, 32, 33 of the semiconductor element 3 or the plurality of electrodes 6 are formed. The plurality of connection wirings 83 correspond to the plurality of connection wirings 21 of the semiconductor device A1. As shown in FIG. 13, each of the plurality of connection wirings 83 has an embedded portion 831 and a rewiring portion 832. The embedded portion 831 is embedded in the first insulating layer 82 and is connected to either the main surface electrodes 31, 32, 33 or the plurality of electrodes 6. The rewiring portion 832 is arranged on the first insulating layer 82 and is connected to the embedded portion 831. As shown in FIG. 13, each of the embedded portion 831 and the rewiring portion 832 of the plurality of connecting wirings 83 has a base layer 83A and a plating layer 83B. The step of forming the plurality of connection wirings 83 includes a step of depositing the base layer 83A on the surface of the first insulating layer 82 and a step of forming a plating layer 83B covering the base layer 83A.

First, as shown in FIG. 11, the base layer 83A is deposited on the surface of the first insulating layer 82. In this step, as shown in FIG. 10, a plurality of holes 821 and a plurality of grooves 822 are formed in the first insulating layer 82 by a laser. The plurality of holes 821 penetrate the first insulating layer 82 in the z direction. The main surface electrodes 31, 32, 33 and the electrodes 6 of the semiconductor element 3 are individually exposed from the plurality of holes 821. The plurality of holes 821 are formed in the first insulating layer 82 until the main surface electrodes 31, 32, 33 and the electrodes 6 are exposed while recognizing the positions of the main surface electrodes 31, 32, 33 and the electrodes 6 by an infrared camera or the like. It is formed by irradiating a laser. The position where the laser is irradiated is corrected one by one based on the position information of the main surface electrodes 31, 32, 33 and the electrode 6 obtained by image recognition. The plurality of grooves 822 are recessed from the surface of the first insulating layer 82 and are connected to the plurality of holes 821. The plurality of grooves 822 are formed by irradiating the surface of the first insulating layer 82 with a laser. The laser is, for example, an ultraviolet laser having a wavelength of 355 nm and a beam diameter of 17 μm. By forming the plurality of holes 821 and the plurality of grooves 822 in the first insulating layer 82, as shown in FIG. 11, the base layer 83A covering the wall surface defining each of the plurality of holes 821 and the plurality of grooves 822. Is deposited. The base layer 83A is composed of metal elements contained in the additive contained in the first insulating layer 82. The metal element contained in the additive is excited by laser irradiation. As a result, the metal layer containing the metal element is precipitated as the base layer 83A.

Next, as shown in FIG. 13, a plating layer 83B covering the base layer 83A is formed. The plating layer 83B is made of a material containing copper. The plating layer 83B is formed by electroless plating. As a result, as shown in FIG. 12, an embedded portion 831 is formed in each of the plurality of holes 821. In addition, a rewiring portion 832 is formed in each of the plurality of grooves 822. As described above, a plurality of connection wirings 83 are formed.

Next, as shown in FIG. 14, a second insulating layer 84 is formed which is laminated on the first insulating layer 82 and covers the plurality of connection wirings 83. The second insulating layer 84 is made of the same material as the first insulating layer 82. The second insulating layer 84 is formed by compression molding.

Next, as shown in FIG. 15, the uneven portion 15 is formed on the surface of the second insulating layer 84 at a position overlapping the semiconductor element 3 in the z-direction view. The uneven portion 15 is formed by irradiating the laser. The laser irradiates the region of the uneven portion 15 excluding the portion left as the convex portion 152. As a result, the laser-irradiated region of the surface of the second insulating layer 84 is recessed, the laser-irradiated region remains, and the uneven portion 15 is formed. The laser is, for example, an ultraviolet laser having a wavelength of 355 nm and a beam diameter of 17 μm.

Finally, the sealing resin 81, the first insulating layer 82, and the second insulating layer 84 are cut into a plurality of pieces by cutting along a predetermined cutting line with a dicing blade or the like. The piece is configured to include two semiconductor elements 3, a plurality of connection wirings 83 connected to them, and a plurality of electrodes 6. The sealing resin 81, the first insulating layer 82, and the second insulating layer 84, which are individually formed by this step, are the sealing resin 4, the first insulating layer 11, and the second insulating layer 12 of the semiconductor device A1, respectively. Corresponds to. Through the above steps, the semiconductor device A1 is manufactured.

Next, the action and effect of the semiconductor device A1 will be described.

According to this embodiment, each semiconductor element 3 has a heat spreader 5 bonded to the back surface 3b of the element. The back surface 5b of the spreader of the heat spreader 5 is exposed from the back surface 4b of the resin of the sealing resin 4. The semiconductor device A1 is mounted on a wiring board by an external terminal 601 exposed from the resin back surface 4b. At this time, the spreader back surface 5b exposed from the resin back surface 4b is also joined to the wiring board by a joining member such as solder. As a result, the semiconductor device A1 can release the heat generated by the semiconductor element 3 to the wiring board via the heat spreader 5. Therefore, the semiconductor device A1 has higher heat dissipation than the conventional semiconductor device in which the semiconductor element 3 is covered with the insulating layer 1 and the sealing resin 4.

Further, according to the present embodiment, the insulating layer 1 includes an uneven portion 15 formed on the main surface 1a of the insulating layer. The uneven portion 15 functions as a heat sink for releasing the heat generated by the semiconductor element 3. As a result, the semiconductor device A1 can also release the heat generated by the semiconductor element 3 from the uneven portion 15. Therefore, the semiconductor device A1 has higher heat dissipation. Further, the uneven portion 15 according to the present embodiment overlaps the semiconductor element 301 and the semiconductor element 302 as a whole in the z-direction view. Therefore, the heat dissipation effect is high.

Further, according to the present embodiment, a heat spreader 5 made of Cu is bonded to each semiconductor element 3. As a result, it is possible to prevent the semiconductor device A1 from warping due to thermal expansion.

Further, according to the present embodiment, the connection wiring 22 of the semiconductor device A1 irradiates the first insulating layer 82 made of a material containing an additive containing a metal element with a laser to precipitate the base layer 83A. It is formed by forming a plating layer 83B that covers the above. Laser irradiation is performed while being corrected one by one based on the position information of each electrode obtained by image recognition. Therefore, even when the semiconductor element 3 or the electrode 6 is displaced due to the curing shrinkage of the sealing resin 4, the connection wiring 22 can be formed with high accuracy according to the actual position of each electrode. This makes it possible to suppress the positional deviation at the joint between each electrode and the connection wiring 22.

Further, according to the present embodiment, the uneven portion 15 is formed by irradiating the second insulating layer 84 with a laser. Since the same method as the step of precipitating the base layer 83A on the first insulating layer 82 is used, the equipment for manufacturing can be simplified as compared with the case of forming by another method.

In the present embodiment, the simplest example in which the insulating layer 1 is composed of two laminated layers of the first insulating layer 11 and the second insulating layer 12 has been described, but the present invention is not limited to this. Three or more layers of the insulating layer 1 may be laminated. In this case, a layer to be further laminated is added between the first insulating layer 11 and the second insulating layer 12. For example, when the insulating layer 1 is composed of three layers, the third insulating layer 13 is laminated between the first insulating layer 11 and the second insulating layer 12 (see FIG. 26 described later) and embedded in the third insulating layer 13. A connection wiring consisting of an embedded portion and a rewiring portion arranged between the third insulating layer 13 and the second insulating layer 12 is added. As the number of layers of the insulating layer 1 increases, the degree of freedom in arranging the connection wiring increases.

Further, in the present embodiment, the case where the first insulating layer 11 and the second insulating layer 12 are made of the same material has been described, but the present invention is not limited to this. The second insulating layer 12 does not have to be a material containing an additive containing a metal element.

Further, in the present embodiment, in the manufacturing process, the first insulating layer 82 made of a material containing an additive containing a metal element is irradiated with a laser to precipitate the base layer 83A, and a plating layer 83B covering the base layer 83A is formed. The case where the connection wiring 83 (connection wiring 22) is formed by the above is described, but the present invention is not limited to this. The connection wiring 22 may be formed by other methods. For example, by photolithography patterning using a mask, a plurality of openings are formed in the first insulating layer 82 so that each electrode is exposed, and a connection wiring 83 is formed by plating on the openings and the first insulating layer 82. May be good. In this case, the first insulating layer 82 does not have to be a material containing an additive containing a metal element.

Further, in the present embodiment, the case where the uneven portion 15 is formed by irradiation with a laser has been described, but the present invention is not limited to this. The uneven portion 15 may be formed by another method. For example, the uneven portion 15 may be formed by cutting. Further, the shape of the uneven portion 15 is formed in the portion where the insulating layer main surface 1a of the mold is formed when the second insulating layer 12 is formed, and the uneven portion 15 is formed at the same time as the formation of the second insulating layer 12. It may be formed.

Further, in the present embodiment, the case where the concave-convex portion 15 has the convex portion 152 having a rectangular shape in the z-direction arranged inside the concave portion 151 in a staggered manner has been described, but the present invention is not limited to this. Various variations can be considered in the shape of the uneven portion 15. A modified example of the uneven portion 15 will be described below with reference to FIGS. 16 to 18. The uneven portion 15 may have an appropriate shape in consideration of the heat dissipation effect and the ease of formation.

FIG. 16 is a plan view showing a first modified example of the uneven portion 15, and is a view corresponding to FIG. In the concave-convex portion 15 according to the first modification, each convex portion 152 has an elongated rectangular shape extending long to the vicinity of both ends of the concave portion 151 in the y-direction in the z-direction view, and is arranged parallel to each other at equal intervals. Each convex portion 152 may have a long rectangular shape that is long in the x direction in the z direction. Further, each convex portion 152 may have a shape extending in a wavy shape instead of a shape extending straight in the y direction (x direction) in the z-direction view.

FIG. 17 is a plan view showing a second modified example of the uneven portion 15, and is a view corresponding to FIG. The concave-convex portion 15 according to the second modification does not include the concave portion 151 and the plurality of convex portions 152 that define the outer shape of the concave-convex portion 15 in the z-direction view, and the plurality of concave portions recessed in the z-direction from the main surface 1a of the insulating layer. It has only 153. The plurality of recesses 153 have a long rectangular shape that is long in the y direction in the z direction, and are arranged in a staggered manner. Each recess 153 may have a long rectangular shape that is long in the x direction in the z direction. In the case of the modified example, the region to be irradiated with the laser for forming the uneven portion 15 is smaller than that of the concave-convex portion 15 according to the first embodiment (only the concave portion 153 portion). Therefore, the time required for the step of forming the uneven portion 15 can be shortened. Also in the modified example, the shape and arrangement of each recess 153 in the z-direction may be the shape and arrangement described in the first modified example.

FIG. 18 is a partially enlarged cross-sectional view showing a third modified example of the uneven portion 15, and is a view corresponding to FIG. 7. The convex portion 152 according to the third modification has a trapezoidal shape in a cross section orthogonal to the y direction, and the concave portion between the convex portion 152 and the convex portion 152 in the cross section has a triangular shape. In the case of the modified example, the laser is irradiated to form the concave portion between the convex portion 152 and the convex portion 152 as compared with the case where the cross section of the convex portion 152 orthogonal to the y direction has a rectangular shape. Time can be shortened. Therefore, the time required for the step of forming the uneven portion 15 can be shortened. Further, when the uneven portion 15 is formed by the mold, the mold can be easily released from the mold. The shape of the cross section of the convex portion 152 orthogonal to the y direction may be an arc shape. Further, also in the modified example, the shape and arrangement of each convex portion 152 in the z-direction view may be the shape and arrangement described in the first modified example. Further, when a plurality of recesses 153 are provided as in the second modification, the shape of the cross section of the recesses 153 orthogonal to the y direction may be triangular.

19-26 show other embodiments of the present disclosure. In these figures, the same or similar elements as those in the above embodiment are designated by the same reference numerals as those in the above embodiment.

<Second Embodiment>
FIG. 19 is a diagram for explaining the semiconductor device A2 according to the second embodiment of the present disclosure. FIG. 19 is a partially enlarged cross-sectional view showing the semiconductor device A2, and is a view corresponding to FIG. 7. The semiconductor device A2 of the present embodiment is different from the first embodiment in that it further includes a heat radiating metal layer 79 that covers the uneven portion 15.

The semiconductor device A2 further includes a heat radiating metal layer 79. The heat radiating metal layer 79 is formed so as to cover the uneven portion 15, and has a base layer and a plating layer like the connection wiring 21. The base layer is composed of metal elements contained in the additive contained in the second insulating layer 12, and is in contact with the second insulating layer 12. The plating layer is made of, for example, a material containing copper (Cu) and is in contact with the base layer.

The semiconductor device A2 is manufactured in the same manufacturing process as the semiconductor device A1 according to the first embodiment until the step of forming the second insulating layer 84 (second insulating layer 12). In the case of the present embodiment, in the step of forming the uneven portion 15 with the laser, the laser is also irradiated to the upper surface of each convex portion 152 (the surface facing the same side as the main surface 1a of the insulating layer). As a result, the metal element contained in the additive contained in the second insulating layer 84 is excited, and the base layer covering the entire uneven portion 15 is deposited. Then, a plating layer covering the base layer is formed by electroless plating. As a result, the heat radiating metal layer 79 that covers the uneven portion 15 is formed. The subsequent steps are the same as those of the semiconductor device A1.

According to the present embodiment, since the semiconductor device A2 includes the heat spreader 5 and the uneven portion 15, heat dissipation is high as in the semiconductor device A1 of the first embodiment. Further, since the heat-dissipating metal layer 79 that covers the uneven portion 15 is formed in the semiconductor device A2, the heat-dissipating property is further enhanced.

<Third Embodiment>
FIG. 20 is a diagram for explaining the semiconductor device A3 according to the third embodiment of the present disclosure. FIG. 20 is a cross-sectional view showing the semiconductor device A3, and is a diagram corresponding to FIG. The semiconductor device A3 of the present embodiment is different from the first embodiment in that the heat spreader 5 is not provided.

The semiconductor device A3 does not include the heat spreader 5, and the element back surface 3b of each semiconductor element 3 is exposed from the resin opening 4c. In this embodiment, the resin back surface 4b and the element back surface 3b are flush with each other. The back surface 3b of the element may be partially exposed from the back surface 4b of the resin, and may be partially covered with the sealing resin 4. When the semiconductor device A3 is mounted on the wiring board, the back surface 3b of the element is joined to the wiring board by a joining member such as solder. As a result, each semiconductor element 3 can release the generated heat from the element back surface 3b to the wiring board.

According to this embodiment, the element back surface 3b of each semiconductor element 3 is exposed from the resin back surface 4b of the sealing resin 4, and is joined to the wiring board when the semiconductor device A3 is mounted on the wiring board. As a result, the semiconductor device A3 can release the heat generated by the semiconductor element 3 to the wiring board. Therefore, the semiconductor device A3 has higher heat dissipation than the conventional semiconductor device in which the semiconductor element 3 is covered with the insulating layer 1 and the sealing resin 4. Further, the semiconductor device A3 is provided with the uneven portion 15 as in the first embodiment. As a result, the semiconductor device A3 can also release the heat generated by the semiconductor element 3 from the uneven portion 15. Therefore, the semiconductor device A3 has higher heat dissipation.

<Fourth Embodiment>
FIG. 21 is a diagram for explaining the semiconductor device A4 according to the fourth embodiment of the present disclosure. FIG. 21 is a cross-sectional view showing the semiconductor device A4, and is a diagram corresponding to FIG. The semiconductor device A4 of the present embodiment is different from the first embodiment in that a plurality of connection wirings 22 for mounting the electronic component 9 are further provided on the main surface 1a of the insulating layer. In FIG. 21, the electronic component 9 is shown by an imaginary line (dashed line). The same applies to the following figure.

The semiconductor device A4 is designed so that the electronic component 9 can be mounted on the main surface 1a of the insulating layer, and further includes a plurality of connection wirings 22. The electronic component 9 is, for example, a resistor, a capacitor, a driver IC, or the like, but is not limited thereto. Further, the number of electronic components 9 mounted on the semiconductor device A4 and the arrangement position of each electronic component 9 are not limited.

The plurality of connection wirings 22 are conductors that connect the electronic component 9 to the electrodes 6, the connection wirings 21, and the like, and form a conductive path. The plurality of connection wirings 22 are arranged in the insulating layer 1. The structure of each connection wiring 22 is the same as that of the connection wiring 21, and each connection wiring 22 includes an embedded portion 221 and a rewiring portion 222, respectively. At least a part of the embedded portion 221 is embedded in the second insulating layer 12. The embedded portion 221 of the connection wiring 22 connected to the connection wiring 21 is completely embedded in the second insulating layer 12. Further, the embedded portion 221 of the connection wiring 22 connected to the electrode 6 is embedded through the first insulating layer 11 and the second insulating layer 12. The rewiring portion 222 is arranged on the surface of the second insulating layer 12 opposite to the first insulating layer 11, that is, the main surface 1a of the insulating layer. The rewiring portion 222 is connected to the embedded portion 221. The rewiring unit 222 functions as wiring and can join the terminals of the electronic component 9.

Each of the embedded portion 221 and the rewiring portion 222 has a base layer 201 and a plating layer 202, similarly to the embedded portion 211 and the rewiring portion 212. The base layer 201 is composed of a metal element contained in the additive contained in the second insulating layer 12, and is in contact with the second insulating layer 12. The plating layer 202 is made of, for example, a material containing copper (Cu) and is in contact with the base layer 201. The base layer 201 of the embedded portion 221 is in contact with the second insulating layer 12. The plating layer 202 of the embedded portion 221 is surrounded by the base layer 201 of the embedded portion 221. The base layer 201 of the rewiring portion 222 is in contact with the second insulating layer 12. The plating layer 202 of the rewiring portion 222 covers the base layer 201 of the rewiring portion 222.

The semiconductor device A4 is manufactured in the same manufacturing process as the semiconductor device A1 according to the first embodiment until the step of forming the second insulating layer 84 (second insulating layer 12). In the case of the present embodiment, in the step of forming the uneven portion 15 on the second insulating layer 84 with a laser, a plurality of holes and a plurality of grooves are formed in the second insulating layer 84 and connected to these holes and grooves. The base layer 201 of the wiring 22 is deposited. Next, the plating layer 202 covering the base layer 201 is formed by electroless plating. As a result, the connection wiring 22 is formed. The subsequent steps are the same as those of the semiconductor device A1.

According to the present embodiment, since the semiconductor device A4 includes the heat spreader 5 and the uneven portion 15, heat dissipation is high as in the semiconductor device A1 of the first embodiment. Further, since the semiconductor device A4 includes the connection wiring 22 having the rewiring portion 222 arranged on the insulating layer main surface 1a and functioning as wiring, the electronic component 9 can be mounted on the insulating layer main surface 1a.

<Fifth Embodiment>
22 and 23 are diagrams for explaining the semiconductor device A5 according to the fifth embodiment of the present disclosure. FIG. 22 is a plan view showing the semiconductor device A5, and is a diagram corresponding to FIG. FIG. 23 is a cross-sectional view showing the semiconductor device A5, and is a diagram corresponding to FIG. In the semiconductor device A5 of the present embodiment, the arrangement position of the uneven portion 15 in the z-direction view is different from that of the fourth embodiment.

The semiconductor device A5 is designed so that a plurality of electronic components 9 (four examples are described in the drawings) are mounted on one side (left side in FIGS. 22 and 23) of the main surface 1a of the insulating layer in the x direction. Has been done. The number and arrangement of the electronic components 9 are shown as an example, and are not limited thereto. In the semiconductor device A5, the uneven portion 15 is arranged on the other side (right side in FIGS. 22 and 23) of the main surface 1a of the insulating layer in the x direction, avoiding the arrangement position of the electronic component 9. The uneven portion 15 does not overlap the entire semiconductor element 3 in the z-direction view, but a part thereof overlaps a part of each semiconductor element 3. Further, as shown in FIG. 23, a rewiring portion 212 of the connection wiring 21 is arranged between each semiconductor element 3 and the uneven portion 15 in the z direction. The rewiring portion 212 contains Cu having a high thermal conductivity, and overlaps each semiconductor element 3 in the z-direction view. Further, a part of the rewiring portion 212 extends to the end portion of the insulating layer 1 on the other side (right side in FIGS. 22 and 23) in the x direction. Such a rewiring portion 212 functions as a heat transfer metal layer that transfers the heat generated by each semiconductor element 3 to the end portion of the uneven portion 15 (the right end portion in FIGS. 22 and 23).

Also in this embodiment, the insulating layer 1 includes an uneven portion 15 formed on the main surface 1a of the insulating layer. The heat dissipation effect of the uneven portion 15 is smaller than that of the semiconductor device A4 according to the fourth embodiment, but the semiconductor device A5 has higher heat dissipation than the conventional semiconductor device. Further, the semiconductor device A5 has a higher degree of freedom in arranging the electronic components 9 to be mounted as compared with the semiconductor device A4 according to the fourth embodiment.

In the present embodiment, the case where a part of the uneven portion 15 overlaps a part of each semiconductor element 3 in the z-direction view has been described, but the present invention is not limited to this. The uneven portion 15 does not have to overlap each semiconductor element 3. Even in this case, a part of the rewiring portion 212 functions as a heat transfer metal layer, and the heat generated by each semiconductor element 3 is transferred to the uneven portion 15. As a result, the uneven portion 15 can release the heat generated by each semiconductor element 3. In this case, since the heat dissipation effect of the uneven portion 15 is low, it is desirable to adopt the configuration of the sixth embodiment or the seventh embodiment described later.

<Sixth Embodiment>
24 and 25 are diagrams for explaining the semiconductor device A6 according to the sixth embodiment of the present disclosure. FIG. 24 is a plan view showing the semiconductor device A6, and is a diagram corresponding to FIG. FIG. 25 is a plan view showing the semiconductor device A6, which is a view through which the second insulating layer 12 is transmitted, and is a view corresponding to FIG. The semiconductor device A6 of the present embodiment is different from the fourth embodiment in the arrangement position of the uneven portion 15 in the z-direction view, and further includes an insulating metal layer 71.

The semiconductor device A6 is designed so that a plurality of electronic components 9 (four examples are described in FIG. 24) are mounted on the other side (right side in FIG. 24) from the center of the main surface 1a of the insulating layer in the x direction. Has been done. The number and arrangement of the electronic components 9 are shown as an example, and are not limited thereto. In the semiconductor device A6, the uneven portion 15 is arranged on one side (left side in FIG. 24) of the main surface 1a of the insulating layer in the x direction, avoiding the arrangement position of the electronic component 9. The uneven portion 15 does not overlap each semiconductor element 3 in the z-direction view.

Further, as shown in FIG. 25, the semiconductor device A6 further includes a plurality of insulating metal layers 71. The insulating metal layer 71 is arranged between the first insulating layer 11 and the second insulating layer 12. The insulating metal layer 71 is such that the rewiring portion 212 of the connection wiring 21 is not connected to the embedded portion 211. Therefore, each insulating metal layer 71 is insulated from the connection wiring 21, the electrode 6, and the semiconductor element 3 by the insulating layer 1. Further, the insulating metal layer 71 has a base layer 201 and a plating layer 202. The plating layer 202 is made of, for example, a material containing copper (Cu). The insulating metal layer 71 is similarly formed when the rewiring portion 212 is formed. Each insulating metal layer 71 extends between the rewiring portions 212 in the z-direction. Further, the insulating metal layer 71 partially overlaps the semiconductor element 3 in the z-direction view, and a part of the insulating metal layer 71 is located outside the semiconductor element 3 and overlaps the uneven portion 15. The insulating metal layer 71 transfers the heat generated by the semiconductor element 3 to the uneven portion 15. The insulating metal layer 71 corresponds to the "heat transfer metal layer" of the present disclosure. The shape and number of the insulating metal layers 71 are not limited, and are appropriately designed according to the shape and arrangement of the rewiring portions 212.

According to the present embodiment, in addition to the rewiring portion 212, the insulating metal layer 71 also functions as a heat transfer metal layer that transfers the heat generated by the semiconductor element 3 to the uneven portion 15. Therefore, the semiconductor device A6 can enhance the heat dissipation effect of the uneven portion 15 as compared with the case where the insulating metal layer 71 is not provided.

<7th Embodiment>
FIG. 26 is a diagram for explaining the semiconductor device A7 according to the seventh embodiment of the present disclosure. FIG. 26 is a cross-sectional view showing the semiconductor device A7, and is a diagram corresponding to FIG. The semiconductor device A7 of the present embodiment is different from the sixth embodiment in that it includes a third insulating layer 13 and an insulating metal layer 73 instead of the insulating metal layer 71. The plan view showing the semiconductor device A7 is the same as that in FIG. 24.

The semiconductor device A7 is designed to mount a plurality of electronic components 9 on the other side (right side in FIGS. 24 and 26) from the center of the main surface 1a of the insulating layer in the x direction. The number and arrangement of the electronic components 9 are shown as an example, and are not limited thereto. In the semiconductor device A7, the uneven portion 15 is arranged on one side (left side in FIGS. 24 and 26) of the main surface 1a of the insulating layer in the x direction, avoiding the arrangement position of the electronic component 9. The uneven portion 15 does not overlap each semiconductor element 3 in the z-direction view.

In the semiconductor device A7, the insulating layer 1 further includes a third insulating layer 13 as shown in FIG. Like the first insulating layer 11 and the second insulating layer 12, the third insulating layer 13 contains a thermosetting synthetic resin and an additive containing a metal element that constitutes a part of a plurality of connecting wirings 21. Consists of materials containing. The third insulating layer 13 is laminated between the first insulating layer 11 and the second insulating layer 12. That is, the third insulating layer 13 is in contact with the first insulating layer 11 and is in contact with the second insulating layer 12. The third insulating layer 13 is formed in the same manner as the second insulating layer 12 after forming the first insulating layer 11 and the connecting wiring 21 and before forming the second insulating layer 12.

The semiconductor device A7 includes an insulating metal layer 73 instead of the insulating metal layer 71. The insulating metal layer 73 is arranged between the third insulating layer 13 and the second insulating layer 12. The insulating metal layer 73 is the same as the insulating metal layer 71 formed on the first insulating layer 11 in the sixth embodiment, and is formed on the third insulating layer 13. The insulating metal layer 73 is insulated from the connection wirings 21 and 22, the electrodes 6, and the semiconductor element 3 by the insulating layer 1. Further, the insulating metal layer 73 has a base layer 201 and a plating layer 202. The plating layer 202 is made of, for example, a material containing copper (Cu). The insulating metal layer 73 is formed in the same manner as the rewiring portion 212 of the connection wiring 21 is formed on the first insulating layer 11 after the third insulating layer 13 is formed. The third insulating layer 13 may be formed with a connecting wiring having an embedded portion and a rewiring portion, similarly to the connecting wiring 21 formed in the first insulating layer 11.

The insulating metal layer 73 extends so as to overlap each of the semiconductor elements 3 and the uneven portion 15 in the z-direction view. Further, the insulating metal layer 73 includes a plurality of penetrating portions 73a penetrating in the z direction. The embedded portion 221 of the connection wiring 22 penetrates the penetrating portion 73a and is also embedded in the third insulating layer 13. The insulating metal layer 73 may not have the penetrating portion 73a and may have a shape that avoids the embedded portion 221 in the z-direction view. In this case, the insulating metal layer 73 may be divided into a plurality of pieces. A part of the insulating metal layer 73 overlaps the semiconductor element 3, and a part of the insulating metal layer 73 is located outside the semiconductor element 3 and overlaps the uneven portion 15. The insulating metal layer 73 transfers the heat generated by the semiconductor element 3 to the uneven portion 15. The insulating metal layer 73 corresponds to the “heat transfer metal layer” of the present disclosure. The shape and number of the insulating metal layers 73 are not limited.

According to the present embodiment, in addition to the rewiring portion 212, the insulating metal layer 73 also functions as a heat transfer metal layer that transfers the heat generated by the semiconductor element 3 to the uneven portion 15. Therefore, the semiconductor device A7 can enhance the heat dissipation effect of the uneven portion 15 as compared with the case where the insulating metal layer 73 is not provided. Further, since the insulating metal layer 73 is formed in a layer different from each rewiring portion 212, the shape of the insulating metal layer 73 does not depend on the shape of each rewiring portion 212. The semiconductor device A7 may further include the insulating metal layer 71 according to the sixth embodiment. In this case, the heat dissipation effect of the uneven portion 15 can be further enhanced.

In the first to seventh embodiments, the case where the two semiconductor elements 3 are arranged has been described, but the present invention is not limited to this. The number of semiconductor elements 3 may be one, or three or more. Further, in the first to seventh embodiments, the case where the semiconductor device 3 includes the electrode only on the element main surface 3a has been described, but the present invention is not limited to this. The semiconductor element 3 may be provided with a back surface electrode 34 on the back surface 3b of the element. In this case, when the semiconductor devices A1 to A2 and A4 to A7 are mounted on the wiring board, the spreader back surface 5b of the heat spreader 5 exposed from the resin opening 4c is joined to the wiring of the wiring board by a conductive joining member. Becomes an external terminal. In this case, the heat spreader 5 needs to have conductivity. Further, when the semiconductor device A3 is mounted on the wiring board, the element back surface 3b of the semiconductor element 3 exposed from the resin opening 4c becomes an external terminal that is joined to the wiring of the wiring board by a conductive joining member.

The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely redesigned.

〔付記６〕
前記半導体素子は、前記厚さ方向視において、第１辺の寸法がＷ１で前記第１辺に直交する第２辺の寸法がＬ１の矩形状であり、
前記ヒートスプレッダは、前記厚さ方向視において、前記第１辺に平行な辺の寸法がＷ２で前記第２辺に平行な辺の寸法がＬ２の矩形状であり、
Ｗ２はＷ１の０．８倍以上１．５倍以下であり、
Ｌ２はＬ１の０．８倍以上１．５倍以下である、
付記３ないし５のいずれかに記載の半導体装置。
〔付記７〕
前記絶縁層は、前記絶縁層主面から前記厚さ方向に凹む凹部を含む凹凸部を有している、
付記１ないし６のいずれかに記載の半導体装置。
〔付記８〕
前記凹凸部は、前記厚さ方向視において、少なくとも一部が前記半導体素子に重なっている、
付記７に記載の半導体装置。
〔付記９〕
前記凹凸部は、前記厚さ方向視において、前記半導体素子の全体に重なっている、
付記８に記載の半導体装置。
〔付記１０〕
前記凹凸部は、前記厚さ方向視において、少なくとも一部が前記伝熱金属層に重なっている、
付記７ないし９のいずれかに記載の半導体装置。
〔付記１１〕
前記凹凸部を覆う放熱金属層をさらに備えている、
付記７ないし１０のいずれかに記載の半導体装置。
〔付記１２〕
前記凹部の深さは、５μｍ以上３００μｍ以下である、
付記７ないし１１のいずれかに記載の半導体装置。
〔付記１３〕
前記凹凸部は、前記厚さ方向視において、前記凹部の内側に、長矩形状の凸部が複数千鳥状に配置されている、
付記７ないし１２のいずれかに記載の半導体装置。
〔付記１４〕
前記絶縁層は、積層された第１絶縁層および第２絶縁層を有し、
前記第１絶縁層は、前記絶縁層裏面を含み、
前記第２絶縁層は、前記凹凸部が配置され、
前記伝熱金属層は、前記第１絶縁層と前記第２絶縁層との間に配置されている、
付記７ないし１３のいずれかに記載の半導体装置。
〔付記１５〕
前記第１絶縁層は、熱硬化性の合成樹脂、および、前記伝熱金属層の一部を組成する金属元素が含有された添加剤を含む材料からなる、
付記１４に記載の半導体装置。
〔付記１６〕
前記伝熱金属層は、前記第１絶縁層に接する下地層と、前記下地層に接するめっき層と、を有し、
前記下地層は、前記添加剤に含有された前記金属元素により組成される、
付記１５に記載の半導体装置。
〔付記１７〕
前記伝熱金属層は、前記主面電極および前記外部端子に導通する接続配線である、
付記１ないし１６のいずれかに記載の半導体装置。
〔付記１８〕
前記伝熱金属層は、前記絶縁層によって絶縁されている、
付記１ないし１６のいずれかに記載の半導体装置。
〔付記１９〕
前記半導体素子は、前記素子裏面に配置された裏面電極をさらに備えている、
付記１ないし１８のいずれかに記載の半導体装置。
〔付記２０〕
前記封止樹脂に一部が覆われている第２の半導体素子をさらに備え、
前記半導体素子および前記第２の半導体素子は、窒化物半導体からなる電子走行層を有するトランジスタである、
付記１ないし１９のいずれかに記載の半導体装置。 [Appendix 1]
A semiconductor device having an element main surface and an element back surface facing opposite sides in the thickness direction, and a main surface electrode arranged on the element main surface.
An insulating layer having an insulating layer back surface that covers the element main surface and faces the element main surface, and an insulating layer main surface that faces the side opposite to the insulating layer back surface in the thickness direction.
A sealing resin having a resin main surface in contact with the back surface of the insulating layer and a resin back surface facing the opposite side of the resin main surface in the thickness direction and covering a part of the semiconductor element.
An external terminal that is exposed from the back surface of the resin and conducts to the main electrode.
A heat transfer metal layer arranged inside the insulating layer, at least partly overlapping the semiconductor element in the thickness direction, and at least partly located outside the semiconductor element.
With
The sealing resin has a resin opening on the back surface side of the resin that overlaps the semiconductor element in the thickness direction.
Semiconductor device.
[Appendix 2]
The back surface of the element is exposed from the resin opening.
The semiconductor device according to Appendix 1.
[Appendix 3]
Further provided with a heat spreader bonded to the back surface of the element,
The heat spreader
The main surface of the spreader facing the back surface of the element and
The back surface of the spreader facing the opposite side of the main surface of the spreader in the thickness direction, and the back surface of the spreader.
Have,
The back surface of the spreader is exposed from the resin opening.
The semiconductor device according to Appendix 1.
[Appendix 4]
The thickness direction dimension t1 of the sealing resin is larger than the thickness direction dimension t2 of the heat spreader.
The linear expansion coefficient α1 of the sealing resin is smaller than the linear expansion coefficient α2 of the heat spreader.
The semiconductor device according to Appendix 3.
[Appendix 5]
When the Young's modulus of the sealing resin is E1 and the Young's modulus of the heat spreader is E2, the dimension t2 satisfies the following formula.
The semiconductor device according to Appendix 4.

[Appendix 6]
The semiconductor element has a rectangular shape in which the dimension of the first side is W1 and the dimension of the second side orthogonal to the first side is L1 in the thickness direction view.
The heat spreader has a rectangular shape in which the dimension of the side parallel to the first side is W2 and the dimension of the side parallel to the second side is L2 in the thickness direction view.
W2 is 0.8 times or more and 1.5 times or less of W1.
L2 is 0.8 times or more and 1.5 times or less of L1.
The semiconductor device according to any one of Appendix 3 to 5.
[Appendix 7]
The insulating layer has an uneven portion including a recess recessed in the thickness direction from the main surface of the insulating layer.
The semiconductor device according to any one of Appendix 1 to 6.
[Appendix 8]
At least a part of the uneven portion overlaps the semiconductor element in the thickness direction view.
The semiconductor device according to Appendix 7.
[Appendix 9]
The uneven portion overlaps the entire semiconductor element in the thickness direction.
The semiconductor device according to Appendix 8.
[Appendix 10]
At least a part of the uneven portion overlaps the heat transfer metal layer in the thickness direction.
The semiconductor device according to any one of Appendix 7 to 9.
[Appendix 11]
A heat-dissipating metal layer that covers the uneven portion is further provided.
The semiconductor device according to any one of Appendix 7 to 10.
[Appendix 12]
The depth of the recess is 5 μm or more and 300 μm or less.
The semiconductor device according to any one of Supplementary note 7 to 11.
[Appendix 13]
In the uneven portion, in the thickness direction view, a plurality of oblong rectangular convex portions are arranged in a staggered manner inside the concave portion.
The semiconductor device according to any one of Appendix 7 to 12.
[Appendix 14]
The insulating layer has a laminated first insulating layer and a second insulating layer.
The first insulating layer includes the back surface of the insulating layer.
The uneven portion is arranged on the second insulating layer.
The heat transfer metal layer is arranged between the first insulating layer and the second insulating layer.
The semiconductor device according to any one of Appendix 7 to 13.
[Appendix 15]
The first insulating layer is made of a material containing a thermosetting synthetic resin and an additive containing a metal element constituting a part of the heat transfer metal layer.
The semiconductor device according to Appendix 14.
[Appendix 16]
The heat transfer metal layer has a base layer in contact with the first insulating layer and a plating layer in contact with the base layer.
The base layer is composed of the metal element contained in the additive.
The semiconductor device according to Appendix 15.
[Appendix 17]
The heat transfer metal layer is a connection wiring that conducts to the main surface electrode and the external terminal.
The semiconductor device according to any one of Appendix 1 to 16.
[Appendix 18]
The heat transfer metal layer is insulated by the insulating layer.
The semiconductor device according to any one of Appendix 1 to 16.
[Appendix 19]
The semiconductor device further includes a back surface electrode arranged on the back surface of the device.
The semiconductor device according to any one of Appendix 1 to 18.
[Appendix 20]
A second semiconductor element whose sealing resin is partially covered with the sealing resin is further provided.
The semiconductor element and the second semiconductor element are transistors having an electron traveling layer made of a nitride semiconductor.
The semiconductor device according to any one of Supplementary note 1 to 19.

A1, A2, A3, A4, A5, A6, A7: Semiconductor device 1: Insulation layer 1a: Insulation layer main surface 1b: Insulation layer back surface 11: First insulation layer 12: Second insulation layer 13: Third insulation layer 15 : Concavo-convex portion 151: Concave portion 152: Convex portion 153: Recessed portion 21: Connection wiring 211: Embedded portion 212: Rewiring portion 22: Connection wiring 221: Embedded portion 222: Rewiring portion 201: Underlayer layer 202: Plating layer 3 , 301, 302: Semiconductor element 3a: Element main surface 3b: Element back surface 31, 32, 33: Main surface electrode 34: Back surface electrode 4: Sealing resin 4a: Resin main surface 4b: Resin back surface 4c: Resin opening 5: Heat spreader 5a: Spreader main surface 5b: Spreader back surface 6, 61-65: Electrode 601: External terminal 602: Internal terminal 603: Connection part 9: Electronic component 71, 73: Insulating metal layer 73a: Penetration part 79: Heat dissipation metal layer 81: Sealing resin 82: First insulating layer 821: Hole 822: Groove 83: Connection wiring 831: Embedded portion 832: Rewiring portion 83A: Underlayer layer 83B: Plating layer 84: Second insulating layer

Claims (20)

A semiconductor device having an element main surface and an element back surface facing opposite sides in the thickness direction, and a main surface electrode arranged on the element main surface.
An insulating layer having an insulating layer back surface that covers the element main surface and faces the element main surface, and an insulating layer main surface that faces the side opposite to the insulating layer back surface in the thickness direction.
A sealing resin having a resin main surface in contact with the back surface of the insulating layer and a resin back surface facing the opposite side of the resin main surface in the thickness direction and covering a part of the semiconductor element.
An external terminal that is exposed from the back surface of the resin and conducts to the main electrode.
A heat transfer metal layer arranged inside the insulating layer, at least partly overlapping the semiconductor element in the thickness direction, and at least partly located outside the semiconductor element.
With
The sealing resin has a resin opening on the back surface side of the resin that overlaps the semiconductor element in the thickness direction.
Semiconductor device. The back surface of the element is exposed from the resin opening.
The semiconductor device according to claim 1. Further provided with a heat spreader bonded to the back surface of the element,
The heat spreader
The main surface of the spreader facing the back surface of the element and
The back surface of the spreader facing the opposite side of the main surface of the spreader in the thickness direction, and the back surface of the spreader.
Have,
The back surface of the spreader is exposed from the resin opening.
The semiconductor device according to claim 1. The thickness direction dimension t1 of the sealing resin is larger than the thickness direction dimension t2 of the heat spreader.
The linear expansion coefficient α1 of the sealing resin is smaller than the linear expansion coefficient α2 of the heat spreader.
The semiconductor device according to claim 3. When the Young's modulus of the sealing resin is E1 and the Young's modulus of the heat spreader is E2, the dimension t2 satisfies the following formula.
The semiconductor device according to claim 4.

The semiconductor element has a rectangular shape in which the dimension of the first side is W1 and the dimension of the second side orthogonal to the first side is L1 in the thickness direction view.
The heat spreader has a rectangular shape in which the dimension of the side parallel to the first side is W2 and the dimension of the side parallel to the second side is L2 in the thickness direction view.
W2 is 0.8 times or more and 1.5 times or less of W1.
L2 is 0.8 times or more and 1.5 times or less of L1.
The semiconductor device according to any one of claims 3 to 5. The insulating layer has an uneven portion including a recess recessed in the thickness direction from the main surface of the insulating layer.
The semiconductor device according to any one of claims 1 to 6. At least a part of the uneven portion overlaps the semiconductor element in the thickness direction view.
The semiconductor device according to claim 7. The uneven portion overlaps the entire semiconductor element in the thickness direction.
The semiconductor device according to claim 8. At least a part of the uneven portion overlaps the heat transfer metal layer in the thickness direction.
The semiconductor device according to any one of claims 7 to 9. A heat-dissipating metal layer that covers the uneven portion is further provided.
The semiconductor device according to any one of claims 7 to 10. The depth of the recess is 5 μm or more and 300 μm or less.
The semiconductor device according to any one of claims 7 to 11. In the uneven portion, in the thickness direction view, a plurality of oblong rectangular convex portions are arranged in a staggered manner inside the concave portion.
The semiconductor device according to any one of claims 7 to 12. The insulating layer has a laminated first insulating layer and a second insulating layer.
The first insulating layer includes the back surface of the insulating layer.
The uneven portion is arranged on the second insulating layer.
The heat transfer metal layer is arranged between the first insulating layer and the second insulating layer.
The semiconductor device according to any one of claims 7 to 13. The first insulating layer is made of a material containing a thermosetting synthetic resin and an additive containing a metal element constituting a part of the heat transfer metal layer.
The semiconductor device according to claim 14. The heat transfer metal layer has a base layer in contact with the first insulating layer and a plating layer in contact with the base layer.
The base layer is composed of the metal element contained in the additive.
The semiconductor device according to claim 15. The heat transfer metal layer is a connection wiring that conducts to the main surface electrode and the external terminal.
The semiconductor device according to any one of claims 1 to 16. The heat transfer metal layer is insulated by the insulating layer.
The semiconductor device according to any one of claims 1 to 16. The semiconductor device further includes a back surface electrode arranged on the back surface of the device.
The semiconductor device according to any one of claims 1 to 18. A second semiconductor element whose sealing resin is partially covered with the sealing resin is further provided.
The semiconductor element and the second semiconductor element are transistors having an electron traveling layer made of a nitride semiconductor.
The semiconductor device according to any one of claims 1 to 19.

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