JP2021118353A - Board processing method and board processing system - Google Patents

Abstract

To appropriately perform static elimination treatment of a substrate after plasma treatment is performed.SOLUTION: A board treatment method includes a step (a) of placing a board on an electrostatic chuck and adsorbing the board to the electrostatic chuck by applying a DC voltage to the electrostatic chuck, a step (b) of supplying high-frequency power to the electrode and generating plasma with inert gas, a step (c) of stopping the application of a DC voltage to the electrostatic chuck, and a step (d) of gradually reducing the high frequency power supplied to the electrode to make high frequency power 0 W.SELECTED DRAWING: Figure 2

Description

The present disclosure relates to a substrate processing method and a substrate processing system.

Patent Document 1 discloses a method of detaching a wafer attracted to an electrostatic chuck. In such a method, when the residual charge of the wafer adsorbed on the electrostatic chuck is removed by using the plasma of the inert gas, the static electricity elimination voltage V _plasma is applied to the chuck electrode. V _plasma corresponds to the self-bias potential V _{dc of the wafer when plasma is applied.}

Patent Document 2 discloses a method of detaching a wafer adsorbed on a sample table. In this method, a direct current applied to the electrode for electrostatically adsorbing the wafer to the sample table after a predetermined time has elapsed after starting the process of separating the sample from the sample table and stopping the supply of high-frequency power for plasma generation. The voltage is changed from a predetermined value to approximately 0V. The predetermined value is a value obtained in advance so that the potential of the wafer becomes approximately 0V when the DC voltage is approximately 0V. The predetermined time is a time defined based on the time during which the charged particles generated by the plasma disappear or the time during which the afterglow discharge disappears.

Japanese Unexamined Patent Publication No. 2004-47511 Japanese Unexamined Patent Publication No. 2018-22756

The technique according to the present disclosure appropriately performs static elimination treatment of the substrate after plasma treatment.

One aspect of the present disclosure is a method of processing a substrate, wherein the substrate is placed on the electrostatic chuck and a DC voltage is applied to the electrostatic chuck to make the substrate into the electrostatic chuck. (B) A step of supplying high-frequency power to the electrodes to generate plasma with an inert gas, (c) a step of stopping the application of the DC voltage to the electrostatic chuck, and (d). ) A step of gradually reducing the high-frequency power supplied to the electrode to reduce the high-frequency power to 0 W.

According to the present disclosure, it is possible to appropriately perform the static elimination treatment of the substrate after the plasma treatment.

It is explanatory drawing which shows the outline of the structure of the plasma processing system which concerns on this Embodiment. It is explanatory drawing which shows the processing process of the wafer detachment processing in this embodiment. It shows the potential of the wafer, the speed of the lifter pin, and the time-dependent change of the high-frequency power supplied to the lower electrode in the wafer detachment process. The changes over time in the wafer potential, lifter pin speed, and high-frequency power supplied to the lower electrode in the wafer detachment process are shown, and the examples and comparative examples are compared. The potential of the wafer, the speed of the lifter pin, and the change over time of the high-frequency power supplied to the lower electrode in the wafer detachment process are shown, and the decrease time of the high-frequency power is varied and compared. It is a graph which shows the potential fluctuation of the wafer when the reduction time is varied when the high frequency power is reduced from 200W to 0W. It is explanatory drawing which shows the processing process of the wafer detachment processing in another embodiment. It is explanatory drawing which shows the processing process of the wafer detachment processing in another embodiment. It is explanatory drawing which shows the processing process of the wafer detachment processing in another embodiment.

In the process of manufacturing a semiconductor device, a plasma processing apparatus generates plasma by exciting a processing gas, and processes a semiconductor wafer (hereinafter, referred to as “wafer”) by the plasma. Such a plasma processing apparatus is provided with an electrostatic chuck (ESC: Electrostatic Chuck) on which a wafer is placed and attracted, and plasma processing is performed in a state where the wafer is attracted and held on the electrostatic chuck.

There are various suction methods for the electrostatic chuck. For example, by applying a DC voltage to the electrostatic chuck, a Coulomb force is generated between the electrostatic chuck and the wafer to suck and hold the wafer. In such a case, when the wafer is separated from the electrostatic chuck, the electric charge remains on the wafer. Therefore, the holding force of the electrostatic chuck with respect to the wafer is maintained, and the wafer may not be properly detached, resulting in misalignment or breakage of the wafer. Therefore, conventionally, various measures have been taken against the residual charge at the time of wafer detachment. For example, there is a method of removing the residual charge of the wafer using plasma.

However, even if the residual charge of the wafer can be removed to the extent that the wafer is properly detached, particles may adhere to the wafer due to this residual charge. That is, when the wafer is lifted up with a lifter pin while the charge remains on the wafer, the residual charge is given a positional change, so that the electric field changes and the charged particles around the wafer are electrically charged on the wafer. Attracted to.

Here, in principle, the electric charge of the wafer is proportional to the high frequency power (power) when generating plasma. Therefore, in order to remove the residual charge of the wafer, a method of reducing the power of this plasma can be considered. However, due to the device configuration, there is a limit to the control of plasma power, and the residual charge of the wafer cannot be reduced to zero.

It is also conceivable to increase the processing pressure when performing the static elimination processing to reduce the self-bias potential of the wafer when plasma is applied. However, in this case, it becomes difficult to sufficiently exchange the processing gas when switching from the plasma processing of the wafer to the static elimination processing. Further, even if the processing pressure of the static elimination treatment is increased, the residual charge of the wafer cannot be reduced to zero.

Further, a method is also conceivable in which the charge of the wafer is transferred to the processing gas while the supply of the processing gas is maintained after the static elimination treatment is performed to reduce the residual charge of the wafer. However, in this case, the throughput of wafer processing is significantly deteriorated.

Further, the detaching method disclosed in Patent Document 1 is also a method of removing the residual charge of the wafer by using plasma. Specifically, a voltage corresponding to the self-bias potential of the wafer when plasma is applied is applied to the chuck electrode, the potential difference between the wafer and the chuck electrode is made almost zero, and the adsorption force based on the self-bias is made almost zero. I'm trying. Here, since the self-bias potential of the wafer does not always match for each wafer, it is necessary to accurately measure the self-bias potential in order to carry out this detachment method. However, it is difficult to measure such a self-bias potential, and in practice, the residual charge of the wafer cannot be reduced to zero.

Further, in the detachment method disclosed in Patent Document 2, after stopping the supply of high-frequency power for plasma generation, a predetermined time is provided in consideration of the disappearance time of charged particles on the wafer, and a sample table (electrostatic chuck) is provided. ) Is set to zero DC voltage. However, if the DC voltage applied to the electrostatic chuck is set to zero after the supply of high-frequency power is stopped, the potential of the wafer changes significantly and many particles are generated.

Here, when the dry etching process is performed as the plasma process, the electric charge remains in the wiring structure formed on the wafer by the dry etching process. Then, in the subsequent wet step, defects such as elution and corrosion of the wiring metal may occur due to the residual charge. The wet step is, for example, a chemical treatment step for removing a specific layer on the wafer or removing foreign matter on the wafer. Then, in order to suppress the above defects, a method of minimizing the residual charge of the wafer after the completion of the dry etching process is required. However, in the conventional static elimination treatment of the wafer described above, the residual charge of the wafer cannot be reduced to zero.

As described above, regardless of which method is used, when the wafer is separated from the electrostatic chuck, the residual charge of the wafer cannot be reduced to zero, and particles adhere to the wafer. Further, even after the dry etching process is completed, the residual charge of the wafer cannot be reduced to zero, and there is a possibility that defects may occur in the wafer in the subsequent wet step. Therefore, there is room for improvement in the conventional method for removing static electricity from wafers.

The technique according to the present disclosure suppresses particles from adhering to the substrate when the substrate attracted and held by the electrostatic chuck is detached, and appropriately detaches the substrate. Hereinafter, the present embodiment will be described with reference to the drawings. In the present specification and the drawings, elements having substantially the same functional configuration are designated by the same reference numerals, so that duplicate description will be omitted.

<Plasma processing system>
First, a plasma processing system as a substrate processing system according to an embodiment will be described. FIG. 1 is a vertical cross-sectional view schematically showing an outline of the configuration of the plasma processing system 1.

In one embodiment, the plasma processing system 1 includes a plasma processing device 1a and a control unit 1b. The plasma processing apparatus 1a includes a plasma processing chamber 10, a gas supply unit 20, an RF (Radio Frequency) power supply unit 30, and an exhaust system 40. Further, the plasma processing apparatus 1a includes a support portion 11 and an upper electrode shower head 12. The support portion 11 is arranged in the lower region of the plasma processing space 10s in the plasma processing chamber 10. The upper electrode shower head 12 is located above the support portion 11 and may function as part of the ceiling of the plasma processing chamber 10.

The support portion 11 is configured to support the wafer W in the plasma processing space 10s. In one embodiment, the support portion 11 includes a lower electrode 111, an electrostatic chuck 112, and an edge ring 113. The electrostatic chuck 112 is arranged on the lower electrode 111 and is configured to support the wafer W on the upper surface of the electrostatic chuck 112. The edge ring 113 is arranged so as to surround the wafer W on the upper surface of the peripheral edge portion of the lower electrode 111. Further, although not shown, in one embodiment, the support portion 11 may include a lifter pin that penetrates the support portion 11 and is configured to be able to move up and down in contact with the lower surface of the wafer W. Further, although not shown, in one embodiment, the support portion 11 may include a temperature control module configured to adjust at least one of the electrostatic chuck 112 and the wafer W to the target temperature. The temperature control module may include a heater, a flow path, or a combination thereof. A temperature control fluid such as a refrigerant or a heat transfer gas flows through the flow path.

The upper electrode shower head 12 is configured to supply one or more processing gases from the gas supply unit 20 to the plasma processing space 10s. In one embodiment, the upper electrode shower head 12 has a gas inlet 12a, a gas diffusion chamber 12b, and a plurality of gas outlets 12c. The gas inlet 12a communicates with the gas supply unit 20 and the gas diffusion chamber 12b. The plurality of gas outlets 12c communicate with the gas diffusion chamber 12b and the plasma processing space 10s in a fluid manner. In one embodiment, the upper electrode shower head 12 is configured to supply one or more processing gases from the gas inlet 12a to the plasma processing space 10s via the gas diffusion chamber 12b and the plurality of gas outlets 12c.

The gas supply unit 20 may include one or more gas sources 21 and one or more flow controllers 22. In one embodiment, the gas supply unit 20 is configured to supply one or more treated gases from the corresponding gas sources 21 to the gas inlets 12a via the corresponding flow rate controllers 22. .. Each flow rate controller 22 may include, for example, a mass flow controller or a pressure-controlled flow rate controller. Further, the gas supply unit 20 may include one or more flow rate modulation devices that modulate or pulse the flow rate of one or more processing gases.

The RF power supply unit 30 transmits RF power, for example one or more RF signals, to one or more such as the lower electrode 111, the upper electrode shower head 12, or both the lower electrode 111 and the upper electrode shower head 12. It is configured to supply to the electrodes of. As a result, plasma is generated from one or more processing gases supplied to the plasma processing space 10s. Therefore, the RF power supply unit 30 can function as at least a part of the plasma generation unit configured to generate plasma from one or more processing gases in the plasma processing chamber. In one embodiment, the RF power supply unit 30 includes two RF generation units 31a, 31b and two matching circuits 32a, 32b. In one embodiment, the RF power supply unit 30 supplies the first RF signal of the first high frequency power HF from the first RF generation unit 31a to the lower electrode 111 via the first matching circuit 32a. It is composed. For example, the first RF signal may have frequencies in the range of 27 MHz to 100 MHz.

Further, in one embodiment, the RF power supply unit 30 supplies the second RF signal of the second high frequency power LF from the second RF generation unit 31b to the lower electrode 111 via the second matching circuit 32b. It is configured as follows. For example, the second RF signal may have a frequency lower than that of the first RF signal and may have a frequency in the range of 400 kHz to 13.56 MHz. Instead, a DC (Direct Current) pulse generation unit may be used instead of the second RF generation unit 31b.

Further, although not shown, other embodiments can be considered in the present disclosure. For example, in an alternative embodiment, the RF power supply unit 30 supplies the first RF signal from the RF generation unit to the lower electrode 111, and supplies the second RF signal from the other RF generation unit to the lower electrode 111. A third RF signal may be configured to be supplied to the lower electrode 111 from yet another RF generator. In addition, in other alternative embodiments, a DC voltage may be applied to the upper electrode shower head 12.

Furthermore, in various embodiments, the amplitude of one or more RF signals (ie, first RF signal, second RF signal, etc.) may be pulsed or modulated. Amplitude modulation may include pulsing the RF signal amplitude between the on and off states, or between two or more different on states.

The exhaust system 40 may be connected to, for example, an exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure valve and a vacuum pump. The vacuum pump may include a turbo molecular pump, a roughing pump or a combination thereof.

In one embodiment, the control unit 1b processes computer-executable instructions that cause the plasma processing apparatus 1a to perform the various steps described in the present disclosure. The control unit 1b may be configured to control each element of the plasma processing apparatus 1a to perform the various steps described herein. In one embodiment, a part or all of the control unit 1b may be included in the plasma processing device 1a. The control unit 1b may include, for example, a computer 51. The computer 51 may include, for example, a processing unit (CPU: Central Processing Unit) 511, a storage unit 512, and a communication interface 513. The processing unit 511 may be configured to perform various control operations based on the program stored in the storage unit 512. The storage unit 512 may include a RAM (Random Access Memory), a ROM (Read Only Memory), an HDD (Hard Disk Drive), an SSD (Solid State Drive), or a combination thereof. The communication interface 513 may communicate with the plasma processing device 1a via a communication line such as a LAN (Local Area Network).

Although various exemplary embodiments have been described above, various additions, omissions, substitutions, and changes may be made without being limited to the above-mentioned exemplary embodiments. It is also possible to combine elements in different embodiments to form other embodiments.

<Plasma processing method>
Next, the plasma processing performed by using the plasma processing system 1 configured as described above will be described. The plasma treatment is not particularly limited, and examples thereof include a dry etching treatment and a film forming treatment.

First, the wafer W is carried into the plasma processing chamber 10, and the wafer W is placed on the electrostatic chuck 112 by raising and lowering the lifter pin. After that, by applying a DC voltage to the electrodes of the electrostatic chuck 112, the wafer W is electrostatically attracted to and held by the electrostatic chuck 112 by Coulomb force. Further, after the wafer W is carried in, the inside of the plasma processing chamber 10 is depressurized to a predetermined degree of vacuum by the exhaust system 40.

Next, the processing gas is supplied from the gas supply unit 20 to the plasma processing space 10s via the upper electrode shower head 12. Further, the RF power supply unit 30 supplies the first high-frequency power HF for plasma generation to the lower electrode 111 to excite the processing gas to generate plasma. At this time, the RF power supply unit 30 may supply a second high-frequency power LF for ion attraction. Then, the wafer W is subjected to plasma treatment by the action of the generated plasma.

During the plasma processing, the temperature of the wafer W attracted and held by the electrostatic chuck 112 is adjusted by the temperature control module. At this time, in order to efficiently transfer heat to the wafer W, a heat transfer gas such as He gas or Ar gas is supplied toward the back surface of the wafer W adsorbed on the upper surface of the electrostatic chuck 112.

When ending the plasma processing, first, the supply of the first high-frequency power HF from the RF power supply unit 30 and the supply of the processing gas by the gas supply unit 20 are stopped. Further, when the second high frequency power LF is supplied during the plasma processing, the supply of the second high frequency power LF is also stopped. Next, the supply of the heat transfer gas to the back surface of the wafer W is stopped, and the adsorption and holding of the wafer W by the electrostatic chuck 112 is stopped.

After that, the wafer W is raised by the lifter pin to separate the wafer W from the electrostatic chuck 112. The details of the method of removing the wafer W will be described later. Then, the wafer W is carried out from the plasma processing chamber 10, and a series of plasma processing on the wafer W is completed.

<Wafer detachment method>
Next, a method of separating the wafer W from the electrostatic chuck 112 after performing plasma treatment on the wafer W as described above will be described with reference to FIGS. 2 and 3.

FIG. 2 is an explanatory diagram showing a processing process in the wafer W detachment processing. FIG. 2 shows the time course of the following parameters. “RF” indicates the radio frequency power (HF) supplied to the lower electrode 111. “B.He” indicates the pressure of the heat transfer gas (He gas in this embodiment). “ESC HV” indicates a DC voltage applied to the electrostatic chuck 112. “Chamber Press” indicates the pressure inside the plasma processing chamber 10. “Pin” indicates the timing for raising and lowering the lifter pin. Further, in FIG. 2, “Dechuck-Step” indicates a process for detaching the wafer W, and “Pre-Step” indicates a process (including plasma processing) before the wafer W is detached. The numerical values of electric power (power), voltage, and pressure in FIG. 2 are examples, and are changed according to the recipe of plasma processing.

FIG. 3 shows the potential of the wafer W (“Wafer V” in FIG. 3), the speed of the lifter pin (“Pin SPD” in FIG. 3), and the high frequency power supplied to the lower electrode 111 in the detachment process of the wafer W (FIG. 3). It shows the time course of "HF") in 3. In FIG. 3, the start time of the wafer W detachment process (the start time of “Dechuck-Step” in FIG. 2) is set to 0 seconds, and the time-dependent change of the above parameters after 2 seconds is shown. The values of the wafer W potential (“Voltage” in FIG. 3) and high-frequency power (“RF Power” in FIG. 3) in FIG. 3 are also examples, and are changed according to the plasma treatment recipe.

In the following description, the wafer W detachment process will be described separately in steps S1 to S4.

(Step S1)
Step S1 is a step immediately after the plasma processing is completed. In step S1, the supply of high-frequency power to the lower electrode 111 is stopped and the high-frequency power becomes 0 W, and the supply of heat transfer gas to the back surface of the wafer W is stopped and the pressure of the heat transfer gas becomes 0 Torr. Further, Ar gas is supplied from the gas supply unit 20 at a flow rate of, for example, 600 sccm, and the pressure in the plasma processing chamber 10 is increased from 50 mTorr to 100 mTorr to 250 mTorr, and in the present embodiment, up to 100 mTorr. The reason for increasing the pressure in the plasma processing chamber 10 in this way is to reduce the self-bias potential of the wafer W and facilitate the detachment of the wafer W. In step S1, the DC voltage is continuously applied to the electrostatic chuck 112, and the wafer W is adsorbed and held by the electrostatic chuck 112.

(Step S2)
In step S2, high frequency power (HF) is supplied to the lower electrode 111, and plasma is generated by the inert gas. Specifically, an inert gas composed of only Ar gas is supplied from the gas supply unit 20 to the plasma processing space 10s via the upper electrode shower head 12. Further, the RF power supply unit 30 supplies high-frequency power to excite the inert gas to generate plasma. When the high frequency power is changed suddenly, the matching circuit 32a may not follow sufficiently and the plasma may become unstable. In order to prevent this, the high frequency power is gradually increased from the state of 0 W, for example, 100 W to 400 W, or 200 W in the present embodiment. The basis for the high frequency power of 100 W to 400 W will be described later.

Further, in step S2, the application of the DC voltage to the electrostatic chuck 112 is stopped. The timing of stopping the application of the DC electrode is after a predetermined time has elapsed after the high-frequency power reaches 200 W and the plasma is generated. This predetermined time is sufficient for the high frequency power to stabilize, for example, 2 seconds. Then, the generated plasma is used to stop the application of the DC voltage to the electrostatic chuck 112, and then the electric charge remaining on the wafer is removed.

(Step S3)
In step S3, the high frequency power supplied to the lower electrode 111 is gradually reduced to 0 W. The timing of starting the decrease in the high frequency power is after a predetermined time (hereinafter, referred to as “delay time”) has elapsed after the application of the DC voltage to the electrostatic chuck 112 is stopped. The delay time is provided in order to suppress the influence of the change in the electric field around the wafer W by stopping the application of the DC voltage to the electrostatic chuck 112 in the state where the plasma is stably generated. The delay time is, for example, 1 second. Then, the high frequency power is reduced at a constant speed, that is, it is reduced linearly. The time for reducing the high frequency power is, for example, 0.5 seconds to 4 seconds. The basis for this decrease time of 0.5 seconds to 4 seconds will be described later.

Here, as a result of diligent studies by the present inventors, when the high-frequency power supplied to the lower electrode 111 is instantaneously reduced from 200 W to 0 W, the electric charge due to the self-bias potential remains on the wafer W, and the electric charge of the wafer W remains. It turns out that the potential cannot be completely reduced to zero. The self-bias potential of the wafer W is proportional to the high frequency power when generating plasma. Therefore, the present inventors considered that the residual charge of the wafer W can be reduced by gradually reducing the high-frequency power supplied to the lower electrode 111. Then, as shown in FIG. 3, it was found that the residual charge of the wafer W can be made substantially zero and the potential of the wafer W can be made substantially zero by gradually reducing the high frequency power in step S3.

(Step S4)
In step S4, the wafer W is raised by the lifter pin, and the wafer W is separated from and separated from the electrostatic chuck 112. With reference to FIG. 3, there are three peaks P1 to P3 for the speed of the lifter pin. The first peak P1 is the speed of the lifter pin until the lifter pin comes into contact with the lower surface of the wafer W. The speed of the lifter pin is increased in order to improve the throughput. The second peak P2 is the speed of the lifter pin when the wafer W is separated from the electrostatic chuck 112 and raised immediately after the lifter pin comes into contact with the lower surface of the wafer W. The third peak P3 is the speed of the lifter pin when the wafer W is raised to the position where the wafer W is carried out after the wafer W is detached from the electrostatic chuck 112. At this time, no attractive force is generated between the electrostatic chuck 112 and the wafer W, and the speed of the lifter pin is increased in order to improve the throughput.

Here, if the electric charge remains on the wafer W at the second peak P2, the capacitance between the upper surface of the electrostatic chuck 112 and the wafer W when the wafer W is detached from the electrostatic chuck 112 Decreases, and the potential of the wafer W also fluctuates. In this respect, in the present embodiment, since the residual charge of the wafer W is made substantially zero by gradually reducing the high frequency power in step S3, the fluctuation of the potential of the wafer W becomes substantially zero.

According to the above embodiment, since the high frequency power supplied to the lower electrode 111 is gradually reduced in step S3, the residual charge of the wafer W is set to substantially zero when the wafer W is separated from the electrostatic chuck 112. Therefore, the potential of the wafer W can be made substantially zero. That is, the static elimination treatment of the wafer W after the plasma treatment can be appropriately performed. Therefore, it is possible to prevent particles from adhering to the wafer W. note that. The particles are composed of, for example, Si, O, C, Al, etc., and have a diameter of, for example, 20 nm to 100 nm.

Further, since the potential of the wafer W can be made substantially zero in this way, the Coulomb force acting between the electrostatic chuck 112 and the wafer W can be reduced, and a smooth lift can be performed when the wafer W is raised by the lifter pin. Can be up. Further, this makes it possible to prevent the wafer W from being damaged when the wafer W is detached from the electrostatic chuck 112. Further, it is possible to suppress the deviation of the center position of the wafer W.

<Effect of this embodiment>
According to the above embodiment, the potential of the wafer W can be made substantially zero as described above. This effect will be described below.

FIG. 4 shows changes with time of the potential of the wafer W, the speed of the lifter pin, and the high-frequency power supplied to the lower electrode 111 in the detachment process of the wafer W. This is a comparison of the comparative example. FIG. 4A shows Comparative Example 1, in which the pressure in the plasma processing chamber 10 is 100 mTorr, and the high frequency power supplied to the lower electrode 111 is instantaneously reduced from 200 W to 0 W. FIG. 4B shows Comparative Example 2, in which the pressure in the plasma processing chamber 10 is 250 mTorr, and the high frequency power supplied to the lower electrode 111 is instantaneously reduced from 100 W to 0 W. FIG. 4C shows an example in which the pressure in the plasma processing chamber 10 is 100 mTorr, and the high frequency power supplied to the lower electrode 111 is gradually reduced from 200 W to 0 W over 2 seconds. show.

As described above, if the electric charge remains on the wafer W at the second peak P2 at the speed of the lifter pin, the potential of the wafer W fluctuates when the wafer W is separated from the electrostatic chuck 112. Therefore, the potential fluctuations of the wafer W are compared between Example 1 and Comparative Examples 1 and 2. The fluctuation of the potential of the wafer W is shown as “ΔV” in FIG. 4 (a).

In Comparative Example 1 shown in FIG. 4A, the potential fluctuation ΔV of the wafer W was -470V, and in Comparative Example 2 shown in FIG. 4B, the potential fluctuation ΔV of the wafer W was −95V. This result means that in Comparative Examples 1 and 2, the electric charge remains on the wafer W when the wafer W is detached.

On the other hand, in Example 1 shown in FIG. 4C, the potential fluctuation ΔV of the wafer W was −10 V. This -10V is within the margin of error and is virtually zero. Therefore, in the first embodiment, the residual charge at the time of detaching the wafer W is substantially zero, and it is possible to suppress the adhesion of particles to the wafer W.

Further, Comparative Example 1 shown in FIG. 4A and Example 1 shown in FIG. 4C were performed on a plurality of wafers W. Then, when the number of parameters attached to the plurality of wafers W was measured and the average value per wafer W was calculated, it was 8.5 in Comparative Example 1, whereas in Example 1, it was 8.5. It was 3.5 pieces. Therefore, it was found that in the present embodiment, it is possible to suppress the actual adhesion of particles to the wafer W.

<Conditions in step S3>
Next, as described above, in step S3, when the high frequency power supplied to the lower electrode 111 is gradually reduced, a suitable range of the reduction time and the high frequency power (power) at the start of the reduction will be described.

FIG. 5 shows changes over time in the potential of the wafer W, the speed of the lifter pin, and the high-frequency power supplied to the lower electrode 111 in the detachment process of the wafer W, and is compared by varying the reduction time. FIG. 5A is the same Comparative Example 1 as in FIG. 4A, and shows an example in which the reduction time is 0 seconds, that is, the high frequency power is instantaneously reduced. FIG. 5 (b) is the same Example 1 as in FIG. 4 (c), and the reduction time is 2 seconds. FIG. 5C shows the second embodiment, and the reduction time is 4 seconds. In FIGS. 5A to 5C, the high frequency power was reduced from 200W to 0W.

In Comparative Example 3 shown in FIG. 5A, the potential fluctuation ΔV of the wafer W was -470V. Therefore, in Comparative Example 3, the electric charge remained on the wafer W when the wafer W was detached.

On the other hand, in the example shown in FIG. 5B, the potential fluctuation ΔV of the wafer W was −10V, and in Example 2 shown in FIG. 5C, the potential fluctuation ΔV of the wafer W was 23V. These -10V and 23V are within the margin of error, respectively, and are substantially zero. Therefore, in Examples 1 and 2, the residual charge at the time of detaching the wafer W is substantially zero, and it is possible to suppress the adhesion of particles to the wafer W.

FIG. 6 is a graph showing the potential fluctuation ΔV of the wafer W when the reduction time is varied when the high frequency power is reduced from 200 W to 0 W. That is, in FIG. 6, the horizontal axis represents the lowering time, and the vertical axis represents the potential fluctuation ΔV of the wafer W.

With reference to FIG. 6, it can be seen that when the decrease time of the high frequency power is 0.5 seconds to 4 seconds, the potential fluctuation ΔV of the wafer W is 65 V or less in absolute value, which is substantially zero. In other words, the preferred range of reduction time is 0.5 seconds to 4 seconds. If the lowering time is too short, it means that the wafer W cannot be completely discharged, which determines the lower limit of the lowering time. Further, if the reduction time is too long, the plasma for static elimination cannot be maintained, which also means that the wafer W cannot be completely statically eliminated, thereby determining the upper limit value of the reduction time.

Here, the high-frequency power and the self-bias potential of the wafer W are proportional to each other, and the larger the high-frequency power, the larger the self-bias potential of the wafer W. Therefore, it is preferable that the high frequency power is as small as possible, and as a result of diligent studies by the present inventors, it has been found that the upper limit value is 400 W. Further, in reality, there is a limit to lowering the high frequency power from the viewpoint of plasma stability, and as a result of diligent studies by the present inventors, it was found that the lower limit of the high frequency power is 100 W. Therefore, a suitable range of high frequency power (power) at the start of reduction is 100 W to 400 W.

<Other Embodiments>
In the above embodiment, as shown in FIG. 2, in step S2, after the delay time elapses after the application of the DC voltage to the electrostatic chuck 112 is stopped, the high frequency power to the lower electrode 111 in step S3 is applied. Started to decline. In this regard, the delay time may be zero as shown in FIG. However, it is preferable to provide a delay time because the high frequency power can be started to decrease after the change in the electric field around the wafer W due to the application of the DC voltage to the electrostatic chuck 112 is surely decreased.

Further, in the above embodiment, as shown in FIG. 2, in step S2, the application of the DC voltage to the electrostatic chuck 112 was instantaneously stopped, but as shown in FIG. 8, the application of the DC voltage was gradually stopped. It may be lowered and stopped. In such a case, the change in the electric field around the wafer W can be minimized, and the particles electrically attracted to the wafer W can be reduced.

Further, the plasma processing apparatus 1a of the above embodiment is configured to supply the first high frequency power HF to the lower electrode 111, but the first high frequency power HF is supplied to the upper electrode shower head 12. It may be configured to be. In such a case, the second high-frequency power LF may be configured to be supplied to the lower electrode 111.

Even when the first high-frequency power HF is supplied to the upper electrode shower head 12 in this way, the self-bias potential of the wafer when plasma is applied is not zero. Therefore, by gradually reducing the high-frequency power supplied to the lower electrode 111 in step S3 as in the above embodiment, it is possible to enjoy the effect that the potential of the wafer W can be made substantially zero.

However, the self-bias potential of the wafer when plasma is applied is larger when the first high-frequency power HF is supplied to the lower electrode 111. Therefore, the effect that the potential of the wafer W described above can be made substantially zero becomes even greater.

In the above embodiment, when the wafer W is detached from the electrostatic chuck 112, the high frequency power HF having a high frequency is supplied to the lower electrode 111, but the high frequency power LF having a low frequency may be supplied. Even in such a case, the same effect as that of the above embodiment can be enjoyed, that is, the potential of the wafer W can be made substantially zero. However, the high-frequency power supplied when the wafer W is detached from the electrostatic chuck 112 is either the high-frequency power HF or the high-frequency power LF.

<Other Embodiments>
In the above embodiment, the electric charge of the wafer W is removed by the plasma generated in step S2, and the high frequency power supplied to the lower electrode 111 is gradually reduced in step S3 due to the self-bias potential of the wafer W. Residual charge can be reduced. As a result, the potential of the wafer W can be made substantially zero. However, depending on the surface condition of the electrostatic chuck 112, even if the application of the DC voltage to the electrostatic chuck 112 is stopped, the electric charge may remain on the surface of the electrostatic chuck 112. For example, there are cases where deposits adhere to the surface of the electrostatic chuck 112 and the surface of the electrostatic chuck 112 is altered by repeated plasma treatment. In such a case, the electric charge may remain on the wafer W due to the influence of the electric charge remaining on the surface of the electrostatic chuck 112.

Therefore, in the present embodiment, the wafer W is separated from the electrostatic chuck 112 and separated from the electrostatic chuck 112 before the plasma generated in step S2 is extinguished, and then the high frequency power supplied to the lower electrode 111 is gradually reduced. Dissipate the plasma. In such a case, as a result of diligent studies by the present inventors, it is possible to remove the electric charge of the wafer W without being affected by the surface state of the electrostatic chuck 112, and the wafer generated when plasma is generated in step S2. It was found that the residual charge due to the self-bias potential of W can be reduced. As a result, the potential of the wafer W can be made substantially zero.

Next, in the present embodiment, a method of detaching the wafer W from the electrostatic chuck 112 will be described with reference to FIG. FIG. 9 is an explanatory diagram showing a processing process in the wafer W detachment processing. FIG. 9 corresponds to FIG. 2 of the above embodiment, and also corresponds to the terms in the figure.

In the following description, the wafer W detachment process will be described separately in steps T1 to T4, as in the above embodiment.

(Step T1)
Step T1 is a step immediately after the plasma treatment is completed. In step T1, the same processing as in step S1 of the above embodiment is performed.

(Step T2)
In step T2, high frequency power (LF) is supplied to the lower electrode 111, and plasma is generated by the inert gas. In step T1, as the high-frequency power, a second high-frequency power LF is used instead of the first high-frequency power HF in step S2 of the above-described embodiment. Except for this point, the same processing as in step S2 of the above-described embodiment is used. Is done.

(Step T3)
In step T3, the wafer W is raised by the lifter pin while maintaining the supply of high-frequency power to the lower electrode 111 in step T2, that is, while maintaining the generation of plasma, and the wafer W is separated from the electrostatic chuck 112. To leave.

(Step T4)
In step T4, the high frequency power supplied to the lower electrode 111 is gradually reduced to 0 W, and the plasma is extinguished. Here, as in the above embodiment, when the high frequency power supplied to the lower electrode 111 is instantaneously reduced from 200 W to 0 W, the electric charge due to the self-bias potential remains on the wafer W, and the potential of the wafer W is completely reduced. Cannot be zero. Therefore, the residual charge of the wafer W is reduced by gradually reducing the high-frequency power supplied to the lower electrode 111. Then, by gradually reducing the high frequency power in step T4, the residual charge of the wafer W can be made substantially zero, and the potential of the wafer W can be made substantially zero. Moreover, at this time, the residual charge of the wafer W can be made substantially zero without being affected by the surface condition of the electrostatic chuck 112.

According to the above embodiment, after the wafer W is separated from the electrostatic chuck 112 in step T3 and separated from the wafer W, the high-frequency power supplied to the lower electrode 111 is gradually reduced in step T4, so that the wafer W is used. The residual charge of the wafer W can be made substantially zero, and the potential of the wafer W can be made substantially zero. That is, the static elimination treatment of the wafer W after the plasma treatment can be appropriately performed.

As described above, when the dry etching process is performed as the plasma process, if the electric charge remains in the wiring structure on the wafer W, defects such as elution and corrosion of the wiring metal may occur due to the residual electric charge in the subsequent wet process. be. According to this embodiment, since the potential of the wafer W after the plasma treatment can be made substantially zero, such defects can be suppressed.

The embodiments disclosed this time should be considered to be exemplary in all respects and not restrictive. The above embodiments may be omitted, replaced or modified in various forms without departing from the scope of the appended claims and their gist.

1 Plasma processing system 1a Plasma processing equipment 1b Control unit 20 Gas supply unit 111 Lower electrode 112 Electrostatic chuck W wafer

Claims (16)

It ’s a way to process the board.
(A) A step of placing the substrate on the electrostatic chuck and adsorbing the substrate to the electrostatic chuck by applying a DC voltage to the electrostatic chuck.
(B) A process of supplying high-frequency power to the electrodes and generating plasma with an inert gas.
(C) A step of stopping the application of the DC voltage to the electrostatic chuck and
(D) A step of gradually reducing the high frequency power supplied to the electrode to reduce the high frequency power to 0 W.
A substrate processing method having. After the step (d),
(E) A step of raising the substrate and separating the substrate from the electrostatic chuck.
The substrate processing method according to claim 1. Between the step (c) and the step (d),
(E) A step of raising the substrate and separating the substrate from the electrostatic chuck.
The substrate processing method according to claim 1. Between the step (a) and the step (b),
(F) A step of supplying a first high-frequency power to the electrode and plasma-treating the substrate.
(G) The step of stopping the supply of the first high-frequency power and
The substrate processing method according to any one of claims 1 to 3. The substrate treatment according to claim 4, wherein in the step (f), the first high-frequency power and the second high-frequency power having a frequency different from that of the first high-frequency power are supplied to the electrode. Method. The substrate processing method according to claim 5, wherein the frequency of the first high-frequency power is higher than the frequency of the second high-frequency power. Between the step (a) and the step (b),
(H) A step of supplying heat transfer gas to the back surface of the substrate and
(I) The step of stopping the supply of the heat transfer gas and
The substrate processing method according to any one of claims 1 to 6, which has the above. The substrate processing method according to any one of claims 1 to 7, wherein in the step (d), the high frequency power is gradually reduced over 0.5 seconds to 4 seconds. The substrate processing method according to any one of claims 1 to 8, wherein in the step (d), the high frequency power is reduced at a constant speed. The substrate processing method according to any one of claims 1 to 9, wherein in the step (c), the DC voltage is gradually reduced. The substrate processing method according to any one of claims 1 to 10, wherein in the step (b), the high frequency power is gradually increased. The substrate processing method according to any one of claims 1 to 11, wherein in the step (b), the inert gas comprises only argon gas. The substrate processing method according to any one of claims 1 to 12, wherein in the step (b), the high frequency power is 100 W to 400 W. The substrate processing method according to any one of claims 1 to 13, wherein the electrode is a lower electrode arranged below the electrostatic chuck. The substrate processing method according to any one of claims 1 to 13, wherein the electrode is an upper electrode arranged above the electrostatic chuck. A system that processes substrates
An electrostatic chuck that attracts and holds the substrate,
With electrodes
A high-frequency power supply unit that supplies high-frequency power to the electrodes,
The gas supply unit that supplies the inert gas and
It has the electrostatic chuck, the high frequency power supply unit, and a control unit that controls the gas supply unit.
The control unit
(A) A step of placing the substrate on the electrostatic chuck and adsorbing the substrate to the electrostatic chuck by applying a DC voltage to the electrostatic chuck.
(B) A step of supplying the high-frequency power to the electrode and generating plasma with an inert gas.
(C) A step of stopping the application of the DC voltage to the electrostatic chuck and
(D) The electrostatic chuck, the high-frequency power supply unit, and the gas supply unit are controlled so as to execute a step of gradually reducing the high-frequency power supplied to the electrode to reduce the high-frequency power to 0 W. Substrate processing system.

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