JP2021096715A - Communication device and processing method for communication device - Google Patents

Abstract

To reduce the power consumption by making the data transfer to an external device more efficient.SOLUTION: A communication device includes a first memory, a first semiconductor integrated circuit connected to the first memory, a second memory, and a second semiconductor integrated circuit connected to the first semiconductor integrated circuit, the second memory, and an external device. When the transfer access unit that the external device allows is less than a threshold, the first semiconductor integrated circuit and the second semiconductor integrated circuit transfer the data stored in the first memory to the second memory, and transfer the data transferred to the second memory further to the external device. When the transfer access unit that the external device allows is more than or equal to the threshold, the first semiconductor integrated circuit and the second semiconductor integrated circuit transfer the data stored in the first memory to the external device without transferring the data to the second memory.SELECTED DRAWING: Figure 2

Description

The present invention relates to a communication device and a processing method of the communication device.

A camera system equipped with a plurality of semiconductor integrated circuits is known in order to realize high resolution and high frame rate of captured images. For example, a camera system capable of handling an image signal input from an image sensor having a high pixel rate by using a plurality of semiconductor integrated circuits having different specifications has been published (see Patent Document 1).

In an image processing device such as a camera system composed of a plurality of semiconductor integrated circuits as in Patent Document 1, the communication unit with an external device such as a recording medium is only one of the plurality of semiconductor integrated circuits. An image processing device having a configuration to be mounted is assumed. In that case, all the data to be recorded in the external device is once aggregated in the memory connected to the semiconductor integrated circuit having the communication part with the external device, and then the semiconductor integrated circuit having the communication part with the external device is on the memory. It is conceivable to transfer the data to an external device.

Japanese Unexamined Patent Publication No. 2013-197608

However, even for data that is already configured to be transferable to the external device as it is on the memory connected to the semiconductor integrated circuit to which the external device is not connected, the semiconductor integrated circuit once has a communication unit with the external device. Aggregate data into memory. Aggregating data into the above-mentioned memory only for the reason of accessing an external device wastes memory bandwidth, and further causes a problem that power is wasted by memory access.

An object of the present invention is to make it possible to reduce power consumption by improving the efficiency of data transfer to an external device.

The communication device of the present invention includes a first memory, a first semiconductor integrated circuit connected to the first memory, a second memory, the first semiconductor integrated circuit, and the second memory. If it has a second semiconductor integrated circuit connected to an external device and the transfer access unit allowed by the external device is less than the threshold value, the first semiconductor integrated circuit and the second semiconductor integrated circuit Transfers the data stored in the first memory to the second memory, transfers the data transferred to the second memory to the external device, and transfers the transfer access unit allowed by the external device. When is equal to or greater than the threshold value, the first semiconductor integrated circuit and the second semiconductor integrated circuit do not allow the data stored in the first memory to pass through the second memory. , Transfer to the external device.

According to the present invention, power consumption can be reduced by improving the efficiency of data transfer to an external device.

It is a block diagram which shows the structural example of an image processing apparatus. It is a flowchart explaining a data transfer procedure. It is a block diagram which shows the structural example of an image processing apparatus. It is a flowchart explaining a data transfer procedure.

(First Embodiment)
FIG. 1 is a block diagram showing a configuration example of the image processing device 100 according to the first embodiment. The image processing device 100 is a communication device and includes a front engine 101, a DRAM 109, a back engine 102, a DRAM 118, and a recording medium 119.

The front engine 101 includes a CPU 103, a sensor IF 104, a moving image codec 105, a PCIe control unit 106, a CPU bus 107, and a memory bus 108. The back engine 102 includes a CPU 110, a PCIe control unit 111, a recording medium control unit 112, a moving image codec 113, a voice processing unit 114, a DMAC 115, a CPU bus 116, and a memory bus 117.

The front engine 101 is connected to the DRAM 109. The back engine 102 is connected to the front engine 101, the DRAM 109, and the recording medium 119. The PCIe control unit 106 is connected to the DRAM 109. The PCIe control unit 111 is connected to the PCIe control unit 106 and the DRAM 118. The recording medium control unit 112 is connected to the DRAM 118 and the recording medium 119.

The front engine 101 is a semiconductor integrated circuit having a connection portion with an image sensor (not shown) and having a function mainly related to image processing. The back engine 102 is a semiconductor integrated circuit having a connection portion with the recording medium 119 and having a function mainly related to recording processing.

The CPU 103 has a function of controlling the entire front engine 101 including each component via the CPU bus 107. The sensor IF 104 has a function of converting a video signal input from an imaging sensor (not shown) into image data and writing the image data to the DRAM 109.

The moving image codec 105 has an image data coding processing function. For example, the moving image codec 105 is a coding unit, and the H.A. Image data is encoded by a coding process that conforms to the 265 / HEVC coding method. The moving image codec 105 has a function of reading out the unencoded image data stored in the DRAM 109, performing an encoding process, and writing back the encoded image data to the DRAM 109.

The DRAM 109 is a dynamic random access memory, which is connected to the sensor IF 104 and the moving image codec 105 via the memory bus 108 in the front engine 101, and has a function of storing data used by each component.

The CPU 110 has a function of controlling the entire back engine 102 including each component via the CPU bus 116. The moving image codec 113 has an image data coding processing function. For example, the moving image codec 113 is a coding unit, and the H.A. Image data is encoded by a coding process that conforms to the 264 / AVC coding method. The moving image codec 113 has a function of reading the unencoded image data stored in the DRAM 118, performing the coding process, and writing back the encoded image data to the DRAM 118.

The voice processing unit 114 has a function of performing voice processing. The DMAC 115 is a DMA controller and has a function of reading data on the DRAM 118 and writing back the data to a desired address on the DRAM 118.

The DRAM 118 is a dynamic random access memory, which is connected to the PCIe control unit 111 and the moving image codec 113 via the memory bus 117 in the back engine 102, and has a function of storing data used by each component.

The PCIe control unit 106 and the PCIe control unit 111 are PCI Express compliant control controllers. Hereinafter, PCI Express will be referred to as PCIe. The PCIe control unit 106 and the PCIe control unit 111 are connected by a PCIe bus 120 and control PCIe communication between the front engine 101 and the back engine 102.

The recording medium control unit 112 is a PCIe-compliant control controller, and is a controller that controls a recording medium 119 having a PCIe-compliant interface. The recording medium 119 is a recording medium having a PCIe-compliant interface, and is a recording medium that can be inserted and removed from the image processing device 100. The recording medium 119 may be a recording medium that cannot be inserted or removed.

FIG. 2 is a flowchart showing a processing method of the image processing apparatus 100 according to the first embodiment. Hereinafter, a procedure in which the image processing device 100 records the image data encoded by the moving image codec 105 in the front engine 101 on the recording medium 119 will be described. It is assumed that the payload sizes allowed by the PCIe control units 106 and 111 and the recording medium control unit 112 are all 2 Kbytes.

First, in step S201, the CPU 110 sets an access unit (transfer access unit) of data to be transferred by the PCIe bus 120 between the front engine 101 and the back engine 102, that is, a threshold value of the so-called payload size. For example, the upper limit payload size allowed by the PCIe control unit 106 and the PCIe control unit 111 is 2 Kbytes, and the threshold value is set to 2 Kbytes, which is the upper limit payload size allowed by the PCIe control unit 106 and the PCIe control unit 111. ..

Next, in step S202, the recording medium control unit 112 confirms the payload size allowed by the recording medium 119 connected to the image processing device 100. The CPU 110 determines whether or not the payload size allowed by the recording medium 119 is equal to or greater than the threshold value set in step S201. The CPU 110 proceeds to step S203 when the payload size allowed by the recording medium 119 is less than the threshold value, and proceeds to step S205 when the payload size allowed by the recording medium 119 is equal to or larger than the threshold value.

In step S203, the PCIe control units 106 and 111 transfer the image data to be recorded on the recording medium 119 stored on the DRAM 109 to a desired address of the DRAM 118. The PCIe control units 106 and 111 transfer image data using the PCIe bus 120. The PCIe control units 106 and 111 transfer with a payload size of 2 Kbytes, which is the threshold value set in step S201.

Next, in step S204, the DMA controller of the recording medium control unit 112 is transferred to the DRAM 118 in step S203, reads the image data stored on the DRAM 118, and transfers the read image data to the recording medium 119. The payload size in the communication between the recording medium control unit 112 and the recording medium 119 is set to the upper limit payload size allowed by the recording medium 119. The upper limit payload size allowed by the recording medium 119 is, for example, 128 bytes. After that, the image processing device 100 proceeds to step S206.

In step S205, the PCIe control units 106 and 111 and the recording medium control unit 112 transfer the image data stored in the DRAM 109 to the recording medium 119 without going through the DRAM 118. The recording medium control unit 112 notifies the recording medium 119 of the address information indicating the memory space of the PCIe control unit 111. For example, the above memory space is from 0x80050,000 to 0x8606000. The PCIe control unit 111 has an address translation function that can be arbitrarily set for the access to the memory space. That is, the PCIe control unit 111 can convert the address to be notified to the opposite PCIe control unit 106 with respect to the address accessed in the memory space of the PCIe control unit 111. Here, the PCIe control unit 111 accesses the memory space of the DRAM 109 from the PCIe control unit 111 via the PCIe control unit 106 by converting the address into the memory space of the DRAM 109 connected to the front engine 101. Is possible. Before the start of data transfer, the PCIe control unit 111 is set by the above address translation function to convert the access from the memory space 0x80050,000 to 0x8606000 to the memory space of the DRAM 109 from 0x50000000 to 0x00060000. With the above settings, it is possible to directly point to the desired address of the DRAM 109 from the recording medium control unit 112. Therefore, when data is read from the address notified from the recording medium control unit 112, the recording medium 119 is on the DRAM 109 via the recording medium control unit 112, the PCIe control unit 111, and the PCIe control unit 106. Image data can be read out. Using this path, the PCIe control units 106 and 111 and the recording medium control unit 112 transfer the image data on the DRAM 109 to the recording medium 119. Here, the payload size in the communication between the recording medium control unit 112 and the recording medium 119 is set to the upper limit payload size allowed by the recording medium 119. The upper limit payload size allowed by the recording medium 119 is, for example, 2 Kbytes. Further, the payload size in the communication of the PCIe bus 120 connecting between the PCIe control unit 106 and the PCIe control unit 111 is also set to the upper limit payload size allowed by the recording medium 119. After that, the image processing device 100 proceeds to step S206.

When the image processing device 100 transfers all the predetermined image data in steps S204 and S205, in step S206, the image processing device 100 completes the transfer and ends the processing of the flowchart of FIG.

Although the first embodiment has been described above, various changes can be made to the first embodiment within the scope of the gist thereof. Although the recording medium 119 has been described in the first embodiment, the recording medium 119 can be replaced with an external device having a PCIe interface. Further, the coding method of the moving image codecs 105 and 113 is not limited.

(Second embodiment)
FIG. 3 is a block diagram showing a configuration example of the image processing device 100 according to the second embodiment. The image processing device 100 of FIG. 3 is provided with a PCIe control unit 301 and a wireless module 302 in place of the recording medium control unit 112 and the recording medium 119 for the image processing device 100 of FIG. Hereinafter, the difference between the second embodiment and the first embodiment will be described.

The back engine 102 has a PCIe control unit 301. The PCIe control unit 301 has a function of controlling communication with the wireless module 302 connected by the PCIe interface. The wireless module 302 has a PCIe interface and has a wireless transmission function such as WiFi for image data.

FIG. 4 is a flowchart showing a processing method of the image processing apparatus 100 according to the second embodiment. Hereinafter, a procedure in which the image processing device 100 transfers the image data encoded by the moving image codec 105 in the front engine 101 to the wireless module 302 will be described with reference to FIG. For example, the payload sizes allowed by the PCIe control units 106, 111, and 301 are all 2 Kbytes.

First, in step S401, the image processing device 100 sets the operation mode of the image processing device 100. For example, the image processing device 100 operates both the moving image codec 105 and the moving image codec 113 to set a mode for transferring image data of two types of coding methods to the wireless module 302.

In step S402, the CPU 110 sets an access unit of data to be transferred by the PCIe bus 120 between the front engine 101 and the back engine 102, that is, a threshold value of the so-called payload size, according to the above operation mode. Here, in the operation mode set in step S401, the encoded image data encoded by the moving image codec 105 is about 2.4 Gbps, and the unencoded image data encoded by the moving image codec 113 is about 10 Gbps. is there. The PCIe control units 106 and 111 need to communicate both of these data from the front engine 101 to the back engine 102 using the PCIe bus 120. Here, when the PCIe bus 120 transfers in two lanes of 8 Gbps of PCIe, the maximum communication rate of communication is 16 Gbps. However, since an overhead of about 20% is usually applied to the bandwidth of the communication data of the high-speed interface, the effective bandwidth of the PCIe bus 120 is about 15 Gbps. When communicating 12.4 Gbps data with the PCIe bus 120 having an effective bandwidth of 15 Gbps, the overhead due to the payload size of the data is 10% of the above 20% overhead. In that case, if the payload size of the encoded image data of the moving image codec 105 in the 2.4 Gbps communication is smaller than 512 bytes, there is a possibility that the entire communication of the image processing device 100 cannot be established. Therefore, when the image processing device 100 operates both the moving image codec 105 and the moving image codec 113 of FIG. 1 and sets a mode for transferring image data of two types of coding methods to the wireless module 302, this threshold value is set. It is set to 512 bytes.

Next, in step S403, the CPU 110 determines whether or not the payload size allowed by the wireless module 302 is equal to or greater than the threshold value. The CPU 110 proceeds to step S404 when the payload size allowed by the wireless module 302 is less than the threshold value, and proceeds to step S406 when the payload size allowed by the wireless module 302 is equal to or larger than the threshold value.

In step S404, the PCIe control units 106 and 111 transfer the image data to be transferred to the wireless module 302 stored on the DRAM 109 to the desired address of the DRAM 118. The PCIe control units 106 and 111 transfer image data using the PCIe bus 120. The PCIe control units 106 and 111 may transfer with a payload size of 512 bytes or more, which is the threshold value specified in step S402. For example, the payload size of the transfer is 2 Kbytes, which is the upper limit of the payload size allowed by the PCIe control units 106 and 111.

Next, in step S405, the PCIe control unit 301 is transferred to the DRAM 118 in step S404, and the image data stored on the DRAM 118 is transferred to the wireless module 302. For example, the payload size in the transfer between the PCIe control unit 301 and the wireless module 302 is 128 bytes. After that, the image processing device 100 proceeds to step S407.

In step S406, the PCIe control units 106, 111 and 301 transfer the image data stored in the DRAM 109 to the wireless module 302 without going through the DRAM 118. The CPU 110 sets an address indicating the memory space of the PCIe control unit 111 to the PCIe control unit 301. For example, the above memory space is from 0x80050,000 to 0x8606000. The PCIe control unit 111 has an address translation function that can be arbitrarily set for the access to the memory space. That is, the PCIe control unit 111 can convert the address to be notified to the opposite PCIe control unit 106 with respect to the address accessed in the memory space of the PCIe control unit 111. Here, the PCIe control unit 111 accesses the memory space of the DRAM 109 from the PCIe control unit 111 via the PCIe control unit 106 by converting the address into the memory space of the DRAM 109 connected to the front engine 101. Is possible. Before the start of data transfer, the PCIe control unit 111 is set by the above address translation function to convert the access from the memory space 0x80050,000 to 0x8606000 to the memory space of the DRAM 109 from 0x50000000 to 0x00060000. With the above settings, it is possible to directly point to the desired address of the DRAM 109 from the PCIe control unit 301. Therefore, the PCIe control unit 301 is on the DRAM 109 via the PCIe control unit 111 and further the PCIe control unit 106 by issuing a data read request to the memory space of the PCIe control unit 111 as described above. Image data can be read out. The PCIe control units 106, 111, and 301 read the image data on the DRAM 109 using this path, and transfer the read image data to the wireless module 302. Here, the payload size in the communication between the PCIe control unit 301 and the wireless module 302 is the upper limit payload size allowed by the wireless module 302. The payload size in the communication of the PCIe bus 120 connecting between the PCIe control unit 106 and the PCIe control unit 111 is also the upper limit payload size allowed by the wireless module 302. After that, the image processing device 100 proceeds to step S407.

When the image processing device 100 transfers all the predetermined image data in steps S405 and S406, in step S407, the image processing device 100 completes the transfer and ends the processing of the flowchart of FIG.

The PCIe control units 106 and 111 transfer the unencoded image data stored in the DRAM 109 to the DRAM 118. The moving image codec 113 reads out the unencoded image data stored in the DRAM 118, performs coding processing, and writes the encoded image data back to the DRAM 118. The PCIe control unit 301 transfers the encoded image data stored in the DRAM 118 to the wireless module 302.

The second embodiment has been described above, but the second embodiment can be changed in various ways within the scope of the gist thereof. Although the wireless module 302 has been described in the second embodiment, the wireless module 302 can be replaced with an external device having a PCIe interface. Further, the coding method of the moving image codecs 105 and 113 is not limited.

According to the first and second embodiments, the image processing apparatus 100 can realize a reduction in power consumption by improving the efficiency of data transfer to an external device such as a recording medium 119 or a wireless module 302.

(Other embodiments)
The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by the processing to be performed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

It should be noted that all of the above embodiments merely show examples of embodiment in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner by these. That is, the present invention can be implemented in various forms without departing from the technical idea or its main features.

101 front engine, 102 back engine, 103 CPU, 104 sensor IF, 105 video codec, 106 PCIe control unit, 107 CPU bus, 108 memory bus, 109 DRAM, 110 CPU, 111 PCIe control unit, 112 recording medium control unit, 113 Video codec, 114 audio processing unit, 115 DMAC, 116 CPU bus, 117 memory bus, 118 DRAM, 119 recording medium, 120 PCIe bus

Claims (18)

The first memory and
A first semiconductor integrated circuit connected to the first memory,
Second memory and
It has the first semiconductor integrated circuit, the second memory, and a second semiconductor integrated circuit connected to an external device.
When the transfer access unit allowed by the external device is less than the threshold value, the first semiconductor integrated circuit and the second semiconductor integrated circuit transfer data stored in the first memory to the second. The data transferred to the second memory is transferred to the external device, and the data is transferred to the external device.
When the transfer access unit allowed by the external device is equal to or greater than the threshold value, the first semiconductor integrated circuit and the second semiconductor integrated circuit can transfer data stored in the first memory. A communication device characterized by transferring data to the external device without going through a second memory. The first semiconductor integrated circuit has a first control unit connected to the first memory.
The second semiconductor integrated circuit is
The first control unit, the second control unit connected to the second memory, and
The communication device according to claim 1, further comprising the second memory and a third control unit connected to the external device. The communication device according to claim 2, wherein the threshold value is an upper limit transfer access unit allowed by the first control unit and the second control unit. The communication device according to claim 1 or 2, wherein the threshold value is set according to an operation mode. The communication device according to any one of claims 1 to 3, wherein the external device is a recording medium. The communication device according to any one of claims 1, 2 and 4, wherein the external device is a wireless module. The communication device according to any one of claims 1 to 6, wherein the first semiconductor integrated circuit and the second semiconductor integrated circuit perform PCI Express-compliant transfer. The communication device according to any one of claims 1 to 7, wherein the first semiconductor integrated circuit and the second semiconductor integrated circuit transfer image data. The first semiconductor integrated circuit has a first coding unit that encodes image data by the first coding method.
The communication device according to any one of claims 1 to 8, wherein the second semiconductor integrated circuit has a second coding unit that encodes image data by a second coding method. .. The first memory and
A first semiconductor integrated circuit connected to the first memory,
Second memory and
A processing method for a communication device including the first semiconductor integrated circuit, the second memory, and a second semiconductor integrated circuit connected to an external device.
When the transfer access unit allowed by the external device is less than the threshold value, the first semiconductor integrated circuit and the second semiconductor integrated circuit transfer data stored in the first memory to the second. The data transferred to the second memory is transferred to the external device, and the data is transferred to the external device.
When the transfer access unit allowed by the external device is equal to or greater than the threshold value, the first semiconductor integrated circuit and the second semiconductor integrated circuit can transfer data stored in the first memory. A processing method of a communication device, characterized in that the data is transferred to the external device without going through a second memory. The first semiconductor integrated circuit has a first control unit connected to the first memory.
The second semiconductor integrated circuit is
The first control unit, the second control unit connected to the second memory, and
The processing method for a communication device according to claim 10, further comprising the second memory and a third control unit connected to the external device. The processing method of a communication device according to claim 11, wherein the threshold value is an upper limit transfer access unit allowed by the first control unit and the second control unit. The processing method of a communication device according to claim 10 or 11, wherein the threshold value is set according to an operation mode. The processing method of a communication device according to any one of claims 10 to 12, wherein the external device is a recording medium. The processing method for a communication device according to any one of claims 10, 11, and 13, wherein the external device is a wireless module. The processing method for a communication device according to any one of claims 10 to 15, wherein the first semiconductor integrated circuit and the second semiconductor integrated circuit perform PCI Express-compliant transfer. The processing method for a communication device according to any one of claims 10 to 16, wherein the first semiconductor integrated circuit and the second semiconductor integrated circuit transfer image data. The first semiconductor integrated circuit has a first coding unit that encodes image data by the first coding method.
The communication device according to any one of claims 10 to 17, wherein the second semiconductor integrated circuit includes a second coding unit that encodes image data by a second coding method. Processing method.

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