JP2021096462A - Array substrate, display panel, and display device - Google Patents

Abstract

To suppress the occurrence of white spots that cause display defects.SOLUTION: An array substrate comprises a switching element 32, a pixel electrode 34 and a common electrode 35 capable of forming a fringe electric field between the pixel electrodes 34 and itself. The pixel electrode 34 includes a contact part 34B that penetrates at least an interlayer insulating film 38 and is connected to a first electrode 32D. The common electrode 35 includes an opening 37 at a position that overlaps the contact part 34B in a plan view. Th opening 37 is divided into an overlapping opening 37A that overlaps the pixel electrode 34 in a plan view and a non-overlapping opening 37B that does not overlap the pixel electrode 34, an interelectrode distance L1 between the pixel electrode 34 and the common electrode 35 facing each other via the non-overlapping opening 37B, in an in-plane direction, being 5 μm and over to less than 10 μm.SELECTED DRAWING: Figure 6

Description

The present invention relates to an array substrate, a display panel, and a display device.

A liquid crystal display device that switches liquid crystal molecules in the plate surface direction (horizontal direction) of a substrate is known to operate in an FFS (Fringe Field Switching) mode, and an example thereof is described in Patent Document 1. In the FFS mode liquid crystal display device, a pixel electrode and a common electrode are both formed on one of a pair of substrates (array substrate) that sandwiches the liquid crystal, and these are arranged in different layers via an interlayer insulating film. The orientation of the liquid crystal molecules is controlled by an oblique electric field (so-called fringe electric field) generated between the pixel electrode and the common electrode.

The liquid crystal display device described in Patent Document 1 has a fringe between a pixel electrode (upper layer electrode) having a slit which is an elongated opening, an interlayer insulating film having a relative permittivity smaller than that of a liquid crystal, and a pixel electrode. It has a common electrode (lower layer electrode) that forms an electric field. The liquid crystal display device of Patent Document 1 makes it possible to suppress the problem that the fringe electric field becomes locally excessive and display defects such as burn-in occur by using a material having a small relative permittivity for the interlayer insulating film.

Japanese Patent No. 5858869

By the way, the pixel electrode is connected to a TFT (Thin film Transistor) which is a switching element through a contact hole. Around the contact hole, fine white spots of about 0.3 mm to about 1 mm may be displayed due to the local excess of the fringe electric field. Therefore, if a material having a small relative permittivity is used for the interlayer insulating film as in Patent Document 1 in order to relax the fringe electric field, the leakage current between the electrodes increases or the light transmittance decreases. Is the reality.

The technique described in the specification of the present application has been completed based on the above circumstances, and an object thereof is to suppress the occurrence of white spots that cause display defects.

(1) The array substrate according to the technique described in the present specification is a pixel connected to an insulating substrate, a switching element arranged on the upper layer side of the insulating substrate, and a first electrode constituting the switching element. The electrode, a common electrode arranged on a layer different from the pixel electrode and capable of forming a fringe electric field between the pixel electrodes, an interlayer insulating film arranged between the pixel electrode and the common electrode, and the above-mentioned A pixel electrode, the common electrode, and an insulating alignment film covering the interlayer insulating film are provided, and the pixel electrode has a contact portion that penetrates at least the interlayer insulating film and is connected to the first electrode. However, the common electrode has an opening at a position where it overlaps with the contact portion when viewed in a plane, and the opening overlaps with the pixel electrode and a superimposed opening which is superimposed on the pixel electrode when viewed in a plane. The distance between the electrode of the pixel electrode and the common electrode facing each other through the non-superimposed opening is 5 μm or more and less than 10 μm in the in-plane direction of the insulating substrate. ..

(2) Further, in the array substrate, in addition to the above (1), the alignment film is superposed on the common electrode facing the pixel electrode through the non-superimposing opening in a plan view, and the insulation is provided. It has a flat portion extending along the in-plane direction of the sex substrate and an inclined portion that superimposes on the non-superimposing opening in a plane and is inclined so as to intersect the in-plane direction of the insulating substrate. The ratio T2 / T1 of the film thickness T1 of the flat portion to the film thickness T2 of the inclined portion may be 0.60 or more and 1.20 or less.

(3) Another array substrate related to the technique described in the present specification is connected to an insulating substrate, a switching element arranged on the upper layer side of the insulating substrate, and a first electrode constituting the switching element. A common electrode arranged on a layer different from the pixel electrode and capable of forming a fringe electric field between the pixel electrodes, and an interlayer insulating film arranged between the pixel electrode and the common electrode. A contact portion comprising the pixel electrode, the common electrode, and an insulating alignment film covering the interlayer insulating film, the pixel electrode penetrating at least the interlayer insulating film and being connected to the first electrode. The common electrode has an opening at a position where it overlaps with the contact portion when viewed in a plane, and the opening has a superposed opening which overlaps with the pixel electrode when viewed in a plane and the pixel electrode. The alignment film is divided into a non-superimposition opening that does not superimpose on the surface of the insulating substrate, and the alignment film is superposed on the common electrode facing the pixel electrode through the non-superimposition opening. The flat portion has a flat portion extending along the inward direction and an inclined portion that superimposes on the non-superimposing opening in a plane and is inclined so as to intersect the in-plane direction of the insulating substrate. The ratio T2 / T1 of the film thickness T1 of the portion to the film thickness T2 of the inclined portion is 0.60 or more and 1.20 or less.

(4) Further, the array substrate is an organic resin material in which the alignment film contains at least one of γ-butyrolactone, N-methylpyrodrin, and butyl cellosolve in addition to the above (2) or (3). It may consist of.

(5) Further, in the array substrate, in addition to any one of the above (1) to (4), the switching element is a thin film transistor, the first electrode is a drain electrode, and the pixel electrode is an interlayer. The common electrode may be arranged on the upper layer side of the insulating film, and the common electrode may be arranged on the lower layer side of the interlayer insulating film.

(6) The display panel according to the technique described in the present specification includes an array substrate according to any one of (1) to (5) above, an opposing substrate arranged to face the array substrate, and the array substrate and the above. A liquid crystal layer sandwiched between the facing substrate and the liquid crystal layer is provided.

(7) The display device related to the technique described in the present specification includes the display panel of (6) above and a lighting device capable of irradiating the display panel with light.

According to the technique described in the present specification, it is possible to suppress the occurrence of white spots that cause display defects.

Perspective view of the liquid crystal display device according to the first embodiment Cross section of liquid crystal panel Equivalent circuit diagram of display pixels Partial plan view showing the wiring structure of the array board Partially enlarged view of the pixel electrode and the common electrode in FIG. Partial cross-sectional view of the liquid crystal panel cut at the AA line position in FIG. Partial cross-sectional view of the liquid crystal panel according to Comparative Example 1 cut at the AA line position in FIG. Table showing the experimental results of Comparative Experiment 1 Top view showing the wiring structure of the array board which concerns on 2nd Embodiment Partial cross-sectional view of the liquid crystal panel cut at the position BB in FIG. The figure which shows the electric charge which is accumulated in the interface between the liquid crystal layer and the alignment film in the gate writing period in the liquid crystal panel which concerns on 2nd Embodiment. The figure which shows the electric charge which is accumulated in the interface between the liquid crystal layer and the alignment film in the gate non-writing period in the liquid crystal panel which concerns on 2nd Embodiment. The figure which shows the electric charge which is accumulated in the interface between the liquid crystal layer and the alignment film in the gate writing period in the liquid crystal panel which concerns on Comparative Example 4. The figure which shows the electric charge which is accumulated in the interface between the liquid crystal layer and the alignment film in the gate non-writing period in the liquid crystal panel which concerns on Comparative Example 4. Table showing the experimental results of Comparative Experiment 2

<First Embodiment>
The liquid crystal display device 100 (an example of the display device) according to the first embodiment will be described with reference to FIGS. 1 to 8. The X-axis, Y-axis, and Z-axis are shown in a part of each drawing other than the table, and each axis direction is drawn so as to be a common direction in each drawing. Further, the + Z axis direction is the front side, and the −Z axis direction is the back side.

As shown in FIG. 1, the liquid crystal display device 100 includes a liquid crystal panel 10 (an example of a display panel) capable of displaying an image, a driver 12 for driving the liquid crystal panel 10, and a control for supplying various signals to the driver 12. A flexible substrate 14 that electrically connects the substrate 16, the liquid crystal panel 10 and the control substrate 16, and an external light source that is arranged on the back side of the liquid crystal panel 10 and irradiates the liquid crystal panel 10 with light for display. It includes at least a backlight device 80 (an example of a lighting device).

As shown in FIG. 1, the liquid crystal panel 10 has a vertically long rectangular shape as a whole, and the inside of the liquid crystal panel 10 has a display area (active area) AA capable of displaying an image and arranged on the center side, and a display area AA. It is divided into a non-display area (non-active area) NAA which is arranged on the outer peripheral side in a form surrounding the above and forms a frame shape (frame shape) when viewed on a flat surface. The short side direction of the liquid crystal panel 10 coincides with the X-axis direction of each drawing, the long side direction coincides with the Y-axis direction of each drawing, and the plate thickness direction coincides with the Z-axis direction. In FIG. 1, the alternate long and short dash line represents the outer shape of the display area AA, and the area outside the alternate long and short dash line is the non-display area NAA.

As shown in FIG. 2, the liquid crystal panel 10 has a pair of substrates 20 and 30, a liquid crystal layer 18, and a sealing portion 50. The liquid crystal layer 18 is sandwiched between the substrates 20 and 30, and contains liquid crystal molecules which are substances whose optical characteristics change with the application of an electric field. The seal portion 50 is arranged in the non-display area NAA so as to surround the liquid crystal layer 18, and is interposed between the two substrates 20 and 30 to maintain the cell gap corresponding to the thickness of the liquid crystal layer 18 and to hold the liquid crystal layer 18. It is sealed.

Of the pair of substrates 20 and 30, the front side is the CF substrate (color filter substrate, facing substrate) 20 and the back side is the array substrate (active matrix substrate, TFT substrate) 30. On the CF substrate 20 and the array substrate 30, various films are laminated and formed on the liquid crystal layer 18 side of the glass substrate GS (an example of an insulating substrate) by a known photolithography method. Polarizing plates 10C and 10D are attached to the outer surfaces of the substrates 20 and 30 (opposite to the liquid crystal layer 18), respectively.

In the display area AA of the CF substrate 20, a large number of color filters are provided side by side in a matrix. In the color filter, three colored films of R (red), G (green), and B (blue) are repeatedly arranged in a predetermined order. In the array substrate 30, pixel electrodes 34, which will be described later, are arranged at positions facing each colored film. One display pixel PX, which is a display unit, is composed of each of the three colored films of R, G, and B and a set of three pixel electrodes 34 facing the colored films.

As shown in FIG. 3, a large number of TFTs 32 and pixel electrodes 34, which are switching elements, are provided side by side in a matrix in the display area AA of the array substrate 30. Further, the gate wiring (scanning line) 36G and the source wiring (data line, signal line) 36S are provided in a grid pattern so as to surround the TFT 32 and the pixel electrode 34. The TFT 32 has a gate electrode 32G connected to the gate wiring 36G, a source electrode 32S connected to the source wiring 36S, and a drain electrode 32D (an example of the first electrode) connected to the pixel electrode 34. Further, the TFT 32 has a semiconductor film in which one end side is connected to the source electrode 32S and the other end side is connected to the drain electrode 32D. The TFT 32 is driven based on the gate signal supplied to the gate wiring 36G. When the source signal is supplied to the source wiring 36S during the gate writing period when the gate signal is equal to or higher than the gate threshold voltage, a current flows between the source electrode 32S and the drain electrode 32D via a channel made of a semiconductor film, and the pixel electrode 34 Is charged to a potential corresponding to the source signal.

As shown in FIG. 4, the gate electrode 32G is branched from the gate wiring 36G and projects from the gate wiring 36G toward the pixel electrode 34 side (upper side) along the Y-axis direction. The source electrode 32S is branched from the source wiring 36S, projects toward the gate electrode 32G side (right side) along the X-axis direction, and a part thereof overlaps with the gate electrode 32G. The drain electrode 32D is arranged at intervals in the X-axis direction with respect to the source electrode 32S, and a part thereof overlaps with the gate electrode 32G. The source wiring 36S, the gate wiring 36G, the source electrode 32S, the drain electrode 32D, and the gate electrode 32G are made of a single layer film of a metal such as copper (Cu) or an alloy, or a laminated film thereof. The semiconductor film is arranged so as to overlap with the gate electrode 32G via a gate insulating film made of an inorganic insulating material. The semiconductor film is made of an oxide semiconductor such as IGZO (Indium Gallium Zinc Oxide).

As shown in FIG. 4, the pixel electrode 34 has a vertically long rectangular shape as a whole. The pixel electrode 34 is made of a transparent electrode film such as ITO (Indium Tin Oxide), and is arranged on the upper layer side of the TFT 32. The pixel electrode 34 is formed with three openings of elongated slits 34A extending along its long side and slightly bent. Further, a part of the pixel electrode 34 projects toward the drain electrode 32D along the Y-axis direction and overlaps with the drain electrode 32D. The pixel electrode 34 has a contact portion 34B at a portion that overlaps with the drain electrode 32D. As shown in FIG. 6, the contact portion 34B penetrates between the layers between the pixel electrode 34 and the drain electrode 32D (specifically, the interlayer insulating film 38 and the flattening film 39 described later), and the drain electrode 32D on the lower layer side penetrates. Is connected to. The contact portion 34B ensures the continuity between the pixel electrode 34 and the drain electrode 32D.

Further, the common electrode 35 is formed in a substantially solid shape in the display region AA of the array substrate 30. The common electrode 35 is made of a transparent electrode film such as ITO (Indium Tin Oxide). As shown in FIGS. 4 and 5, the common electrode 35 has an opening 37 so as to overlap with at least the contact portion 34B, and is formed in a solid shape except for the opening 37. The opening 37 is defined by the opening edge 35A of the common electrode 35, and the outer shape of the opening 37 coincides with the opening edge 35A. The opening 37 and the contact hole CH described later allow the contact portion 34B of the pixel electrode 34 to penetrate between the layers.

As shown in FIG. 6, the common electrode 35 is provided on the lower layer side of the pixel electrode 34 via the interlayer insulating film 38. A reference potential is applied to the common electrode 35. The interlayer insulating film 38 is made of an inorganic insulating material such as _{silicon nitride (SiN x} ) or silicon oxide (SiO _2). When a potential difference occurs between the pixel electrode 34 and the common electrode 35 during the gate writing period, the liquid crystal layer 18 has a plate of the array substrate 30 in addition to a component along the plate surface (XY plane) of the array substrate 30. A fringe electric field containing a component in the normal direction (Z-axis direction) with respect to the surface is applied. The fringe electric field changes the orientation state of the liquid crystal molecules in the liquid crystal layer 18. As a result, the transmittance of the light transmitted through the liquid crystal panel 10 changes, and the display state of the display pixel PX changes. The liquid crystal display device 100 controls the light transmittance in this way, and expresses a color image by a large number of display pixels PX.

As shown in FIG. 5, the openings 37 of the common electrode 35 include a superposed opening 37A that overlaps with the pixel electrode 34 when viewed in a plane, and a non-superimposed opening 37B (shaded portion in FIG. 5) that does not superimpose on the pixel electrode 34. It is divided into ,. The non-superimposing opening 37B is defined by a part of the outer edge of the pixel electrode 34 and a part of the opening edge 35A of the common electrode 35. Assuming that the portion of the outer edge of the pixel electrode 34 that defines the non-overlapping opening 37B is the pixel electrode edge 34E, and the portion of the opening edge 35A of the common electrode 35 that defines the non-overlapping opening 37B is the common electrode edge 35E, the pixel electrode The edge 34E and the common electrode edge 35E include portions facing each other via the non-overlapping opening 37B. The distance between the pixel electrodes 34 (pixel electrode edges 34E) and the common electrodes 35 (common electrode edges 35E) facing each other via the non-superimposition opening 37B is defined as the distance between the electrodes L1. In the array substrate 30 according to the present embodiment, the distance L1 between electrodes is set within a predetermined range.

Specifically, as shown in the result of Comparative Experiment 1 described later, the array substrate 30 has an inter-electrode distance L1 of 5 μm or more and less than 10 μm in the in-plane direction (XY in-plane direction) of the glass substrate GS. Therefore, when mounted on the liquid crystal display device 100, white spots (including spots having a significantly higher brightness than other portions) are generated, which causes display defects while appropriately changing the orientation state of the liquid crystal molecules in the liquid crystal layer 18. Can be none. In the pixel electrode 34 and the common electrode 35, as shown in FIG. 5, the pixel electrode edge 34E and the common electrode edge 35E both extend in the Y-axis direction, and in the X-axis direction via the non-overlapping opening 37B. The portion facing the Y-axis direction and the portion facing the Y-axis direction through the non-overlapping opening 37B while the pixel electrode edge 34E and the common electrode edge 35E both extend in the X-axis direction are included. There is. The distance L1 between the electrodes is 5 μm or more and less than 10 μm in any of the facing portions.

Next, the laminated structure of various films of the array substrate 30 will be described. As shown in FIG. 6, in the array substrate 30, a drain electrode 32D, a flattening film 39, a common electrode 35, an interlayer insulating film 38, and a pixel electrode 34 are laminated and formed on the glass substrate GS in this order around the contact portion 34B. ing. An alignment film 40 is applied to the uppermost layer (the layer closest to the liquid crystal layer 18) of the array substrate 30 so as to cover these various laminated films.

The flattening film 39 is made of a transparent organic insulating material such as an acrylic resin (PMMA or the like) or a polyimide resin, and its film thickness is larger than that of other insulating films (interlayer insulating film 38 or the like). The surface of the display region AA of the array substrate 30 is flattened by the flattening film 39. As shown in FIG. 6, a contact hole CH penetrating the interlayer insulating film 38 and the flattening film 39 is formed as an opening. The interlayer insulating film 38 and the flattening film 39 are formed in a solid shape in the display region AA except for the contact hole CH. The contact hole CH is provided so as to overlap with the opening 37 of the common electrode 35. The contact portion 34B is formed by laminating the pixel electrode 34 on the contact hole CH.

The alignment film 40 is arranged over the entire display region AA of the array substrate 30. As shown in FIG. 6, the alignment film 40 is in contact with the liquid crystal layer 18 of the liquid crystal panel 10 and aligns the liquid crystal molecules contained in the liquid crystal layer 18. The alignment film 40 is made of an organic resin material such as a polyimide resin, and is a photoalignment film oriented by light in a specific wavelength region (for example, ultraviolet rays). The alignment film 40 is formed by applying the raw material with a flexographic printing device, an inkjet printing device, or the like.

As described above, the array substrate 30 is connected to the glass substrate GS, the TFT 32 arranged on the upper layer side of the glass substrate GS, and the drain electrode 32D constituting the TFT 32, and is arranged on the upper layer side of the drain electrode 32D. An interlayer insulating film arranged between the pixel electrode 34 and a common electrode 35 arranged on a layer different from the pixel electrode 34 and capable of forming a fringe electric field between the pixel electrode 34 and between the pixel electrode 34 and the common electrode 35. 38, a pixel electrode 34, a common electrode 35, and an insulating alignment film 40 covering the interlayer insulating film 38 are provided, and the pixel electrode 34 penetrates at least the interlayer insulating film 38 and is connected to the drain electrode 32D. The common electrode 35 has a contact portion 34B, and the common electrode 35 has an opening 37 at a position where the contact portion 34B is viewed in a plane and overlaps with the pixel electrode 34. And the non-superimposition opening 37B that does not overlap with the pixel electrode 34, and the electrode-to-electrode distance L1 between the pixel electrode 34 and the common electrode 35 facing each other via the non-superimposition opening 37B is in the plane of the glass substrate GS. It is 5 μm or more and less than 10 μm in the direction (in-plane direction of XY).

The occurrence of white spots around the contact hole CH, which causes display defects, is that the impurity ions contained in the liquid crystal layer 18 are accumulated at the interface between the liquid crystal layer 18 and the alignment film 40 by the fringe electric field, and the accumulated impurity ions are accumulated. This is due to the increase in the charge of the liquid crystal. In the FFS mode liquid crystal display device 100, since the pixel electrode 34 and the common electrode 35 are both formed on the array substrate 30, for example, the pixel electrode is formed on the array substrate and the common electrode is formed on the CF substrate. Compared to the liquid crystal display device in the Alignment) mode, a strong electric field is likely to be generated between the pixel electrode 34 and the common electrode 35. If the fringe electric field between the pixel electrode 34 and the common electrode 35 becomes excessively large around the contact hole CH, the amount of accumulated charge (charge amount) increases, and it becomes easy to be visually recognized as a white spot. Therefore, by setting the distance L1 between the pixel electrodes 34 and the common electrodes 35 to 5 μm or more in the in-plane direction of the glass substrate GS, the fringe between the pixel electrodes 34 and the common electrodes 35 is set around the contact hole CH. The strength of the electric field can be relaxed.

FIG. 6 schematically shows the electric lines of force F1 of the fringe electric field of the liquid crystal panel 10 according to the present embodiment. Further, FIG. 7 schematically shows an electric field line F2 of a fringe electric field of a liquid crystal panel according to Comparative Example 1 (when the distance L1 between electrodes is less than 5 μm). Comparing the densities of the electric lines of force of FIGS. 6 and 7, the electric lines of force F1 of FIG. 6 are sparse and the electric lines of force F2 of FIG. 7 are dense. That is, it can be seen that the array substrate 30 in FIG. 6 has a small electric field density of the fringe electric field, and the strength is relaxed. By relaxing the electric field, the amount of electric charge accumulated at the interface between the liquid crystal layer 18 and the alignment film 40 is reduced, so that the generation of white spots can be suppressed.

However, if the distance L1 between the pixel electrodes 34 and the common electrodes 35 is 10 μm or more in the in-plane direction of the glass substrate GS, the strength of the fringe electric field becomes too small and the transmittance decreases due to poor alignment of the liquid crystal molecules. May occur. Further, if the opening 37 of the common electrode 35 is widened in order to increase the distance L1 between the electrodes to 10 μm or more, the electrical resistance of the common electrode 35 may increase and crosstalk, flicker, or the like may occur. Further, when the opening 37 is widened, the reference potential applied to the common electrode 35 becomes unstable, and as a result, the voltage applied to the liquid crystal layer 18 may vary, resulting in uneven horizontal streaks due to the difference in brightness. is there. Therefore, by setting the distance L1 between the electrodes to 5 μm or more and less than 10 μm, it is possible to suppress display defects due to the occurrence of white spots while preventing a decrease in transmittance.

<Comparative experiment 1>
Comparative experiment 1 was carried out in order to demonstrate the above-mentioned actions and effects. In Comparative Experiment 1, examples in which the distance L1 between electrodes was different under the following conditions were designated as Example 1 to Example 2 and Comparative Example 1 to Comparative Example 3, and the white point display was evaluated for these Examples and Comparative Examples. .. The results of Comparative Experiment 1 are shown in the table of FIG. In addition, in Example 1 to Example 2 and Comparative Example 1 to Comparative Example 3, the film thickness ratio T2 / T1 of the alignment film 40 is 0.57. The film thickness ratio T2 / T1 is an index showing the film thickness uniformity of the alignment film 40, and will be described in detail in the second embodiment.

<Conditions>
-Source signal level: 255 maximum gradation (normally white white display)
-Applied voltage between the pixel electrode and the common electrode: range between 5V and 8V-Interlayer insulation film thickness: 100nm to 300nm film thickness-Pixel electrode film thickness: 40nm to 80nm film thickness: Common electrode film thickness: Range from 40 nm to 100 nm ・ Film thickness of flattening film: Range from 2000 nm to 4000 nm

<Evaluation of white dot display>
Test samples of the liquid crystal panel according to the examples and comparative examples, the white point display performs energization installed more prone high-temperature environment (70 ° C. from 90 ° C.), white spots per 12inch ² from the plane size 8inch ² The number of occurrences of was visually measured. A high temperature environment of 70 ° C. to 90 ° C. is assumed to be the temperature inside the vehicle under intense heat, for example, when the liquid crystal display device 100 is used for an automobile. The evaluation was rated as ⊚ when no white spots were generated, and as 〇 or × depending on the density of the white spots when white spots were generated. It was evaluated as 〇 when the density of white spots was low and was slight and did not cause display defects, and was evaluated as × when the density of white spots was high and display defects occurred.

In Comparative Examples 1 to 3, 5 or more white spots were observed. In Comparative Example 1 and Comparative Example 2, the density of the generated white spots was high, so that the display was evaluated as x, which resulted in poor display. Comparative Example 3 contained white spots having a lighter density than Comparative Examples 1 and 2, but also contained dark white spots, and was evaluated as x as a whole. In Example 1 and Example 2, no white spots were generated, so the evaluation was ⊚.

<Second Embodiment>
The array substrate 130 according to the second embodiment will be described with reference to FIGS. 9 to 13. In the second embodiment, in the array substrate 130, the distance L1 between the pixel electrodes 34 and the common electrodes 135 is not limited to 5 μm or more and less than 10 μm, and the film thickness uniformity of the alignment film 140 is set within a predetermined range. The point is different from the first embodiment. It should be noted that duplicate description of the same structure, action and effect as in the first embodiment described above will be omitted.

As shown in FIGS. 9 and 10, the size of the opening 137 of the common electrode 135 is smaller than that of the first embodiment. As a result, the distance L1 between the pixel electrodes 34 and the common electrode 135 facing each other via the non-superimposed opening 137B is as short as less than 5 μm (for example, 2 μm). The alignment film 140 is made of an organic resin material containing γ-butyrolactone, N-methylpyrodrin, butyl cellosolve, or the like. By containing any of γ-butyrolactone, N-methylpyrodrin, or butyl cellosolve in the alignment film 140, the leveling (step followability) of the alignment film 140 with respect to the layer to be coated is enhanced, and the alignment film 140 around the contact hole CH is enhanced. The uniformity of the film thickness can be improved.

The film thickness uniformity around the contact hole CH of the alignment film 140 is shown as a film thickness ratio T2 / T1 (a value obtained by dividing the film thickness T2 by the film thickness T1) of the following two film thicknesses T1 and T2. As shown in FIG. 10, the film thickness T1 is vertically superimposed on the common electrode 135 facing the pixel electrode 34 through the non-overlapping opening 137B in the alignment film 140, and is in-plane of the glass substrate GS. It is the film thickness of the flat portion 141 extending along the direction (in-plane direction of XY). The film thickness T2 is the film thickness of the inclined portion 142 of the alignment film 140 that is superposed on the non-overlapping opening 137B in a plane view and is inclined so as to intersect the in-plane direction of the glass substrate GS.

In the present embodiment, the alignment film 140 is formed so that the film thickness ratio T2 / T1 is set to 0.60 or more and 1.20 or less. By doing so, as shown in the result of Comparative Experiment 2 described later, the alignment film 140 can be applied along the shape around the contact hole CH without uneven wetting, and white spots causing display defects can be suppressed. When the film thicknesses of the flat portion 141 and the inclined portion 142 vary, the film thickness ratio T2 / T1 is formed to be 0.60 or more and 1.20 or less in the film thickness range including the variation. It is supposed to be.

As described above, in the generation of white spots, the impurity ions contained in the liquid crystal layer 18 are accumulated at the interface between the liquid crystal layer 18 and the alignment film 140 by the fringe electric field, and the accumulated charge (charge amount) of the impurity ions is generated. Is due to the increase. The mechanism of generating the white spots will be described in detail with reference to FIGS. 12A and 13A. When the film thickness ratio T2 / T1 of the alignment film 940 is less than 0.60, specifically assuming Comparative Example 4 (table of FIG. 13) in which the film thickness ratio T2 / T1 is 0.58, the inclination The film thickness T2 of the portion 942 is 40 nm, which is sufficiently smaller than the film thickness T1 of the flat portion 141, which is 70 nm. In the liquid crystal panel according to Comparative Example 4, during the gate writing period in which the pixel electrode 34 is charged, an electric charge e is accumulated at the interface between the liquid crystal layer 18 and the alignment film 940 by the fringe electric field, as shown in FIG. 12A. Then, as shown in FIG. 12B, these charges e have a portion (a portion where the amount of charge increases) where the charge is collected by redistributing (diffusing) the charge during the gate non-writing period in which the pixel electrode 34 is discharged. It occurs, and this becomes a white spot W and is visually recognized.

On the other hand, the alignment film 140 according to the present embodiment has a film thickness ratio T2 / T1 of 0.60 or more, and the film thickness uniformity of the inclined portion 142 and the flat portion 141 is higher than that of Comparative Example 4. As shown in FIGS. 11A and 11B, the electric charge e is accumulated at the interface between the liquid crystal layer 18 and the alignment film 140, but the redistribution (diffusion) of the electric charge is unlikely to occur during the gate non-writing period, and the electric charge amount increases. Hateful. As a result, it is suppressed that it is visually recognized as a white spot. However, when the film thickness ratio T2 / T1 of the alignment film 140 exceeds 1.20, it becomes difficult for the alignment film 140 to be filled along the shape of the contact hole CH, and there is a possibility that uneven wetting is likely to occur. Therefore, by setting the film thickness ratio T2 / T1 to 0.60 or more and 1.20 or less, it is possible to prevent display defects due to the occurrence of white spots while preventing uneven wetting of the alignment film 140.

<Comparative experiment 2>
Comparative experiment 2 was carried out in order to demonstrate the above-mentioned actions and effects. In the comparative experiment 2, examples in which the film thickness ratio T2 / T1 of the alignment film is different are set as Examples 3 to 7, and Comparative Example 4, and the same conditions and evaluation methods as in Comparative Experiment 1 are applied to these Examples and Comparative Examples. The white dot display was evaluated by. The results of Comparative Experiment 2 are shown in the table of FIG.

In Comparative Example 4, 5 or more dark white spots were visually recognized, so the evaluation was evaluated as x. In both Example 3 and Example 4, 5 white spots were generated, but the density of the white spots was low enough not to cause display defects, so the evaluation was evaluated as 〇. In addition, in Examples 5 to 7, no white spots were generated, so the evaluation was ⊚.

<Third Embodiment>
The array substrate 230 according to the third embodiment will be described. Overlapping description of the same structure, action and effect as those of the first embodiment and the second embodiment described above will be omitted. In the array substrate 230, the distance L1 between the pixel electrodes 34 and the common electrodes 35 is set to 5 μm or more and less than 10 μm as in the first embodiment, and the film thickness ratio of the alignment film 140 is set as in the second embodiment. It is assumed that it is set to 0.60 or more and 1.20 or less. According to such an array substrate 230, it is possible to more reliably suppress display defects due to the occurrence of white spots.

<Other Embodiments>
The techniques described in the present specification are not limited to the embodiments described above and the drawings, and for example, the following embodiments are also included in the technical scope of the present invention.

(1) The shapes of the superposed openings 37A and the non-superimposed openings 37B and 137B shown in the figure are examples and can be changed as appropriate. For example, in FIG. 5, the non-overlapping opening 37B has a symmetrical shape, but it may be asymmetrical. Further, the ratio of the plane sizes of both openings is not limited to the drawing, and can be changed as appropriate.

(2) The shape of the pixel electrode 34 and the shape and number of the slits 34A are not limited to those shown in the drawing, and can be changed as appropriate.

(3) In the array substrate 130 according to the second embodiment, the pixel electrode 34 may be provided on the lower layer side, and the common electrode 135 may be provided on the upper layer side via the interlayer insulating film 38.

(4) The interlayer insulating film 38 and the flattening film 39 may each be composed of two or more insulating films.

(5) The TFT 32 may be a top gate type, a bottom gate type, or a dual gate type.

(6) When the liquid crystal panel 10 does not display in color, the CF substrate 20 may not be provided with a color filter.

(7) The overall shape of the liquid crystal panel 10 may be another shape such as a horizontally long rectangular shape or a non-rectangular shape including a curved portion. Further, the plane size of the liquid crystal panel 10 is not limited, and the technique described in the present specification can be widely applied to the small to large liquid crystal panel 10.

10 ... Liquid crystal panel (display panel), 18 ... Liquid crystal layer, 20 ... CF substrate (opposite substrate), 30,130,230 ... Array substrate, 32 ... TFT (switching element), 32D ... Drain electrode (first electrode), 34 ... pixel electrode, 34B ... contact part, 35,135 ... common electrode, 37,137 ... opening, 37A ... superposed opening, 37B, 137B ... non-superimposed opening, 38 ... interlayer insulating film, 40,140 ... alignment film , 50 ... Seal part, 80 ... Backlight device (lighting device), 100 ... Liquid crystal display device (display device), 141 ... Flat part, 142 ... Inclined part, GS ... Glass substrate (insulating substrate), L1 ... Between electrodes distance

Claims (7)

Insulating board and
A switching element arranged on the upper layer side of the insulating substrate and
A pixel electrode connected to a first electrode constituting the switching element,
A common electrode arranged on a layer different from the pixel electrode and capable of forming a fringe electric field with the pixel electrode,
An interlayer insulating film arranged between the pixel electrode and the common electrode,
The pixel electrode, the common electrode, and an insulating alignment film covering the interlayer insulating film are provided.
The pixel electrode has a contact portion that penetrates at least the interlayer insulating film and is connected to the first electrode.
The common electrode has an opening at a position where it superimposes on the contact portion in a plane.
The opening is divided into a superposed opening that overlaps with the pixel electrode when viewed on a plane and a non-superimposed opening that does not superimpose on the pixel electrode.
An array substrate in which the distance between the pixel electrodes facing each other through the non-superimposed opening and the common electrode is 5 μm or more and less than 10 μm in the in-plane direction of the insulating substrate. The alignment film has a flat portion that superimposes on the common electrode facing the pixel electrode through the non-superimposition opening in a plane and extends along the in-plane direction of the insulating substrate, and the flat portion. It has a non-superimposing opening and an inclined portion that superimposes on a plane and is inclined so as to intersect the in-plane direction of the insulating substrate.
The array substrate according to claim 1, wherein the ratio T2 / T1 of the film thickness T1 of the flat portion to the film thickness T2 of the inclined portion is 0.60 or more and 1.20 or less. Insulating board and
The switching element arranged on the upper layer side of the insulating substrate and
A pixel electrode connected to a first electrode constituting the switching element,
A common electrode arranged on a layer different from the pixel electrode and capable of forming a fringe electric field with the pixel electrode,
An interlayer insulating film arranged between the pixel electrode and the common electrode,
The pixel electrode, the common electrode, and an insulating alignment film covering the interlayer insulating film are provided.
The pixel electrode has a contact portion that penetrates at least the interlayer insulating film and is connected to the first electrode.
The common electrode has an opening at a position where it superimposes on the contact portion in a plane.
The opening is divided into a superposed opening that overlaps with the pixel electrode when viewed on a plane and a non-superimposed opening that does not superimpose on the pixel electrode.
The alignment film has a flat portion that superimposes on the common electrode facing the pixel electrode through the non-superimposition opening in a plane and extends along the in-plane direction of the insulating substrate, and the flat portion. It has a non-superimposing opening and an inclined portion that superimposes on a plane and is inclined so as to intersect the in-plane direction of the insulating substrate.
An array substrate in which the ratio T2 / T1 of the film thickness T1 of the flat portion to the film thickness T2 of the inclined portion is 0.60 or more and 1.20 or less. The array substrate according to claim 2 or 3, wherein the alignment film is made of an organic resin material containing at least one of γ-butyrolactone, N-methylpyrodrin, and butyl cellosolve. The switching element is a thin film transistor.
The first electrode is a drain electrode and
The array substrate according to any one of claims 1 to 4, wherein the pixel electrodes are arranged on the upper layer side of the interlayer insulating film, and the common electrodes are arranged on the lower layer side of the interlayer insulating film. .. The array substrate according to any one of claims 1 to 5.
A facing board arranged to face the array board and
A display panel including a liquid crystal layer sandwiched between the array substrate and the facing substrate. The display panel according to claim 6 and
A display device including a lighting device capable of irradiating the display panel with light.

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