JP2021087049A - Circuit device, electronic device, and moving body - Google Patents

Abstract

To provide a circuit device or the like capable of generating a high-frequency spread spectrum clock.SOLUTION: A circuit device 100 includes a PLL circuit 20 and a spread spectrum circuit 10. The PLL circuit 20 generates an output clock signal CKQ having a frequency higher than that of a reference clock signal CKREF on the basis of the reference clock signal CKREF. The spread spectrum circuit 10 is provided in front of the PLL circuit 20. The spread spectrum circuit 10 performs spread spectrum processing on an input clock signal CKIN, and outputs a clock signal obtained by the spread spectrum processing to the PLL circuit 20 as the reference clock signal CKREF.SELECTED DRAWING: Figure 1

Description

The present invention relates to circuit devices, electronic devices, mobile bodies, and the like.

Spread spectrum is known as a method for reducing EMI in electronic devices. EMI is an abbreviation for Electromagnetic Interference. Spread spectrum is a method of spreading the spectrum peak of a signal by modulating the period of a periodic signal such as a clock signal. Patent Document 1 discloses a spread spectrum clock generator in which a spread spectrum circuit is provided after the clock source.

JP-A-2007-243305

When a PLL circuit is used as the clock source of Patent Document 1, spread spectrum is performed on the clock signal output from the PLL circuit. The PLL circuit multiplies the reference clock signal to generate a high-frequency clock signal, and the higher the frequency of the high-frequency clock signal, the smaller the modulation width for one cycle in spread spectrum. Therefore, there is a problem that it is difficult to raise the frequency of the clock signal generated by the PLL circuit, that is, to generate a high frequency spread spectrum clock.

One aspect of the present disclosure is a PLL circuit that generates an output clock signal having a frequency higher than that of the reference clock signal based on the reference clock signal, and a PLL circuit that is provided in front of the PLL circuit and spread spectrum with respect to the input clock signal. The present invention relates to a circuit device including a spread spectrum circuit that performs processing and outputs a clock signal obtained by the spread spectrum processing to the PLL circuit as the reference clock signal.

Configuration example of a circuit device. A waveform diagram illustrating the operation of a circuit device. The figure which shows the relationship between the clock cycle and the modulation width of a reference clock signal. The figure which shows the relationship between the clock cycle and the modulation width of the output clock signal generated by a PLL circuit. A second configuration example of a circuit device. Detailed configuration example of a spread spectrum circuit. Detailed configuration example of the selector. The waveform diagram explaining the operation of a duty conversion circuit and a spread spectrum circuit. A second detailed configuration example of a spread spectrum circuit. Detailed configuration example of the PLL circuit. Configuration example of electronic equipment. An example of a mobile body.

Hereinafter, preferred embodiments of the present disclosure will be described in detail. It should be noted that the present embodiment described below does not unreasonably limit the contents described in the claims, and not all of the configurations described in the present embodiment are essential constituent requirements.

1. 1. Circuit device FIG. 1 is a configuration example of the circuit device 100 according to the present embodiment. The circuit device 100 includes a spread spectrum circuit 10 and a PLL circuit 20. PLL is an abbreviation for Phase Locked Loop.

The spread spectrum circuit 10 is provided in front of the PLL circuit 20. The first stage means the front side in the order of signal processing, and the output of the spread spectrum circuit 10 becomes the input of the PLL circuit 20. An input clock signal CKIN is input to the spread spectrum circuit 10, and the spread spectrum circuit 10 performs spread spectrum processing on the input clock signal CKIN, and the clock signal obtained by the spread spectrum processing is used as a reference clock signal CKREF. Output. The spread spectrum processing is a processing for performing periodic modulation with reference to the period of the input clock signal CKIN. This modulation diffuses the spectrum peak of the reference clock signal CKREF.

A reference clock signal CKREF is input to the PLL circuit 20 from the spread spectrum circuit 10, and the PLL circuit 20 generates an output clock signal CKQ based on the reference clock signal CKREF. The frequency of the output clock signal CKQ is higher than the frequency of the reference clock signal CKREF. Specifically, the PLL circuit 20 generates the output clock signal CKQ by multiplying the reference clock signal CKREF. The PLL circuit 20 attempts to phase-lock the output clock signal CKQ with respect to the spread spectrum reference clock signal CKREF. Therefore, the output clock signal CKQ becomes a spread spectrum clock signal.

The phase of the reference clock signal CKREF and the phase of the output clock signal CKQ do not necessarily have to match. It suffices that the state in which the PLL circuit 20 follows the phase of the output clock signal CKQ with respect to the phase of the reference clock signal CKREF is maintained.

According to the present embodiment, by providing the spread spectrum circuit 10 in front of the PLL circuit 20, it is possible to perform spread spectrum on the input clock signal CKIN having a frequency lower than that of the output clock signal CKQ. As a result, the frequency of the clock signal generated by the PLL circuit can be increased, and a spread spectrum clock having a higher frequency can be generated as compared with the case where the spread spectrum circuit 10 is provided after the PLL circuit 20.

For example, it is assumed that the upper limit of the clock frequency that the spread spectrum circuit 10 can spread spectrum is 100 MHz. When the spread spectrum circuit 10 is provided after the PLL circuit 20, the upper limit of the frequency of the spread spectrum clock is 100 MHz. On the other hand, when the spectrum spread circuit 10 is provided in front of the PLL circuit 20, the input clock signal CKIN having a frequency lower than 100 MHz is spread spectrum, and the input clock signal CKIN is multiplied by the PLL circuit 20 to increase the frequency from 100 MHz. It is possible to obtain a high frequency output clock signal CKQ. Therefore, the upper limit of the frequency of the spread spectrum clock can be higher than 100 MHz.

2. Operation and Detailed Configuration Example The operation and detailed configuration example of the circuit device 100 will be described below. FIG. 2 is a waveform diagram illustrating the operation of the circuit device 100.

As shown in FIG. 2, the period Rate of the input clock signal CKIN is constant. The edges of the input clock signal CKIN are set to EI1, EI2, EI3, and EI4 in this order. The spread spectrum circuit 10 delays the edges ER1, ER2, ER3, and ER4 of the reference clock signal CKREF with respect to the edges EI1, EI2, EI3, and EI4 of the input clock signal CKIN by the delay times Tdly, 3Tdly, 6Tdly, and 10Tdly. As will be described later in FIG. 6, the input clock signal CKIN is delayed by a delay line including a plurality of delay elements, and the delay time of one of the delay elements corresponds to Tdry.

When the edge is delayed as described above, the period of the reference clock signal CKREF becomes Rate + 2Tdly, Rate + 3Tdly, and Rate + 4Tdly. That is, the difference between the period of the reference clock signal CKREF and the period Rate of the input clock signal CKIN changes as 2Tdly, 3Tdly, and 4Tdly. The difference between the period of the reference clock signal CKREF and the period Rate of the input clock signal CKIN is called a modulation width. The modulation width changes by 1 Tdly per cycle. The amount of change in the modulation width per cycle is called the modulation width for one cycle.

FIG. 3 is a diagram showing the relationship between the clock cycle of the reference clock signal CKREF and the modulation width. The horizontal axis shows the number of clock cycles. If the clock cycle is converted to time, the horizontal axis indicates time. The vertical axis indicates the modulation width in Tdly units as an integer. For example, "3" means a modulation width of 3 Tdly.

The modulation width at 0 cycles is 0. The spread spectrum circuit 10 increases the modulation width by 1 Tdly in the cycles 1 to 4, decreases the modulation width by 1 Tdly in the cycles 5 to 12, and increases the modulation width by 1 Tdly in the cycles 13 to 16. The modulation width at the number of cycles 16 returns to 0. With 16 clock cycles as the modulation cycle TMD, the same modulation is repeated thereafter.

In FIG. 3, the maximum value of the modulation width is MDR = 4Tdry. The ratio of the maximum value MDR of the modulation width to the period Rate of the reference clock signal CKREF is called the modulation factor. In the example of FIG. 3, the modulation factor is represented by MDR / Rate × 100%. In the present embodiment, the frequency of the reference clock signal CKREF is 1 MHz, and therefore Rate = 1000 ns. The modulation width Tdry = 0.2 ns. Therefore, MDR = 4Tdry = 0.8ns. As a result, the modulation factor of the reference clock signal CKREF = 0.8 ns / 1000 ns × 100 = 0.08%. Further, the modulation width for one cycle is MDW1, which corresponds to the slope of the time change of the modulation width. That is, the larger the MDW1, the larger the slope of the time change of the modulation width. The one obtained by converting MDW1 into a modulation factor, that is, the ratio of MDW1 to the periodic Rate of the reference clock signal CKREF is referred to as one clock modulation factor. In the example of FIG. 3, MDW1 = 1Tdry, and one clock modulation factor is represented by MDW1 / Rate × 100%. In the present embodiment, one clock modulation factor of the reference clock signal CKREF = 0.2 ns / 1000 ns × 100 = 0.02%.

In FIG. 3, parameters such as a modulation cycle, a modulation rate, and a modulation width for one cycle are determined for easy illustration, but these parameters are not limited to FIG. For example, the modulation factor of spread spectrum may be such that a sufficient EMI reduction effect can be obtained.

FIG. 4 is a diagram showing the relationship between the clock cycle and the modulation width of the output clock signal CKQ generated by the PLL circuit 20. The PLL circuit 20 multiplies the reference clock signal CKREF by m. m is an integer of 2 or more. FIG. 4 illustrates the case where m = 100. The horizontal axis of FIG. 4 is the number of clock cycle cycles as in FIG. 3, but since the modulation cycle of the output clock signal CKQ is the same as the modulation cycle TMD of the reference clock signal CKREF, it is viewed on a time scale. At that time, the horizontal axis of FIG. 4 and the horizontal axis of FIG. 3 are shown so as to coincide with each other.

In the present embodiment, the period Rate'of the output clock signal CKQ is set to 1 / m of the period Rate'of the reference clock signal CKREF. Further, the modulation width Tdry'for one cycle of the output clock signal CKQ is set to 1 / m ² of the modulation width Tdry'for one cycle of the reference clock signal CKREF. Here, since the 1-clock modulation rate of the output clock signal CKQ is MDW1'= Tdry', the 1-clock modulation rate of the output clock signal CKQ is MDW1'/ Rate' × 100% = (1 / m ² · Tdly) / (1). / M · Rate) x 100% = 1 / m · Tdry / Rate. That is, 1 / m = 1/100 of the 1-clock modulation rate of the reference clock signal CKREF is the 1-clock modulation rate of the output clock signal CKQ. In other words, the 1-clock modulation rate of the reference clock signal CKREF is m times = 100 times the 1-clock modulation rate of the output clock signal CKQ.

The PLL circuit 20 phase-locks the output clock signal CKQ with respect to the reference clock signal CKREF, but when the modulation cycle TMD of the reference clock signal CKREF is too short or the one clock modulation factor of the reference clock signal CKREF is too large, , The reference clock signal CKREF cannot be followed.

Therefore, in the present embodiment, the spread spectrum circuit 10 outputs the reference clock signal CKREF having a modulation period TMD such that the modulation factor of the output clock signal CKQ is the same as the modulation factor of the reference clock signal CKREF. In the present embodiment, the maximum value of the modulation width of the output clock signal CKQ is MDR'= 4Tdly "= 4.1 / m · Tdry, and the period Rate'= 1 / m · Rate. Modulation rate = MDR'/ Rate'= (4.1 / m · Tdly) / (1 / m · Rate) = 4 · Tdry / Rate = Reference clock signal CKREF modulation factor. The modulation width for each m clock cycle, in which the output clock signal CKQ is the number of clock cycles corresponding to one clock cycle of the reference clock signal CKREF. In other words, "Tdry" is a modulation width that is m times the modulation width Tdry'of the output clock signal CKQ.

It is assumed that the modulation rate is fixed and the modulation cycle TMD is shortened. At this time, if the modulation cycle TMD is shorter than a certain lower limit, the PLL circuit 20 does not follow the reference clock signal CKREF. In the present embodiment, the spread spectrum circuit 10 generates a reference clock signal CKREF having a modulation period TMD longer than this lower limit. As a result, the PLL circuit 20 can follow the spread spectrum reference clock signal CKREF, so that a spread spectrum high frequency output clock signal CKQ can be obtained. The modulation factor of the output clock signal CKQ and the modulation factor of the reference clock signal CKREF do not have to be exactly the same. That is, if the PLL circuit 20 follows the reference clock signal CKREF, there may be a slight difference between the modulation rate of the output clock signal CKQ and the modulation rate of the reference clock signal CKREF.

Here, the fact that the PLL circuit 20 follows the reference clock signal CKREF means that the PLL circuit 20 is in phase comparison with the reference clock signal CKREF for each m clock of the output clock signal CKQ. On the contrary, the fact that the PLL circuit 20 cannot follow the reference clock signal CKREF means that the PLL circuit 20 is in phase comparison with the reference clock signal CKREF at an erroneous edge instead of every m clock of the output clock signal CKQ.

Further, in the present embodiment, the spread spectrum circuit 10 uses the reference clock signal CKREF having a modulation period TMD such that m times the one clock modulation factor of the output clock signal CKQ is the same as the one clock modulation factor of the reference clock signal CKREF. Output. In other words, the slope of the time change of the modulation width in the output clock signal CKQ is the same as the slope of the time change of the modulation width in the reference clock signal CKREF.

When the 1-clock modulation rate of the reference clock signal CKREF is increased, the PLL circuit 20 does not follow the reference clock signal CKREF at a 1-clock modulation rate larger than a certain upper limit. In the present embodiment, the spread spectrum circuit 10 generates a reference clock signal CKREF having a clock modulation factor smaller than this upper limit. As a result, the PLL circuit 20 can follow the spread spectrum reference clock signal CKREF, so that a spread spectrum high frequency output clock signal CKQ can be obtained. It should be noted that the m times of one clock modulation factor of the output clock signal CKQ and the one clock modulation factor of the reference clock signal CKREF do not have to be exactly the same. That is, if the PLL circuit 20 follows the reference clock signal CKREF, there may be a slight difference between m times the one clock modulation factor of the output clock signal CKQ and the one clock modulation factor of the reference clock signal CKREF.

Further, in the present embodiment, the spread spectrum circuit 10 outputs a reference clock signal CKREF in which the modulation width MDW1 for one cycle of the reference clock signal CKREF is smaller than the allowable cycle-to-cycle jitter of the PLL circuit 20. Cycle-to-cycle jitter is the periodic variation between cycles of the reference clock signal CKREF. That is, the cycle-to-cycle jitter is the difference between the period of the reference clock signal CKREF in one cycle and the period in the next cycle. The permissible cycle-to-cycle jitter is the upper limit of the cycle-to-cycle jitter that the PLL circuit 20 can follow.

Specifically, the modulation cycle TMD and one clock modulation factor of the reference clock signal CKREF are set so that the modulation width MDW1 for one cycle of the reference clock signal CKREF is smaller than the allowable cycle-to-cycle jitter of the PLL circuit 20. ing. As a result, the modulation factor of the output clock signal CKQ becomes the same as the modulation factor of the reference clock signal CKREF, or m times the modulation factor of one clock of the output clock signal CKQ becomes the same as the modulation factor of one clock of the reference clock signal CKREF. The condition of becoming is satisfied.

FIG. 5 is a second configuration example of the circuit device 100. The circuit device 100 includes a duty conversion circuit 13, a spread spectrum circuit 10, and a PLL circuit 20. The components already described are designated by the same reference numerals, and the description of the components will be omitted as appropriate.

The second input clock signal CKIN'is input to the duty conversion circuit 13. The duty conversion circuit 13 converts the second input clock signal CKIN'to an input clock signal CKIN whose high-width duty is smaller than 50%, and outputs the input clock signal CKIN to the spread spectrum circuit 10. The second input clock signal CKIN'may be input from the outside of the circuit device 100, or may be generated by an oscillation circuit (not shown) built in the circuit device 100 or the like.

Specifically, when the ratio of the high width to the low width of the input clock signal CKIN output by the duty conversion circuit 13 is 1: p, p is a real number larger than 1. The spread spectrum circuit 10 performs spread spectrum processing on the input clock signal CKIN from the duty conversion circuit 13. The duty of the second input clock signal CKIN'is arbitrary.

FIG. 6 is a detailed configuration example of the spread spectrum circuit 10. The spread spectrum circuit 10 includes a delay line 11, a selector 12, a duty conversion circuit 13, and a control circuit 14. In the following, the input clock signal CKIN is also referred to as a clock signal CK0.

The delay line 11 includes n delay elements connected in series. n is an integer of 3 or more, and here n = 16. The 16 delay elements are inverters IV1 to IV16. Connecting in series means that the output of the inverter IVj is input to the inverter IVj + 1. j is an integer of 1 or more and 15 or less. The inverters IV1 to IV16 sequentially delay the clock signal CK0.

The output nodes of k of the inverters IV1 to IV16 are connected to the selector 12. k is an integer greater than or equal to 1 and less than n. In FIG. 5, k = 7, and the k inverters are IV1, IV3, IV6, IV10, IV13, IV15, and IV16. Therefore, the clock signals CK1, CK3, CK6, CK10, CK13, CK15, and CK16 are input to the selector 12. Further, the clock signal CK0 is input to the selector 12.

The selector 12 selects one clock signal from the clock signals CK0, CK1, CK3, CK6, CK10, CK13, CK15, and CK16, and outputs the clock signal as the reference clock signal CKREF. Specifically, the selector 12 selects clock signals CK0, CK1, CK3, CK6, CK10, CK13, CK15, and CK16 in clock cycles 0, 1, 2, 3, 4, 5, 6, 7, and 8. The delays of the clock signals CK0, CK1, CK3, CK6, CK10, CK13, CK15, and CK16 are 0, 1, 3, 6, 10, 13, 15, and 16 in Tdry units. Therefore, the modulation widths in clock cycles 0, 1, 2, 3, 4, 5, 6, 7, and 8 are 0, 1, 2, 3, 4, 3, 2, and 1 in Tdry units. The selector 12 selects clock signals CK15, CK13, CK10, CK6, CK3, CK1, and CK0 in clock cycles 9, 10, 11, 12, 13, 14, 15, and 16. As a result, the modulation widths in clock cycles 9, 10, 11, 12, 13, 14, 15, and 16 become 0, -1, -2, -3, -4, -3, -2, -1, 0. Become. In this way, the modulation described in FIG. 3 is realized.

The control circuit 14 controls the clock selection operation of the selector 12. Specifically, the selector 12 is controlled so as to select the reference clock signal CKREF in the order described above. The control circuit 14 operates based on the input clock signal CKIN. Specifically, the control circuit 14 causes the selector 12 to switch the reference clock signal CKREF at the edge timing of the clock signal CK0.

According to the present embodiment, since a plurality of clock signals CK1 to CK16 having different delay times are generated by using only one delay line 11, delay adjustment between the clock signals CK1 to CK16 is easy. That is, the delay time of the delay element fluctuates due to fluctuations in voltage, temperature, and process, but since there is only one delay line 11, the context between the clock signals CK1 to CK16 does not change, and the clock. The delay time between them is also equal.

Further, according to the present embodiment, clock signals are input to the selector 12 from 7 inverters IV1, IV3, IV6, IV10, IV13, IV15, and IV16 out of 16 inverters IV1 to IV16. For example, FIG. 12 of Patent Document 1 describes a spread spectrum clock generator in which clock signals are input to selectors from all delay elements. Compared to such a configuration, in the present embodiment, the number of wires connecting the delay line 11 and the selector 12 is reduced, so that the circuit scale can be reduced.

The seven inverters IV1, IV3, IV6, IV10, IV13, IV15, IV16 are selected based on the difference sequence. The difference sequence is a sequence generated from the original sequence, and the difference between adjacent terms in the original sequence is made into a sequence.

Specifically, if the numbers of the above seven inverters are the terms of a sequence, the sequence is {1,3,6,10,13,15,16}. Here, 0 is added as a term corresponding to the clock signal CK0, and the sequence is {0,1,3,6,10,13,15,16}. If this is used as the base sequence, the difference sequence is {1,2,3,4,3,2,1}. {1,2,3,4} is an arithmetic progression with a tolerance of 1, and {4,3,2,1} is an arithmetic progression with a tolerance of -1. Arithmetic progression is a sequence in which the differences between adjacent terms are common, and the common differences are called tolerances. As described above, in the present embodiment, seven inverters are selected so that the arithmetic progression becomes an arithmetic progression.

FIG. 7 is a detailed configuration example of the selector 12. The selector 12 includes input circuits BFS0, IVS1, IVS3, BFS6, BFS10, IVS13, IVS15, BFS16, and a delay adjustment circuit 15.

The clock signal CK0 is input to the input circuit BFS0. Input circuits IVS1, IVS3, BFS6, BFS10, IVS13, IVS15, and BFS16 are k input circuits into which k clock signals are input, and here, k = 7. That is, clock signals CK1, CK3, CK6, CK10, CK10, CK13, CK15, and CK16 are input to the input circuits IVS1, IVS3, BFS6, BFS10, IVS13, IVS15, and BFS16.

The input circuit BFS0 is a buffer. The input circuits IVS1, IVS3, IVS13, and IVS15 to which the clock signals CK1, CK3, CK13, and CK15 are input from the odd-numbered inverters IV1, IV3, IV13, and IV15 are inverters. The input circuits BFS6, BFS10, and BFS16 to which the clock signals CK6, CK10, and CK16 are input from the even-numbered inverters IV6, IV10, and IV16 are buffers. The buffer in FIG. 6 is a logic element that outputs an output signal having the same logic as the logic of the input signal.

As described with reference to FIG. 6, the delay element constituting the delay line 11 is an inverter. Therefore, the logic of the clock signals CK1, CK3, CK13, and CK15 output from the odd-numbered inverters IV1, IV3, IV13, and IV15 is inverted with respect to the clock signal CK0. In the present embodiment, since the input circuits IVS1, IVS3, IVS13, and IVS15 are inverters, the clock signals output by the input circuits IVS1, IVS3, IVS13, and IVS15 have the same logic as the clock signal CK0. The logic inversion and the same logic here mean that the logic is inverted or the same logic if the delay time due to the inverter is ignored.

The control circuit 14 outputs the selection signals SEL0, SEL1, SEL3, SEL6, SEL10, SEL13, SEL15, and SEL16 to the input circuits IVS1, IVS3, BFS6, BFS10, IVS13, IVS15, and BFS16. The control circuit 14 activates any one of these selection signals and deactivates the other selection signals. The input circuit to which the active selection signal is input is enabled and passes the input clock signal. The output of the input circuit to which the inactive selection signal is input becomes high impedance. Let the clock signal selected by the selection signal be CKSQ.

The delay adjustment circuit 15 adjusts the delay of the clock signal CKSQ and outputs the adjusted clock signal as the reference clock signal CKREF. The delay adjustment is an adjustment that reduces an error with respect to a desired delay amount of the clock signal. Specifically, since there is a difference in the amount of delay between the clock signal output from the inverter and the clock signal output from the buffer in the input circuit, the delay adjustment circuit 15 adjusts the difference. The delay adjustment circuit 15 includes buffers BADJ1, BADJ2, and BADJQ.

The control circuit 14 outputs the adjustment control signals SADJ1 and SADJ2 to the buffers BADJ1 and BADJ2. The control circuit 14 activates the adjustment control signal SADJ1 when enabling any of the buffer input circuits BFS0, BFS6, BFS10, and BFS16. The buffer BADJ1 is enabled and drives the clock signal CKSQ. At this time, the adjustment control signal SADJ2 is inactive, and the output of the buffer BADJ2 has high impedance. The control circuit 14 activates the adjustment control signal SADJ2 when enabling any of the input circuits IVS1, IVS3, IVS13, and IVS15, which are inverters. The buffer BADJ2 is enabled and drives the clock signal CKSQ. At this time, the adjustment control signal SADJ1 is inactive, and the output of the buffer BADJ1 has high impedance.

The delay time of the buffer BADJ1 and the delay time of the buffer BADJ2 are different, and the error with respect to the desired delay amount is corrected. That is, the difference between the delay amount of the clock signal output from the inverter and the delay amount of the clock signal output from the buffer in the input circuit is corrected. The buffer BADJQ drives the clock signal output from the buffer BADJ1 or the buffer BADJ2 and outputs it as a reference clock signal CKREF.

According to this embodiment, since the input circuit of the selector 12 matches the logic of the clock signal, it is possible to use the inverters IV1 to IV16 as the delay element of the delay line 11.

If a buffer is used as the delay element, the output of the delay element has the same logic, so that the rising edge of the clock signal input to the delay line is also the rising edge of the output of each delay element. Similarly, the falling edge of the clock signal input to the delay line is also the falling edge at the output of each delay element. At this time, if there is a difference between the delay with respect to the rising edge and the delay with respect to the falling edge of the delay element, the duty of the clock signal passing through the delay line collapses.

In this respect, since the delay element of the delay line 11 is an inverter in the present embodiment, the rising edge of the clock signal input to the delay line alternately becomes a rising edge and a falling edge at the output of each inverter. Therefore, even if there is a difference between the delay with respect to the rising edge and the delay with respect to the falling edge of the inverter, they are alternately affected and averaged. The same applies to the falling edge of the clock signal input to the delay line. As a result, the duty of the clock signal that has passed through the delay line 11 is unlikely to collapse.

FIG. 8 is a waveform diagram illustrating the operation of the duty conversion circuit 13 and the spread spectrum circuit 10.

The duty conversion circuit 13 generates a clock signal CK0 having a high-width and low-width duty of 1: 7. As described above, the high width duty of the clock signal CK0 may be smaller than 50%.

Inverters IV1 to IV16 output clock signals CK1 to CK16. In FIG. 8, the clock signals CK1 to CK16 are shown in positive logic by ignoring the logic inversion by the inverter in order to make the illustration easier to understand. The clock signals CK1 to CK16 are sequentially delayed by Tdry with respect to the clock signal CK0. Tdry is a delay time for one inverter.

The selector 12 selects the reference clock signal CKREF in the cycle of the clock signal CK0. Specifically, the selector 12 sets the reference clock signal CKREF to the clock signals CK0, CK1, CK3, CK6, CK10, CK13, CK15 at the selection timings TSa, TSb, TSc, TSd, TSe, TSf, TSg, TSh, and TSi. , Switch to CK16. The selection timings TSa to TSi are edge timings of the clock signal CK0.

Selection timing Any one of TSa to TSh is set as the first selection timing. The second selection timing is the selection timing next to the first selection timing. Hereinafter, the first selection timing will be referred to as TSa, and the second selection timing will be referred to as TSb. In the first selection timing TSa and the second selection timing TSb, the clock signals CK1 to CK16 are the first voltage level. Then, between the first selection timing TSa and the second selection timing TSb, the clock signals CK1 to CK16 transition from the first voltage level to the second voltage level, and transition from the second voltage level to the first voltage level. In FIG. 8, the first voltage level is set to the low level and the second voltage level is set to the high level.

When there is a clock signal having a high level at the selection timing, when the selector 12 selects the clock signal, two clock pulses may be generated in the reference clock signal CKREF during a period that should be one cycle. In the present embodiment, since the clock signals CK1 to CK16 are all low level at the selection timing, only one clock pulse can be generated in the reference clock signal CKREF during the period that should originally be one cycle.

The clock signal CK16 output by the last inverter IV16 of the delay line 11 is the most delayed with respect to the clock signal CK0. If the duty of the clock signal CK0 is large, the margin for the clock signal CK16 to become a high level at the selection timing or the clock signal CK16 to become a low level at the selection timing is insufficient. In the present embodiment, the duty conversion circuit 13 makes the high-width duty of the clock signal CK0 smaller than 50%, so that a margin for the clock signal CK16 to become a low level at the selection timing can be secured.

FIG. 9 is a second detailed configuration example of the spread spectrum circuit 10. In FIG. 9, the spread spectrum circuit 10 includes two delay lines. Specifically, the spread spectrum circuit 10 includes a first delay line 31, a second delay line 32, a selector 33, and a control circuit 34.

Each of the first delay line 31 and the second delay line 32 includes a plurality of delay elements. The first delay line 31 generates a first plurality of clock signals based on the input clock signal CKIN, and the second delay line 32 generates a second plurality of clock signals based on the input clock signal CKIN. When the first plurality of clock signals and the second plurality of clock signals are combined into a plurality of clock signals, the plurality of clock signals have different delay times from each other. The selector 33 selects one of the clock signals from the plurality of clock signals based on the control from the control circuit 34, and outputs the selected clock signal as the reference clock signal CKREF.

FIG. 10 is a detailed configuration example of the PLL circuit 20. The PLL circuit 20 includes a comparison circuit 21, a loop filter 22, an oscillation circuit 23, and a frequency dividing circuit 24. The PLL circuit 20 in FIG. 10 is an example, and the configuration of the PLL circuit 20 is not limited to this.

The frequency dividing circuit 24 divides the output clock signal CKQ and outputs the divided clock signal as the divided clock signal CKDIV. The comparison circuit 21 compares the phase of the reference clock signal CKREF with the phase of the frequency-divided clock signal CKDIV, and outputs the comparison result as a signal CPQ. The loop filter 22 performs loop filter processing on the signal CPQ and outputs the processed signal as a control value LPQ. The oscillation circuit 23 oscillates at an oscillation frequency controlled by the control value LPQ, and outputs a clock signal obtained by the oscillation as an output clock signal CKQ.

For example, the comparison circuit 21 is a charge pump circuit, the loop filter 22 is an analog filter composed of passive elements, the control value LPQ is a voltage, and the oscillation circuit 23 is a voltage control oscillation circuit. Alternatively, the PLL circuit 20 may be an ADPLL. ADPLL is an abbreviation for All Digital Phase Locked Loop. In this case, the comparison circuit 21 is a time digital conversion circuit, the loop filter 22 is a digital filter, the control value LPQ is digital data, and the oscillation circuit 23 is a digital control oscillation circuit.

3. 3. Electronic device, mobile FIG. 11 is a configuration example of an electronic device including the circuit device of the present embodiment. The electronic device 300 includes a processing device 310, a circuit device 320, a display driver 330, a display panel 340, a storage device 350, an operation device 360, and a communication device 370. The circuit device 320 corresponds to the circuit device 100 of FIG. 1 or FIG.

The processing device 310 transfers the image data stored in the storage device 350 or the image data received by the communication device 370 to the circuit device 320. In the example of FIG. 11, the circuit device 320 is a display controller. The circuit device 320 operates based on the spread spectrum output clock signal CKQ. The output clock signal CKQ is, for example, the master clock of the circuit device 320. The circuit device 320 performs image processing on the image data, display timing control, generation of image data to be transferred to the display driver, and the like. The display driver 330 drives the display panel 340 to display an image based on the image data transferred from the circuit device 320 and the display timing control by the circuit device 320. The display panel 340 is, for example, a liquid crystal display panel, an EL display panel, or the like. The storage device 350 is, for example, a memory, a hard disk drive, an optical disk drive, or the like. The operation device 360 is a device for a user to operate the electronic device 300, and is, for example, a button, a touch panel, a keyboard, or the like. The communication device 370 is, for example, a device that performs wired communication or a device that performs wireless communication. Wired communication is, for example, LAN, USB, or the like. The wireless communication is, for example, a wireless LAN, wireless proximity communication, or the like.

FIG. 12 is an example of a mobile body including the circuit device 320. The moving body includes a display device 400 and a control device 208. The control device 208 includes a circuit device 320 and a processing device 310 that transmits image data to the circuit device 320. The control device 208 is an ECU (Electronic Control Unit), and a circuit device 320 and a processing device 310 are incorporated in the ECU. The circuit device 320 may be incorporated in the display device 400. The circuit device 320 operates based on the spread spectrum output clock signal CKQ. The output clock signal CKQ is, for example, the master clock of the circuit device 320. The circuit device 320 of the present embodiment can be incorporated into various moving bodies such as a car, an airplane, a motorcycle, a bicycle, or a ship. The moving body is, for example, a device or device provided with a drive mechanism such as an engine or a motor, a steering mechanism such as a steering wheel or a rudder, and various electronic devices, and moves on the ground, in the sky, or on the sea. FIG. 12 schematically shows an automobile 206 as a specific example of the moving body. In the example of FIG. 12, the circuit device 320 is a display controller. The circuit device 320 performs image processing on the image data, display timing control, generation of image data to be transferred to the display driver, and the like. The display device 400 displays an image based on the image data transferred from the circuit device 320 and the display timing control by the circuit device 320.

In the above, the configurations of the electronic device and the mobile body have been described by taking the case where the circuit device 320 is a display controller as an example, but the application target of the circuit device 320 is not limited to the display controller. That is, the circuit device 320 may be various circuit devices that operate based on the spread spectrum clock signal.

The circuit device of the present embodiment described above includes a PLL circuit and a spread spectrum circuit. The PLL circuit generates an output clock signal having a frequency higher than that of the reference clock signal based on the reference clock signal. The spread spectrum circuit is provided in front of the PLL circuit, performs spread spectrum processing on the input clock signal, and outputs the clock signal obtained by the spread spectrum processing to the PLL circuit as a reference clock signal.

According to the present embodiment, by providing the spread spectrum circuit in front of the PLL circuit, it is possible to perform spread spectrum on an input clock signal having a frequency lower than that of the output clock signal. As a result, a high-frequency spread spectrum clock can be generated as compared with the case where the spread spectrum circuit is provided after the PLL circuit.

Further, in the present embodiment, the spread spectrum circuit may output a reference clock signal having a modulation period such that the modulation factor of the output clock signal is the same as the modulation factor of the reference clock signal.

The fact that the modulation factor of the output clock signal is the same as the modulation factor of the reference clock signal means that the PLL circuit can follow the spread spectrum reference clock signal. In the present embodiment, the spread spectrum circuit generates the reference clock signal of such a modulation period, so that the PLL circuit can output the spread spectrum output clock signal.

Further, in the present embodiment, the PLL circuit may multiply the reference clock signal by m. m is an integer of 2 or more. At this time, the spread spectrum circuit may output a reference clock signal having a modulation cycle such that m times of one clock modulation factor of the output clock signal is the same as one clock modulation factor of the reference clock signal.

The fact that m times the 1-clock modulation factor of the output clock signal is the same as the 1-clock modulation factor of the reference clock signal means that the PLL circuit can follow the spread-spectrum reference clock signal. In the present embodiment, the spread spectrum circuit generates the reference clock signal of such a modulation period, so that the PLL circuit can output the spread spectrum output clock signal.

Further, in the present embodiment, the spread spectrum circuit may output a reference clock signal in which the modulation width for one cycle of the reference clock signal is smaller than the allowable cycle-to-cycle jitter of the PLL circuit.

The permissible cycle-to-cycle jitter is the upper limit of the cycle-to-cycle jitter that the PLL circuit can follow. By making the modulation width for one cycle of the reference clock signal smaller than the allowable cycle-to-cycle jitter, the PLL circuit can follow the reference clock signal. That is, the condition is that the modulation factor of the output clock signal is the same as the modulation factor of the reference clock signal, or m times the modulation factor of one clock of the output clock signal is the same as the modulation factor of one clock of the reference clock signal. It is filled.

Further, in the present embodiment, the spread spectrum circuit may include n delay elements connected in series and a selector. n is an integer of 3 or more. To the selector, k clock signals are input from k delay elements out of n delay elements. k is an integer greater than or equal to 1 and less than n. The selector may output a reference clock signal based on a clock signal selected from k clock signals.

In this embodiment, n delay elements form a delay line. According to this embodiment, the number of wires connecting the delay line and the selector is reduced to k as compared with the configuration in which the clock signal is input to the selector from all the delay elements of the delay line, so that the circuit scale is reduced. it can.

Further, in the present embodiment, the k delay elements may be delay elements selected from n delay elements based on the difference sequence.

In spread spectrum, the period between the clock edges of a reference clock signal is the difference between the delay time of the edge at the beginning of the period and the delay time of the edge at the end of the period. That is, the difference sequence of the delay time is the period between the clock edges of the reference clock signal. In the present embodiment, the modulation pattern of spread spectrum is set by selecting k delay elements from the n delay elements based on the difference sequence.

Further, in the present embodiment, each delay element of the n delay elements may be an inverter circuit.

According to the present embodiment, the rising edge of the clock signal input to the delay line alternately becomes a rising edge and a falling edge at the output of each inverter. Therefore, even if there is a difference between the delay with respect to the rising edge and the delay with respect to the falling edge of the inverter, they are alternately affected and averaged. The same applies to the falling edge of the clock signal input to the delay line. As a result, the duty of the clock signal that has passed through the delay line is unlikely to collapse.

Further, in the present embodiment, the selector may have k input circuits into which k clock signals are input. Of the k input circuits, the input circuit in which the clock signal is input from the odd-numbered delay elements of the n delay elements may be an inverter. Of the k input circuits, the input circuit in which the clock signal is input from the even-numbered delay elements of the n delay elements may be a buffer.

When the delay element is an inverter, the logic of the clock signal output from the odd-numbered delay elements is inverted with respect to the input clock signal. In the present embodiment, since the input circuit in which the clock signal is input from the odd-th delay element is an inverter, the clock signal output by the input circuit has the same logic as the input clock signal. In this way, the input circuit of the selector can match the logic of the clock signal.

Further, in the present embodiment, the selector may select a reference clock signal from k clock signals at a selection timing corresponding to the edge timing of the input clock signal. Each clock signal of the k clock signals is the first voltage level at the first selection timing of the selector and the second selection timing following the first selection timing, and is between the first selection timing and the second selection timing. , The first voltage level may be changed to the second voltage level, and the second voltage level may be changed to the first voltage level.

If there is a clock signal with a high level at the selection timing among the k clock signals, when the selector selects the clock signal, two clock pulses are generated in the period that should be one cycle in the reference clock signal. there's a possibility that. In the present embodiment, since all k clock signals are at low level at the selection timing, only one clock pulse can be generated in the reference clock signal during the period that should originally be one cycle.

Further, in the present embodiment, the circuit device may include a duty conversion circuit. The duty conversion circuit may input a second input clock signal and convert the second input clock signal into an input clock signal having a high-width duty of less than 50%. The spread spectrum circuit may perform spread spectrum processing on the input clock signal from the duty conversion circuit.

According to the present embodiment, the duty conversion circuit makes the high-width duty of the clock signal smaller than 50%, so that a margin for the n clock signals generated by the delay line to become low level at the selection timing can be secured. ..

Further, the electronic device of the present embodiment includes the circuit device according to any one of the above.

Further, the mobile body of the present embodiment includes the circuit device according to any one of the above.

Although the present embodiment has been described in detail as described above, those skilled in the art will easily understand that many modifications that do not substantially deviate from the new matters and effects of the present disclosure are possible. Therefore, all such variations are included in the scope of the present disclosure. For example, a term described at least once in a specification or drawing with a different term in a broader or synonymous manner may be replaced by the different term anywhere in the specification or drawing. All combinations of the present embodiment and modifications are also included in the scope of the present disclosure. Further, the configuration and operation of the circuit device, the electronic device, the mobile body, and the like are not limited to those described in the present embodiment, and various modifications can be performed.

10 ... Spectrum diffusion circuit, 11 ... Delay line, 12 ... Selector, 13 ... Duty conversion circuit, 14 ... Control circuit, 15 ... Delay adjustment circuit, 20 ... PLL circuit, 21 ... Comparison circuit, 22 ... Loop filter, 23 ... Oscillation Circuit, 24 ... frequency division circuit, 31 ... first delay line, 32 ... second delay line, 33 ... selector, 34 ... control circuit, 100 ... circuit device, 206 ... automobile, 208 ... control device, 300 ... electronic device, 310 ... Processing device, 320 ... Circuit device, 330 ... Display driver, 340 ... Display panel, 350 ... Storage device, 360 ... Operation device, 370 ... Communication device, 400 ... Display device, BFS0, BFS6, BFS10, BFS16 ... Input circuit , CKIN ... Input clock signal, CKIN'... Second input clock signal, CKQ ... Output clock signal, CKREF ... Reference clock signal, IV1 to IV16 ... Inverter, IVS1, IVS3, IVS13, IVS15 ... Input circuit, MDW1 ... 1 cycle Modulation width, TMD ... Modulation cycle, TSa to TSi ... Selection timing, Tdry ... Delay time

Claims (12)

A PLL circuit that generates an output clock signal having a frequency higher than that of the reference clock signal based on the reference clock signal.
A spread spectrum circuit provided in front of the PLL circuit, which performs spread spectrum processing on an input clock signal and outputs the clock signal obtained by the spread spectrum processing to the PLL circuit as the reference clock signal.
A circuit device characterized by including. In the circuit device according to claim 1,
The spread spectrum circuit
A circuit device for outputting the reference clock signal having a modulation period such that the modulation factor of the output clock signal is the same as the modulation factor of the reference clock signal. In the circuit device according to claim 1,
When the PLL circuit multiplies the reference clock signal by m (m is an integer of 2 or more).
The spread spectrum circuit
A circuit device for outputting the reference clock signal having a modulation period such that m times of one clock modulation factor of the output clock signal is the same as one clock modulation factor of the reference clock signal. In the circuit device according to any one of claims 1 to 3.
The spread spectrum circuit
A circuit device characterized by outputting the reference clock signal in which the modulation width for one cycle of the reference clock signal is smaller than the allowable cycle-to-cycle jitter of the PLL circuit. In the circuit device according to any one of claims 1 to 4.
The spread spectrum circuit
N delay elements (n is an integer of 3 or more) connected in series,
K clock signals are input from k delay elements (k is an integer greater than or equal to 1 and smaller than n) among the n delay elements, and the reference is based on a clock signal selected from the k clock signals. A selector that outputs a clock signal and
A circuit device characterized by including. In the circuit device according to claim 5,
A circuit device characterized in that the k delay elements are delay elements selected from the n delay elements based on a difference sequence. In the circuit device according to claim 5 or 6.
Each delay element of the n delay elements
A circuit device characterized by being an inverter circuit. In the circuit device according to claim 7.
The selector is
It has k input circuits into which the k clock signals are input.
Of the k input circuits, the input circuit in which the clock signal is input from the odd-numbered delay elements of the n delay elements is an inverter.
A circuit device characterized in that, of the k input circuits, an input circuit in which a clock signal is input from an even number of delay elements of the n delay elements is a buffer. In the circuit device according to any one of claims 5 to 8.
The selector is
The reference clock signal is selected from the k clock signals at the selection timing corresponding to the edge timing of the input clock signal.
Each clock signal of the k clock signals is
It is the first voltage level at the first selection timing of the selector and the second selection timing following the first selection timing, and from the first voltage level between the first selection timing and the second selection timing. A circuit device characterized by transitioning to a second voltage level and transitioning from the second voltage level to the first voltage level. In the circuit device according to any one of claims 1 to 9.
A duty conversion circuit in which a second input clock signal is input and the second input clock signal is converted into the input clock signal having a high width duty of less than 50% is included.
The spread spectrum circuit
A circuit device characterized in that the spread spectrum processing is performed on the input clock signal from the duty conversion circuit. An electronic device comprising the circuit device according to any one of claims 1 to 10. A mobile body including the circuit device according to any one of claims 1 to 10.

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