JP2021086277A - Electronic control device - Google Patents

Abstract

To manage a synchronization even outside an operating system operating section.SOLUTION: An ECU 1 includes CPU cores 11 to 13. The first CPU core 11 is a master core, and the second CPU core 12 and the third CPU core 13 are each a slave core. The first CPU core 11 executes necessary processes for operating an application on the second CPU core 12 and on the third CPU core 13. The first CPU core 11 changes, for each of the CPU cores 11 to 13, whether or not to execute a barrier synchronization in both inside and outside an OS operating section where an OS is operating using involved core identification data 24 managed by the first CPU core 11.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to an electronic control device including a plurality of CPU cores.

There is known an electronic control device mounted on a vehicle and equipped with a microcomputer having a plurality of CPU cores. A plurality of CPU cores can operate independently of each other, and tasks, threads, or processes assigned to the respective CPU cores can be executed in parallel. This makes it possible to improve the processing performance. However, if the processing order between a plurality of CPU cores is not guaranteed, there is a concern that the system may break down or the power consumption may increase according to the number of CPU cores.

As a method of guaranteeing the processing order between CPU cores in a microcomputer having a plurality of CPU cores, a barrier synchronization mechanism for waiting for processing between CPU cores is known.
Further, as a method of reducing power consumption, a mode control mechanism for switching a control mode (for example, a normal control mode and a power saving control mode) according to a system usage status or the like is known. A microcomputer having a plurality of CPU cores can generally put each CPU core into a sleep state individually, and reduces the overall power consumption by putting the CPU core into a sleep state in the power saving control mode. To do.

In a microcomputer having a plurality of CPU cores, when the barrier synchronization mechanism and the mode control mechanism are used in combination, the operation of the microcomputer may be hindered. Specifically, it was intended that the progress of processing is hindered by the CPU core that is the synchronization partner in the sleep state during the power saving control mode, or that the synchronization required when returning to the normal control mode is not executed. The processing order cannot be guaranteed.

Patent Document 1 is mentioned as a technique for solving such a problem. In Patent Document 1, some CPU cores are put to sleep during the power saving control mode, the task arrangement status on the CPU core is changed, and the task operation information is assigned to the CPU core according to the arrangement status and the task operation information. It is described to switch whether to perform synchronization within the task being performed.

JP-A-2018-106472

There are known ways to operate a microcomputer intermittently to meet stricter power consumption requirements. In this method, all CPU cores are put to sleep when the system is not used, and then only a specific CPU core is woken up and put to sleep again when necessary processing is completed.

In addition, there are generally a plurality of types of sleep of the CPU core, and many microcomputers provide a deep sleep that reduces the sleep to a state where almost no power is supplied. When waking up from a deep sleep, initialization processing for each CPU core including boot processing of the operating system is required. When transitioning to deep sleep, termination processing for each CPU core, including termination processing of the operating system, is required. In other words, every time the microcomputer wakes up using deep sleep, the process is executed outside the operating system operating section.

Therefore, during the execution of the process outside the operating system operating section, the progress of the process may be hindered by the CPU core as the synchronization partner being in the sleep state.
The present disclosure is intended to manage synchronization even outside the operating system operating section.

One aspect of the present disclosure is an electronic control device (1) including a plurality of CPU cores (11, 12, 13), and the master core (11) includes a synchronization switching unit (S10 to S90, S210 to S290). .. The master core is one CPU core out of a plurality of CPU cores. The slave cores (12, 13) are CPU cores other than the master core among the plurality of CPU cores.

The master core executes the processing necessary to run the application on the slave core.
The synchronization switching unit uses the synchronization management information (24) managed by the master core, both inside and outside the OS operating section, with the section in which the operating system is operating as the OS operating section, and uses each of the plurality of CPU cores. Is configured to switch whether or not to perform synchronization.

The electronic control device of the present disclosure configured in this way switches whether or not to execute synchronization for each of a plurality of CPU cores not only within the OS operating section but also outside the OS operating section. Therefore, the electronic control device of the present disclosure can manage the synchronization of each of the plurality of CPU cores even outside the OS operating section. As a result, in the electronic control device of the present disclosure, the progress of the initialization process is hindered by the slave core as the synchronization partner being in the sleep state during the initialization process executed when the master core wakes up from the deep sleep. It is possible to suppress the occurrence of such a situation. Similarly, in the electronic control device of the present disclosure, the progress of the termination process is hindered by the slave core as the synchronization partner being in the sleep state during the termination process executed when the master core transitions to the deep sleep. It is possible to suppress the occurrence of a situation.

It is a block diagram which shows the structure of an ECU. It is a figure which shows the specific example of the synchronization place identification data, the synchronization timing identification data, the normal participation core data, and the participation core identification data. It is a timing chart which shows the specific example of the operation of the 1st, 2nd, and 3rd CPU cores. It is a flowchart which shows the 1st synchronization setting process. It is a flowchart which shows the 2nd synchronization setting process. It is a flowchart which shows the synchronization process.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.
The electronic control device 1 (hereinafter, ECU 1) of the present embodiment is mounted on a vehicle and includes a microcomputer 2 (hereinafter, microcomputer 2), an input circuit 3, and an output circuit 4, as shown in FIG. ECU is an abbreviation for Electronic Control Unit.

The microcomputer 2 detects, for example, the state of the engine based on various signals input via the input circuit 3. Then, the microcomputer 2 outputs a control signal for controlling the engine via the output circuit 4 based on the state of the engine.

The microcomputer 2 includes a first CPU core 11, a second CPU core 12, a third CPU core 13, a ROM 14, a RAM 15, an input / output unit 16, and a bus 17. Hereinafter, the first CPU core 11, the second CPU core 12, and the third CPU core 13 are collectively referred to as CPU cores 11 to 13.

Various functions of the microcomputer are realized by the CPU cores 11 to 13 executing a program stored in a non-transitional substantive recording medium. In this example, ROM 14 corresponds to a non-transitional substantive recording medium in which a program is stored. In addition, by executing this program, the method corresponding to the program is executed. In addition, a part or all of the functions executed by the CPU cores 11 to 13 may be configured in hardware by one or a plurality of ICs or the like. Further, the number of microcomputers constituting the ECU 1 may be one or a plurality.

The first CPU core 11, the second CPU core 12, and the third CPU core 13 distribute and execute various control processes for controlling the engine mounted on the vehicle.
The ROM 14 is a non-volatile memory and stores a control program for executing various control processes for controlling the engine.

The RAM 15 is a volatile memory and temporarily stores the calculation results of the CPU cores 11 to 13.
The input / output unit 16 is a circuit for inputting / outputting data between the outside of the microcomputer 2 and the CPU cores 11 to 13.

The bus 17 connects the CPU cores 11 to 13, the ROM 14, the RAM 15, and the input / output unit 16 to each other so that data can be input and output.
The ECU 1 includes a barrier synchronization mechanism that waits for processing between CPU cores 11 to 13 in order to guarantee the processing order between CPU cores 11 to 13. The barrier synchronization mechanism sets in advance the locations where the CPU cores 11 to 13 perform synchronization (hereinafter, synchronization locations) and the CPU cores 11 to 13 (hereinafter, participating cores) to be synchronized at the synchronization locations. The processes between the CPU cores 11 to 13 can be synchronized at any synchronization point.

The ECU 1 includes a mode control mechanism for switching the control mode between the normal control mode and the power saving control mode depending on the situation in order to reduce the power consumption. When the control mode becomes the power saving control mode, the ECU 1 periodically performs an intermittent operation in which all the CPU cores 11 to 13 are put to sleep, and then only the CPU core 11 is woken up to execute necessary processing and then put to sleep again. To run.

The sleep executed by the CPU cores 11 to 13 is a sleep (hereinafter referred to as a deep sleep) that drops the power to a state in which almost no power is supplied. When the CPU cores 11 to 13 wake up from a deep sleep, initialization processing (hereinafter, startup processing) for each CPU core 11 to 13 including the startup processing of the operating system (hereinafter, OS) is required. Further, when the CPU cores 11 to 13 transition to a deep sleep, termination processing (hereinafter, shutdown processing) for each CPU core 11 to 13 including OS termination processing is required.

The first CPU core 11 is a master core that is started first among the CPU cores 11 to 13 after the power is turned on to the ECU 1. The second CPU core 12 and the third CPU core 13 are slave cores activated by the first CPU core 11, which is a master core.

The first CPU core 11, which is the master core, executes the processing necessary for operating the application on the slave cores (that is, the second CPU core 12 and the third CPU core 13). Specifically, the first CPU core 11 executes slave core activation, barrier synchronization setting, control mode management, and activation or invalidation of hardware resources possessed by the ECU 1.

The second CPU core 12 and the third CPU core 13, which are slave cores, execute application processing assigned to the second CPU core 12 and the third CPU core 13, respectively. The application process is an arithmetic process and a control process using hardware resources, and examples thereof include a process of acquiring external world information and a process of controlling an actuator.

The RAM 15 stores the synchronization location identification data 21, the synchronization timing identification data 22, the normal participation core data 23, the participation core identification data 24, the barrier synchronization entry data 25, the control mode identification data 26, and the operating core identification data 27.

The synchronization location identification data 21 is information in which each of the CPU cores 11 to 13 identifies a synchronization location of barrier synchronization.
The synchronization timing identification data 22 is information for identifying a processing section in which each synchronization is executed. The processing section is any of a startup processing section, an OS operating section, and a shutdown processing section.

The normal time participation core data 23 is information for identifying CPU cores that participate in synchronization in the normal control mode.
The participating core identification data 24 is information for identifying CPU cores participating in synchronization at each synchronization location.

The barrier synchronization entry data 25 is information for identifying CPU cores 11 to 13 that have reached the synchronization location at each synchronization location.
The control mode identification data 26 is information for identifying the control mode executed in the ECU 1. The first CPU core 11, which is the master core, determines the current control mode, and appropriately rewrites the contents of the control mode identification data 26 based on the determination result.

The operating core identification data 27 is information for identifying the operating CPU cores 11 to 13.
Next, specific examples of the synchronization location identification data 21, the synchronization timing identification data 22, the normal participation core data 23, and the participation core identification data 24 will be shown.

As shown in FIG. 2, the synchronization location identification data 21 stores, for example, 1, 2, 3, 4, 5 synchronization identification numbers for each of the five synchronization locations.
The synchronization timing identification data 22 stores information indicating a processing section for each of the five synchronization points. For example, a startup processing section is set for the synchronization location where the synchronization identification numbers 1 and 2. Similarly, the OS operating section is set for the synchronization location where the synchronization identification number is 3, and the shutdown processing section is set for the synchronization location where the synchronization identification numbers are 4 and 5.

The normal participation core data 23 stores information indicating whether or not the CPU cores 11 to 13 participate in each of the five synchronization points. For example, the first CPU core 11 and the second CPU core 12 are set to "participate" and the third CPU core 13 is set to "non-participate" with respect to the synchronization points having the synchronization identification numbers 1 and 5. The first CPU core 11 and the third CPU core 13 are set to "participate" and the second CPU core 12 is set to "non-participate" with respect to the synchronization points having the synchronization identification numbers 2 and 4. The second CPU core 12 and the third CPU core 13 are set to "participate" and the first CPU core 11 is set to "non-participate" with respect to the synchronization location where the synchronization identification number is 3.

The information stored in the synchronization location identification data 21, the synchronization timing identification data 22, and the normal participation core data 23 is a preset fixed value and is stored in the ROM 14. After the power is turned on to the ECU 1, the first CPU core 11 reads the above fixed value from the ROM 14 and stores it in the synchronization location identification data 21, the synchronization timing identification data 22, and the normal participation core data 23 provided in the RAM 15. To do.

The participating core identification data 24 stores information indicating whether or not the CPU cores 11 to 13 participate in each of the six synchronization points. The participating core identification data 24 is appropriately rewritten by the first synchronization setting process and the second synchronization setting process described later.

Next, a specific example of the operation of the CPU cores 11 to 13 will be described.
As shown in FIG. 3, it is assumed that the control mode is switched to the normal control mode at time t1. As a result, as shown in the sections PI1 and PI21, the CPU cores 11 to 13 shift to the startup processing section and execute the startup processing.

When the startup processing section ends at time t2, the CPU cores 11 to 13 shift to the OS operating section as shown in the sections PI2 and PI22.

After that, when the first CPU core 11 determines that the processing in the normal control mode is unnecessary, the first CPU core 11 notifies the second CPU core 12 and the third CPU core 13 to that effect, and the OS operating section is set at time t3. Is finished. As a result, as shown in the sections PI3 and PI23, the CPU cores 11 to 13 shift to the shutdown processing section and execute the shutdown processing.
When the shutdown process is completed, the control mode is switched from the normal control mode to the power saving control mode at time t4. That is, the CPU cores 11 to 13 transition to a deep sleep as shown in the sections PI4 and PI24.

In the power saving control mode, the first CPU core 11 executes the above-mentioned intermittent operation. Specifically, as shown in the section PI5, the first CPU core 11 shifts to the startup processing section at time t5 and executes the startup processing. As shown in the section PI6, the first CPU core 11 shifts to the OS operating section at time t6. As shown in the section PI7, the first CPU core 11 shifts to the shutdown processing section at time t7 and executes the shutdown processing. As shown in the section PI8, the first CPU core 11 transitions to a deep sleep at time t8. As shown in the section PI9, the first CPU core 11 shifts to the startup processing section at time t9 and executes the startup processing.

When a return event occurs in this startup processing section as shown by the pulse signal PS, the control mode is switched from the power saving control mode to the normal control mode at time t10. As a result, as shown in the section PI25, the second CPU core 12 and the third CPU core 13 shift to the startup processing section and execute the startup processing.

Then, when the startup processing section ends at time t11, the first CPU core 11 shifts to the OS operating section as shown by the section PI10. Further, when the startup processing section ends at time t12, the second CPU core 12 and the third CPU core 13 shift to the OS operating section as shown by the section PI26.

After that, when the first CPU core 11 determines that the processing in the normal control mode is unnecessary, the first CPU core 11 notifies the second CPU core 12 and the third CPU core 13, and the OS operating section is set at time t13. Is finished. As a result, as shown in the sections PI11 and PI27, the CPU cores 11 to 13 shift to the shutdown processing section and execute the shutdown processing. When the shutdown process is completed, the control mode is switched from the normal control mode to the power saving control mode at time t14.

The participating core identification data 24 stores the normal participating core data 23 in the section PI31 at time t1 to time t4. Participating core identification data 24 is not referenced in the interval PI32 from time t4 to time t5. This is because the CPU cores 11 to 13 are in deep sleep. The participating core identification data 24 stores the power-saving participation core data, which will be described later, in the section PI33 at time t5 to time t8.

Participating core identification data 24 is not referenced in the interval PI34 from time t8 to time t9. This is because the CPU cores 11 to 13 are in deep sleep. The participating core identification data 24 stores the participating core data at the time of power saving in the section PI35 from the time t9 to the time t10. The participating core identification data 24 stores the participating core data at the time of return, which will be described later, in the section PI36 at time t10 to time t14.

The first CPU core 11 executes synchronization in the section PI41 at time t1 to time t4. The first CPU core 11 does not execute synchronization in the section PI42 from time t4 to time t13. The first CPU core 11 executes synchronization in the section PI43 from time t13 to time t14.

The second and third CPU cores 12 and 13 execute synchronization in the section PI51 at time t1 to time t4. The second and third CPU cores 12 and 13 do not execute synchronization in the section PI52 from time t4 to time t10. The second and third CPU cores 12 and 13 execute synchronization in the section PI53 at time t10 to time t14.

Next, the procedure of the first synchronization setting process executed by the first CPU core 11 will be described. The first synchronization setting process is a process executed at the timing when the start-up process is started under the normal control mode or at the timing when the start-up process is started under the power saving control mode.

When the first synchronization setting process is executed, the first CPU core 11 first acquires the control mode identification data 26 in S10 as shown in FIG.
The first CPU core 11 determines in S20 whether or not the current control mode is the normal control mode based on the control mode identification data 26 acquired in S10. Here, when the current control mode is the normal control mode, the first CPU core 11 sets the same information stored in the normal participation core data 23 for each of the plurality of synchronization identification numbers in S30. It is stored in the participating core identification data 24 corresponding to the synchronization identification number, and the first synchronization setting process is completed. For example, in the normal participation core data 23 corresponding to the synchronization identification number 2, the first CPU core 11 and the third CPU core 13 are set to "participation", and the second CPU core 12 is set to "non-participation". Therefore, in the participating core identification data 24 corresponding to the synchronization identification number 2, the first CPU core 11 and the third CPU core 13 are set to "participate", and the second CPU core 12 is set to "non-participate".

On the other hand, when the current control mode is not the normal control mode, the first CPU core 11 stores 0 in the synchronization identification number indicated value i provided in the RAM 15 in S40.
Then, in S50, the first CPU core 11 stores the added value obtained by adding 1 to the value stored in the synchronous identification number indicated value i in the synchronous identification number indicated value i.

In S60, the first CPU core 11 acquires the normal participation core data 23 of the synchronization identification number corresponding to the synchronization identification number indicated value i.
In S70, the first CPU core 11 generates power saving participation core data corresponding to the synchronization identification number indicated value i. Specifically, the first CPU core 11 participates in the information in which the first CPU core 11, the second CPU core 12, and the third CPU core 13 are set to "non-participate" at the time of power saving corresponding to the synchronization identification number indicated value i. Generate as core data.

Next, the first CPU core 11 determines in S80 whether or not the value stored in the synchronous identification number indicated value i is equal to or greater than the preset identification number maximum value k. Here, when the value stored in the synchronous identification number indicated value i is less than the maximum identification number k, the first CPU core 11 shifts to S50.

On the other hand, when the value stored in the synchronization identification number indicated value i is equal to or greater than the maximum identification number value k, the first CPU core 11 participates in S90 for each of the plurality of synchronization identification numbers during power saving. The core data is stored in the participating core identification data 24 corresponding to the same synchronization identification number, and the first synchronization setting process is completed. As a result, in the participating core identification data 24 corresponding to the synchronous identification number indicated value i, the first CPU core 11, the second CPU core 12, and the third CPU core 13 are set to “non-participating”. i is an integer from 1 to k.

Next, the procedure of the second synchronization setting process executed by the first CPU core 11 will be described. The second synchronization setting process is a process executed at the timing when an event (that is, a return event) that triggers the return to the normal control mode occurs under the power saving control mode.

When the second synchronization setting process is executed, the first CPU core 11 first determines in S210 whether the first CPU core 11 is in the shutdown process or in the deep sleep, as shown in FIG. Here, when the first CPU core 11 is in the shutdown process and in the deep sleep, the first CPU core 11 ends the second synchronization setting process.

On the other hand, when the first CPU core 11 is not in the shutdown process or in the deep sleep, the first CPU core 11 stores 0 in the synchronization identification number indicated value i in S220.
Then, in S230, the first CPU core 11 stores the added value obtained by adding 1 to the value stored in the synchronous identification number indicated value i in the synchronous identification number indicated value i.

In S240, the first CPU core 11 acquires the normal participation core data 23 and the synchronization timing identification data 22 of the synchronization identification number corresponding to the synchronization identification number indicated value i.
The first CPU core 11 determines in S250 whether or not the processing section indicated by the synchronization timing identification data 22 acquired in S240 is a startup processing section or an OS operating section.

Here, when the processing section is the startup processing section or the OS operating section, the first CPU core 11 generates the participating core data at the time of return in which the master core is changed to "non-participating" in S260, and shifts to S280. .. Specifically, the first CPU core 11 is set to "non-participation" in the normal participation core data 23 acquired in S240 (that is, the normal participation core data 23 of the synchronization identification number corresponding to the synchronization identification number indicated value i). The information is generated as the participation core data at the time of restoration of the synchronization identification number corresponding to the synchronization identification number indicated value i.

On the other hand, when the processing section is not the startup processing section and the OS operating section, the first CPU core 11 uses S270 to identify the normal participation core data 23 acquired in S240 by synchronization identification corresponding to the synchronization identification number indicated value i. It is generated as participating core data when the number is restored, and is transferred to S280.

Upon shifting to S280, the first CPU core 11 determines whether or not the value stored in the synchronization identification number indicated value i is equal to or greater than the maximum identification number value k. Here, when the value stored in the synchronous identification number indicated value i is less than the maximum identification number k, the first CPU core 11 shifts to S230.

On the other hand, when the value stored in the synchronization identification number indicated value i is equal to or greater than the maximum identification number value k, the first CPU core 11 participates in S290 for each of the plurality of synchronization identification numbers at the time of return. The data is stored in the participating core identification data 24 corresponding to the same synchronization identification number, and the second synchronization setting process is completed.

Next, the procedure of the synchronous processing executed by the CPU cores 11 to 13 will be described. The synchronization process is a process executed when each of the CPU cores 11 to 13 reaches the synchronization point.
Hereinafter, it will be described that the second CPU core 12 is executing the synchronization process on behalf of the CPU cores 11 to 13.

When the synchronization process is executed, as shown in FIG. 6, the second CPU core 12 first identifies the participating cores at the synchronization point (hereinafter referred to as the cause synchronization point) that caused the start of the synchronization process in S410. Acquire data 24.

The second CPU core 12 determines in S420 whether or not the second CPU core 12 participates in the synchronization at the cause synchronization location based on the participation core identification data 24 acquired in S410. Specifically, the second CPU core 12 determines that the second CPU core 12 participates in the synchronization when the second CPU core 12 is set to "participate" in the acquired participating core identification data 24. Further, the second CPU core 12 determines that the second CPU core 12 does not participate in the synchronization when the second CPU core 12 is set to "non-participate" in the acquired participating core identification data 24.

Here, if it does not participate in the synchronization, the second CPU core 12 ends the synchronization process. On the other hand, when participating in synchronization, in S430, the second CPU core 12 sets the barrier synchronization entry data 25 corresponding to the cause synchronization location with an arrival value indicating that the second CPU core 12 has reached the cause synchronization location. By writing, the barrier synchronization entry data 25 is updated.

The second CPU core 12 determines in S440 whether or not barrier synchronization has been established. Specifically, the second CPU core 12 is the CPU cores 11 to 13 (hereinafter, synchronous participation) set to "participate" in the acquired participating core identification data 24 in the barrier synchronization entry data 25 corresponding to the cause synchronization location. Judge whether the reached value of core) is written.

Therefore, the second CPU core 12 determines that the barrier synchronization has been established when the reached values of all the synchronization participating cores are written in the barrier synchronization entry data 25 corresponding to the cause synchronization location. On the other hand, the second CPU core 12 determines that the barrier synchronization has not been established when at least one reached value of the synchronization participating cores is not written in the barrier synchronization entry data 25 corresponding to the cause synchronization location.

Here, when the barrier synchronization is not established, the second CPU core 12 waits until the barrier synchronization is established by repeating the process of S440. On the other hand, when barrier synchronization is established, the second CPU core 12 ends the synchronization process.

The ECU 1 configured in this way includes CPU cores 11 to 13. The first CPU core 11 is a master core, and the second CPU core 12 and the third CPU core 13 are slave cores.

The first CPU core 11 executes processing necessary for operating an application on the second CPU core 12 and the third CPU core 13.
Whether or not the first CPU core 11 executes barrier synchronization for each of the CPU cores 11 to 13 by using the participating core identification data 24 managed by the first CPU core 11 both inside and outside the OS operating section. Switch.

In this way, the ECU 1 switches whether or not to execute barrier synchronization for each of the CPU cores 11 to 13 not only within the OS operating section but also outside the OS operating section. Therefore, the ECU 1 can manage the barrier synchronization of the CPU cores 11 to 13 even outside the OS operating section. As a result, the ECU 1 advances the startup process by causing the second CPU core 12 and the third CPU core 13, which are barrier synchronization partners, to be in the sleep state during the startup process executed when the first CPU core 11 wakes up from the deep sleep. It is possible to suppress the occurrence of a situation in which Similarly, in the ECU 1, the shutdown process proceeds because the second CPU core 12 and the third CPU core 13, which are barrier synchronization partners, are in the sleep state during the shutdown process executed when the first CPU core 11 transitions to the deep sleep. It is possible to suppress the occurrence of a situation in which

Further, the first CPU core 11 switches whether or not to execute barrier synchronization for each of the CPU cores 11 to 13 by updating the participating core identification data 24. As a result, the CPU cores 11 to 13 determine whether or not to execute the barrier synchronization by the procedure common to all the CPU cores 11 to 13 that the participating core identification data 24 is referred to when the barrier synchronization is executed. be able to.

Further, the ECU 1 puts the normal control mode for continuously operating the OS and all the CPU cores 11 to 13 to sleep, and then wakes up only the first CPU core 11 to execute necessary processing and then puts it to sleep again. It is configured to switch the control mode between the power saving control mode that periodically executes intermittent operation. The first CPU core 11 is configured to execute a startup process when waking up from sleep and a shutdown process when transitioning to sleep. Then, the first CPU core 11 updates the participating core identification data 24 when the first CPU core 11 executes the startup process and when the first CPU core 11 returns from the power saving control mode to the normal control mode. In this way, the ECU 1 sets the update timing at the time of executing the start-up process and the time of returning from the power saving control mode to the normal control mode, so that the ECU 1 can immediately switch between the control mode and the control mode. The participating core identification data 24 can be updated.

The first CPU core 11 updates the participating core identification data 24 based on the control mode when the first CPU core 11 executes the startup process. As a result, the ECU 1 updates the participating core identification data 24 according to the control mode immediately after the first CPU core 11 wakes up from the deep sleep, so that the operation of the ECU 1 can be guaranteed even if the control mode is updated. Become.

When returning from the power saving control mode to the normal control mode, the first CPU core 11 updates the participating core identification data 24 based on the processing executed by the first CPU core 11. As a result, when returning from the power saving control mode to the normal control mode, the ECU 1 can execute barrier synchronization at a necessary synchronization point in order to maintain the consistency of processing. Therefore, the ECU 1 can execute the process for returning to the normal control mode without resetting the ECU 1, and can secure high responsiveness regarding the return to the normal control mode.

In the embodiment described above, the first CPU core 11 corresponds to the master core, the second CPU core 12 and the third CPU core 13 correspond to the slave core, the participating core identification data 24 corresponds to the synchronization management information, and S10 to S90, S210 to S290 correspond to the processing as the synchronization switching unit.

In addition, the startup process corresponds to the initialization process, and the shutdown process corresponds to the termination process.
Although one embodiment of the present disclosure has been described above, the present disclosure is not limited to the above embodiment, and can be implemented in various modifications.

[Modification 1]
For example, in the above embodiment, the mode of switching the synchronous participation cores participating in the barrier synchronization is shown, but the present invention is not limited to the barrier synchronization, and the synchronous participation cores participating in the synchronization other than the barrier synchronization may be switched. Good.
[Modification 2]
In the above embodiment, the microcomputer 2 has three CPU cores, but the microcomputer 2 may have two CPU cores or four or more CPU cores.

The ECU 1 and its method described in the present disclosure are realized by a dedicated computer provided by configuring a processor and memory programmed to perform one or more functions embodied by a computer program. You may. Alternatively, the ECU 1 and its method described in the present disclosure may be realized by a dedicated computer provided by configuring the processor with one or more dedicated hardware logic circuits. Alternatively, the ECU 1 and its method described in the present disclosure are configured by a combination of a processor and memory programmed to perform one or more functions and a processor composed of one or more hardware logic circuits. It may be realized by one or more dedicated computers. The computer program may also be stored on a computer-readable non-transitional tangible recording medium as an instruction executed by the computer. The method for realizing the functions of each part included in the ECU 1 does not necessarily include software, and all the functions may be realized by using one or a plurality of hardware.

A plurality of functions possessed by one component in the above embodiment may be realized by a plurality of components, or one function possessed by one component may be realized by a plurality of components. Further, a plurality of functions possessed by the plurality of components may be realized by one component, or one function realized by the plurality of components may be realized by one component. Further, a part of the configuration of the above embodiment may be omitted. In addition, at least a part of the configuration of the above embodiment may be added or replaced with the configuration of the other above embodiment.

In addition to the above-mentioned ECU 1, various systems such as a system having the ECU 1 as a component, a program for operating a computer as the ECU 1, a non-transitional substantive recording medium such as a semiconductor memory in which this program is recorded, and a device control method are used. The present disclosure can also be realized in the form.

1 ... ECU, 11 ... 1st CPU core, 12 ... 2nd CPU core, 13 ... 3rd CPU core, 24 ... Participating core identification data

Claims (5)

An electronic control device (1) having a plurality of CPU cores (11, 12, 13).
Of the plurality of CPU cores, one CPU core is designated as a master core (11), and the CPU cores other than the master core are designated as slave cores (12, 13).
The master core executes the processing necessary for operating the application on the slave core, and performs the processing necessary for operating the application.
The master core uses a section in which the operating system is operated as an OS operating section, and uses synchronous management information (24) managed by the master core both inside and outside the OS operating section to use a plurality of the CPU cores. An electronic control device including a synchronization switching unit (S10 to S90, S210 to S290) configured to switch whether or not to execute synchronization for each of the above. The electronic control device according to claim 1.
The synchronization switching unit is an electronic control device that switches whether or not to execute the synchronization for each of the plurality of CPU cores by updating the synchronization management information. The electronic control device according to claim 2.
The electronic control device has a normal control mode in which the operating system is continuously operated, and an intermittent operation in which all the CPU cores are put to sleep, and then only the master core is awakened to perform necessary processing and then put to sleep again. It is configured to switch the control mode between the power saving control mode that executes the operation periodically.
The master core is configured to execute an initialization process when waking up from sleep, and execute an end process when transitioning to the sleep.
The synchronization switching unit is an electronic control device that updates the synchronization management information when the master core executes the initialization process and when the master core returns from the power saving control mode to the normal control mode. The electronic control device according to claim 3.
The synchronization switching unit is an electronic control device that updates the synchronization management information based on the control mode when the master core executes the initialization process. The electronic control device according to claim 3.
The synchronization switching unit is an electronic control device that updates the synchronization management information based on the processing executed by the master core when returning from the power saving control mode to the normal control mode.

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