JP2021083309A - Light-emitting element driving device - Google Patents

Abstract

To provide a light-emitting element driving device that can in advance prevent the wrong operation based on the abnormality of an external setting component.SOLUTION: A light-emitting element driving device for driving a light-emitting element includes a diagnosis unit that diagnoses whether abnormality exists in an externally connected setting component when the light-emitting element driving device is activated, and a control unit that cancels the activation of the light-emitting element driving device if the diagnosis unit has diagnosed that the abnormality exists. The diagnosis unit diagnoses whether there is an abnormality that the setting component that is a resistor is disconnected. The light-emitting element driving device further includes an external terminal connected to one end of the resistor. The diagnosis unit includes a constant-current circuit that feeds constant current to the resistor through the external terminal, a comparator to which the voltage generated in the external terminal is input, and a transistor that switches between the connection and disconnection of a route where the constant current flows. The resistor is disposed in a route different from the current route where the current flows to the light-emitting element.SELECTED DRAWING: Figure 1

Description

The present invention relates to a light emitting element driving device.

Conventionally, various power supply drivers including an LED driver for driving an LED (light emitting diode) are generally configured as a semiconductor device of one chip. In such a semiconductor device, a large number of setting resistors and setting capacitors are often provided externally.

For example, when the semiconductor device is a power supply driver, a voltage dividing resistor that divides the output voltage for feedback control that feeds back the output voltage or a voltage dividing resistor that divides the output voltage for overvoltage detection is provided externally. May be Such a voltage dividing resistor functions as a setting resistor for setting a target value or an overvoltage set value of the output voltage.

Further, when the semiconductor device is a power supply driver, an external setting capacitor may be provided for setting the soft start function or the frequency spread (spread spectrum) function.

Japanese Unexamined Patent Publication No. 2014-21146

However, since the setting resistor or the setting capacitor as described above is externally attached, there is a risk that the connection may be disconnected or an error may occur in the setting of the resistance value or the capacitance value. For example, when an abnormality occurs in the state of the setting resistor described above, the target value of the output voltage becomes abnormal or the overvoltage setting value becomes abnormal, so that the output voltage becomes, for example, the withstand voltage of the external component or the withstand voltage of the semiconductor device. There was a risk that it would exceed the limit or the heat generation would become abnormal. This may lead to device destruction.

Further, for example, when an abnormality occurs in the state of the setting capacitor described above, there is a possibility that the operation and characteristics of the semiconductor device may be adversely affected.

Here, conventionally, for example, when the semiconductor device is an LED driver, there is a self-diagnosis function for checking whether or not an LED is connected when the semiconductor device is started. However, such a function cannot detect an abnormality of an external setting component at startup, so that a malfunction cannot be prevented.

Although Patent Document 1 discloses an input circuit for self-diagnosing whether or not an abnormality has occurred in an external capacitor, the capacitor is a filter capacitor, not a setting component.

In view of the above situation, it is an object of the present invention to provide a light emitting element driving device capable of suppressing a malfunction due to an abnormality of an external setting component.

In order to achieve the above object, one aspect of the present invention is a light emitting element driving device for driving a light emitting element.
When the light emitting element driving device is activated, a diagnostic unit that diagnoses whether or not there is an abnormality in the setting component connected to the outside of the light emitting element driving device, and a diagnostic unit that diagnoses that there is an abnormality by the diagnostic unit, A control unit for stopping the activation of the light emitting element driving device is provided.
The diagnostic unit diagnoses whether there is an abnormality in which the setting component, which is a resistor, is disconnected, and the light emitting element driving device further includes an external terminal connected to one end of the resistor.
The diagnostic unit includes a constant current circuit that allows a constant current to flow through the resistor via the external terminal, a comparator that inputs a voltage generated at the external terminal, and a transistor that switches connection / disconnection of the path through which the constant current flows. Have,
The resistor is arranged in a path different from the current path through which the current flows through the light emitting element (first configuration).
Further, in the first configuration, a dimming control unit may be further provided (second configuration).
Further, in the first or second configuration, an overcurrent protection circuit may be further provided (third configuration).
Further, in any of the first to third configurations, a terminal for outputting a signal related to an abnormal signal may be further provided (fourth configuration).
Further, in any of the first to fourth configurations, a current adjusting circuit for adjusting the current applied to the light emitting element may be further provided (fifth configuration).
Further, in the second configuration, a PWM signal may be input to the dimming control unit (sixth configuration).
Further, in the fourth configuration, the abnormal signal has a plurality of bits, and the control unit causes the abnormal signal output unit to output the abnormal signal of bit data different depending on the abnormality type from the terminal. This may be the case (seventh configuration).

According to the present invention, it is possible to suppress a malfunction due to an abnormality of an external setting component.

It is a figure which shows the whole structure of the switching power supply circuit which concerns on one Embodiment of this invention. It is a figure which shows the structure of the constant current control circuit which concerns on one Embodiment of this invention. It is a timing chart which shows the operation (mode when the dimming rate is high) of the switching power supply circuit which concerns on one Embodiment of this invention. It is a timing chart which shows the operation (mode when the dimming rate is low) of the switching power supply circuit which concerns on one Embodiment of this invention. It is a flowchart about self-diagnosis processing which concerns on one Embodiment of this invention. It is a figure which shows the structure of the external resistance diagnosis part which concerns on one Embodiment of this invention. It is a figure which shows the structure of the external resistance diagnosis part which concerns on one Embodiment of this invention. It is a figure which shows the structure of the external volume diagnostic part which concerns on one Embodiment of this invention. It is a figure which shows the structure of the error signal output part which concerns on one Embodiment of this invention. It is a flowchart about capacity value diagnosis processing which concerns on one Embodiment of this invention. It is a side view which shows the schematic structure of the liquid crystal display device which concerns on one Embodiment of this invention. It is a figure which shows the appearance that the vehicle-mounted display which concerns on one Embodiment of this invention is arranged in a vehicle.

An embodiment of the present invention will be described below with reference to the drawings.

<Overall configuration of switching power supply circuit>
FIG. 1 is a diagram showing an overall configuration of a switching power supply circuit 60 according to an embodiment of the present invention for driving an LED 70. The switching power supply circuit 60 is a DC / DC converter mainly including a semiconductor device 50 and an output stage 55. The switching power supply circuit 60 also includes an input capacitor Ci, a resistor R3, a resistor R4, and an abnormality flag output unit 30.

The output stage 55 provided outside the semiconductor device 50 has a switching element Q1, a switching element Q2, a diode D1, a diode D2, a coil L1, a bootstrap capacitor Cb, an output capacitor Co, a resistor R1, and a resistor R2. .. The semiconductor device 50 functions as a switching driver IC that switches and drives the switching elements Q1 and Q2. The semiconductor device 50 can also be regarded as an LED driver IC (light emitting element driving device).

The semiconductor device 50 includes a logic unit (control unit) 1, an internal power supply voltage generation unit 2, a UVLO (Under Voltage Lock Out) unit 3, a driver control unit 4, a comparator 5, an oscillator 6, a frequency diffusion unit 7, and a slope voltage generation unit. 8, error amplifier 9, switch 10, switch 11, inverter 12, constant current control circuit 13, comparator 14, overcurrent protection circuit 15, switch unit 16, transistor 17, soft start unit 18, dimming control unit 19, duty setting A unit 20, an external resistance diagnosis unit 21, an external resistance diagnosis unit 22, and an external capacitance diagnosis unit 23 to 25 are provided, and each of these components is integrated and configured. Further, the semiconductor device 50 includes external terminals T1 to T15 for establishing an electrical connection with the outside.

An input voltage Vin is applied to one end of the input capacitor Ci and is connected to one end of the resistor R3. The other end of the resistor R3 is connected to the drain of the switching element Q1 composed of the n-channel MOSFET together with one end of the resistor R4. The other end of the resistor R4 is connected to the external terminal T14 included in the semiconductor device 50.

The cathode of the diode D1 is connected to the source of the switching element Q1. The cathode of the diode D1 is connected to the external terminal T3 included in the semiconductor device 50. The anode of the diode D1 is connected to the application end of the ground potential. The gate of the switching element Q1 is connected to the external terminal T2 included in the semiconductor device 50.

One end of the coil L1 is connected to the connection point between the switching element Q1 and the diode D1, and the drain of the switching element Q2 composed of the anode of the diode D2 and the n-channel MOSFET is commonly connected to the other end of the coil L1. .. The source of the switching element Q2 is connected to the application end of the ground potential. The gate of the switching element Q2 is connected to the external terminal T4 included in the semiconductor device 50. One end of the output capacitor Co is connected to the cathode of the diode D2, and the other end of the output capacitor Co is connected to the application end of the ground potential.

Further, one end of the bootstrap capacitor Cb is connected to the connection point between the switching element Q1 and the coil L1. The other end of the bootstrap capacitor Cb is connected to the external terminal T1 included in the semiconductor device 50.

An output voltage Vout is generated at the connection point between the cathode of the diode D2 and one end of the output capacitor Co. A resistor R1 and a resistor R2 for voltage division are connected in series between the connection point and the end where the ground potential is applied. An external terminal T5 included in the semiconductor device 50 is connected to the connection point P1 between the resistor R1 and the resistor R2. Further, the anode side of the LED 70 is connected to the connection point between the cathode of the diode D2 and one end of the output capacitor Co. The cathode side of the LED 70 is connected to the external terminal T6 included in the semiconductor device 50.

The connection point P1 between the resistor R1 and the resistor R2 is connected to the first inverting input terminal (−) of the error amplifier 9 via the external terminal T5 and the switch 10. The cathode side of the LED 70 is connected to the second inverting input terminal (−) of the error amplifier 9 via the external terminal T6 and the switch 11. The first reference voltage Vref1 is applied to the non-inverting input terminal (+) of the error amplifier 9.

The switch 10 is switched on and off by the first switching signal SW1 sent from the logic unit 1. The switch 11 is switched on and off by a signal in which the first switching signal SW1 is logically inverted by the inverter 12. That is, it is possible to switch between a state in which the switch 10 is on and the switch 11 is off and a state in which the switch 10 is off and the switch 11 is on, according to the logic level of the first changeover signal SW1.

The error amplifier 9 amplifies the difference between the divided voltage Vdv1 after dividing the output voltage Vout by the resistors R1 and R2, the cathode voltage Vc of the LED 70, and the reference voltage Vref1 to obtain the error voltage ERR. Is output. The error voltage ERR is input to the inverting input end (−) of the comparator 5.

The slope voltage generation unit 8 generates a sawtooth wave-shaped or triangular wave-shaped slope voltage SL in synchronization with the clock signal output by the oscillator 6. The slope voltage SL is input to the non-inverting input end (+) of the comparator 5. The comparator 5 compares the error voltage ERR and the slope voltage SL, and outputs the comparison signal SC as the comparison result to the driver control unit 4.

The driver control unit 4 generates a pulse-like PWM (Pulse Width Modulation) signal Spwm1 or Spwm2 whose duty is adjusted based on the comparison signal SC, and outputs each to the driver Dr1 or the driver Dr2.

The driver Dr1 uses the voltage obtained by adding the input voltage Vin to the voltage generated in the bootstrap capacitor Cb (= the forward voltage of the internal power supply voltage Vreg-diode Db) by charging with the internal power supply voltage Vreg as the gate signal G1 and sets the external terminal T2. By outputting to the gate of the switching element Q1 via the device, the switching element Q1 is turned on. Further, the driver Dr1 turns off the switching element Q1 by outputting a gate signal G1 that short-circuits the gate and the source of the switching element Q1. The driver Dr1 outputs a gate signal G1 in response to the PWM signal Spwm1 from the driver control unit 4 to switch drive the switching element Q1.

The driver Dr2 turns on / off the switching element Q2 by outputting the internal power supply voltage Vreg and the ground potential as gate signals G2 to the gate of the switching element Q2 via the external terminal T4, respectively. The driver Dr2 outputs a gate signal G2 in response to the PWM signal Spwm2 from the driver control unit 4 to switch drive the switching element Q2.

Here, when the switching element Q2 is kept off by the driver Dr2 and the switching element Q1 is controlled on and off by the driver Dr1, the step-down mode is set in which the input voltage Vin is stepped down and the output voltage Vout is output. On the other hand, when the switching element Q1 is kept on by the driver Dr1 and the switching element Q2 is controlled on and off by the driver Dr2, the step-up mode is set in which the input voltage Vin is boosted and the output voltage Vout is output. These modes are used properly according to the number of stages of the LED element and the input voltage Vin depending on the application.

When the switch 10 is turned on and the switch 11 is turned off by the first switching signal SW1, the divided voltage Vdv1 after dividing the output voltage Vout by the resistors R1 and R2 is input to the error amplifier 9. Therefore, feedback control is performed using the voltage dividing voltage Vdv1 as a feedback signal, the duty of the PWM signal Spwm1 or Spwm2 is adjusted by PWM control, and the output voltage Vout is controlled to be constant (first feedback control mode). ..

On the other hand, when the switch 10 is turned off and the switch 11 is turned on by the first switching signal SW1, the cathode voltage Vc of the LED 70 is input to the error amplifier 9. Therefore, the feedback control using the cathode voltage Vc as the feedback signal is performed, the duty of the PWM signal Spwm1 or Spwm2 is adjusted by the PWM control, and the cathode voltage Vc is controlled to be constant (second feedback control mode).

Here, FIG. 2 is a diagram showing a specific configuration of the constant current control circuit 13. The constant current control circuit 13 includes a MOS transistor 131, a resistor 132, an error amplifier 133, a switch 134, a switch 135, an inverter 136, and a switch 137. The drain of the MOS transistor 131 composed of the n-channel MOSFET is connected to the external terminal T6 (FIG. 1) to which the cathode side of the LED 70 is connected. The source of the MOS transistor 131 is connected to one end of the resistor 132. The other end of the resistor 132 is connected to the end where the ground potential is applied. The connection point between the MOS transistor 131 and the resistor 132 is connected to the inverting input end (−) of the error amplifier 133 via the switch 135. The second reference voltage Vref2 is applied to the non-inverting input end (+) of the error amplifier 133. The output end of the error amplifier 133 is connected to the gate of the MOS transistor 131 via the switch 134. The connection point between the switch 134 and the MOS transistor 131 is connected to the application end of the ground potential via the switch 137.

The switch 134 and the switch 135 are switched on and off by the second switching signal SW2 sent from the logic unit 1. The switch 137 is switched on and off by a signal in which the second switching signal SW2 is logically inverted by the inverter 136. That is, it is possible to switch between a state in which the switch 134 and the switch 135 are turned on and the switch 137 is turned off and a state in which the switch 134 and the switch 135 are turned off and the switch 137 is turned on according to the logic level of the second changeover signal SW2. is there.

When the switch 134 and the switch 135 are turned on and the switch 137 is turned off by the second switching signal SW2, the current detection signal obtained by converting the current IL flowing through the LED 70 and the MOS transistor 131 into a voltage by the resistor 132 is input to the error amplifier 133. To. Then, the error amplifier 133 drives and controls the MOS transistor 131 by outputting a signal obtained by amplifying the difference between the current detection signal and the second reference voltage Vref 2 to the MOS transistor 131. As a result, constant current control is performed so that the current IL is constant.

On the other hand, when the switch 134 and the switch 135 are turned off and the switch 137 is turned on by the second switching signal SW2, the gate of the MOS transistor 131 is short-circuited with the ground potential, so that the MOS transistor 131 is kept off. As a result, the current IL is cut off.

Further, the frequency spreading unit 7 has a function of continuously changing and spreading the oscillation frequency of the clock signal generated by the oscillator 6. As a result, it is possible to reduce the noise peak of the radiated electromagnetic noise (EMI).

A dimming signal DM as a PWM signal (pulse signal) whose duty is adjusted is input to the dimming control unit 19 from the outside via the external terminal T12. The dimming control unit 19 generates a dimming control signal DCR based on the dimming signal DM and outputs it to the logic unit 1. The brightness of dimming can be adjusted by the duty of the dimming signal DM.

The duty setting unit 20 generates a duty setting signal DS and outputs it to the logic unit 1. The duty setting signal DS indicates the duty threshold value of the dimming signal DM.

The logic unit 1 compares the duty of the dimming signal DM with the set threshold value based on the dimming control signal DCR and the duty setting signal DS, and the first feedback control mode and the second feedback control described above are compared according to the comparison result. Switch between modes.

When it is determined that the duty of the dimming signal DM is equal to or higher than the threshold value, the logic unit 1 turns off the switch 10 by the first switching signal SW1 and turns on the switch 11 to make the cathode voltage Vc constant. Enable control mode. An example of various signal waveforms at this time is shown in FIG.

As shown in FIG. 3, when the dimming signal DM rises to the High level at the timing t1, the logic unit 1 turns on the switch 134 and the switch 135 and turns off the switch 137 by the second switching signal SW2. As a result, the current IL rises to the set current Issue. At this time, the forward voltage generated in the LED 70 becomes high. Therefore, for example, if the output voltage Vout is about 30 V, the cathode voltage Vc is about 1 V, and if the first reference voltage Vref1 is 1 V, the cathode voltage Vc is 1 V. The PWM signal Spwm1 or Spwm2 is generated so as to be constant. As a result, the switching elements Q1 or Q2 are on / off controlled.

Then, when the dimming signal DM falls at the timing t2 while the current IL is constantly controlled to be the set current Set, the logic unit 1 turns off the switch 134 and the switch 135 by the second switching signal SW2. Since the switch 137 is turned on, the current IL is reduced to zero. At this time, the forward voltage generated in the LED 70 becomes low, and in the above example, for example, the cathode voltage Vc rises to about 10V. Therefore, the cathode voltage Vc is considerably higher than the first reference voltage Vref1 which is 1V, the Low level is maintained as the PWM signal Spwm1 or Spwm2, and the switching element Q1 or Q2 is kept off.

By repeating such an operation, it is possible to perform bright dimming of the LED 70 while suppressing switching loss.

On the other hand, when it is determined that the duty of the dimming signal DM is lower than the threshold value, the logic unit 1 turns on the switch 10 and turns off the switch 11 by the first switching signal SW1 to make the output voltage Vout constant. Enable the feedback control mode. FIG. 4 shows an example of various signal waveforms at this time.

As shown in FIG. 4, at the timing t11 when the dimming signal DM rises, the logic unit 1 turns on the switch 134 and the switch 135 and turns off the switch 137 by the second switching signal SW2, so that the current IL sets the current Iset. Stand up to. Then, when the dimming signal DM falls at the timing t12 while the current IL is constantly controlled to be the set current Set, the logic unit 1 turns off the switch 134 and the switch 135 by the second switching signal SW2. Since the switch 137 is turned on, the current IL is reduced to zero. By repeating such an operation, it is possible to perform dark dimming of the LED 70.

At this time, since the first feedback control mode is effective, the PWM signal Spwm1 or Spwm2 is always generated in order to keep the output voltage Vout constant regardless of the level of the dimming signal DM (on / off of the current IL). If the second feedback control mode is enabled when the duty of the dimming signal DM is low, the PWM signal Spwm1 or Spwm2 is generated only in a short period when the dimming signal DM is at the high level, so the output voltage Vout is set. Cannot maintain level. Therefore, when the duty of the dimming signal DM is low, the first feedback control mode is enabled so that the output voltage Vout can be maintained at a predetermined level.

Further, the overcurrent protection circuit 15 issues a command to the logic unit 1 when the coil current flowing through the coil L1 detected by the voltage signal input via the external terminal T14 reaches a predetermined overcurrent set value. As a result, the driver control unit 4 forcibly lowers the PWM signal Spwm1 or Spwm2 to the Low level and turns off the switching element Q1 or Q2 by the command from the logic unit 1. Therefore, the coil current is limited so as not to exceed the overcurrent set value.

The soft start unit 18 controls to gradually increase the current limit value in the overcurrent protection circuit 15 when the semiconductor device 50 is started. As a result, the peak of the coil current gradually rises, and then the coil current reaches a steady state.

The comparator 14 compares the divided voltage Vdv1 obtained by dividing the output voltage Vout with a predetermined reference voltage, and outputs a logic level comparison signal DET1 indicating to that effect when the divided voltage Vdv1 exceeds the reference voltage to the logic unit 1. To do. In response to this, the logic unit 1 controls to turn off the switching element Q1 or Q2. As a result, overvoltage protection is performed in which the output voltage Vout is limited to the overvoltage set value or less.

The internal power supply voltage generation unit 2 receives a power supply voltage Vcc based on the input voltage Vin from the outside via the external terminal T8, and generates an internal power supply voltage Vreg based on the power supply voltage Vcc. The internal power supply voltage Vreg is supplied to each unit including the logic unit 1.

When the enable signal EN indicating enable is input to the internal power supply voltage generation unit 2 from the outside via the external terminal T7, the internal power supply voltage generation unit 2 raises the internal power supply voltage Vreg. The UVLO unit 3 keeps the logic unit 1 in the standby state while the internal power supply voltage Vreg does not reach a predetermined UVLO release voltage. Then, when the internal power supply voltage Vreg reaches the UVLO release voltage, the UVLO unit 3 releases the standby state of the logic unit 1. As a result, the semiconductor device 50 is activated.

When the enable signal EN indicating disable is input to the internal power supply voltage generation unit 2, the internal power supply voltage generation unit 2 lowers the internal power supply voltage Vreg. When the internal power supply voltage Vreg falls below a predetermined UVLO detection voltage, the UVLO unit 3 puts the logic unit 1 in the standby state. As a result, the switching elements Q1 and Q2 are kept off, and the semiconductor device 50 is in the power-off state. At this time, the logic unit 1 discharges the output capacitor Co via the external terminal T15 by turning on the transistor 17. As a result, the output voltage Vout can be surely set to 0V.

Further, the switch unit 16 and the abnormality flag output unit 30 constitute an error signal output unit that outputs an error signal to the outside when an abnormality is detected, and the details thereof will be described later.

<Self-diagnosis function of external setting parts>
Here, the voltage dividing resistor R2 provided outside the semiconductor device 50 functions as a setting resistor for setting the target voltage of the output voltage Vout in the first feedback control mode and setting the overvoltage set value.

Further, the resistor Rs1 externally connected to the oscillator 6 via the external terminal T10 functions as a setting resistor for setting the oscillation frequency of the oscillator 6.

The capacitor Cs1 connected to the frequency spreading unit 7 via the external terminal T9 functions as a setting capacitor for setting the fluctuation width or fluctuation cycle of the oscillation frequency by the frequency spreading unit 7.

The capacitor Cs2 connected to the soft start unit 18 via the external terminal T11 functions as a setting capacitor for setting the soft start time (rise time of the output voltage Vout).

The capacitor Cs3 connected to the duty setting unit 20 via the external terminal T13 functions as a setting capacitor for setting the duty threshold value of the dimming signal DM for switching between the first feedback control mode and the second feedback control mode.

Since these setting resistors and setting capacitors are external, there is a risk that the connection may be disconnected or an error may occur in the setting of the resistance value or capacitance value. Therefore, the semiconductor device 50 of the present embodiment has a self-diagnosis function for diagnosing whether or not these external setting parts are in an abnormal state at the time of starting the device, and this will be described with reference to the flowchart shown in FIG. To do.

The flowchart of FIG. 5 is started when the standby state of the logic unit 1 is released by the UVLO unit 3 and the semiconductor device 50 is started.

First, in step S1, it is diagnosed whether or not the voltage dividing resistor R2 is disconnected. This diagnosis is performed using the external resistance diagnosis unit 21. The configuration of the external resistance diagnosis unit 21 is shown in FIG. The external resistance diagnosis unit 21 includes a transistor 21A, a constant current circuit 21B, and a comparator 21C.

A predetermined power supply voltage V21 is applied to the source of the transistor 21A composed of the p-channel MOSFET. The drain of the transistor 21A is connected to one end of the constant current circuit 21B. The other end of the constant current circuit 21 is connected to the connection point between the resistors R1 and R2 via the external terminal T5, and is also connected to the non-inverting input end (+) of the comparator 21C. A reference voltage Vref 21 is applied to the inverting input end (−) of the comparator 21C. The comparator 21C outputs the detection signal DET 21 to the logic unit 1.

In step S1, the logic unit 1 applies a gate signal to the transistor 21A, turns on the transistor 21A, and attempts to generate a constant current I21. Here, if the connection of the resistor R2 is normal, a voltage based on the voltage drop generated by the constant current I21 flowing through the resistor R2 is applied to the non-inverting input end of the comparator 21C, so that the output of the comparator 21 A certain detection signal DET21 becomes the Low level. On the other hand, when the resistor R2 is disconnected, the constant current I21 does not flow and the power supply voltage V21 is applied to the non-inverting input end of the comparator 21, so that the detection signal DET21 becomes a high level. In this way, it is possible to diagnose whether or not the resistor R2 is disconnected by the logic level of the detection signal DET21.

The logic unit 1 determines whether or not the connection of the resistor R21 is abnormal according to the logic level of the detection signal DET21 (step S2), and if it is abnormal (Y in step S2), proceeds to step S8. In step S8, the logic unit 1 stops starting the semiconductor device 50. At the same time, the logic unit 1 notifies the error signal to the outside by using the switch unit 16 and the abnormality flag output unit 30.

Here, the configuration of the switch unit 16 and the abnormality flag output unit 30 is shown in FIG. The switch unit 16 has a transistor 16A, a transistor 16B, and a transistor 16C. All of these transistors are composed of n-channel MOSFETs. The abnormality flag output unit 30 has a power supply voltage V30, a resistor 30A, a resistor 30B, and a resistor 30C.

The drain of the transistor 16A is connected to one end of a pull-up resistor 30A via an external terminal T16 included in the semiconductor device 50. The drain of the transistor 16B is connected to one end of a pull-up resistor 30B via an external terminal T17 included in the semiconductor device 50. The drain of the transistor 16C is connected to one end of a pull-up resistor 30C via an external terminal T18 included in the semiconductor device 50. A power supply voltage V30 is applied to the other ends of the resistors 30A to 30C.

According to the on / off switching of the transistor 16A by the logic unit 1, the abnormality flag signal flg1 is output from the external terminal T16 via the abnormality output flag unit 30 with the Low / High level switched. According to the on / off switching of the transistor 16B by the logic unit 1, the abnormality flag signal flg2 is output from the external terminal T17 via the abnormality output flag unit 30 with the Low / High level switched. According to the on / off switching of the transistor 16C by the logic unit 1, the abnormality flag signal flg3 is output from the external terminal T18 via the abnormality output flag unit 30 with the Low / High level switched.

That is, a 3-bit error signal Serr composed of the abnormality flag signals flg1 to flg3 is generated by the combination of turning on and off the transistors 16A to 16C under the control of the logic unit 1. The bit data of the error signal Serr is generated differently according to each abnormality type such as when an overvoltage occurs, when an overcurrent occurs, and when step S8 in the self-diagnosis occurs.

When the semiconductor device 50 is for in-vehicle use, for example, the error signal Serr is sent to, for example, a microcomputer included in an ECU (Electronic Control Unit).

Returning the explanation to the flowchart of FIG. 5, if there is no abnormality in the connection of the resistor R2 in step S2 (N in step S2), the process proceeds to step S3. In step S3, it is diagnosed whether the resistance value of the external resistor Rs1 is within the specified range. This diagnosis is performed using the external resistance diagnosis unit 22. The configuration of the external resistance diagnosis unit 22 is shown in FIG. The external resistance diagnosis unit 22 includes a transistor 22A, a resistor 22B, a first comparator 22C, and a second comparator 22D.

A power supply voltage V22 is applied to the source of the transistor 22A composed of the p-channel MOSFET. The drain of the transistor 22A is connected to one end of the resistor 22B. The other end of the resistor 22B is connected to one end of the resistor Rs1 via the external terminal T10, and is also connected to the inverting input end (−) of the first comparator 22C and the non-inverting input end (+) of the second comparator 22D. To. The first reference voltage Vref221 is applied to the non-inverting input end (+) of the first comparator 22C. The second reference voltage Vref 222 is applied to the inverting input end (−) of the second comparator 22D. The first comparator 22C outputs the first detection signal DET221 to the logic unit 1. The second comparator 22D outputs the second detection signal DET 222 to the logic unit 1.

In step S2, the logic unit 1 turns on the transistor 22A. As a result, the voltage dividing voltage Vdv22 obtained by dividing the power supply voltage V22 by the resistor 22B and the resistor Rsc1 is monitored by the first comparator 22C and the second comparator 22D. If the resistance value of the resistor Rs1 exceeds the upper limit value of the specified range, the second detection signal DET222, which is the output of the second comparator 22D, becomes the High level. If the resistance value of the resistor Rs1 is less than the lower limit value of the specified range, the first detection signal DET221 which is the output of the first comparator 22C becomes the High level. When the resistance value of the resistor Rs1 is not more than the upper limit value and not more than the lower limit value, both the first detection signal DET221 and the second detection signal DET222 are at the Low level.

Therefore, when either the first detection signal DET221 or the second detection signal DET222 is at the High level, the resistance value of the resistor Rs1 is out of the specified range, which is an abnormal state, and when both are at the Low level, the resistance value is specified. It will be normal within the range.

The logic unit 1 determines whether or not there is an abnormality in the setting of the resistance value of the resistor Rs1 based on the first detection signal DET221 and the second detection signal DET222 (step S4), and if there is an abnormality (step S4). Y), the process proceeds to step S8, the activation is stopped, and the error signal Serr is output to the outside.

On the other hand, if there is no abnormality in the setting of the resistance value of the resistor Rs1 (N in step S4), the process proceeds to step S5. In step S5, it is diagnosed whether the capacitance values of the external capacitors Cs1 to Cs3 are within the specified range. This diagnosis is performed using the external volume diagnostic units 23 to 25. Here, FIG. 8 shows the configuration of the external capacitance diagnosis unit 23 that diagnoses the capacitance value of the capacitor Cs1.

The external capacitance diagnosis unit 23 includes a transistor 23A, a constant current circuit 23B, a constant current circuit 23C, a transistor 23D, a comparator 23E, and a control unit / timer unit 23F. A power supply voltage V23 is applied to the source of the transistor 23A composed of the p-channel MOSFET. The drain of the transistor 23A is connected to one end of the constant current circuit 23B. The other end of the constant current circuit 23B is connected to one end of the capacitor Cs1 via the external terminal T9 and is connected to the non-inverting input end (+) of the comparator 23E. A reference voltage Vref23 is applied to the inverting input end (−) of the comparator 23E. The external terminal T9 is connected to one end of the constant current circuit 23C. The other end of the constant current circuit 23C is connected to the drain of the transistor 23D composed of the n-channel MOSFET. The source of the transistor 23D is connected to the application end of the ground potential. The comparator 23E outputs the detection signal DET 23 to the control unit / timer unit 23F.

The capacity value diagnosis process by the external capacity diagnosis unit 23 will be described with reference to the flowchart shown in FIG.

The flowchart of FIG. 10 is started. First, in step S51, the logic unit 1 issues a command to the control unit / timer unit 23F to start the capacity diagnosis. As a result, the control unit / timer unit 23 turns off the transistor 23A and turns on the transistor 23D only for the period of the first predetermined time. As a result, the capacitor Cs1 is discharged from the capacitor Cs1 via the external terminal T9 and the transistor 23D at the constant current I232 for a period of the first predetermined time. Then, in step S52, when the first predetermined time elapses, the control unit / timer unit 23F turns off the transistor 23A and turns off the transistor 23D to stop the discharge. Here, the control unit / timer unit 23 confirms the detection signal DET23 which is the output of the comparator 23E.

When the semiconductor device 50 is restarted after the semiconductor device 50 is in the power-off state, the electric charge remains in the capacitor Cs1. From the current value of the constant current I232 and the upper limit of the capacitance in the specified range of the capacitor Cs1, the drop rate due to the discharge of the terminal voltage Vt generated at the external terminal T9 is determined. The first predetermined time is determined as the time from the falling speed and the voltage generated by the electric charge remaining in the capacitor Cs1 at the time of restart until the terminal voltage Vt becomes 0V (zero electric charge) by discharging.

Therefore, if the capacitance value of the capacitor Cs1 is equal to or less than the capacitance upper limit value, the terminal voltage Vt reaches 0V by discharging within the first predetermined time. In this case, when the first predetermined time elapses, the terminal voltage Vt is 0V, so that the detection signal DET23, which is the output of the comparator 23E, becomes the Low level. On the other hand, if the capacitance value of the capacitor Cs1 is larger than the capacitance upper limit value, the terminal voltage Vt becomes higher than 0V because the voltage drop rate is low even if discharging is performed for the first predetermined time period. Therefore, the detection signal DET23, which is the output of the comparator 23E, has a high level. That is, in step S52, the control unit / timer unit 23 can determine whether the capacitance value of the capacitor Cs1 is larger than the capacitance upper limit value based on the logic level of the detection signal DET23.

If the capacity value is larger than the capacity upper limit value (Y in step S52), the process proceeds to step S56, and the control unit / timer unit 23 outputs a diagnosis result signal indicating that the capacity value is abnormal to the logic unit 1. The process of FIG. 10 is completed. On the other hand, if the capacity value is equal to or less than the capacity upper limit value (N in step S52), the process proceeds to step S53.

In step S53, the control unit / timer unit 23F turns on the transistor 23A and turns off the transistor 23D for a period of the second predetermined time. As a result, charging is performed from the power supply voltage V23 via the transistor 23A and the external terminal T9 at the constant current I231 for a period of a second predetermined time. Then, in step S54, when the second predetermined time elapses, the control unit / timer unit 23F turns off the transistor 23A and turns off the transistor 23D to stop charging. Here, the control unit / timer unit 23 confirms the detection signal DET23.

The terminal voltage Vt has become 0V due to the previous discharge. From the current value of the constant current I231 and the lower limit of the capacitance in the specified range of the capacitor Cs1, the rising speed of the terminal voltage Vt generated in the external terminal T9 due to charging is determined. Based on this rising speed, a second predetermined time is set as the time from the terminal voltage Vt of 0V to the power supply voltage V23 by charging.

Therefore, when the capacitance value of the capacitor Cs1 is smaller than the capacitance lower limit value, charging is completed within the second predetermined time, and the terminal voltage Vt reaches the power supply voltage V23. In this case, when the second predetermined time elapses, the terminal voltage Vt is the power supply voltage V23, so that the detection signal DET23, which is the output of the comparator 23E, becomes the High level. On the other hand, when the capacitance value of the capacitor Cs1 is equal to or greater than the lower limit of the capacitance, the terminal voltage Vt does not reach the power supply voltage V23 because the voltage drop rate is low even if charging is performed for the second predetermined time period. Therefore, the detection signal DET23, which is the output of the comparator 23E, becomes the Low level. That is, in step S54, the control unit / timer unit 23 can determine whether the capacitance value of the capacitor Cs1 is smaller than the capacitance lower limit value based on the logic level of the detection signal DET23. At this time, the control unit / timer unit 23 switches the reference voltage Vref 23 to a voltage value different from that in step S52.

If the capacitance value is smaller than the capacitance lower limit value (Y in step S54), the process proceeds to step S56, and the control unit / timer unit 23 outputs a diagnosis result signal indicating that the capacitance value is abnormal to the logic unit 1. The process of FIG. 10 is completed. On the other hand, if the capacitance value is equal to or greater than the capacitance lower limit value (N in step S54), the process proceeds to step S55, and a diagnosis result signal indicating that the capacitance value is within the specified range and there is no abnormality is output to the logic unit 1. The process of FIG. 10 ends.

The configuration of the external capacity diagnosis unit 23 (FIG. 8) described above is the same as the configuration of the external capacity diagnosis units 24 and 25. Further, the capacitance value diagnosis processing of the capacitors Cs2 and Cs3 using the external capacitance diagnosis units 24 and 25 is the same as the processing of FIG. 10 described above.

In step S5 in the flowchart of FIG. 5, the capacitance value diagnosis of the above capacitors Cs1 to Cs3 is sequentially performed, but on the way, when the capacitance value is determined to be abnormal, the subsequent capacitors are not diagnosed. In step S6, the logic unit 1 determines that an abnormality has occurred in the capacitance value. When there is no abnormality in all the capacitance values of the capacitors Cs1 to Cs3, the logic unit 1 determines in step S6 that no abnormality has occurred in the capacitance values.

If it is determined in step S6 that an abnormality has occurred in the capacitance value (Y in step S6), the process proceeds to step S8, the startup is stopped, and the error signal Serr is output to the outside. On the other hand, if it is determined in step S6 that no abnormality has occurred in the capacitance value (N in step S6), the process proceeds to step S7. In step S7, the switching drive of the switching element Q1 or Q2 is started by the control of the logic unit 1, and the soft start by the soft start unit 18 is started. As a result, the output voltage Vout rises from 0V. Since the soft start is started after diagnosing the capacitor Cs2 for setting the soft start unit 18, the soft start time becomes abnormally short, the output voltage Vout overshoots, and the overvoltage protection cannot be achieved in time. You can avoid that.

As described above, according to the present embodiment, when the semiconductor device 50 is started up, the resistors R2, the resistors Rs1, and the capacitors Cs1 to Cs3, which are external setting components, are sequentially diagnosed to see if they are abnormal. When is detected, the start of the device can be stopped to prevent malfunction.

The following may be used as a modification of the present embodiment. For example, in the configuration of the external resistance diagnostic unit 22 shown in FIG. 7, when the external resistor Rs1 is disconnected, the external terminal T10 is opened, so that the second detection, which is the output of the second comparator 22D, is performed. The signal DET222 becomes the High level. Therefore, the external resistance diagnosis unit 22 can detect an abnormality in the resistance value of the resistor Rs1 as well as an abnormality in which the resistance Rs1 is disconnected. As a result, the same configuration as that of the external resistance diagnosis unit 22 may be used for diagnosing the resistance R2 for voltage division. In this case, an abnormality in which the resistance value of the resistor R2 is smaller than the lower limit value can be detected.

Further, the order of diagnosis (steps S1, S3, S5) of the external setting parts shown in FIG. 5 is not limited to this, and is arbitrary.

Further, in the above embodiment, even if an abnormality occurs in any of the external setting components, the error signal Serr of the same bit data is uniformly output according to the configuration shown in FIG. 9 in step S8 (FIG. 5). However, the bit data of the error signal Serr may be different for each setting component in which the abnormality has occurred. As a result, it is possible to notify which setting component has an abnormality. Although eight types of abnormalities can be notified by the number of 3 bits as shown in FIG. 9, the number of bits may be increased if the number of abnormalities is insufficient.

<Application to liquid crystal display (LCD)>
A liquid crystal display device will be described as an example of a target to which the semiconductor device (switching power supply circuit) according to the above-described embodiment is applied. A configuration example of the liquid crystal display device is shown in FIG. The configuration shown in FIG. 11 is a so-called edge light system, and is not limited to this, and a direct system may be used.

The liquid crystal display device X shown in FIG. 11 includes a backlight 81 and a liquid crystal panel 82. The backlight 81 is a lighting device (an example of a light emitting device) that illuminates the liquid crystal panel 82 from the back surface. The backlight 81 includes an LED light source unit 811, a light guide plate 812, a reflector plate 813, and optical sheets 814.

The LED light source unit 811 includes an LED and a substrate on which the LED is mounted, and the above-described embodiment can be applied as the switching power supply circuit for driving the LED. The light emitted from the LED light source unit 811 enters the inside from the side surface of the light guide plate 812. For example, the light guide plate 812 made of an acrylic plate guides the light entering the inside to the entire inside while totally reflecting the light, and emits the light as planar light from the surface on the side where the optical sheets 814 are arranged. The reflector 813 reflects the light leaked from the light guide plate 812 and returns it to the inside of the light guide plate 812. The optical sheets 814 are made of a diffusion sheet, a lens sheet, or the like, and have an object of making the brightness of the light illuminating the liquid crystal panel 82 uniform or improving the brightness.

<About in-vehicle display>
The liquid crystal display device to which the semiconductor device according to the above-described embodiment is applied is particularly preferably applied to an in-vehicle display. The technology for preventing malfunctions as described above is important in terms of safety in the situation where ISO 26262, which is an international standard for functional safety of automobiles, has been established.

The in-vehicle display is provided on the dashboard in front of the driver's seat of the vehicle, for example, as in the in-vehicle display Y shown in FIG. The in-vehicle display Y can display various images such as car navigation information, a captured image of the rear of the vehicle, a speedometer, a tachometer, a fuel gauge, a fuel consumption meter, and a shift position, and can convey various information to the user. ..

<Others>
It should be considered that the above-described embodiment is an example in all respects and is not restrictive, and the technical scope of the present invention is not the description of the above-mentioned embodiment but the scope of claims. It is shown and should be understood to include all modifications that fall within the meaning and scope of the claims.

The present invention can be used, for example, in an in-vehicle LED driver IC.

1 Logic part 2 Internal power supply voltage generation part 3 UVLO part 4 Driver control part 5 Comparator 6 Oscillator 7 Frequency spread part 8 Slope voltage generation part 9 Error amplifier 10 Switch 11 Switch 12 Inverter 13 Constant current control circuit 14 Transistor 15 Overcurrent protection circuit 16 Switch part 16A to 16C Transistor 17 Transistor 18 Soft start part 19 Dimming control part 20 Duty setting part 21 External resistance diagnosis part 21A Transistor 21B Constant current circuit 21C Comparator 22 External resistance diagnosis part 22A Transistor 22B Resistance 22C First comparator 22D No. 2 comparator 23 external capacitance diagnostic unit 23A transistor 23B constant current circuit 23C constant current circuit 23D transistor 23E comparator 23F control unit / timer unit 24 external capacitance diagnostic unit 25 external capacitance diagnostic unit 30 abnormality flag output unit 30A to 30C resistance 50 semiconductor device 55 Output stage 60 Switching power supply circuit 70 LED
81 Backlight 82 Liquid crystal panel 811 LED light source 812 Light guide plate 813 Reflector 814 Optical sheets 131 Transistor 132 Resistance 133 Error amplifier 134 Switch 135 Switch 136 Inverter 137 Switch Q1, Q2 Switching element Cb Bootstrap capacitor D1, D2 Diode L1 Coil Co Output Capacitor Ci Input Capacitor R1 to R4, Rs1 Resistor Cs1 to Cs3 Capacitor T1 to T18 External Terminal X Liquid Crystal Display Y In-Vehicle Display

Claims (7)

A light emitting element driving device that drives a light emitting element.
When the light emitting element driving device is activated, a diagnostic unit that diagnoses whether or not there is an abnormality in the setting component connected to the outside of the light emitting element driving device, and a diagnostic unit that diagnoses that there is an abnormality by the diagnostic unit, A control unit for stopping the activation of the light emitting element driving device is provided.
The diagnostic unit diagnoses whether there is an abnormality in which the setting component, which is a resistor, is disconnected, and the light emitting element driving device further includes an external terminal connected to one end of the resistor.
The diagnostic unit includes a constant current circuit that allows a constant current to flow through the resistor via the external terminal, a comparator that inputs a voltage generated at the external terminal, and a transistor that switches connection / disconnection of the path through which the constant current flows. Have,
A light emitting element driving device in which the resistor is arranged in a path different from the current path through which a current flows through the light emitting element. The light emitting element driving device according to claim 1, further comprising a dimming control unit. The light emitting element driving device according to claim 1 or 2, further comprising an overcurrent protection circuit. The light emitting element driving device according to any one of claims 1 to 3, further comprising a terminal for outputting a signal related to an abnormal signal. The light emitting element driving device according to any one of claims 1 to 4, further comprising a current adjusting circuit for adjusting a current applied to the light emitting element. The light emitting element driving device according to claim 2, wherein a PWM signal is input to the dimming control unit. The abnormal signal has a plurality of bits and has a plurality of bits.
The light emitting element driving device according to claim 4, wherein the control unit causes the abnormality signal output unit to output the abnormality signal of bit data different depending on the abnormality type from the terminal.

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