JP2021076433A - Clock adjustment device, program, and clock adjustment method - Google Patents

Abstract

To provide a clock adjustment device and a program that can accurately determine time synchronization with a reference clock.SOLUTION: In a time server 10, a time synchronization determination unit 28 assumes that the previously-calculated intrinsic pace matches the pace of a reference clock, and then calculates the current theoretical time difference by using the previous time difference, the previously-calculated time difference cancellation pace, and the previously-calculated intrinsic pace. The time synchronization determination unit determines whether the pace of the reference clock matches the pace of a clock unit based on the difference between the calculated theoretical time difference and the current time difference.SELECTED DRAWING: Figure 4

Description

The present invention relates to a clock adjusting device, a program, and a clock adjusting method, and more particularly to a clock adjusting device, a program, and a clock adjusting method for adjusting the clock of the own device.

Conventionally, there is a time server that acquires time information from a reference clock, adjusts the precise clock of its own device, and distributes the time to its subordinate devices.

The time server periodically receives time information from the reference clock and checks the time difference between its own clock and the reference clock. Normally, the current rate F of the own clock is determined by calculation based on the time difference. Further, this calculation is obtained by adding a part that matches the step with the reference clock and a part that eliminates the time difference.

Further, a time control device that synchronizes time information with a master device on a network with high accuracy is known (Patent Document 1). This time controller is applied to PTP (Precision Time Protocol) slaves.

Further, there is known a synchronization device that shortens the time from activation to reaching the target level of synchronization accuracy (Patent Document 2).

Japanese Unexamined Patent Publication No. 2013-83450 Japanese Unexamined Patent Publication No. 2018-10326

When synchronizing the time with the PTP master, a general PTP slave adjusts the slave clock value and the value addition speed (rate) so that the offsetFrommaster value becomes 0.

The offsetFromMaster value represents the time difference between the internal clocks of the PTP slave and the PTP master. By adjusting this to 0, the time is synchronized. At this time, the offsetFromMaster value converges from, for example, about 1500 ns to about 10 ns or less in several seconds to several tens of seconds. However, since this value is simply 10 ns or less, it cannot be judged that the time is synchronized. The reason will be explained below.

First, a general time synchronization framework will be described. A logical feedback circuit using a PID controller as shown in FIG. 8 is generally used for step adjustment for maintaining the offsetFrommaster value at 0. Since the PID controller is used in this rate adjustment, the behavior until the offsetFrommaster value is converged to 0 is not limited. For example, the curve until convergence becomes various curves as shown in FIG.

For curve A, if the offsetFromMaster value is 10 ns or less, it may be judged that "time synchronization", but for curves B and C, a simple judgment as to whether or not it is 10 ns or less is ". By the time it really converges, the judgment results of "time synchronized" and "time not synchronized" will be exchanged multiple times.

In order to prevent such "time synchronization judgment" deviation, for example, when the offsetFrommaster value is within 10 ns, it is confirmed that the user stays within 10 ns for a while (for example, 30 seconds), and then the time is synchronized. However, in reality, it is still in the transient response stage and may not be in a steady state. Further, it is impossible to judge whether the transient response is in progress or the steady state by this method.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a clock adjusting device, a program, and a clock adjusting method capable of accurately determining time synchronization with a reference clock. To do.

In order to achieve the above object, the clock adjusting device according to the present invention includes a communication unit that receives time information of a reference clock, a clock unit that outputs time information determined based on the current rate, and the clock unit. Based on the current time difference between the time information output by the reference clock and the time information of the reference clock, the time difference elimination step for eliminating the time difference from the reference clock and the intrinsic step for adjusting to the speed of the reference clock. Is calculated, the current rate with respect to the clock unit is determined based on the time difference elimination rate and the inherent rate, and the clock adjustment unit that updates the rate of the clock unit, and the current time difference and the theoretical time difference. The theoretical time difference includes a time synchronization determination unit that determines whether or not the rate of the reference clock and the rate of the clock unit match based on the difference of the reference clock. It is assumed that the clock adjusting device is calculated by using the previous time difference, the previously calculated time difference elimination step, and the previously calculated natural rate.

According to the present invention, assuming that the eigenstep calculated last time matches the reference clock, the current theory uses the time difference of the previous time, the time difference elimination step calculated last time, and the eigenstep calculated last time. Calculate the time difference. Then, based on the difference between the calculated theoretical time difference and the current time difference, it is determined whether or not the rate of the reference clock and the rate of the clock section match, thereby accurately determining the time synchronization with the reference clock. can do.

Here, the step is the degree of advancement or lag of the clock, for example, the length (nanoseconds) of increasing or decreasing the speed per second. The speed of the reference clock is the length of 1 second (nanoseconds) of the reference clock.

Further, in the clock adjusting device, the time synchronization determination unit can further determine that the reference clock and the time match when the absolute value of the current time difference is less than the threshold value.

Further, in the clock adjusting device, the time synchronization determination unit is based on the time difference obtained last time, the time interval between the time when the time difference was obtained last time and the time when the time difference was calculated this time, and the time difference obtained last time. The theoretical time difference can be calculated based on the calculated time difference elimination step and the inherent step.

Further, the program of the present invention is a program for causing the computer to function as each part of the clock adjusting device of the present invention.

Further, in the clock adjustment method of the present invention, the communication unit receives the time information of the reference clock, the clock unit outputs the time information determined based on the current rate, and the clock adjustment unit outputs the time information determined based on the current rate. Based on the current time difference between the time information output by the reference clock and the time information of the reference clock, the time difference elimination step for eliminating the time difference from the reference clock and the unique step for adjusting to the speed of the reference clock. Is calculated, the current step with respect to the clock section is determined based on the time difference elimination step and the inherent step, the step of the clock section is updated, and the time synchronization determination section determines the current time difference and the theory. The theoretical time difference includes determining whether or not the step of the reference clock and the step of the clock section match based on the difference from the time difference, and the theoretical time difference is the step of the reference clock whose inherent step calculated last time is the step of the reference clock. It is assumed that the clock adjustment method is calculated by using the previous time difference, the previously calculated time difference elimination step, and the previously calculated natural step.

According to the present invention, the time synchronization with the reference clock can be accurately determined.

It is a figure for demonstrating the clock adjustment method. It is a graph which shows the convergence curve of the time difference with reference clock. It is a figure which shows an example of the clock adjustment system which concerns on embodiment of this invention. It is a block diagram which shows the structure of the time server which concerns on embodiment of this invention. It is a figure which shows the flowchart of the clock adjustment processing of the time server which concerns on embodiment of this invention. It is a figure which shows the flowchart of the time synchronization determination processing of the time server which concerns on embodiment of this invention. It is a figure which shows the flowchart of the time synchronization determination processing of the time server which concerns on embodiment of this invention. It is a figure for demonstrating the clock adjustment method in a PTP slave. It is a graph which shows the convergence curve of the time difference with the clock of a PTP master.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Outline of Embodiment of the present invention>
First, an outline of an embodiment of the present invention will be described.

In the embodiment of the present invention, the convergence test, which is not enough to determine whether the time difference is 10 ns or less, is performed more strictly, and when the curves B and C in FIG. 9 are also "really converged", "time synchronization" is performed. Is determined. " The judgment principle will be described below.

For time synchronization, it is necessary to match the time and the rate with the PTP master. Even if only the time is correct, if the pace is different, a non-zero time difference will be confirmed each time the time difference is confirmed with the PTP master.

On the other hand, even if there is only a rate, if the time difference from the PTP master is not 0, the time difference will never become 0. That is, for time synchronization, it is necessary to match both the time and the rate.

FIG. 1 is a diagram for explaining a clock adjustment method. In the present embodiment, a PID controller as shown in FIG. 1 is used to match the time and the rate. With this PID controller, an additional step (also referred to as an intrinsic step or frequency drift value. The unit is ppb (parts per billion)) for eliminating the time difference from the PTP master is calculated. It is also called the time difference elimination rate. The unit is ppb).

This part is mathematically described as follows.

Incidentally, r _{(t i)} in FIG. 1 is a time _{t i} (in seconds) Time indicated by the PTP master clock in nanoseconds. y _{(t i)} is the time _{t i} (in seconds) Time indicated by the PTP slave clock in nanoseconds. x _{(t i)} is the time _{t i} of the PTP slave in seconds the clock and the PTP master clock time difference _(ns), with x (t _{i) =} r (t i) -y _{(t i)} is there. K _P , K _I , and K _D are predetermined coefficients. f _{(t i)} is the output value of the PID controller at time _{t i} (in seconds).

here,

And put

Can be written. P _{(t i)} is the time difference eliminate pace. I _{(t i)} it is a unique pace.

Now, assume an ideal environment without noise. Here, all the _{t i (i = 0,1,2, ...} ) with respect to, those if that multiplied _{(1 + I (t i)} / 10 9) the pace of the PTP slave, consistent with pace of PTP master if it is, the following equation theory difference x between PTP master shown in [expression _{3] '(t i + 1} ) _should match the real time difference x at _{t i + 1} time _{(t i + 1).}

Incidentally, ¹⁰⁹ indicates that the second is the length = 10 ⁹ nsec.

In this case, theoretically, under the condition that the parameters designed not to overshoot, x (t _i) and x 'can assume code and is always equal to (t i _{+ 1),} the convergence curves as in Figure 2 It becomes a graph of monotonically decreasing or monotonically increasing.

On the other hand, it is a point of the time synchronization determination according to the present embodiment to utilize the fact that the opposite is true.

Here, if the theoretical time difference and the actual time difference match, there is a proposition that the natural rate (frequency drift value) at that time is equal to the rate of the PTP master.

_{Specifically, x '(t i) =} x (t i) if PTP slave pace a _{(1 + I (t i)} / 10 9) multiplied by those is consistent with pace of PTP master, proposition There is.

This proposition is proved as follows.

Note that by definition of PID controller, P (ti _-1 ) can be calculated from measured values rather than estimated values. Therefore, assuming that the correct intrinsic step at the time of _{ti-1 is F (ti-1} ), the equation [Equation 3] is used.

と記述できる。これをｘ’（ｔ_ｉ）の定義式と比較して、結果的に

Can be described as. This was compared with the defining equation of x '(t _i), resulting in

To get.

From the above, if the predicted value of x (t) and the measured value match, that is, if the measured value does not deviate from the theoretical convergence curve, it can be said that the peculiar rate of the PTP slave is correct.

Therefore, in light of the above-mentioned time synchronization conditions, the time synchronization can be determined as follows with two user-settable threshold values.

Using the constants a, b> 0,

(Time judgment), and

Satisfying both conditions of being (rate determination) can be a determination condition that both the time and the rate match. Further, when only the condition for determining the rate is satisfied, it can be said that the frequency is synchronized.

<System configuration of the embodiment of the present invention>
The configuration of the clock adjustment system according to the embodiment of the present invention will be described. As shown in FIG. 3, the clock adjustment system 100 according to the embodiment of the present invention includes a time server 10, reference clock transmitters 16-1 to 16-n, and a client terminal 18-1. The time server 10 and the client terminal 18-1 are connected to each other via a network 3 such as a LAN (Local Area Network), and the time server 10 and the reference clock transmitters 16-1 to 16-n are connected to the network 3. Is connected via another network or dedicated communication (for example, GNSS (Global Navigation Client System) or Tel-JJY (provided in standard time by telephone line)). The time server 10 is an example of a clock adjusting device.

The time server 10 is a server that adjusts the clock of its own device by using the time information of the reference clock and distributes the time information to the client terminal 18-1. Further, the time server 10 adjusts the clock of its own device, generates various signals using the clock information, and receives the measuring device 18-2, the wireless device 18-3, the video device 18-4, and the signal reception. The generated signal is delivered to the device 18-n. For example, as shown in FIG. 3, a phase signal of 1 PPS for the measuring instrument 18-2, a frequency signal of 10 MHz for the wireless device 18-3, and an analog image such as BB / LTC for the video device 18-4. Generates and distributes a synchronization signal.

Reference clock transmission devices 16-1 to 16-n are server devices that transmit time information of the reference clock. Although the description of the specific embodiment of the reference clock transmitting device 16-1 to 16-n is omitted, the reference clock transmitting device 16-1 to 16-n has a reference clock and provides time information of the reference clock. It is also possible to distribute via a network different from the network 3 or a dedicated communication.

The time server 10 in the present embodiment can be configured by a computer including a CPU, a RAM, and a ROM that stores a program for executing various processing routines described later and various data. Functionally, as shown in FIG. 4, the time server 10 has a communication unit 20, a signal generation / distribution unit 21, its own system clock or hardware clock unit 22, a time difference calculation unit 24, and a time synchronization determination. A unit 28 and a own system clock control unit 30 are provided.

The communication unit 20 receives the time information of the reference clock from the reference clock transmitting devices 16-1 to 16-n via a network different from the network 3 or dedicated communication. Further, the signal generation / distribution unit 21 transmits the time information of the own clock output from the own system clock or the hardware clock unit 22 to the client terminal 18-1 via the network 3. Further, the signal generation / distribution unit 21 generates a phase signal of 1PPS and distributes it to the measuring instrument 18-2, generates a frequency signal of 10 MHz and distributes it to the wireless device 18-3, and analogs such as BB / LTC. A video synchronization signal is generated and distributed to the video equipment 18-4.

The own system clock or the hardware clock unit 22 determines the time information of the own clock based on the current rate, and outputs the time information to the time difference calculation unit 24 and the signal generation / distribution unit 21. The own system clock or the hardware clock unit 22 is an example of the clock unit.

When the time difference calculation unit 24 receives the time information of the reference clock, the time difference calculation unit 24 calculates the current time difference between the time information of the own clock and the time information of the reference clock, and sets the calculated current time difference as the own system clock control unit 30. Notify to. The time difference calculation unit 24 does not calculate the current time difference while the time information of the reference clock is not received.

The own system clock control unit 30 includes a own clock adjustment unit 34. The own clock adjustment unit 34 is an example of the clock adjustment unit.

When the time difference calculation unit 24 notifies the current time difference, the own clock adjusting unit 34 accelerates the rate of the own clock and delays it if the reference clock advances with respect to the own clock based on the current time difference. If so, update the rate of the own clock so as to loosen the rate of the own clock.

Specifically, based on the current time difference, the previous time difference, and the interval from the previous time, the time difference elimination step P for eliminating the time difference from the reference clock is set so that the current time difference is directed to 0. Along with the calculation, the intrinsic step I for matching the speed of the reference clock is calculated so that the step difference between the reference clock and the own clock is directed to 0. Then, based on the time difference elimination step P and the intrinsic step I, the step of the own clock is updated as shown in the following equation, and the own system clock or the hardware clock unit 22 uses the current time y (t). _i ) is calculated.

However, the unit of f is ppb (ns / s), and the units of P and I are also ppb (ns / s).

The time synchronization determination unit 28 calculates the previous time difference, the previously calculated time difference elimination step P, and the previously calculated unique step I on the assumption that the previously calculated unique step I matches the reference clock. Use to calculate the current theoretical time difference.

Specifically, the time synchronization determination unit 28 determines the time difference elimination step P and the unique step I calculated based on the interval between the time difference obtained last time and the time point when the time difference was obtained last time, and the time difference obtained last time. Based on the above, the theoretical time difference is calculated according to the above equation [Equation 3].

When the difference between the theoretical time difference and the current time difference is less than the threshold value b, the time synchronization determination unit 28 determines that the step of the reference clock matches, and the difference between the theoretical time difference and the current time difference is If it is equal to or higher than the threshold value b, it is determined that the step does not match the step of the reference clock.

Further, the time synchronization determination unit 28 determines that the reference clock and the time match when the absolute value of the current time difference is less than the threshold value a, and when the absolute value of the current time difference is equal to or more than the threshold value a. In addition, it is determined that the reference clock and the time do not match.

The time synchronization determination unit 28 outputs the determination result. For example, the result of the time synchronization determination is displayed on a CLI (Command-Line Interface) or GUI (Graphical User Interface) so that the user can understand the result, or an LED lamp indicating the synchronization state is turned on. Further, when it becomes asynchronous, the user may be notified by means such as Syslog or SNMP (Simple Network Management Protocol).

<Operation of the embodiment of the present invention>
Next, the processing by the time server 10 according to the embodiment of the present invention will be described with reference to FIGS. 5 to 7. The time server 10 receives the time information of the reference clock from any of the reference clock transmitters 16-1 to 16-n, and calculates the current time difference between the time information of the own clock and the time information of the reference clock. Then, the time server 10 executes the clock adjustment processing routine shown in FIG. The clock adjustment processing routine is executed each time the time information of the reference clock is received.

First, in step S100, the own clock adjusting unit 34 acquires the time information of the current own clock and the current time difference calculated by the time difference calculation unit 24.

In step S102, the own clock adjusting unit 34 eliminates the time difference from the reference clock so that the current time difference is directed to 0 based on the current time difference, the previous time difference, and the interval from the previous time. In addition to calculating the time difference elimination step P of, the specific step I for adjusting to the speed of the reference clock is calculated so that the step difference between the reference clock and the own clock is directed to 0.

In step S104, the own clock adjusting unit 34 stores the time information acquired in step S100 and the current time difference, and the time difference elimination step P and the unique step I calculated in step S102 in a memory (not shown). To do.

Then, in step S106, the self-clock adjusting unit 34 updates the self-clock step based on the time difference elimination step P and the natural step I, outputs the self-clock to the own system clock or the hardware clock unit 22, and performs the clock adjustment process. End the routine.

Further, when the time server 10 receives the time information of the reference clock from the reference clock transmitting device 16 and the current time difference between the time information of the own clock and the time information of the reference clock is calculated, the time server 10 receives the time information of the reference clock. The time synchronization determination processing routine shown in FIG. 6 is executed. The clock adjustment processing routine is executed each time the time information of the reference clock is received.

First, in step S110, the time synchronization determination unit 28 acquires the time information of the current own clock and the current time difference calculated by the time difference calculation unit 24.

Then, in step S112, the time synchronization determination unit 28 acquires the time information of the previous own clock stored in the memory, the previous time difference, the previous time difference elimination step P, and the unique step I.

In step S114, the time synchronization determination unit 28 performs the time synchronization determination process.

In step S116, the time synchronization determination unit 28 outputs the determination result of step S114 and ends the time synchronization determination processing routine.

In this way, instead of predicting and storing the time difference one second later, for example, from the current time difference, the current time difference x'(t) as a predicted value is calculated from the time difference one second ago and used as the measured value. The time synchronization determination can be performed by comparing with the current time difference x (t) of.

The step S114 is realized by the processing routine shown in FIG.

First, in step S120, the time synchronization determination unit 28 determines the time difference elimination step P and the unique step calculated based on the interval between the time difference obtained last time and the time point when the previous time difference was obtained, and the time difference obtained last time. Based on I, the theoretical time difference is calculated according to the above equation [Equation 3].

In step S122, the time synchronization determination unit 28 determines whether or not the absolute value of the current time difference is less than the threshold value a and the absolute value of the difference between the theoretical time difference and the current time difference is less than the threshold value b. To do. When the absolute value of the current time difference is less than the threshold value a and the absolute value of the difference between the theoretical time difference and the current time difference is less than the threshold value b, it is determined that the time is synchronized with the reference clock.

On the other hand, if the absolute value of the current time difference is equal to or greater than the threshold value a, or if the absolute value of the difference between the theoretical time difference and the current time difference is equal to or greater than the threshold value b, the process proceeds to step S124.

In step S124, the time synchronization determination unit 28 determines whether or not the absolute value of the difference between the theoretical time difference and the current time difference is less than the threshold value b. When the absolute value of the difference between the theoretical time difference and the current time difference is less than the threshold value b, it is determined that the frequency is synchronized with the reference clock (the steps are matched). On the other hand, when the absolute value of the difference between the theoretical time difference and the current time difference is equal to or greater than the threshold value b, it is determined that the time difference is asynchronous with the reference clock.

As described above, according to the time server according to the embodiment of the present invention, it is assumed that the inherent rate calculated last time matches the reference clock, and the time difference between the previous time and the time difference calculated last time are eliminated. The current theoretical time difference is calculated using the rate and the inherent rate calculated last time. Then, based on the difference between the calculated theoretical time difference and the current time difference, it is determined whether or not the rate of the reference clock and the rate of the clock section match, thereby accurately determining the time synchronization with the reference clock. can do.

The present invention is not limited to the above-described embodiment, and various modifications and applications are possible without departing from the gist of the present invention.

3 Network 10 Time server (clock regulator)
16 Reference clock transmitter 18 Client terminal 20 Communication unit 21 Signal generation / distribution unit 22 Own system clock or hardware clock unit (clock unit)
24 Time difference calculation unit 28 Time synchronization judgment unit 30 Own system clock control unit 34 Own clock adjustment unit (clock adjustment unit)
100 clock adjustment system

Claims (5)

The communication unit that receives the time information of the reference clock and
A clock section that outputs time information determined based on the current rate, and
Based on the current time difference between the time information output by the clock unit and the time information of the reference clock, the time difference elimination rate for eliminating the time difference with the reference clock and the speed of the reference clock are adjusted. A clock adjusting unit that calculates the unique rate, determines the current rate with respect to the clock unit based on the time difference elimination rate and the natural rate, and updates the rate of the clock unit.
A time synchronization determination unit for determining whether or not the rate of the reference clock and the rate of the clock unit match based on the difference between the current time difference and the theoretical time difference is included.
The theoretical time difference is calculated using the previous time difference, the previously calculated time difference elimination step, and the previously calculated natural step, assuming that the previously calculated natural step matches the step of the reference clock. Clock regulator. The clock adjustment device according to claim 1, wherein the time synchronization determination unit further determines that the reference clock and the time match when the absolute value of the current time difference is less than the threshold value. The time synchronization determination unit includes the time difference obtained last time, the time interval between the time when the previous time difference was obtained and the time when the time difference was calculated this time, the time difference elimination step calculated based on the time difference obtained last time, and the time difference elimination step. The clock adjusting device according to claim 1 or 2, wherein the theoretical time difference is calculated based on the inherent rate. A program for causing a computer to function as each part of the clock adjusting device according to any one of claims 1 to 3. The communication unit receives the time information of the reference clock and
The clock section outputs time information determined based on the current rate,
Based on the current time difference between the time information output by the clock unit and the time information of the reference clock, the clock adjusting unit determines the time difference elimination rate for eliminating the time difference from the reference clock, and the reference clock. The natural step for adjusting to the speed is calculated, the current step with respect to the clock section is determined based on the time difference elimination step and the natural step, and the step of the clock section is updated.
The time synchronization determination unit includes determining whether or not the rate of the reference clock and the rate of the clock unit match based on the difference between the current time difference and the theoretical time difference.
The theoretical time difference is calculated using the previous time difference, the previously calculated time difference elimination step, and the previously calculated natural step, assuming that the previously calculated natural step matches the step of the reference clock. Clock adjustment method.

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