JP2021071392A - Voltage monitoring circuit - Google Patents

Abstract

To obtain a voltage monitoring circuit in which a determination voltage can be fine-adjusted, can be arbitrarily set, and hysteresis can be imparted to the determination voltage.SOLUTION: A voltage monitoring circuit 1c comprises: input terminals T1 and T2 to which V1 and V2 are applied, respectively; a reference voltage generation circuit 2 generating VREF1; a linear power supply circuit 3 generating VREF2 in accordance with VREF1; feedback resistors (4, 5, 8c, 8d) generating a plurality of divided voltages from VREF2 and negatively feeding back one of them as feedback voltage to the linear power supply circuit 3; a comparison unit 6 comparing V1 with VREF3 and generating a comparison signal S2; a comparison unit 7 comparing V2 with VREF4 and generating a comparison signal S2; selection units SW1 and SW2 selecting any two of VREF2 and its divided voltage as switching candidates for VREF3 and switching VREF3 in accordance with the comparison signal S1; and selection units SW3 and SW4 selecting any two of VREF2 and its divided voltage as switching candidates for VREF4 and switching the VREF4 in accordance with the comparison signal S2.SELECTED DRAWING: Figure 14

Description

The present invention relates to a voltage monitoring circuit that monitors the magnitude relationship between the monitored voltage and the determination voltage.

FIG. 21 is a diagram showing a configuration example of a conventional voltage monitoring circuit. The voltage monitoring circuit 11 shown in FIG. 21 is mounted on a one-chip semiconductor integrated circuit device. The voltage monitoring circuit 11 includes resistors 12 and 13, a reference voltage generation circuit 14, a comparator 15, an input terminal T11, and an output terminal T12.

The monitoring target voltage MV is applied to the input terminal T11. The voltage divider circuit composed of resistors 12 and 13 converts the monitored voltage MV into the voltage divider VDIV11 and supplies the voltage divider VDIV11 to the non-inverting input terminal of the comparator 15.

The reference voltage generation circuit 14 generates a predetermined reference voltage VREF11 and supplies the reference voltage VREF11 to the inverting input terminal of the comparator 15.

The comparator 15 generates a comparison signal S11 indicating a comparison result between the divided voltage VDIV 11 and the reference voltage VREF 11, and outputs the comparison signal S11 to the outside of the voltage monitoring circuit 11 via the output terminal T12. When the voltage divider VDIV11 is larger than the reference voltage VREF11, the comparison signal S11 becomes a high level signal. On the other hand, when the divided voltage VDIV11 is smaller than the reference voltage VREF11, the comparison signal S11 becomes a low level signal. When the divided voltage VDIV11 and the reference voltage VREF11 are equal, the comparison signal S11 may be either a high-level signal or a low-level signal.

Here, assuming that the resistance value of the resistor 12 is r12 and the resistance value of the resistor 13 is r13, the following equation (1) is established if the divided voltage VDIV11 and the reference voltage VREF11 are equal.
VDIV11 = VREF11
MV x r13 / (r12 + r13) = VREF11
MV = VREF11 × (r12 + r13) / r13 ... (1)

The voltage monitoring circuit 11 is a circuit that monitors the magnitude relationship between the monitored voltage MV and the determination voltage (VREF11 × (r12 + r13) / r13) and outputs the monitoring result from the output terminal T12.

Then, in the voltage monitoring circuit 11, in order to suppress the influence of the variation of the reference voltage VREF 11 on the determination voltage, the resistors 12 and 13 are each made into a resistance element whose resistance value can be adjusted by trimming.

A circuit similar to the voltage monitoring circuit 11 is disclosed in, for example, Patent Document 1.

Japanese Unexamined Patent Publication No. 2003-75477 (paragraph 0002-0004)

Some users who use the voltage monitoring circuit desire a type of voltage monitoring circuit in which the judgment voltage can be arbitrarily set by the user.

The voltage monitoring circuit 11 shown in FIG. 21 described above cannot adjust the determination voltage after the trimming of the resistors 12 and 13 is completed. Therefore, the voltage monitoring circuit 11 is a type of voltage monitoring circuit in which the determination voltage can be arbitrarily set by the user. Not applicable.

As a type of voltage monitoring circuit in which the determination voltage can be arbitrarily set by the user, for example, the voltage monitoring circuit 21 shown in FIG. 22 can be mentioned.

The voltage monitoring circuit 21 is mounted on a one-chip semiconductor integrated circuit device. The voltage monitoring circuit 21 includes a reference voltage generation circuit 22, a comparator 23, an input terminal T21, and an output terminal T22.

The resistors R1 and R2 are externally connected to a one-chip semiconductor integrated circuit device on which the voltage monitoring circuit 21 is mounted. More specifically, the monitored voltage MV is applied to one end of the resistor R1, the other end of the resistor R1 and one end of the resistor R2 are connected to the input terminal T21, and the other end of the resistor R2 is connected to the ground potential.

The voltage divider circuit composed of resistors R1 and R2 converts the monitored voltage MV into the voltage divider VDIV1 and supplies the voltage divider VDIV1 to the input terminal T21. The input terminal T21 supplies the divided voltage VDIV1 to the non-inverting input terminal of the comparator 23.

The reference voltage generation circuit 22 generates a predetermined reference voltage VREF 21 and supplies the reference voltage VREF 21 to the inverting input terminal of the comparator 23.

The comparator 23 generates a comparison signal S21 indicating a comparison result between the divided voltage VDIV1 and the reference voltage VREF21, and outputs the comparison signal S21 to the outside of the voltage monitoring circuit 21 via the output terminal T22. When the voltage divider VDIV1 is larger than the reference voltage VREF21, the comparison signal S21 becomes a high level signal. On the other hand, when the divided voltage VDIV1 is smaller than the reference voltage VREF21, the comparison signal S21 becomes a low level signal. When the divided voltage VDIV1 and the reference voltage VREF21 are equal, the comparison signal S21 may be either a high-level signal or a low-level signal.

Here, assuming that the resistance value of the resistor R1 is r1 and the resistance value of the resistor R2 is r2, the following equation (2) is established if the voltage dividing VDIV1 and the reference voltage VREF21 are equal.
VDIV1 = VREF21
MV x r2 / (r1 + r2) = VREF21
MV = VREF21 × (r1 + r2) / r2 ... (2)

The voltage monitoring circuit 21 is a circuit that monitors the magnitude relationship between the monitored voltage MV and the determination voltage (VREF21 × (r1 + r2) / r2) and outputs the monitoring result from the output terminal T22.

Since the resistors R1 and R2 are so-called external resistors, the voltage monitoring circuit 21 can adjust the determination voltage by selecting the resistance value r1 of the resistor R1 and the resistance value r2 of R2. However, the voltage monitoring circuit 21 has a problem that it cannot suppress the influence of the variation of the reference voltage VREF 21 on the determination voltage.

Further, the voltage monitoring circuit 21 has a problem that hysteresis cannot be applied to the determination voltage.

In view of the above situation, the present invention is a voltage monitoring circuit that monitors the magnitude relationship between the monitored voltage and the determination voltage, can suppress the influence of the variation of the reference voltage on the determination voltage, and can arbitrarily set the determination voltage. It is an object of the present invention to provide a voltage monitoring circuit which can be set to.

For example, the voltage monitoring circuit disclosed in the present specification includes an input terminal to which a monitored voltage or a divided voltage of the monitored voltage is applied, a reference voltage generating circuit that generates a first reference voltage, and the first reference voltage generation circuit. 1 A linear power supply circuit that generates a second reference voltage corresponding to a reference voltage, and a feedback resistor that generates a divided voltage of the second reference voltage and negatively feeds back the divided voltage of the second reference voltage to the linear power supply circuit. The configuration includes a comparison unit for comparing the second reference voltage with the monitored voltage applied to the input terminal or the divided voltage of the monitored voltage.

Further, for example, the voltage monitoring circuit disclosed in the present specification includes a first input terminal to which a first input voltage is applied, a second input terminal to which a second input voltage is applied, and a first reference voltage. A reference voltage generation circuit that generates a reference voltage, a linear power supply circuit that generates a second reference voltage corresponding to the first reference voltage, and a plurality of divided voltages generated from the second reference voltage, and one of them is used as a feedback voltage. A feedback resistor that negatively feeds back to the linear power supply circuit, a first comparison unit that compares the first input voltage with the third reference voltage to generate a first comparison signal, and the second input voltage and the fourth reference voltage. The second comparison unit that generates a second comparison signal by comparing the two, and any two of the second reference voltage and the plurality of divided voltages are used as switching candidates for the third reference voltage, and the first comparison is performed. The first selection unit that switches the third reference voltage according to the signal, and any two of the second reference voltage and the plurality of divided voltages are used as switching candidates for the fourth reference voltage, and the second comparison is made. It is configured to include a second selection unit that switches the fourth reference voltage according to a signal.

Further, for example, the voltage monitoring circuit disclosed in the present specification includes an input terminal to which a monitored voltage or a divided voltage thereof is applied as an input voltage, a reference voltage generating circuit for generating a first reference voltage, and the above. A linear power supply circuit that generates a second reference voltage according to the first reference voltage, a feedback resistor that generates a divided voltage of the second reference voltage and negatively feeds back to the linear power supply circuit, the input voltage, and the second reference voltage. A comparison unit for comparing with a reference voltage is provided, and the voltage division ratio of the feedback resistance can be switched according to the output of the comparison unit.

Further, for example, the voltage monitoring circuit disclosed in the present specification includes a first input terminal to which a monitored voltage or a first divided voltage thereof is applied as a first input voltage, and the first input voltage as a second input voltage. A second input terminal to which a second divided voltage of the monitored voltage whose value is different from the input voltage is applied, a reference voltage generation circuit that generates a first reference voltage, and a second reference voltage corresponding to the first reference voltage. The first comparison comparing the first input voltage and the second reference voltage with the linear power supply circuit that generates the above, the feedback resistor that generates the divided voltage of the second reference voltage and negatively feeds back to the linear power supply circuit. A unit and a second comparison unit that compares the second input voltage with the second reference voltage are provided, and the voltage division ratio of the feedback resistance corresponds to the output of each of the first comparison unit and the second comparison unit. It is configured to be switchable.

The other features, elements, steps, advantages, and properties of the present invention will be further clarified by the detailed description of the embodiments that follow and the accompanying drawings.

According to the voltage monitoring circuit disclosed in the present specification, it is possible to suppress the influence of the variation of the reference voltage on the determination voltage and to arbitrarily set the determination voltage. Further, an appropriate hysteresis can be added to the determination voltage.

The figure which shows the structure of the voltage monitoring circuit which concerns on 1st Embodiment The figure which shows one configuration example of a reference voltage generation circuit The figure for demonstrating the modification of 1st Embodiment The figure for demonstrating another modification of 1st Embodiment The figure which shows the structure of the voltage monitoring circuit which concerns on 2nd Embodiment Top schematic of a one-chip semiconductor integrated circuit device equipped with the voltage monitoring circuit according to the second embodiment. The figure which shows the output behavior when hysteresis is not given to the judgment voltage. The figure which shows the structure of the voltage monitoring circuit which concerns on 3rd Embodiment The figure which shows the output behavior when hysteresis is applied to the judgment voltage. The figure which shows the structure of the voltage monitoring circuit which concerns on 4th Embodiment The figure which shows the normal operation of the power reduction detection and the overpower detection in the 4th embodiment. The figure for demonstrating the modification of 4th Embodiment The figure which shows a mode that false detection occurs in the modification of 4th Embodiment The figure which shows the structure of the voltage monitoring circuit which concerns on 5th Embodiment The figure for demonstrating the switching control of the 3rd reference voltage. The figure for demonstrating the switching control of the 4th reference voltage. The figure which shows the normal operation of the current reduction detection and the overpower detection in the fifth embodiment. The figure which shows the structure of the voltage monitoring circuit which concerns on 6th Embodiment The figure which shows the configuration example of the control device which includes a voltage monitoring circuit. External view of the vehicle equipped with the voltage monitoring circuit The figure which shows one configuration example of the conventional voltage monitoring circuit The figure which shows the other configuration example of the conventional voltage monitoring circuit The figure which shows the other structural example of the conventional voltage monitoring circuit.

<First Embodiment>
FIG. 1 is a diagram showing a configuration of a voltage monitoring circuit according to the first embodiment. The voltage monitoring circuit 1 shown in FIG. 1 is mounted on a one-chip semiconductor integrated circuit device. The voltage monitoring circuit 1 includes a reference voltage generation circuit 2, a linear power supply circuit 3, feedback resistors 4 and 5, a comparator 6, an input terminal T1, and an output terminal T2.

The resistors R1 and R2 are externally connected to a one-chip semiconductor integrated circuit device on which the voltage monitoring circuit 1 is mounted. More specifically, the monitored voltage MV is applied to one end of the resistor R1, the other end of the resistor R1 and one end of the resistor R2 are connected to the input terminal T1, and the other end of the resistor R2 is connected to the ground potential.

The voltage divider circuit composed of resistors R1 and R2 converts the monitored voltage MV into the voltage divider VDIV1 and supplies the voltage divider VDIV1 to the input terminal T1. The input terminal T1 supplies the divided voltage VDIV1 to the non-inverting input terminal of the comparator 6.

The reference voltage generation circuit 2 generates a predetermined first reference voltage VREF1 and supplies the first reference voltage VREF1 to the linear power supply circuit 3.

A configuration example of the reference voltage generation circuit 2 is shown in FIG. The reference voltage generation circuit 2 of the configuration example shown in FIG. 2 includes an N-channel type depletion type MOSFET (metal-oxide-semiconductor field-effect transistor) 2A and an N-channel type enhancement type MOSFET 2B. A power supply voltage VDD is applied to the drain of the depletion type MOSFET 2A, and the source of the enhancement type MOSFET 2B is connected to the ground potential. The source and gate of the depletion type MOSFET 2A and the drain and gate of the enhancement type MOSFET 2B are commonly connected, and the first reference voltage VREF1 is output from the common connection node.

The first reference voltage VREF1 is represented by the following equation (3). _{However, V thn} is the threshold voltage of the enhancement type _{MOSFET2B, W DEP} is the gate width of the depletion mode _{MOSFET2A, L DEP} is the gate length of the depletion mode MOSFET2A, _{W N} is the gate of the enhancement type MOSFET2B Width, where L _N is the gate length of the enhancement type MOSFET 2B.
VREF1 = V _thn −√ {(W _DEP × L _N ) / (W _N × L _DEP )}… (3)

The reference voltage generation circuit 2 is not limited to the configuration example shown in FIG. 2, and may be, for example, a general bandgap type reference voltage generation circuit. However, the reference voltage generation circuit 2 of the configuration example shown in FIG. 2 can have a significantly smaller circuit area than a general bandgap type reference voltage generation circuit.

Further, the reference voltage generation circuit 2 of the configuration example shown in FIG. 2 also has a feature that the temperature characteristics are good. The rate of change dVREF1 / dT of the first reference voltage VREF1 with respect to temperature in the reference voltage generation circuit 2 of the configuration example shown in FIG. 2 is represented by the following equation (4). However, V _thDEP is the threshold voltage of the depletion type MOSFET 2A, dV _thDEP / dT is the rate of change of the threshold voltage of the depletion type MOSFET 2A with respect to the temperature, and dV _thn / dT is the threshold of the enhancement type MOSFET 2B. The rate of change of the value voltage with respect to temperature.
dVREF1 / dT
= _{DV thn} / dT-dV _thDEP / dT × √ {(W _DEP × L _N ) / (W _N × L _DEP )}
… (4)

Since the rate of change _dV thn / dT for temperature change rate _{dV thDEP} / dT, the threshold voltage of the enhancement type MOSFET2B for temperature of the threshold voltage of the depletion type MOSFET2A have a both positive, depletion MOSFET2A gate width By _{adjusting the W DEP} , the gate length L _{DEP of} the depletion type MOSFET 2A, the gate width W _{N of} the enhancement type MOSFET 2B, and the gate length L _N of the enhancement type MOSFET 2B, the rate of change of the first reference voltage VREF1 with respect to the temperature dVREF1 / dT Can be made almost zero.

Returning to FIG. 1, the detailed description of the voltage monitoring circuit 1 will be continued. The linear power supply circuit 3 generates a second reference voltage VREF2 corresponding to the first reference voltage VREF1. The linear power supply circuit 3 adjusts the second reference voltage VREF2 so that the feedback voltage VFB1 approaches the first reference voltage VREF1. The details of the feedback voltage VFB1 will be described later.

As the linear power supply circuit 3, for example, an LDO [low drop out] can be used. When an LDO is used for the linear power supply circuit 3, the loss in the linear power supply circuit 3 can be reduced.

The feedback resistors 4 and 5 generate a feedback voltage VFB1 which is a divided voltage of the second reference voltage VREF2, and negatively feed the feedback voltage VFB1 to the linear power supply circuit 3.

The comparator 6 generates a comparison signal S1 indicating a comparison result between the divided voltage VDIV1 and the second reference voltage VREF2, and outputs the comparison signal S1 to the outside of the voltage monitoring circuit 1 via the output terminal T2. When the voltage divider VDIV1 is larger than the second reference voltage VREF2, the comparison signal S1 becomes a high level signal. On the other hand, when the divided voltage VDIV1 is smaller than the second reference voltage VREF2, the comparison signal S1 becomes a low level signal. When the divided voltage VDIV1 and the second reference voltage VREF2 are equal, the comparison signal S1 may be either a high level signal or a low level signal.

Here, assuming that the resistance value of the resistor R1 is r1, the resistance value of the resistor R2 is r2, the resistance value of the feedback resistor 4 is r4, and the resistance value of the feedback resistor 5 is r5, the voltage divider VDIV1 and the second reference voltage are used. If VREF2 is equal, the following equation (5) holds.
VDIV1 = VREF2
MV x r2 / (r1 + r2) = VREF1 x (r4 + r5) / r5
MV = VREF1 × (r1 + r2) × (r4 + r5) / (r2 × r5)… (5)

The voltage monitoring circuit 1 is a circuit that monitors the magnitude relationship between the monitored voltage MV and the determination voltage (VREF1 × (r1 + r2) × (r4 + r5) / (r2 × r5)) and outputs the monitoring result from the output terminal T2. .. Specifically, when the voltage monitoring circuit 1 detects a reduced voltage of the monitored voltage MV, it outputs a low-level signal from the output terminal T2.

Since the resistors R1 and R2 are so-called external resistors, the voltage monitoring circuit 1 can adjust the determination voltage by selecting the resistance value r1 of the resistor R1 and the resistance value r2 of R2. Further, in the voltage monitoring circuit 1, in order to suppress the influence of the variation of the first reference voltage VREF1 on the determination voltage, each of the feedback resistors 4 and 5 is used as a resistance element whose resistance value can be adjusted by trimming. .. Therefore, according to the voltage monitoring circuit 1, it is possible to suppress the variation of the first reference voltage REF1 from affecting the determination voltage, and the determination voltage can be arbitrarily set. From the viewpoint of reducing the area of the feedback resistors 4 and 5, it is preferable that the feedback resistors 4 and 5 are formed of polycrystalline silicon films, respectively.

Since the total area of the linear power supply circuit 3 and the feedback resistors 4 and 5 provided in the voltage monitoring circuit 1 can be made the same as the total area of the resistors 12 and 13 provided in the voltage monitoring circuit 11 shown in FIG. 21, the voltage monitoring circuit 1 The total area of is about the same as the total area of the voltage monitoring circuit 11 shown in FIG.

In the above description, the voltage divider VDIV1 of the monitoring target voltage MV is applied to the input terminal T1, but as shown in FIG. 3, the monitoring target voltage MV may be applied to the input terminal T1. In the state where the monitored voltage MV is applied to the input terminal T1, the voltage divider VDIV1 of the monitored voltage MV is applied to the input terminal T1 in the setting where the ratio of the resistance value r1 of the resistor R1 to the resistance value r2 of the resistor R2 is very small. It is almost the same as the applied state.

Further, in the above description, when the voltage monitoring circuit 1 detects the reduced voltage of the monitored voltage MV, it outputs a low level signal from the output terminal T2, but as shown in FIG. 4, the non-inverting input terminal of the comparator 6 By exchanging the and inverting input terminals, it is possible to change the specification to output a low-level signal from the output terminal T2 when an overvoltage of the monitoring target voltage MV is detected.

<Second Embodiment>
FIG. 5 is a diagram showing a configuration of a voltage monitoring circuit according to a second embodiment. The voltage monitoring circuit 1'shown in FIG. 5 is mounted on a one-chip semiconductor integrated circuit device. The voltage monitoring circuit 1'includes a reference voltage generation circuit 2, a linear power supply circuit 3, feedback resistors 4 and 5, comparators 6 and 7, input terminals T1 and T3, and output terminals T2 and T4. In FIG. 5, the same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The combined resistance of the resistor R2A and the resistor R2B in FIG. 5 corresponds to the resistor R2 in FIG.

When the voltage monitoring circuit 1'detects a reduced voltage of the monitored voltage MV, it outputs a low level signal from the output terminal T2, and when it detects an overvoltage of the monitored voltage MV, it outputs a low level signal from the output terminal T4. To do. Since the detection of the reduced voltage of the monitored voltage MV is the same as that of the first embodiment, the description thereof will be omitted. Hereinafter, detection of overvoltage of the monitored voltage MV will be described.

The voltage divider VDIV2 of the monitoring target voltage MV is applied to the input terminal T3. The voltage divider VDIV2 of the monitored voltage MV is smaller than the voltage divider VDIV1 of the monitored voltage MV. The input terminal T3 supplies the divided voltage VDIV2 to the inverting input terminal of the comparator 7.

The comparator 7 generates a comparison signal S2 indicating a comparison result between the divided voltage VDIV2 and the second reference voltage VREF2, and outputs the comparison signal S2 to the outside of the voltage monitoring circuit 1'via the output terminal T4. When the voltage divider VDIV2 is smaller than the second reference voltage VREF2, the comparison signal S2 becomes a high level signal. On the other hand, when the divided voltage VDIV2 is larger than the second reference voltage VREF2, the comparison signal S2 becomes a low level signal. When the divided voltage VDIV2 and the second reference voltage VREF2 are equal, the comparison signal S2 may be either a high level signal or a low level signal.

Here, the resistance value of the resistor R1 is r1, the resistance value of the combined resistance of the resistors R2A and R2B is r2, the resistance value of the resistor R2B is r2b, the resistance value of the feedback resistor 4 is r4, and the resistance of the feedback resistor 5 is set. Assuming that the value is r5, if the voltage dividing VDIV2 and the second reference voltage VREF2 are equal, the following equation (6) is established.
VDIV2 = VREF2
MV x r2b / (r1 + r2) = VREF1 x (r4 + r5) / r5
MV = VREF1 × (r1 + r2) × (r4 + r5) / (r2b × r5)… (6)

The voltage monitoring circuit 1'monitors the magnitude relationship between the monitored voltage MV and the determination voltage for overvoltage detection (VREF1 × (r1 + r2) × (r4 + r5) / (r2b × r5)), and monitors the monitoring result from the output terminal T4. It is a circuit to output. Specifically, when the voltage monitoring circuit 1'detects an overvoltage of the monitoring target voltage MV, the voltage monitoring circuit 1'outputs a low level signal from the output terminal T4.

Since the resistors R1, R2A, and R2B are so-called external resistors, in the voltage monitoring circuit 1', the resistance value r1 of the resistor R1, the resistance value r2 of the combined resistance of the resistors R2A and R2B, and the resistance value r2b of the resistor R2B are selected. Therefore, the determination voltage for overvoltage detection can be adjusted. Therefore, according to the voltage monitoring circuit 1', it is possible to suppress that the variation of the first reference voltage VREF1 affects the judgment voltage with respect to both the judgment voltage for voltage reduction detection and the judgment voltage for overvoltage detection, and the judgment voltage can be adjusted. Can be set arbitrarily.

Here, the conventional voltage monitoring circuit 11'shown in FIG. 23 will be described for comparison with the voltage monitoring circuit 1'. The conventional voltage monitoring circuit 11'shown in FIG. 23 has a configuration in which resistors 16 and 17, a comparator 18, an input terminal T13, and an output terminal T14 are added to the conventional voltage monitoring circuit 11 shown in FIG. ..

When the voltage monitoring circuit 11'detects a reduced voltage of the monitored voltage MV, it outputs a low level signal from the output terminal T12, and when it detects an overvoltage of the monitored voltage MV, it outputs a low level signal from the output terminal T14. To do. Since the detection of the reduced voltage of the monitored voltage MV is the same as that of the conventional voltage monitoring circuit 11 shown in FIG. 21, the description thereof will be omitted. Hereinafter, detection of overvoltage of the monitored voltage MV will be described.

The monitoring target voltage MV is applied to the input terminal T13. The voltage divider circuit composed of resistors 16 and 17 converts the monitored voltage MV into the voltage divider VDIV12 and supplies the voltage divider VDIV12 to the inverting input terminal of the comparator 18. The voltage divider circuit composed of the resistors 16 and 17 has the same configuration as the voltage divider circuit composed of the resistors 12 and 13, but the trimming implementation status is different from the voltage divider circuit composed of the resistors 12 and 13. ing. As a result, the partial pressure VDIV12 is smaller than the partial pressure VDIV11.

Here, assuming that the resistance value of the resistor 16 is r16 and the resistance value of the resistor 17 is r17, the following equation (7) is established if the divided voltage VDIV12 and the reference voltage VREF11 are equal.
VDIV12 = VREF11
MV x r16 / (r16 + r17) = VREF11
MV = VREF11 × (r16 + r17) / r17… (7)

The voltage monitoring circuit 11'is a circuit that monitors the magnitude relationship between the monitored voltage MV and the determination voltage for overvoltage detection (VREF11 × (r16 + r17) / r17) and outputs the monitoring result from the output terminal T14. Specifically, when the voltage monitoring circuit 11'detects an overvoltage of the monitoring target voltage MV, the voltage monitoring circuit 11'outputs a low level signal from the output terminal T14.

In the voltage monitoring circuit 11', for example, the area of the voltage dividing circuit composed of the resistors 12 and 13 is 30% of the total area of the voltage monitoring circuit 11', and the area of the voltage dividing circuit composed of the resistors 16 and 17 Is 30% of the total area of the voltage monitoring circuit 11', and the area other than the voltage dividing circuit is 40% of the total area of the voltage monitoring circuit 11', the total area of the voltage monitoring circuit 1'shown in FIG. The area is reduced by 30% with respect to the total area of the voltage monitor circuit 11'shown in FIG. That is, the second embodiment can also obtain an area reduction effect on the conventional voltage monitoring circuit, which was not obtained in the first embodiment.

FIG. 6 is a schematic top view of a one-chip semiconductor integrated circuit device equipped with a voltage monitoring circuit 1'. In FIG. 6, the same parts as those in FIG. 5 are designated by the same reference numerals.

The one-chip semiconductor integrated circuit device on which the voltage monitoring circuit 1'is mounted includes a rectangular chip 100. The chip 100 includes a first side 101, a second side 102, a third side 103, and a fourth side 104. The first side 101 and the third side 103 are sides facing each other, and the second side 102 and the fourth side 104 are sides facing each other.

The feedback resistors 4 and 5 are arranged so as to avoid the end portion of the chip 100. In other words, the feedback resistors 4 and 5 are arranged at the center of the chip 100 in order to prevent the value of the feedback voltage VFB1 adjusted by trimming from deviating from the design value due to stress. From the viewpoint of minimizing the stress applied to the feedback resistors 4 and 5, it is preferable that the rectangular center C1 of the chip 100 is included in the arrangement position of the feedback resistors 4 and 5 as shown in FIG.

In order to arrange the feedback resistors 4 and 5 in the central portion of the chip 100, in the arrangement example shown in FIG. 6, the comparators 6 and 7 and the output terminals T2 and T4 are located closer to the first side 101 than the feedback resistors 4 and 5. Is placed in.

In order to arrange the feedback resistors 4 and 5 in the central portion of the chip 100, in the arrangement example shown in FIG. 6, the input terminal T3 and the output terminal T4 are arranged at positions closer to the second side 102 than the feedback resistors 4 and 5. To.

In order to arrange the feedback resistors 4 and 5 in the center of the chip 100, in the arrangement example shown in FIG. 6, the reference voltage generation circuit 2, the linear power supply circuit 3, and the input terminals T1 and T3 are more than the feedback resistors 4 and 5. It is arranged at a position close to the third side 103.

In order to arrange the feedback resistors 4 and 5 in the central portion of the chip 100, in the arrangement example shown in FIG. 6, the input terminal T1 and the output terminal T2 are arranged at positions closer to the fourth side 104 than the feedback resistors 4 and 5. To.

Further, in the arrangement example shown in FIG. 6, the reference voltage generation circuit 2 and the linear power supply circuit 3 are arranged at positions closer to the feedback resistors 4 and 5 than the input terminals T1 and T3. As a result, the wiring in the circuit block composed of the reference voltage generation circuit 2, the linear power supply circuit 3, and the feedback resistors 4 and 5 can be shortened.

Further, in the arrangement example shown in FIG. 6, the reference voltage generation circuit 2 and the linear power supply circuit are located between the input terminals T1 and T3 and the output terminals T2 and T4 in the direction parallel to the second side 102 and the fourth side 104. 3, feedback resistors 4 and 5, and comparators 6 and 7 are arranged. As a result, the wiring between the input terminals T1 and T3 and the circuit block composed of the reference voltage generation circuit 2, the linear power supply circuit 3, the feedback resistors 4 and 5, and the comparators 6 and 7 can be shortened, and the reference voltage generation circuit can be shortened. 2. The wiring between the output terminals T2 and T4 and the circuit block composed of the linear power supply circuit 3, the feedback resistors 4 and 5, and the comparators 6 and 7 can be shortened.

Further, in the arrangement example shown in FIG. 6, the reference voltage generation circuit 2, the linear power supply circuit 3, the feedback resistors 4 and 5, and the output terminals T2 and T4 are arranged in the direction parallel to the second side 102 and the fourth side 104. Comparators 6 and 7 are arranged between them. As a result, the output end of the comparator 6 and the output terminal T2 can be arranged close to each other, and the output end of the comparator 7 and the output terminal T4 can be arranged close to each other. Therefore, the output end and the output terminal of the comparator 6 can be arranged close to each other. The wiring between the T2 and the output end of the comparator 7 and the output terminal T4 can be shortened.

<Consideration on hysteresis>
FIG. 7 is a diagram showing output behavior when hysteresis is not applied to the determination voltage. The voltage to be monitored MV is depicted in the upper part of this figure, and the output signal OUT of the voltage monitoring circuit 1 (corresponding to the comparison signal S1 mentioned above) is depicted in the lower part of this figure.

As shown in this figure, when hysteresis is not applied to the determination voltage Vth (for example, Vth = {(r1 + r2) / r2} · {(r4 + r5) / r5} · VREF1 in accordance with FIG. 1). If the monitored voltage MV fluctuates in the vicinity of the determination voltage Vth, chattering occurs in the output signal OUT, which may interfere with the operation (for example, reset operation) of the subsequent circuit that accepts the input of the output signal OUT.

In the following, various embodiments capable of eliminating chattering of the output signal OUT will be proposed.

<Third Embodiment>
FIG. 8 is a diagram showing a configuration of a voltage monitoring circuit according to a third embodiment. The voltage monitoring circuit 1a according to the present embodiment is based on the first embodiment (FIG. 1) described above, and has a feedback resistor 8 and an NMOSFET 9 as means for eliminating chattering of the comparison signal S1. It further has an inverter 10.

The feedback resistor 8 is connected between the feedback resistor 5 and the reference potential end (GND).

The NMOSFET 9 is connected in parallel to the feedback resistor 8. More specifically, the drain of the NMOSFET 9 is connected to the connection node between the feedback resistors 5 and 8. The source of the NMOSFET 9 is connected to the reference potential end (GND). The gate of the NMOSFET 9 is connected to the output end of the inverter 10 (= the application end of the inversion comparison signal S1B). The NMOSFET 9 is turned on when the inverting comparison signal S1B is at a high level and turned off when the inverting comparison signal S1B is at a low level.

The inverter 10 inverts the logic level of the comparison signal S1 to generate an inverted comparison signal S1B. That is, the inverting comparison signal S1B becomes low level when the comparison signal S1 is high level, and becomes high level when the comparison signal S1 is low level.

First, consider the case where the comparison signal S1 is at a high level (= the case where the reduced voltage is not detected). In this case, since S1B = L, the NMOSFET 9 is turned off. As a result, the feedback resistor 8 is incorporated in the resistor ladder that divides the second reference voltage VREF2 to generate the feedback voltage VFB1. Therefore, assuming that the resistance value of the feedback resistor 8 is r8, the second reference voltage VREF2 is VREF2 = {(r4 + r5 + r8) / (r5 + r8)} · VREF1. At this time, the determination voltage Vth (= lower determination voltage VthL for voltage reduction detection) of the voltage monitoring circuit 1a is VthL = {(r1 + r2) / r2} · {(r4 + r5 + r8) / (r5 + r8)} · VREF1. Become.

Next, consider the case where the comparison signal S1 is at a low level (= when a reduced voltage is detected). In this case, since S1B = H, the NMOSFET 9 is turned on. As a result, the feedback resistor 8 is separated from the resistance ladder. Therefore, the second reference voltage VREF2 is VREF2 = {(r4 + r5) / r5} · VREF1. At this time, the determination voltage Vth (= upper determination voltage VthH for releasing the reduced voltage) of the voltage monitoring circuit 1a is VthH = {(r1 + r2) / r2} · {(r4 + r5) / r5} · VREF1.

In this way, the determination voltage Vth of the voltage monitoring circuit 1a is switched to either the lower determination voltage VthL or the upper determination voltage VthH (however, VthL <VthH) according to the logic level of the comparison signal S1. That is, hysteresis Vhys (= VthH−VthL) is applied to the determination voltage Vth of the voltage monitoring circuit 1a.

FIG. 9 is a diagram showing output behavior when hysteresis is applied to the determination voltage. The monitoring target voltage MV (solid line) and the determination voltage Vth (broken line) are depicted in the upper part of this figure, and the output signal OUT of the voltage monitoring circuit 1a (the previous comparison signal S1 corresponds to this) in the lower part of this figure. ) Is depicted.

Before time t1, the output signal OUT is at a high level (= logical level when no voltage reduction is detected). At this time, the determination voltage Vth is the lower determination voltage VthL.

At time t1, when the monitoring target voltage MV falls below the lower determination voltage VthL, the output signal OUT switches from the high level to the low level (= logical level at the time of low voltage detection). At this time, the determination voltage Vth is switched from the lower determination voltage VthL to the upper determination voltage VthH. Therefore, as shown in this figure, even if the monitored voltage MV fluctuates near the lower determination voltage VthL after time t1, there is no possibility that chattering will occur in the output signal OUT (the thin broken line frame of the output signal OUT). reference).

On the other hand, at time t2, when the monitoring target voltage MV exceeds the upper determination voltage VthH, the output signal OUT switches from the low level to the high level. At this time, the determination voltage Vth is switched from the upper determination voltage VthH to the lower determination voltage VthL. Therefore, although not explicitly shown in this figure, even if the monitored voltage MV fluctuates near the upper determination voltage VthH after time t2, there is no possibility that chattering will occur in the output signal OUT.

As described above, in the voltage monitoring circuit 1a according to the present embodiment, the voltage division ratio of the feedback resistor (resistor ladder) that divides the second reference voltage VREF2 to generate the feedback voltage VFB1 is switched according to the comparison signal S1. .. As a result, arbitrary hysteresis Vhys can be applied to the determination voltage Vth of the voltage monitoring circuit 1a, so that chattering of the output signal OUT (= comparison signal S1) can be eliminated.

Although not shown again, hysteresis is added to the determination voltage of the voltage monitoring circuit 1 by adopting the same configuration as that of the present embodiment based on the modification shown in FIGS. 3 and 4 above. It doesn't matter.

<Fourth Embodiment>
FIG. 10 is a diagram showing a configuration of a voltage monitoring circuit according to a fourth embodiment. The voltage monitoring circuit 1b according to the present embodiment is based on the second embodiment (FIG. 5) described above, and has feedback resistors 8a and 8b as means for eliminating chattering of the comparison signals S1 and S2. , NMOSFETs 9a and 9b, and an inverter 10.

The feedback resistors 8a and 8b are connected in series with each other so as to be inserted between the feedback resistor 5 and the reference potential end (GND).

The NMOSFET 9a is connected in parallel to the feedback resistors 8a and 8b. Specifically, the drain of the NMOSFET 9a is connected to the connection node between the feedback resistors 5 and 8a. The source of the NMOSFET 9a is connected to the reference potential end (GND). The gate of the NMOSFET 9a is connected to the output end of the inverter 10 (= the application end of the inversion comparison signal S1B). The NMOSFET 9a is turned on when the inverting comparison signal S1B is at a high level and turned off when the inverting comparison signal S1B is at a low level.

The NMOSFET 9b is connected in parallel to the feedback resistor 8b. Specifically, the drain of the NMOSFET 9b is connected to the connection node between the feedback resistors 8a and 8b. The source of the NMOSFET 9b is connected to the reference potential end (GND). The gate of the NMOSFET 9b is connected to the output end of the comparator 7 (= the application end of the comparison signal S2). The NMOSFET 9a is turned on when the comparison signal S2 is at a high level and turned off when the comparison signal S2 is at a low level.

The inverter 10 inverts the logic level of the comparison signal S1 to generate an inverted comparison signal S1B. That is, the inverting comparison signal S1B becomes low level when the comparison signal S1 is high level, and becomes high level when the comparison signal S1 is low level.

First, consider the case where both the comparison signals S1 and S2 are at a high level (= no reduced voltage or overvoltage is detected). In this case, since S1B = L and S2 = H, the NMOSFET 9a is turned off and the NMOSFET 9b is turned on. As a result, only the feedback resistor 8a among the feedback resistors 8a and 8b is incorporated in the resistor ladder that divides the second reference voltage VREF2 to generate the feedback voltage VFB1. Therefore, assuming that the resistance value of the feedback resistor 8a is r8a, the second reference voltage VREF2 becomes the intermediate value VREF2M (= {(r4 + r5 + r8a) / (r5 + r8a)} · VREF1).

Next, consider the case where the comparison signal S1 is at a low level and the comparison signal S2 is at a high level (= when a reduced voltage is detected). In this case, since S1B = S2 = H, both NMOSFETs 9a and 9b are turned on. As a result, both the feedback resistors 8a and 8b are separated from the resistance ladder. Therefore, the second reference voltage VREF2 has an upper value VREF2H (= {(r4 + r5) / r5} · VREF1).

Next, consider the case where the comparison signal S1 is at a high level and the comparison signal S2 is at a low level (= when an overvoltage is detected). In this case, since S1B = S2 = L, both NMOSFETs 9a and 9b are turned off. As a result, both the feedback resistors 8a and 8b are incorporated into the resistance ladder. Therefore, assuming that the resistance values of the feedback resistors 8a and 8b are r8a and r8b, respectively, the second reference voltage VREF2 becomes the lower value VREF2L (= {(r4 + r5 + r8a + r8b) / (r5 + r8a + r8b)} · VREF1).

As described above, the second reference voltage VREF2 is any one of the lower value VREF2L, the intermediate value VREF2M, and the upper value VREF2H (however, VREF2L <VREF2M <VREF2H) according to the logic level of each of the comparison signals S1 and S2. Switch to. In other words, the second reference voltage VREF2 is provided with hysteresis Vhys1 (= VREF2H-VREF2M) for low voltage detection / cancellation and hysteresis Vhys2 (= VREF2M-VREF2L) for overvoltage detection / cancellation, respectively.

FIG. 11 is a diagram showing normal operation of power reduction detection and overpower detection in the fourth embodiment. In the upper part of this figure, the divided voltage VDIV1 (solid line) and the divided voltage VDIV2 (small broken line) of the monitored voltage MV, and the second reference voltage VREF2 (large broken line) are drawn. On the other hand, the comparison signals S1 and S2 are depicted in the lower part of this figure.

Before time t11, neither voltage reduction nor overvoltage occurred in the monitored voltage MV, and the comparison signals S1 and S2 were both at high levels. At this time, the second reference voltage VREF2 becomes the intermediate value VREF2M. In such a steady state, VDIV2 <VREF2M <VDIV1 is established as shown in this figure.

At time t11, when the monitored voltage MV is in the reduced voltage state and the divided voltage VDIV1 falls below the second reference voltage VREF2 (= VREF2M), the comparison signal S1 changes from high level to low level (= logical level at the time of voltage reduction detection). Switch to. At this time, the second reference voltage VREF2 switches from the intermediate value VREF2M to the upper value VREF2H. Therefore, even if the partial pressure VDIV1 fluctuates near the intermediate value VREF2M, there is no possibility that chattering will occur in the comparison signal S1. When the monitored voltage MV becomes a reduced voltage state, the divided voltage VDIV2 also decreases. However, since the divided voltage VDIV2 is lower than the second reference voltage VREF2 from before time t11, the comparison signal S2 remains maintained at a high level.

At time t12, when the monitored voltage MV recovers from the reduced voltage state and the divided voltage VDIV1 exceeds the second reference voltage VREF2 (= VREF2H), the comparison signal S1 switches from the low level to the high level. At this time, the second reference voltage VREF2 switches from the upper value VREF2H to the intermediate value VREF2M. Therefore, even if the partial pressure VDIV1 fluctuates near the upper value VREF2H, there is no possibility that chattering will occur in the comparison signal S1. When the monitored voltage MV recovers from the reduced voltage state, the divided voltage VDIV2 also rises. However, the comparison signal S2 remains at a high level unless the voltage divider VDIV2 exceeds the second reference voltage VREF2 (= VREF2M).

At time t13, when the monitored voltage MV becomes an overvoltage state and the divided voltage VDIV2 exceeds the second reference voltage VREF2 (= VREF2M), the comparison signal S2 switches from a high level to a low level (= logical level at the time of overvoltage detection). .. At this time, the second reference voltage VREF2 switches from the intermediate value VREF2M to the lower value VREF2L. Therefore, even if the partial pressure VDIV2 fluctuates near the intermediate value VREF2M, there is no possibility that chattering will occur in the comparison signal S2. When the monitored voltage MV becomes an overvoltage state, the partial pressure VDIV1 also rises. However, since the divided voltage VDIV1 is higher than the second reference voltage VREF2 from before time t13, the comparison signal S1 remains maintained at a high level.

At time t14, when the monitored voltage MV recovers from the overvoltage state and the divided voltage VDIV2 falls below the second reference voltage VREF2 (= VREF2L), the comparison signal S2 switches from the low level to the high level. At this time, the second reference voltage VREF2 switches from the lower value VREF2L to the intermediate value VREF2M. Therefore, even if the partial pressure VDIV2 fluctuates near the lower value VREF2L, there is no possibility that chattering will occur in the comparison signal S2. When the monitored voltage MV recovers from the overvoltage state, the partial pressure VDIV1 also decreases. However, the comparison signal S1 remains maintained at a high level unless the voltage divider VDIV1 falls below the second reference voltage VREF2 (= VREF2M).

As described above, in the voltage monitoring circuit 1b according to the present embodiment, the voltage division ratio of the feedback resistor (resistor ladder) that divides the second reference voltage VREF2 to generate the feedback voltage VFB1 corresponds to the comparison signals S1 and S2. Can be switched. As a result, since arbitrary hysteresis can be applied to the second reference voltage VREF2 (by extension, the determination voltage of the voltage monitoring circuit 1b), chattering of the comparison signals S1 and S2 can be eliminated.

<Problems of the Fourth Embodiment>
FIG. 12 is a diagram for explaining a modified example of the fourth embodiment. In this figure, independent sense voltages SENSE1 and SENSE2 are individually input to the input terminals T1 and T3 instead of the divided voltages VDIV1 and VDIV2 of the monitored voltage MV. That is, in the voltage monitoring circuit 1b of this modification, the devoltage detection process of the sense voltage SENSE1 and the overvoltage detection process of the sense voltage SENSE2 are performed.

The voltage dividers VDIV1 and VDIV2 mentioned above are both voltage dividers of the monitored voltage MV. Therefore, when the monitored voltage MV rises, both the divided voltages VDIV1 and VDIV2 rise, and conversely, when the monitored voltage MV decreases, both the divided voltages VDIV1 and VDIV2 decrease.

On the other hand, the sense voltages SENSE1 and SENSE2 correspond to the monitored voltages independent of each other. Therefore, when one of the sense voltages SENSE1 and SENSE2 is decreasing, the other may increase.

In this way, when the individual inputs of the sense voltages SENSE1 and SENSE2 are accepted, the voltage monitoring circuit 1b according to the fourth embodiment may cause erroneous detection of the comparison signals S1 and S2. Hereinafter, a detailed description will be given with reference to the drawings.

FIG. 13 is a diagram showing how erroneous detection of the comparison signals S1 and S2 occurs in the modified example (FIG. 12) of the fourth embodiment. The sense voltage SENSE1 (solid line), the sense voltage SENSE2 (small dashed line), and the second reference voltage VREF2 (large dashed line) are depicted in the upper part of this figure. On the other hand, the comparison signals S1 and S2 are depicted in the lower part of this figure.

Before time t21, neither the reduced voltage of the sense voltage SENSE1 nor the overvoltage of the sense voltage SENSE2 was detected, and the comparison signals S1 and S2 are both at high levels. At this time, the second reference voltage VREF2 becomes the intermediate value VREF2M. In such a steady state, SENSE2 <VREF2M <SENSE1 is established as shown in this figure.

At time t21, when the sense voltage SENSE1 goes into a reduced voltage state and the sense voltage SENSE1 falls below the second reference voltage VREF2 (= VREF2M), the comparison signal S1 changes from a high level to a low level (= logical level at the time of voltage reduction detection). Switch. At this time, the second reference voltage VREF2 switches from the intermediate value VREF2M to the upper value VREF2H. Therefore, even if the sense voltage SENSE1 fluctuates near the intermediate value VREF2M, there is no possibility that chattering will occur in the comparison signal S1. However, in a state where the second reference voltage VREF2 is raised from the median value VREF2M to the upper value VREF2H, there is a possibility that the overvoltage detection of the sense voltage SENSE2 may be hindered.

More specifically in line with this figure, the sense voltage SENSE2 rises regardless of the depletion of the sense voltage SENSE1 and exceeds the median value VREF2M at time t22. Originally, the comparison signal S2 should be switched from the high level to the low level at this point, but since the second reference voltage VREF2 has been raised to the upper value VREF2H, the comparison signal S2 does not switch to the low level. It is maintained at a high level (see the dashed line behavior of the comparison signal S2).

In this figure, an example is given in which the overvoltage detection of the sense voltage SENSE2 is hindered by giving the hysteresis of the second reference voltage VREF2 (VREF2M → VREF2H) when the reduced voltage of the sense voltage SENSE1 is detected. In addition, the addition of hysteresis of the second reference voltage VREF2 (VREF2M → VREF2L) in the overvoltage detection of the sense voltage SENSE2 may interfere with the voltage reduction detection of the sense voltage SENSE1.

Hereinafter, a fifth embodiment will be proposed in which the comparison signals S1 and S2 are not erroneously detected even when the individual inputs of the sense voltages SENSE1 and SENSE2 are accepted.

<Fifth Embodiment>
FIG. 14 is a diagram showing a configuration of a voltage monitoring circuit according to a fifth embodiment. The voltage monitoring circuit 1c according to the present embodiment is based on the second embodiment (FIG. 5) described above, and has feedback resistors 8c and 8d as means for eliminating chattering of the comparison signals S1 and S2. , Inverters 10a and 10b, and switches SW1 to SW4.

The feedback resistors 8c and 8d are connected in series with each other so as to be inserted between the feedback resistor 4 and the application end of the second reference voltage VREF2.

A plurality of voltage dividers (VREF2a, VREF2b, VFB1) are generated from the second reference voltage VREF2 by the resistance ladder composed of the feedback resistors 4, 5, 8c and 8d, and one of them is used as the feedback voltage VFB1 in the linear power supply circuit 3. Negative feedback. Further, a relationship of VFB1 <VREF2b <VREF2a <VREF2 is established between each of the above voltages.

The inverter 10a inverts the logic level of the comparison signal S1 to generate an inverted comparison signal S1B. That is, the inverting comparison signal S1B becomes low level when the comparison signal S1 is high level, and becomes high level when the comparison signal S1 is low level.

The inverter 10b inverts the logic level of the comparison signal S2 to generate an inverted comparison signal S2B. That is, the inversion comparison signal S2B becomes low level when the comparison signal S2 is high level, and becomes high level when the comparison signal S2 is low level.

The switch SW1 is connected between the output end of the linear power supply circuit 3 (= the application end of the second reference voltage VREF2) and the inverting input end of the comparator 6 (= the application end of the third reference voltage VREF3). The switch SW1 is turned on when S1B = H (S1 = L) and turned off when S1B = L (S1 = H).

The switch SW2 is connected between the connection node between the feedback resistors 8c and 8d (= application end of the divided voltage VREF2a) and the inverting input end of the comparator 6 (= application end of the third reference voltage VREF3). The switch SW2 is turned on when S1 = H and turned off when S1 = L.

The switch SW3 is connected between the connection node between the feedback resistors 8c and 8d (= application end of the divided voltage VREF2a) and the non-inverting input end of the comparator 7 (= application end of the fourth reference voltage VREF4). .. The switch SW3 is turned on when S2 = H and turned off when S2 = L.

The switch SW4 is connected between the feedback resistor 8d and the connection node between the four (= application end of the divided voltage VREF2b) and the non-inverting input end of the comparator 7 (= application end of the fourth reference voltage VREF4). .. The switch SW4 is turned on when S2B = H (S2 = L) and turned off when S2B = L (S2 = H).

The comparator 6 has an input voltage V1 (= divided voltage VDIV1 or sense voltage SENSE1) input to the non-inverting input end (+) and a third reference voltage VREF3 (= second reference) input to the inverting input terminal (-). The comparison signal S1 is generated by comparing with the voltage VREF2 or the divided voltage VREF2a). The comparison signal S1 has a high level when V1> VREF3 and a low level when V1 <VREF3.

The comparator 7 has an input voltage V2 (= voltage divider VDIV2 or sense voltage SENSE2) input to the inverting input terminal (-) and a fourth reference voltage VREF4 (= voltage divider VREF2a) input to the non-inverting input terminal (+). Alternatively, the comparison signal S2 is generated by comparing with the divided voltage VREF2b). The comparison signal S2 has a low level when V2> VREF4 and a high level when V2 <VREF4.

FIG. 15 is a diagram for explaining switching control of the third reference voltage VREF3 by the switches SW1 and SW2.

When the comparison signal S1 is at a low level, the switch SW1 is turned on and the switch SW2 is turned off. In this case, the second reference voltage VREF2 is selected as the third reference voltage VREF3.

On the other hand, when the comparison signal S1 is at a high level, the switch SW1 is turned off and the switch SW2 is turned on. In this case, the partial pressure VREF2a is selected as the third reference voltage VREF3.

As described above, the switches SW1 and SW2 function as a first selection unit for switching the third reference voltage VREF3 according to the comparison signal S1 by using the second reference voltage VREF2 and its divided voltage VREF2a as switching candidates for the third reference voltage VREF3. To do.

The switching candidate for the third reference voltage VREF3 is not limited to the above, and any two of the second reference voltage VREF2 and a plurality of divided voltages can be arbitrarily selected so that the required hysteresis is attached. Just do it.

FIG. 16 is a diagram for explaining switching control of the fourth reference voltage VREF4 by the switches SW3 and SW4.

When the comparison signal S2 is at a low level, the switch SW3 is turned off and the switch SW4 is turned on. In this case, the partial pressure VREF2b is selected as the fourth reference voltage VREF4.

On the other hand, when the comparison signal S2 is at a high level, the switch SW3 is turned on and the switch SW4 is turned off. In this case, the partial pressure VREF2a is selected as the fourth reference voltage VREF4.

As described above, the switches SW3 and SW4 function as a second selection unit that switches the fourth reference voltage VREF4 according to the comparison signal S2 by using the divided voltages VREF2a and VREF2b as switching candidates of the fourth reference voltage VREF4.

The switching candidate for the fourth reference voltage VREF4 is not limited to the above, and any two of the second reference voltage VREF2 and a plurality of divided voltages can be arbitrarily selected so as to have the required hysteresis. Just do it.

FIG. 17 is a diagram showing normal operation of power reduction detection and overpower detection in the fifth embodiment, in order from the top, the sense voltage SENSE1 (solid line), the third reference voltage VREF3 (broken line), and the comparison signal S1. The sense voltage SENSE2 (solid line), the fourth reference voltage VREF4 (dashed line), and the comparison signal S2 are depicted.

Before time t31, neither the reduced voltage of the sense voltage SENSE1 nor the overvoltage of the sense voltage SENSE2 was detected, and the comparison signals S1 and S2 are both at high levels. Therefore, VREF3 = VREF4 = VREF2a. In such a steady state, SENSE2 <VREF3 = VREF4 <SENSE1 is established as shown in this figure.

At time t31, when the sense voltage SENSE1 is in the reduced voltage state and SENSE1 <VREF3 (= VREF2a), the comparison signal S1 is switched from the high level to the low level (= the logical level at the time of detecting the reduced voltage). At this time, the third reference voltage VREF3 is switched from the divided voltage VREF2a to the second reference voltage VREF2. Therefore, even if the sense voltage SENSE1 fluctuates in the vicinity of the divided voltage VREF2a, there is no possibility that chattering will occur in the comparison signal S1. On the other hand, the fourth reference voltage VREF4 remains maintained at the divided voltage VREF2a as long as the comparison signal S2 is at a high level. Therefore, there is no problem in detecting the overvoltage of the sense voltage SENSE2.

At time t32, when the sense voltage SENSE2 becomes an overvoltage state and SENSE2> VREF4 (= VREF2a), the comparison signal S2 switches from a high level to a low level (= logical level at the time of overvoltage detection). At this time, the fourth reference voltage VREF4 is switched from the partial pressure VREF2a to the partial pressure VREF2b. Therefore, even if the sense voltage SENSE2 fluctuates in the vicinity of the divided voltage VREF2a, there is no possibility that chattering will occur in the comparison signal S2. On the other hand, the third reference voltage VREF3 remains maintained at the second reference voltage VREF2 as long as the comparison signal S1 is at a low level. Therefore, there is no problem in recovering the reduced voltage of the sense voltage SENSE1.

At time t33, when the sense voltage SENSE1 recovers from the reduced voltage state and SENSE1> VREF3 (= VREF2), the comparison signal S1 switches from the low level to the high level. At this time, the third reference voltage VREF3 is switched from the second reference voltage VREF2 to the partial pressure VREF2a. Therefore, even if the sense voltage SENSE1 fluctuates near the second reference voltage VREF2, there is no possibility that chattering will occur in the comparison signal S1. On the other hand, the fourth reference voltage VREF4 remains maintained at the divided voltage VREF2b as long as the comparison signal S2 is at a low level. Therefore, there is no problem in recovering the overvoltage of the sense voltage SENSE2.

At time t34, when the sense voltage SENSE2 recovers from the overvoltage state and SENSE2 <VREF4 (= VREF2b), the comparison signal S2 switches from the low level to the high level. At this time, the fourth reference voltage VREF4 is switched from the partial pressure VREF2b to the partial pressure VREF2a. Therefore, even if the sense voltage SENSE2 fluctuates in the vicinity of the divided voltage VREF2b, there is no possibility that chattering will occur in the comparison signal S2. On the other hand, the third reference voltage VREF3 remains maintained at the divided voltage VREF2a as long as the comparison signal S1 is at a high level. Therefore, there is no problem in detecting the reduced voltage of the sense voltage SENSE1.

As described above, in the voltage monitoring circuit 1c according to the present embodiment, the third reference voltage VREF3 for voltage reduction monitoring and the fourth reference voltage VREF4 for overvoltage monitoring are independent of each other and are optional. Hysteresis is given. Therefore, even when the individual inputs of the sense voltages SENSE1 and SENSE2 are accepted, there is no possibility that the comparison signals S1 and S2 are erroneously detected.

In this figure, the case where the individual inputs of the sense voltages SENSE1 and SENSE2 are accepted is illustrated, but even when the inputs of the divided voltages VDIV1 and VDIV2 corresponding to the monitored voltage MV are accepted, the comparison signals S1 and S2 are erroneously detected. Needless to say, there is no risk of causing.

<Sixth Embodiment>
FIG. 18 is a diagram showing a configuration of a voltage monitoring circuit according to a sixth embodiment. The voltage monitoring circuit 1d according to the present embodiment is based on the fifth embodiment (FIG. 14) described above, and is for canceling the negative temperature characteristics of the reference voltage generation circuit 2 and the linear power supply circuit 3. Ingenuity is elaborate.

According to this figure, of the feedback resistors 4, 8c and 8d (= corresponding to the first feedback resistor) connected in series between the application end of the second reference voltage VREF2 and the application end of the feedback voltage VFB1. , The feedback resistors 4 provided on the lower potential side of any of the connection nodes of the switches SW1 to SW4 (= corresponding to the selection nodes of the first selection unit and the second selection unit) are the feedback resistors 8c and 8d excluding this. In addition, it has a temperature characteristic different in inclination from the feedback resistor 5 (= corresponding to the second feedback resistor) connected between the application end of the feedback voltage VFB1 and the reference potential end (GND).

More specifically, only the feedback resistor 4 is a first resistance element having a positive temperature characteristic (for example, a diffusion resistor (P-well resistor)), and the other feedback resistors 5, 8c and 8d are any of them. Is also a second resistance element (for example, a poly resistance) having a negative temperature characteristic.

Assuming that the combined resistance value of the feedback resistors 4, 8c and 8d is R11 and the resistance value of the feedback resistor 5 is R12, the second reference voltage VREF2 is expressed by the formula VREF2 = VREF1 × {(R11 / R12) +1}. To.

Here, the first reference voltage VREF1 has a negative temperature characteristic. Therefore, the feedback resistor 4 having a positive temperature characteristic and the feedback resistors 5, 8c and 8d having a negative temperature characteristic are used in combination, and the temperature characteristic of the resistance ratio (R11 / R12) is appropriately adjusted to be a reference. It is possible to cancel the negative temperature characteristics of the voltage generation circuit 2 and the linear power supply circuit 3 and bring the temperature characteristics of the second reference voltage VREF2 closer to flat.

<Use>
The voltage monitoring circuits 1 and 1'and the voltage monitoring circuits 1a to 1d described above can be suitably used as, for example, a reset circuit. For example, the control device shown in FIG. 19 includes a control circuit CNT1 that controls a controlled object and a voltage monitoring circuit 1'that resets the control circuit CNT1 based on the monitored voltage. The output terminals T2 and T4 of the voltage monitoring circuit 1'are connected to the reset terminal T5 of the control circuit CNT1. One end of the resistor R3 is connected to the reset terminal T5 of the control circuit CNT1, and the other end of the resistor R3 is connected to the power supply terminal T6 of the control circuit CNT1. Then, the power supply voltage VDD is applied to the power supply terminal T6. When the voltage monitoring circuit 1'detects that the monitored voltage MV is a reduced voltage or an overvoltage, it outputs a low level signal (reset signal) to the reset terminal T5 of the control circuit CNT1. The control circuit CNT1 maintains a reset state while a low-level signal (reset signal) is supplied to the reset terminal T5. As the control circuit CNT1, for example, an embedded computing module, a DSP (digital signal processor), a microcontroller, a microprocessor, an FPGA (field-programmable gate array), an ASIC (application specific integrated circuit), or the like can be used.

Further, the voltage monitoring circuits 1 and 1'and the voltage monitoring circuits 1a to 1d described above are preferably mounted on the vehicle X10 shown in FIG. 20, for example, as a circuit for monitoring any of the voltages of the electric system of the vehicle X10. Can be used.

<Summary>
Hereinafter, various embodiments disclosed herein will be described in a comprehensive manner.

For example, the voltage monitoring circuit disclosed in the present specification includes an input terminal to which a monitored voltage or a divided voltage of the monitored voltage is applied, a reference voltage generating circuit that generates a first reference voltage, and the first reference voltage generation circuit. 1 A linear power supply circuit that generates a second reference voltage corresponding to a reference voltage, and a feedback resistor that generates a divided voltage of the second reference voltage and negatively feeds back the divided voltage of the second reference voltage to the linear power supply circuit. A configuration (first configuration) including a comparison unit for comparing the second reference voltage with the monitored voltage applied to the input terminal or the divided voltage of the monitored voltage.

In the voltage monitoring circuit having the first configuration, the input terminal is the first input terminal, the comparison unit is the first comparison unit, and the monitoring target voltage applied to the first input terminal or the monitoring target. Compare the second input terminal to which the divided voltage of the monitored voltage whose value is different from the divided voltage of the voltage is applied, and the divided voltage of the second reference voltage and the monitored voltage applied to the second input terminal. A configuration (second configuration) may be provided in which the second comparison unit is provided.

In the voltage monitoring circuit having the first or second configuration, the reference voltage generation circuit may have a configuration (third configuration) including a depletion type field effect transistor and an enhancement type field effect transistor.

In the voltage monitoring circuit having any of the first to third configurations, the feedback resistor may be configured to be composed of a polycrystalline silicon film (fourth configuration).

In the voltage monitoring circuit having any of the first to fourth configurations, the voltage monitoring circuit is mounted on a one-chip semiconductor integrated circuit device, and the voltage monitoring circuit has an output terminal for outputting a comparison result in the comparison unit. The chip has a rectangular shape having a first side, a second side, a third side, and a fourth side, and has the input terminal, the reference voltage generation circuit, the linear power supply circuit, the comparison unit, and the above. At least one of the output terminals is arranged at a position closer to the first side than the feedback resistor, and at least one of the input terminal, the reference voltage generation circuit, the linear power supply circuit, the comparison unit, and the output terminal is said. At least one of the input terminal, the reference voltage generation circuit, the linear power supply circuit, the comparison unit, and the output terminal is arranged at a position closer to the second side than the feedback resistor, and the third is more than the feedback resistor. At least one of the input terminal, the reference voltage generation circuit, the linear power supply circuit, the comparison unit, and the output terminal is arranged at a position closer to the fourth side than the feedback resistor. (Fifth configuration) may be used.

In the voltage monitoring circuit having the fifth configuration, the center of the rectangular shape may be included in the arrangement position of the feedback resistor (sixth configuration).

In the voltage monitoring circuit having any of the first to sixth configurations, the reference voltage generation circuit and the linear power supply circuit are arranged at positions closer to the feedback resistor than the input terminal (seventh configuration). You may.

The control device disclosed in the present specification includes a control circuit that controls a controlled object, a voltage monitoring circuit having a configuration according to any one of the first to seventh components that resets the control circuit based on the monitored voltage. (8th configuration).

The vehicle disclosed in the present specification has a configuration (9th configuration) including a voltage monitoring circuit having any of the above-mentioned first to seventh configurations.

Further, for example, the voltage monitoring circuit disclosed in the present specification includes a first input terminal to which a first input voltage is applied, a second input terminal to which a second input voltage is applied, and a first reference voltage. A reference voltage generation circuit that generates a reference voltage, a linear power supply circuit that generates a second reference voltage corresponding to the first reference voltage, and a plurality of divided voltages generated from the second reference voltage, and one of them is used as a feedback voltage. A feedback resistor that negatively feeds back to the linear power supply circuit, a first comparison unit that compares the first input voltage with the third reference voltage to generate a first comparison signal, and the second input voltage and the fourth reference voltage. The second comparison unit that generates a second comparison signal by comparing the two, and any two of the second reference voltage and the plurality of divided voltages are used as switching candidates for the third reference voltage, and the first comparison is performed. The first selection unit that switches the third reference voltage according to the signal, and any two of the second reference voltage and the plurality of divided voltages are used as switching candidates for the fourth reference voltage, and the second comparison is made. It is configured to include a second selection unit that switches the fourth reference voltage according to a signal (tenth configuration).

In the voltage monitoring circuit having the tenth configuration, the feedback resistor may have a configuration (11th configuration) including a resistance element whose resistance value can be adjusted by trimming.

In the voltage monitoring circuit having the tenth or eleventh configuration, the feedback resistor is a plurality of first feedback resistors connected in series between the application end of the second reference voltage and the application end of the feedback voltage. It is preferable to have a configuration (12th configuration) including a second feedback resistor connected between the application end of the feedback voltage and the reference potential end.

In the voltage monitoring circuit having the twelfth configuration, among the plurality of first feedback resistors, the first resistance element provided on the lower potential side than the selection node of either the first selection unit or the second selection unit. May have a configuration (13th configuration) having different temperature characteristics from the plurality of first feedback resistors and the second resistance element used as the second feedback resistor, respectively.

In the voltage monitoring circuit having the thirteenth configuration described above, the reference voltage generation circuit and the linear power supply circuit have negative temperature characteristics, and the first resistance element is a diffusion resistor having positive temperature characteristics. The second resistance element may have a configuration (14th configuration) of a poly resistor having a negative temperature characteristic.

In the voltage monitoring circuit having any of the tenth to fourteenth configurations, the first input voltage is the monitored voltage or the first divided voltage thereof, and the second input voltage is different from the first input voltage. It is preferable to use a configuration (15th configuration) which is a second voltage division of the monitored voltage having a value.

Further, for example, the voltage monitoring circuit disclosed in the present specification includes an input terminal to which a monitored voltage or a divided voltage thereof is applied as an input voltage, a reference voltage generating circuit for generating a first reference voltage, and the above. A linear power supply circuit that generates a second reference voltage according to the first reference voltage, a feedback resistor that generates a divided voltage of the second reference voltage and negatively feeds back to the linear power supply circuit, the input voltage, and the second reference voltage. A comparison unit for comparing with a reference voltage is provided, and the voltage division ratio of the feedback resistance is switched according to the output of the comparison unit (16th configuration).

Further, for example, the voltage monitoring circuit disclosed in the present specification includes a first input terminal to which a monitored voltage or a first divided voltage thereof is applied as a first input voltage, and the first input voltage as a second input voltage. A second input terminal to which a second divided voltage of the monitored voltage whose value is different from the input voltage is applied, a reference voltage generation circuit that generates a first reference voltage, and a second reference voltage corresponding to the first reference voltage. The first comparison comparing the first input voltage and the second reference voltage with the linear power supply circuit that generates the above, the feedback resistor that generates the divided voltage of the second reference voltage and negatively feeds back to the linear power supply circuit. A unit and a second comparison unit that compares the second input voltage with the second reference voltage are provided, and the voltage division ratio of the feedback resistance corresponds to the output of each of the first comparison unit and the second comparison unit. It is said that the configuration can be switched (17th configuration).

Further, for example, the control device disclosed in the present specification comprises a control circuit for controlling a control target and any of the 15th to 17th configurations, and resets the control circuit based on the monitored voltage. It is configured to include a voltage monitoring circuit (18th configuration).

Further, for example, the vehicle disclosed in the present specification has a configuration (19th configuration) including a voltage monitoring circuit having any of the 10th to 17th configurations.

<Points to note>
The various technical features disclosed herein can be modified in addition to the above embodiments without departing from the gist of the technical creation. That is, it should be considered that the above embodiments are exemplary in all respects and are not restrictive, and the technical scope of the present invention is not the description of the above embodiments but the claims. It is shown and should be understood to include all modifications that fall within the meaning and scope of the claims.

1,1', 1a, 1b, 1c, 1d Voltage monitoring circuit 2 Reference voltage generation circuit 2A Depletion type MOSFET
2B enhancement type MOSFET
3 Linear power supply circuit 4, 5 Feedback resistor 6, 7 Comparator (comparison section)
8,8a, 8b, 8c, 8d feedback resistor 9,9a, 9b NMOSFET
10, 10a, 10b Inverter 100 Chip 101-104 1st to 4th sides CNT1 Control circuit R1, R2, R2A, R2B Resistance SW1, SW2, SW3, SW4 Switch T1, T3 Input terminal T2, T4 Output terminal X10 Vehicle

Claims (10)

The first input terminal to which the first input voltage is applied and
The second input terminal to which the second input voltage is applied and
A reference voltage generation circuit that generates the first reference voltage,
A linear power supply circuit that generates a second reference voltage corresponding to the first reference voltage, and
A feedback resistor that generates a plurality of partial pressures from the second reference voltage and negatively feeds back to the linear power supply circuit using one of them as a feedback voltage.
A first comparison unit that generates a first comparison signal by comparing the first input voltage with the third reference voltage,
A second comparison unit that generates a second comparison signal by comparing the second input voltage with the fourth reference voltage,
A first selection unit that switches the third reference voltage according to the first comparison signal by using any two of the second reference voltage and the plurality of divided voltages as switching candidates for the third reference voltage.
A second selection unit that uses any two of the second reference voltage and the plurality of divided voltages as switching candidates for the fourth reference voltage and switches the fourth reference voltage according to the second comparison signal.
A voltage monitoring circuit. The voltage monitoring circuit according to claim 1, wherein the feedback resistor includes a resistance element whose resistance value can be adjusted by trimming. The feedback resistor is formed between a plurality of first feedback resistors connected in series between the application end of the second reference voltage and the application end of the feedback voltage, and between the application end of the feedback voltage and the reference potential end. The voltage monitoring circuit according to claim 1 or 2, comprising a second feedback resistor connected. Among the plurality of first feedback resistors, the first resistance element provided on the lower potential side than the selection node of either the first selection unit or the second selection unit is the plurality of first feedback resistors excluding this. The voltage monitoring circuit according to claim 3, which has different temperature characteristics from the second resistance element used as the second feedback resistor. The reference voltage generation circuit and the linear power supply circuit have negative temperature characteristics and have negative temperature characteristics.
The first resistance element is a diffusion resistor having a positive temperature characteristic.
The second resistance element is a polyresistor having a negative temperature characteristic.
The voltage monitoring circuit according to claim 4. The first input voltage is the monitored voltage or the first divided voltage thereof, and the second input voltage is the second divided voltage of the monitored voltage having a value different from the first input voltage. The voltage monitoring circuit according to any one of 1 to 5. An input terminal to which the monitored voltage or its partial pressure is applied as the input voltage,
A reference voltage generation circuit that generates the first reference voltage,
A linear power supply circuit that generates a second reference voltage corresponding to the first reference voltage, and
A feedback resistor that generates a voltage divider of the second reference voltage and negatively feeds it back to the linear power supply circuit.
A comparison unit that compares the input voltage with the second reference voltage,
With
A voltage monitoring circuit in which the voltage division ratio of the feedback resistor is switched according to the output of the comparison unit. The first input terminal to which the monitored voltage or its first partial pressure is applied as the first input voltage,
A second input terminal to which a second partial pressure of the monitored voltage whose value is different from that of the first input voltage is applied as the second input voltage, and
A reference voltage generation circuit that generates the first reference voltage,
A linear power supply circuit that generates a second reference voltage corresponding to the first reference voltage, and
A feedback resistor that generates a voltage divider of the second reference voltage and negatively feeds it back to the linear power supply circuit.
A first comparison unit that compares the first input voltage with the second reference voltage,
A second comparison unit that compares the second input voltage with the second reference voltage,
With
A voltage monitoring circuit in which the voltage division ratio of the feedback resistor is switched according to the output of each of the first comparison unit and the second comparison unit. A control circuit that controls the control target and
The voltage monitoring circuit according to any one of claims 6 to 8, which resets the control circuit based on the monitored voltage.
A control device. A vehicle comprising the voltage monitoring circuit according to any one of claims 1 to 8.

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