JP2021052134A - Electronic control device - Google Patents

Electronic control device Download PDF

Info

Publication number
JP2021052134A
JP2021052134A JP2019175469A JP2019175469A JP2021052134A JP 2021052134 A JP2021052134 A JP 2021052134A JP 2019175469 A JP2019175469 A JP 2019175469A JP 2019175469 A JP2019175469 A JP 2019175469A JP 2021052134 A JP2021052134 A JP 2021052134A
Authority
JP
Japan
Prior art keywords
electronic control
control device
wiring board
printed wiring
barrier member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2019175469A
Other languages
Japanese (ja)
Inventor
近藤　充晃
Mitsuaki Kondo
充晃 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2019175469A priority Critical patent/JP2021052134A/en
Priority to DE102020209603.1A priority patent/DE102020209603B4/en
Publication of JP2021052134A publication Critical patent/JP2021052134A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H05K7/2039—Modifications to facilitate cooling, ventilating, or heating characterised by the heat transfer by conduction from the heat generating element to a dissipating body
    • H05K7/20436—Inner thermal coupling elements in heat dissipating housings, e.g. protrusions or depressions integrally formed in the housing
    • H05K7/20445—Inner thermal coupling elements in heat dissipating housings, e.g. protrusions or depressions integrally formed in the housing the coupling element being an additional piece, e.g. thermal standoff
    • H05K7/20454—Inner thermal coupling elements in heat dissipating housings, e.g. protrusions or depressions integrally formed in the housing the coupling element being an additional piece, e.g. thermal standoff with a conformable or flexible structure compensating for irregularities, e.g. cushion bags, thermal paste
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

To provide an electronic control device that can avoid affecting the operating characteristics of an IC when a heat conductive member is interposed between an IC package and a housing.SOLUTION: When the surface side of a printed wiring board 5 on which an IC 4 is mounted is covered with a metal cover 2, a gel-like material 16 having good thermal conductivity is arranged between the IC 4 and the cover 2. Then, a solder 18 is provided as a barrier member that prevents the gel-like material 16 from entering at a part between the end of a region where the IC 4 is mounted in the printed wiring board 5 and a connection terminal of the IC 4.SELECTED DRAWING: Figure 2

Description

本発明は、ＩＣを備える電子制御装置に関する。 The present invention relates to an electronic control device including an IC.

例えば車両制御を行うＥＣＵ（Electronic Control Unit）のような電子制御装置は、マイクロコンピュータ等のＩＣを備えている。このようなＩＣは動作時にノイズを発生させるため、例えばシールド部材によりマイコンを覆うことで対策を行っている。 For example, an electronic control device such as an ECU (Electronic Control Unit) that controls a vehicle includes an IC such as a microcomputer. Since such an IC generates noise during operation, measures are taken by covering the microcomputer with, for example, a shield member.

特開２００５−２３６０３６号公報Japanese Unexamined Patent Publication No. 2005-236036

しかしながら、マイクロコンピュータのようなＩＣは、動作周波数が上昇して機能が向上することに伴い、消費電力が増加して発熱温度も上昇する傾向にあるため、ノイズ対策と共に放熱対策も行う必要がある。例えば、ＩＣのパッケージに熱伝導部材である放熱ゲルを塗布し、金属製の筐体に接触させることで放熱を行うことが考えられる。この場合、放熱ゲルがパッケージの外周部からＩＣの接続ピン側に回り込むことが想定される。すると、放熱ゲルの誘電率は空気の数倍であることから、高周波信号を扱うＩＣの動作特性に影響を与える可能性がある。 However, ICs such as microcomputers tend to increase power consumption and heat generation temperature as the operating frequency increases and their functions improve. Therefore, it is necessary to take measures against heat dissipation as well as noise countermeasures. .. For example, it is conceivable to apply a heat radiating gel, which is a heat conductive member, to an IC package and bring it into contact with a metal housing to dissipate heat. In this case, it is assumed that the heat radiating gel wraps around from the outer peripheral portion of the package to the connection pin side of the IC. Then, since the dielectric constant of the heat-dissipating gel is several times that of air, it may affect the operating characteristics of the IC that handles high-frequency signals.

本発明は上記事情に鑑みてなされたものであり、その目的は、ＩＣのパッケージと筺体との間に熱伝導部材を介在させる際に、ＩＣの動作特性に影響を及ぼすことを回避できる電子制御装置を提供することにある。 The present invention has been made in view of the above circumstances, and an object of the present invention is electronic control that can avoid affecting the operating characteristics of the IC when a heat conductive member is interposed between the package of the IC and the housing. To provide the equipment.

請求項１記載の電子制御装置によれば、ＩＣと、プリント配線板の当該ＩＣが実装されている面側を覆う金属製のカバーとの間に熱伝導部材を配置する。そして、プリント配線板においてＩＣが実装される領域の端部と当該ＩＣの接続端子との間の少なくとも一部に、熱伝導部材の浸入を防止する障壁部材を備える。このように構成すれば、ＩＣとカバーとの間に配置された熱伝導部材の端部がＩＣの実装面側に回り込もうとした場合でも、実装上の必要に応じて障壁部材を設けることで、熱伝導部材がＩＣの接続端子に接触することを防止できる。 According to the electronic control device according to claim 1, the heat conductive member is arranged between the IC and the metal cover covering the surface side of the printed wiring board on which the IC is mounted. Then, at least a part of the printed wiring board between the end of the region where the IC is mounted and the connection terminal of the IC is provided with a barrier member for preventing the intrusion of the heat conductive member. With this configuration, even if the end of the heat conductive member arranged between the IC and the cover tries to wrap around to the mounting surface side of the IC, a barrier member can be provided as necessary for mounting. Therefore, it is possible to prevent the heat conductive member from coming into contact with the connection terminal of the IC.

請求項３記載の電子制御装置によれば、障壁部材をはんだで構成する。
そして、請求項４記載の電子制御装置のように、はんだをプリント配線板上のランドに配置することで、障壁部材を必要となる配置箇所に容易に形成できる。 According to the electronic control device according to claim 3, the barrier member is made of solder.
Then, by arranging the solder on the land on the printed wiring board as in the electronic control device according to claim 4, the barrier member can be easily formed at the required arrangement location.

請求項７記載の電子制御装置によれば、障壁部材を、少なくとも、発振器が接続される接続端子が配置されるＩＣの一辺側に形成する。すなわち、一般に発振器は高周波帯域の信号を出力するので、前記ＩＣの一辺側に障壁部材を設けることで、熱伝導部材が容量結合してその誘電率が高周波信号の特性に影響を及ぼすことを回避できる。 According to the electronic control device according to claim 7, the barrier member is formed at least on one side of the IC in which the connection terminal to which the oscillator is connected is arranged. That is, since an oscillator generally outputs a signal in a high frequency band, by providing a barrier member on one side of the IC, it is possible to prevent the heat conductive member from being capacitively coupled and its dielectric constant affecting the characteristics of the high frequency signal. it can.

請求項８記載の電子制御装置によれば、障壁部材を、少なくとも、アナログ回路が接続される接続端子が配置される前記ＩＣの一辺側に形成する。このように構成すれば、請求項７と同様に、熱伝導部材が容量結合してその誘電率がアナログ回路の特性に影響を及ぼすことを回避できる。 According to the electronic control device according to claim 8, the barrier member is formed at least on one side of the IC in which the connection terminal to which the analog circuit is connected is arranged. With this configuration, it is possible to prevent the heat conductive member from being capacitively coupled and its dielectric constant affecting the characteristics of the analog circuit, as in claim 7.

第１実施形態であり、電子制御装置の外観を示す斜視図A perspective view showing the appearance of the electronic control device according to the first embodiment. 電子制御装置の分解斜視図An exploded perspective view of the electronic control device 第１カバー及びＩＣを外した状態の電子制御装置の一部を示す平面図Top view showing a part of the electronic control device with the first cover and the IC removed. 図３ＡのＣ−Ｃ断面を示す図The figure which shows the CC cross section of FIG. 3A 第２実施形態であり、図３ＡのＣ−Ｃ断面を示す図2 is a diagram showing a CC cross section of FIG. 3A. 第３実施形態であり、第１カバー及びＩＣを外した状態の電子制御装置の一部を示す平面図A plan view showing a part of the electronic control device in the third embodiment with the first cover and the IC removed. 第４実施形態であり、第１カバー及びＩＣを外した状態の電子制御装置の一部を示す平面図FIG. 4 is a plan view showing a part of the electronic control device in a state where the first cover and the IC are removed, which is the fourth embodiment.

（第１実施形態）
本実施形態の電子制御装置１は、例えば車両制御用のＥＣＵであり車両に搭載される。図１に示す電子制御装置１は、何れも金属製であり四角形状の第１カバー２と第２カバー３とで筐体を構成しており、その筐体の内部に図２に示すＩＣ４等の回路部品が実装されたプリント配線板５が収容されている。 (First Embodiment)
The electronic control device 1 of the present embodiment is, for example, an ECU for vehicle control and is mounted on a vehicle. The electronic control device 1 shown in FIG. 1 is made of metal and has a housing composed of a square first cover 2 and a second cover 3, and the IC4 and the like shown in FIG. 2 are inside the housing. A printed wiring board 5 on which the circuit components of the above are mounted is housed.

プリント配線板５には、コネクタ６が実装されており、電子制御装置１はコネクタ６を介して外部機器と電気的に接続される。第１カバー２には、コネクタ６の図中上方側を覆うためのコネクタカバー部７が形成されている。また、第１カバー２には、ＩＣ４が位置する部位が、ＩＣ４のパッケージ表面との隙間をより狭くするように凹んだ形状の凹部２ａが形成されている。 A connector 6 is mounted on the printed wiring board 5, and the electronic control device 1 is electrically connected to an external device via the connector 6. The first cover 2 is formed with a connector cover portion 7 for covering the upper side of the connector 6 in the drawing. Further, the first cover 2 is formed with a recess 2a in which the portion where the IC 4 is located is recessed so as to narrow the gap between the IC 4 and the package surface.

ＩＣ４は、ＢＧＡ（Ball Grid Array）によってプリント配線板５に実装される。プリント配線板５には、ＩＣ４をはんだボール９を介して電気的に接続する位置に合せて、銅箔のランド１０が格子点状にレイアウトされている。破線αは、ＩＣ４のパッケージ外縁を示している。図３Ａに示すように、ランド１０の外周側には、コンデンサや抵抗等の受動部品１１や、トランジスタ等の半導体部品１２や、発振器ＯＳＣ等が表面実装されている。また、図中の「Ｖｉａ」はビアホールを示す。 The IC4 is mounted on the printed wiring board 5 by a BGA (Ball Grid Array). On the printed wiring board 5, copper foil lands 10 are laid out in a grid pattern so as to be aligned with the positions where the IC 4 is electrically connected via the solder balls 9. The broken line α indicates the outer edge of the IC4 package. As shown in FIG. 3A, passive components 11 such as capacitors and resistors, semiconductor components 12 such as transistors, oscillator OSC, and the like are surface-mounted on the outer peripheral side of the land 10. In addition, "Via" in the figure indicates a via hole.

尚、図１や図２に比較して、図３Ｂに示す図３ＡのＣ−Ｃ断面では、凹部２ａの両側における第１カバー２の高さ寸法が、各部に配置される部品の高さに合せて異なるように示されている。これは、第１カバー２の形状をこのようにしても良いことを、バリエーションとして示したものである。したがって、例えば凹部２ａの図中右側の高さ寸法を、同左側の高さ寸法と同一にしても良い。 Compared to FIGS. 1 and 2, in the CC cross section of FIG. 3A shown in FIG. 3B, the height dimension of the first cover 2 on both sides of the recess 2a is set to the height of the parts arranged in each portion. Together they are shown to be different. This shows as a variation that the shape of the first cover 2 may be changed in this way. Therefore, for example, the height dimension of the concave portion 2a on the right side in the drawing may be the same as the height dimension on the left side of the same.

図２や図３Ｂに示すように、第２カバー３側の四隅には、基板固定用のゴム１３が配置されている。第１カバー２と第２カバー３とは、プリント配線板５を内部に収容するようにして図中下方によりねじ１４をねじ止めして結合される。その際に、プリント配線板５は、第１カバー２の縁部１５とゴム１３との間に挟まれて固定される。 As shown in FIGS. 2 and 3B, rubbers 13 for fixing the substrate are arranged at the four corners on the second cover 3 side. The first cover 2 and the second cover 3 are connected by screwing the screw 14 from the lower part in the drawing so as to accommodate the printed wiring board 5 inside. At that time, the printed wiring board 5 is sandwiched and fixed between the edge portion 15 of the first cover 2 and the rubber 13.

また、第１カバー２と第２カバー３とが結合される際には、ＩＣ４のパッケージ表面にゲル状材料１６が予め載置される。熱伝導部材の一例であるゲル状材料１６は、熱伝導性が良好な誘電体であり、且つ図２に示すように、一定の形状を維持できる程度の粘性を有する材料である。そして、第１カバー２と第２カバー３とが結合される際には、ＩＣ４のパッケージ表面に載置されたゲル状材料１６が凹部２ａにより圧迫され、弾性的に変形することで外周方向に伸びて、ＩＣ４のパッケージ全体を覆うようになる。 Further, when the first cover 2 and the second cover 3 are combined, the gel-like material 16 is placed in advance on the package surface of the IC4. The gel-like material 16 which is an example of the heat conductive member is a dielectric material having good heat conductivity and, as shown in FIG. 2, a material having a viscosity sufficient to maintain a constant shape. When the first cover 2 and the second cover 3 are combined, the gel-like material 16 placed on the package surface of the IC 4 is pressed by the recess 2a and elastically deformed in the outer peripheral direction. It stretches to cover the entire IC4 package.

これに対応して、プリント配線板５には、発振器ＯＳＣに対向するＩＣ４の一辺側に、長方形状のランド１７が形成されており、そのランド１７には障壁部材の一例であるはんだ１８が乗せられる。本実施形態では、プリント配線板５の表面を配線層としており、図３Ａには、発振器ＯＳＣと対応するランド１０ａとを接続する配線パターン１９のみを示している。また、はんだ１８をハッチングで示しており、はんだボール９は図示していない。はんだ１８は、ゲル状材料１６がＩＣ４の外縁側から回り込んで、ランド１０ａに接触することを阻止する目的で配置されている。 Correspondingly, on the printed wiring board 5, a rectangular land 17 is formed on one side of the IC 4 facing the oscillator OSC, and the solder 18 which is an example of the barrier member is placed on the land 17. Be done. In the present embodiment, the surface of the printed wiring board 5 is used as a wiring layer, and FIG. 3A shows only the wiring pattern 19 that connects the oscillator OSC and the corresponding land 10a. Further, the solder 18 is shown by hatching, and the solder balls 9 are not shown. The solder 18 is arranged for the purpose of preventing the gel-like material 16 from wrapping around from the outer edge side of the IC 4 and coming into contact with the land 10a.

尚、図３Ｂには、はんだボール９に接続されるＩＣ４の接続端子であるランド２０を示している。このランド２０とはんだボール９及びランド１０は電気的に接続されるので、はんだボール９及びランド１０も接続端子と見做すことができる。また、第１カバー２と第２カバー３とを結合した際に、ゲル状材料１６が必ずしも図３Ｂに示すようにＩＣ４の実装面側に回り込むとは限らない。図３Ｂは、ワーストケースを想定したものである。 Note that FIG. 3B shows a land 20 which is a connection terminal of the IC 4 connected to the solder ball 9. Since the land 20, the solder ball 9 and the land 10 are electrically connected, the solder ball 9 and the land 10 can also be regarded as connection terminals. Further, when the first cover 2 and the second cover 3 are combined, the gel-like material 16 does not always wrap around to the mounting surface side of the IC 4 as shown in FIG. 3B. FIG. 3B assumes the worst case.

以上のように本実施形態によれば、プリント配線板５のＩＣ４が実装されている面側を金属製のカバー２で覆う際に、ＩＣ４とカバー２との間に熱伝導性が良好なゲル状材料１６を配置する。そして、プリント配線板５においてＩＣ４が実装される領域の端部，すなわち破線αとＩＣ４の接続端子との間の一部に、ゲル状材料１６の浸入を防止する障壁部材としてはんだ１８を備える。このように構成すれば、ゲル状材料１６の端部がＩＣ４の実装面側に回り込もうとした場合でも、はんだ１８により、ゲル状材料１６がＩＣ４の接続端子側に浸入して接触することを防止できる。 As described above, according to the present embodiment, when the surface side of the printed wiring board 5 on which the IC4 is mounted is covered with the metal cover 2, a gel having good thermal conductivity between the IC4 and the cover 2 is used. The shape material 16 is arranged. A solder 18 is provided as a barrier member for preventing the gel-like material 16 from entering the printed wiring board 5 at the end of the region where the IC4 is mounted, that is, a part between the broken line α and the connection terminal of the IC4. With this configuration, even if the end of the gel-like material 16 tries to wrap around to the mounting surface side of the IC 4, the gel-like material 16 penetrates into the connection terminal side of the IC 4 and comes into contact with the solder 18. Can be prevented.

この場合、はんだ１８をプリント配線板５上のランド１７に配置するので、障壁部材を必要となる配置箇所に容易に形成できる。また、はんだ１８を、発振器ＯＳＣが接続されるランド１０ａが配置されるＩＣ４の一辺側に形成する。これにより、ゲル状材料１６が容量結合することで、その誘電率が発振器ＯＳＣが出力する高周波信号の特性に影響を及ぼすことを回避できる。この際に、はんだ１８の配置長さをランド１０ａ，１０ａの配置間隔よりも長くすることで、ランド１０ａ，１０ａの間にゲル状材料１６が浸入することを確実に阻止できる。 In this case, since the solder 18 is arranged on the land 17 on the printed wiring board 5, the barrier member can be easily formed at the required arrangement location. Further, the solder 18 is formed on one side of the IC4 where the land 10a to which the oscillator OSC is connected is arranged. As a result, it is possible to prevent the dielectric constant of the gel-like material 16 from being capacitively coupled to affect the characteristics of the high-frequency signal output by the oscillator OSC. At this time, by making the arrangement length of the solder 18 longer than the arrangement interval of the lands 10a and 10a, it is possible to reliably prevent the gel-like material 16 from entering between the lands 10a and 10a.

（第２実施形態）
以下、第１実施形態と同一部分には同一符号を付して説明を省略し、異なる部分について説明する。図４に示すように、第２実施形態は、ランド１７を、プリント配線板５の内層であるＧＮＤにビアホール２１を介して接続した構成を示す。 (Second Embodiment)
Hereinafter, the same parts as those in the first embodiment are designated by the same reference numerals, description thereof will be omitted, and different parts will be described. As shown in FIG. 4, the second embodiment shows a configuration in which the land 17 is connected to the GND which is the inner layer of the printed wiring board 5 via the via hole 21.

（第３実施形態）
図５に示す第３実施形態は、第１実施形態と同様に形成した障壁部材としてのはんだ２２，２３を、ＩＣ４の二辺に配置した構成である。第３実施形態は、これらのはんだ２２，２３を、ＩＣ４の周辺回路として、受動部品１１により構成される例えばＣＲフィルタなどのアナログ回路に接続されるランド１０ｂ，１０ｃが配置される各辺に対して配置している。このように構成すれば、ゲル状材料１６が容量結合することで、その誘電率がＣＲフィルタの特性に影響を及ぼすことを回避できる。尚、はんだ２２，２３は第１実施形態と同様に、ランド上に配置されている。 (Third Embodiment)
The third embodiment shown in FIG. 5 has a configuration in which solders 22 and 23 as barrier members formed in the same manner as in the first embodiment are arranged on two sides of the IC4. In the third embodiment, these solders 22 and 23 are used as peripheral circuits of the IC4 for each side on which the lands 10b and 10c connected to an analog circuit such as a CR filter composed of the passive component 11 are arranged. Is arranged. With this configuration, it is possible to prevent the dielectric constant from affecting the characteristics of the CR filter due to the capacitive coupling of the gel-like material 16. The solders 22 and 23 are arranged on the land as in the first embodiment.

（第４実施形態）
図６に示す第４実施形態は、第３実施形態において、ランド１０ｂ，１０ｃが配置される辺に対して配置したはんだ２２，２３を、一端が共通するＩＣ４の角部で接続した形状である１つのはんだ２４を配置している。このように構成すれば、第３実施形態におけるはんだ２２，２３の隙間から、ゲル状材料１６が内部側に侵入することを阻止できる。 (Fourth Embodiment)
The fourth embodiment shown in FIG. 6 has a shape in which the solders 22 and 23 arranged with respect to the sides where the lands 10b and 10c are arranged are connected by the corners of the IC4 having one end in common in the third embodiment. One solder 24 is arranged. With this configuration, it is possible to prevent the gel-like material 16 from invading the inside through the gaps between the solders 22 and 23 in the third embodiment.

（その他の実施形態）
障壁部材ははんだに限ることなく、例えばアンダーフィル等を用いても良い。
障壁部材の長さは、必ずしも２つの接続端子の配置間隔より長くする必要は無い。熱電導部材との接触を回避したい接続端子が１つであれば、少なくともその１つの接続端子をカバーできる長さにすれば良い。 (Other embodiments)
The barrier member is not limited to solder, and for example, underfill or the like may be used.
The length of the barrier member does not necessarily have to be longer than the arrangement interval between the two connection terminals. If there is only one connection terminal for which contact with the thermoconducting member is desired, the length may be set so as to cover at least one connection terminal.

また、上記の実施形態では、障壁部材をＩＣが実装される領域の端に係る部分とＩＣの最外周部にある接続端子との間に形成したが、必ずしもこれに限らない。熱電導部材との接触を回避したい接続端子が最外周部以外に配置されている場合は、その接触を回避したい接続端子の位置に応じて障壁部材を配置すれば良い。
障壁部材を、ＩＣの３辺以上に配置しても良い。 Further, in the above embodiment, the barrier member is formed between the portion related to the end of the region where the IC is mounted and the connection terminal on the outermost peripheral portion of the IC, but the present invention is not necessarily limited to this. When the connection terminal for which the contact with the thermoconducting member is to be avoided is arranged other than the outermost peripheral portion, the barrier member may be arranged according to the position of the connection terminal for which the contact is to be avoided.
Barrier members may be arranged on three or more sides of the IC.

本開示は、実施例に準拠して記述されたが、本開示は当該実施例や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 Although the present disclosure has been described in accordance with the examples, it is understood that the present disclosure is not limited to the examples and structures. The present disclosure also includes various modifications and modifications within an equal range. In addition, various combinations and forms, as well as other combinations and forms that include only one element, more, or less, are also within the scope of the present disclosure.

図面中、１は電子制御装置、２は第１カバー、２ａは凹部、３は第２カバー、４はＩＣ、５はプリント配線板、１０はランド、１６はゲル状材料である。 In the drawings, 1 is an electronic control device, 2 is a first cover, 2a is a recess, 3 is a second cover, 4 is an IC, 5 is a printed wiring board, 10 is a land, and 16 is a gel-like material.

Claims (10)

パッケージの一面側に接続端子（２０）を有するＩＣ（４）と、
このＩＣが実装されるプリント配線板（５）と、
このプリント配線板の前記ＩＣが実装されている面側を覆う金属製のカバー（２）と、
前記ＩＣと前記カバーとの間に配置される熱伝導部材（１６）と、
前記プリント配線板において前記ＩＣが実装される領域の端に係る部分と前記接続端子との間の少なくとも一部に配置され、前記熱伝導部材の浸入を防止する障壁部材（１８，２２，２３，２４）とを備える電子制御装置。 IC (4) having a connection terminal (20) on one side of the package,
The printed wiring board (5) on which this IC is mounted and
A metal cover (2) that covers the surface side of the printed wiring board on which the IC is mounted, and
A heat conductive member (16) arranged between the IC and the cover,
Barrier members (18, 22, 23, which are arranged at least a part between the end of the region where the IC is mounted and the connection terminal in the printed wiring board and prevent the heat conductive member from entering. 24) and an electronic control device. 前記障壁部材が、前記領域の端に係る部分と前記ＩＣの最外周部にある接続端子との間に配置されている請求項１記載の電子制御装置。 The electronic control device according to claim 1, wherein the barrier member is arranged between a portion related to the end of the region and a connection terminal on the outermost peripheral portion of the IC. 前記障壁部材は、はんだである請求項１又は２記載の電子制御装置。 The electronic control device according to claim 1 or 2, wherein the barrier member is solder. 前記はんだは、前記プリント配線板上のランド（１７）に配置されている請求項３記載の電子制御装置。 The electronic control device according to claim 3, wherein the solder is arranged on a land (17) on the printed wiring board. 前記ランド（１７）は、電気的に絶縁されている請求項４記載の電子制御装置。 The electronic control device according to claim 4, wherein the land (17) is electrically insulated. 前記障壁部材の長さが、前記接続端子の配置間隔よりも長く形成されている請求項１から５の何れか一項に記載の電子制御装置。 The electronic control device according to any one of claims 1 to 5, wherein the length of the barrier member is formed to be longer than the arrangement interval of the connection terminals. 前記ＩＣの周辺に搭載される発振器（ＯＳＣ）を備え、
前記障壁部材が、少なくとも、前記発振器が接続される接続端子（１０ａ）が配置される前記ＩＣの一辺側に形成されている請求項１から６の何れか一項に記載の電子制御装置。 It is equipped with an oscillator (OSC) mounted around the IC.
The electronic control device according to any one of claims 1 to 6, wherein the barrier member is formed at least on one side of the IC to which the connection terminal (10a) to which the oscillator is connected is arranged. 前記ＩＣの周辺に搭載されるアナログ回路を備え、
前記障壁部材が、少なくとも、前記アナログ回路が接続される接続端子（１０ｂ，１０ｃ）が配置される前記ＩＣの一辺側に形成されている請求項１から７の何れか一項に記載の電子制御装置。 It is equipped with an analog circuit mounted around the IC.
The electronic control according to any one of claims 1 to 7, wherein the barrier member is formed at least on one side of the IC to which connection terminals (10b, 10c) to which the analog circuit is connected are arranged. apparatus. 前記障壁部材（２２，２３，２４）が、前記ＩＣの二辺側以上に形成されている請求項１から８の何れか一項に記載の電子制御装置。 The electronic control device according to any one of claims 1 to 8, wherein the barrier member (22, 23, 24) is formed on two or more sides of the IC. 一端が前記ＩＣの同じ角部側となる二辺側の障壁部材が連結されている請求項９記載の電子制御装置。 The electronic control device according to claim 9, wherein a barrier member on two sides, one end of which is on the same corner side of the IC, is connected.
JP2019175469A 2019-09-26 2019-09-26 Electronic control device Pending JP2021052134A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2019175469A JP2021052134A (en) 2019-09-26 2019-09-26 Electronic control device
DE102020209603.1A DE102020209603B4 (en) 2019-09-26 2020-07-30 Electronic control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019175469A JP2021052134A (en) 2019-09-26 2019-09-26 Electronic control device

Publications (1)

Publication Number Publication Date
JP2021052134A true JP2021052134A (en) 2021-04-01

Family

ID=74872998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019175469A Pending JP2021052134A (en) 2019-09-26 2019-09-26 Electronic control device

Country Status (2)

Country Link
JP (1) JP2021052134A (en)
DE (1) DE102020209603B4 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6221249A (en) * 1985-07-22 1987-01-29 Hitachi Ltd Semiconductor device
JP2005012127A (en) * 2003-06-20 2005-01-13 Denso Corp Electronic control apparatus
US20050074923A1 (en) * 2003-10-03 2005-04-07 Vahid Goudarzi Metallic dam and method of forming therefor
JP2005236036A (en) * 2004-02-19 2005-09-02 Denso Corp Electronic controller for vehicle
JP2011009643A (en) * 2009-06-29 2011-01-13 Denso Corp Electronic device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4691455B2 (en) 2006-02-28 2011-06-01 富士通株式会社 Semiconductor device
US20180233423A1 (en) 2017-02-14 2018-08-16 Skyworks Solutions, Inc. Flip-chip mounting of silicon-on-insulator die
WO2019112582A1 (en) 2017-12-07 2019-06-13 Intel Corporation A heat dissipation structure for an integrated circuit package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6221249A (en) * 1985-07-22 1987-01-29 Hitachi Ltd Semiconductor device
JP2005012127A (en) * 2003-06-20 2005-01-13 Denso Corp Electronic control apparatus
US20050074923A1 (en) * 2003-10-03 2005-04-07 Vahid Goudarzi Metallic dam and method of forming therefor
JP2005236036A (en) * 2004-02-19 2005-09-02 Denso Corp Electronic controller for vehicle
JP2011009643A (en) * 2009-06-29 2011-01-13 Denso Corp Electronic device

Also Published As

Publication number Publication date
DE102020209603B4 (en) 2022-06-15
DE102020209603A1 (en) 2021-04-01

Similar Documents

Publication Publication Date Title
JP4178880B2 (en) Module parts
JP7136553B2 (en) electronic controller
US7130195B2 (en) Electronic apparatus
WO2004010499A1 (en) Module component
KR20040089558A (en) Wiring board and circuit module
WO2020017582A1 (en) Module
JP6790902B2 (en) Electronic device
JP2005026263A (en) Hybrid integrated circuit
WO2022059263A1 (en) Electronic control device
JP2021052134A (en) Electronic control device
JP4327404B2 (en) Electronic equipment
JP2021005580A (en) Electronic control device
KR20150050189A (en) Semiconductor Package
JP5146019B2 (en) High frequency module and electronic device using the same
US20180242459A1 (en) Component mount board
KR20180023488A (en) Semiconductor Package and Manufacturing Method for Semiconductor Package
KR101053296B1 (en) Electronic device with electromagnetic shielding
JP2020136460A (en) Electronic control device
JP4073682B2 (en) Electronic component with shield cap
CN113711160A (en) Electronic device
WO2021075360A1 (en) Electronic control device
WO2021059914A1 (en) Electronic circuit device
JP7307844B2 (en) electronic controller
KR101305581B1 (en) Shield member and pcb comprising the shield member
JP7007057B2 (en) Printed wiring boards, printed circuit boards and electronic devices

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20211217

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20221117

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20221122

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230110

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20230509